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2012-01-21load_image_targphys() should enforce the max sizeBenjamin Herrenschmidt1-1/+5
load_image_targphys() gets passed a max size for the file, but doesn't enforce it at all. Add a check and return -1 (error) if the file is too big, without loading it. Fix the bracing style in the function while we're at it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-01-21virtio: change memcpy to guest readsAlexander Graf1-6/+6
When accessing the device specific virtio config space, we memcpy the data into a variable in QEMU. At that point we're basically pulling host endianness into the game which is a really bad idea. So instead, let's use the target specific load/store helpers for memory pointers which fetch things in target endianness. The whole array is already populated in target endianness anyways (see virtio-blk). Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-01-21virtio-pci: Fix endianness of virtio configBenjamin Herrenschmidt1-2/+26
The virtio config area in PIO space is a bit special. The initial header is little endian but the rest (device specific) is guest native endian. The PIO accessors for PCI on machines that don't have native IO ports assume that all PIO is little endian, which works fine for everything except the above. A complicated way to fix it would be to split the BAR into two memory regions with different endianess settings, but this isn't practical to do, besides, the PIO code doesn't honor region endianness anyway (I have a patch for that too but it isn't necessary at this stage). So I decided to go for the quick fix instead which consists of reverting the swap in virtio-pci in selected places, hoping that when we eventually do a "v2" of the virtio protocols, we sort that out once and for all using a fixed endian setting for everything. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Alexander Graf <agraf@suse.de> [agraf: keep virtio in libhw and determine endianness through a helper function in exec.c] Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-01-21PPC: Bamboo: Integrate SoC instatiation, use qdev for PCIAlexander Graf1-83/+60
Now that we have the SoC init function in the same file, let's integrate it with the board initialization. While at it, also make use of the newly qdev'ified PCI host controller. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-01-21PPC: Bamboo: fold ppc440.c and ppc440_bamboo.c into a single fileAlexander Graf4-130/+89
The separation of ppc440 and ppc440_bamboo makes some sense, since ppc440 is the SoC while ppc440_bamboo is the actual board. But the separation makes things harder for us for no good reason, so let's just fold them in together with each other. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-01-21PPC: 4xx: Qdevify the 440 PCI host controllerAlexander Graf2-60/+74
Due to popular demand, this qdevifies the PCI host controller of 4xx SoCs the same way as e500. We have to introduce a small stub function for pci init that will be removed in a later patch, once we qdev'ified the board, to keep the build working. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-01-21PPC: bamboo: fix whitespaceAlexander Graf1-3/+3
Tabs followed by spaces are a no-go. My editor shows it red, distracting me from actual work! :) Signed-off-by: Alexander Graf <agraf@suse.de>
2012-01-21PPC: bamboo: remove old machine descriptionsAlexander Graf1-21/+1
Nobody needs to run bamboo in 0.12 compat mode. Remove the machine. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-01-21PPC: 440: Default to 440EP CPUAlexander Graf1-1/+1
Today we're exposing a Virtex 440 CPU to the guest despite the fact that we're telling the guest that we're running on a 440EP one in the device tree. So let's better default to a real 440EP to make things synced again. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-01-21PPC: 440: Ignore invalid PCI IRQsAlexander Graf1-0/+4
When running a 440 target, we currently get invalid irq_num values (-1) which completely confuse the IRQ setting code. This is most likely due to the missing qdev conversion. While this shouldn't happen in the first place and should really rather be fixed by converting the target, I dislike segfaults. So for now, let's just print a warning and ignore invalid irq_num values. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-01-21PPC: Bamboo: Set initial TLB entryAlexander Graf1-1/+26
Back in the day when the bamboo target got introduced, the initial TLB was dictated by KVM. TCG has been missing initial TLB values ever since, rendering the target unusable for TCG usage. This patch adds linear TLB maps the way Linux expects them, making the target work. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-01-21PPC: Bamboo: Register CPU resetAlexander Graf1-6/+13
To be able to support CPU reset, we need to put all register initialization and initial state into a CPU reset hook instead of a function that is only called once on bootup. This is a preparation step for the initial TLB setting code and brings bamboo more in line with what e500 and virtex already do. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-01-21PPC: 440EP: Initialize timerAlexander Graf1-0/+1
When using TCG with a BookE PowerPC core, we need to explicitly initialize the BookE timers with the correct frequencies. This was missing for 440EP, since that code came from KVM and was never used with TCG. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-01-20prep: Use i82378 PCI->ISA bridge for 'prep' machineAndreas Färber1-48/+13
Speaker I/O, ISA bus, i8259 PIC, RTC and DMA are no longer set up individually by the machine. Effectively, no-op speaker I/O is replaced by pcspk; PIT and i82374 DMA are introduced. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Remove related dead, alternative code. Wire up PCI host bridge IRQs via GPIO-in IRQs of PCI->ISA bridge. Signed-off-by: Andreas Färber <andreas.faerber@web.de> Cc: Alexander Graf <agraf@suse.de> Cc: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-20prep: Add i82378 PCI-to-ISA bridge emulationAndreas Färber2-0/+265
Prepare Intel 82378 emulation for use by PReP platforms. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Create ISA bus in this device (suggested by Markus). Rebase onto Memory API, mark memory ops as Little Endian. Add VMState. Provide access to i8259 IRQs via qdev GPIOs. Signed-off-by: Andreas Färber <andreas.faerber@web.de> Cc: Markus Armbruster <armbru@redhat.com> Cc: Alexander Graf <agraf@suse.de> Cc: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-20prep: Add i82374 DMA emulationAndreas Färber1-0/+154
Prepare Intel 82374 emulation for use by Intel 82378 PCI->ISA bridge. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Confine to CONFIG_I82374. Add VMState. Signed-off-by: Andreas Färber <andreas.faerber@web.de> Reviewed-by: Alexander Graf <agraf@suse.de>
2012-01-20prep: qdev'ify Raven host bridge (SysBus)Andreas Färber3-38/+63
Drop pci_prep_init() in favor of extended device state. Inspired by patches from Hervé and Alex. Assign the 4 IRQs from the board after device instantiation. This moves the knowledge out of prep_pci and allows for future machines with different IRQ wiring (IBM 40P). Suggested by Alex. Signed-off-by: Andreas Färber <andreas.faerber@web.de> Reviewed-by: Alexander Graf <agraf@suse.de> Cc: Hervé Poussineau <hpoussin@reactos.org> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Anthony Liguori <aliguori@us.ibm.com>
2012-01-20prep_pci: Update I/O to MemoryRegion opsAndreas Färber1-38/+8
Convert to new-style read/write callbacks. Signed-off-by: Andreas Färber <andreas.faerber@web.de> Cc: Alexander Graf <agraf@suse.de> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Avi Kivity <avi@redhat.com> Cc: Benoît Canet <benoit.canet@gmail.com>
2012-01-20prep_pci: Simplify I/O endiannessAndreas Färber1-5/+1
The prep PowerPC CPU is Big Endian. An explicit byte swap therefore effectively becomes Little Endian. Remove explicit byte swaps and mark as Little Endian. Signed-off-by: Andreas Färber <andreas.faerber@web.de> Reviewed-by: Alexander Graf <agraf@suse.de> Cc: Michael S. Tsirkin <mst@redhat.com>
2012-01-20prep: qdev'ify Raven host bridge (PCIDevice)Andreas Färber1-9/+46
Move initialization of vendor ID, etc. to PCIDeviceInfo. Introduce VMState. Signed-off-by: Andreas Färber <andreas.faerber@web.de> Reviewed-by: Alexander Graf <agraf@suse.de> Cc: Hervé Poussineau <hpoussin@reactos.org> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Anthony Liguori <aliguori@us.ibm.com>
2012-01-20prep: Use ISA m48t59Andreas Färber1-1/+1
This simplifies the code later when the i8259 moves to the i82378 PCI->ISA bridge and happens to fix a SysBus m48t59 io_base issue introduced by commit 0fb56ffc5edd66f12ccfc0d71af5f9c79c0a2612 (m48t59: drop obsolete address base arithmetic). Suggested by Hervé and Jan. Signed-off-by: Andreas Färber <andreas.faerber@web.de> Cc: Hervé Poussineau <hpoussin@reactos.org> Cc: Jan Kiszka <jan.kiszka@siemens.com> Cc: Blue Swirl <blauwirbel@gmail.com>
2012-01-20prep: Fix offset of BIOS MemoryRegionAndreas Färber1-2/+2
Since 0c90c52fab5ea92d7f12b29bfe26a7cd75d9efcb (ppc_prep: convert to memory API) OHW was "Trying to execute code outside RAM or ROM at 0xfff00700". The BIOS MemoryRegion is created with a fixed size of 1 MiB. Ensure that the full size can be accessed since the exception vectors are located at 0xfff00000 and the BIOS may want to use them. It thereby no longer depends on the actual BIOS binary size. Signed-off-by: Andreas Färber <afaerber@suse.de> Cc: Avi Kivity <avi@redhat.com> Cc: Alexander Graf <agraf@suse.de>
2012-01-19Merge remote-tracking branch 'spice/spice.v47' into stagingAnthony Liguori1-1/+1
* spice/spice.v47: qxl: Slot sanity check in qxl_phys2virt() is off by one, fix
2012-01-19Merge remote-tracking branch 'stefanha/trivial-patches' into stagingAnthony Liguori1-1/+1
* stefanha/trivial-patches: Makefile: Remove generated headers on clean Makefile: Exclude tests/Makefile in unconfigured tree lm32: Fix mixup of uint32 and uint32_t tests: Silence gtester in Makefile qemu-tool: Fix mixup of int64 and int64_t
2012-01-19Merge remote-tracking branch 'pmaydell/arm-devs.for-upstream' into stagingAnthony Liguori9-75/+193
* pmaydell/arm-devs.for-upstream: arm: make the number of GIC interrupts configurable hw/lan9118: Add save/load support arm: Remove incorrect comment in arm_timer vexpress, realview: Add (dummy) L2 cache controller
2012-01-19Merge remote-tracking branch 'kraxel/usb.37' into stagingAnthony Liguori20-100/+3769
* kraxel/usb.37: usb-redir: Improve some debugging messages usb-redir: Try to keep our buffer size near the target size usb-redir: Pre-fill our isoc input buffer before sending pkts to the host usb-redir: Dynamically adjust iso buffering size based on ep interval usb-redir: Clear iso / irq error when stopping the stream usb: link packets to endpoints not devices usb: add max_packet_size to USBEndpoint usb/debug: add usb_ep_dump usb-desc: USBEndpoint support usb: add ifnum to USBEndpoint usb: add USBEndpoint xhci: Initial xHCI implementation usb: add audio device model usb-desc: audio endpoint support usb: track altsetting in USBDevice usb: track configuration and interface count in USBDevice. usb-host: rip out legacy procfs support
2012-01-19kvm: x86: Add user space part for in-kernel IOAPICJan Kiszka2-1/+128
This introduces the KVM-accelerated IOAPIC model 'kvm-ioapic' and extends the IRQ routing setup by the 0->2 redirection when needed. The kvm-ioapic model has a property that allows to define its GSI base for injecting interrupts into the kernel model. This will allow to disentangle PIC and IOAPIC pins for chipsets that support more sophisticated IRQ routes than the PIIX3. So far the base is kept at 0, i.e. PIC and IOAPIC share pins 0..15. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-19kvm: x86: Add user space part for in-kernel i8259Jan Kiszka3-4/+177
Introduce the alternative 'kvm-i8259' device model that exploits KVM in-kernel acceleration. The PIIX3 initialization code is furthermore extended by KVM specific IRQ route setup. GSI injection differs in KVM mode from the user space model. As we can dispatch ISA-range IRQs to both IOAPIC and PIC inside the kernel, we do not need to inject them separately. This is reflected by a KVM-specific GSI handler. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-19kvm: x86: Add user space part for in-kernel APICJan Kiszka2-5/+148
This introduces the alternative APIC device which makes use of KVM's in-kernel device model. External NMI injection via LINT1 is emulated by checking the current state of the in-kernel APIC, only injecting a NMI into the VCPU if LINT1 is unmasked and configured to DM_NMI. MSI is not yet supported, so we disable this when the in-kernel model is in use. CC: Lai Jiangshan <laijs@cn.fujitsu.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-19kvm: x86: Establish IRQ0 override controlJan Kiszka1-1/+2
KVM is forced to disable the IRQ0 override when we run with in-kernel irqchip but without IRQ routing support of the kernel. Set the fwcfg value correspondingly. This aligns us with qemu-kvm. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-19ioapic: Factor out base class for KVM reuseJan Kiszka3-114/+217
Split up the IOAPIC analogously to APIC and i8259. KVM will share the IOAPICCommonState, the vmstate, reset logic and certain init parts with the user space model. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-19ioapic: Drop post-load irr initializationJan Kiszka1-12/+0
As all devices undergo a reset prior to vmloa, and the reset value of irr is 0, we do not need to do this clearing for older vmstates explicitly. Dropping this redundant code will also make KVM integration a bit simpler. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-19i8259: Factor out base class for KVM reuseJan Kiszka3-128/+253
Analogously to the APIC, we will reuse some parts of the user space i8259 model for KVM. The base class provides a common device state, the vmstate, the property list, a reset core and some shared init bits. This also introduces a common helper to instantiate a single i8259 chip from the cascade-creating i8259_init function. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-19i8259: Completely privatize PicStateJan Kiszka2-10/+14
Use DeviceState instead of PicState in the public i8259 API. This is cleaner and allows to reorganize the PIC data structures for KVM reuse. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-19apic: Open-code timer save/restoreJan Kiszka3-20/+67
To enable migration between accelerated and non-accelerated APIC models, we will need to handle the timer saving and restoring specially and can no longer rely on the automatics of VMSTATE_TIMER. Specifically, accelerated model will not start any QEMUTimer. This patch therefore factors out the generic bits into apic_next_timer and use a post-load callback to implemented model-specific logic. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-19apic: Factor out base class for KVM reuseJan Kiszka4-298/+405
The KVM in-kernel APIC model will reuse parts of the user space model while providing the same frontend view to guest and most management interfaces. Factor out an APIC base class to encapsulate those parts that will be shared by user space and KVM model. This class offers callback hooks for init, base/tpr setting, and the external NMI delivery that will be set via APICCommonInfo structure and implemented specifically in the subclasses. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-19apic: Introduce apic_report_irq_deliveredJan Kiszka2-3/+9
The in-kernel i8259 and IOAPIC backends for KVM will need this, so encapsulate the shared bits. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-19apic: Inject external NMI events via LINT1Jan Kiszka2-0/+8
On real hardware, NMI button events are injected via the LINT1 line of the APICs. E.g. kdump expect this wiring and gets upset if the per-APIC LINT1 mask is not respected, i.e. if NMIs are injected to VCPUs that should not receive them. Change the APIC emulation code to reflect this. Based on qemu-kvm patch by Lai Jiangshan. CC: Lai Jiangshan <laijs@cn.fujitsu.com> Reported-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-19apic: Stop timer on resetJan Kiszka1-0/+2
All LVTs are masked on reset, so the timer becomes ineffective. Letting it tick nevertheless is harmless, but will at least create a spurious trace event. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-19kvm: Move kvmclock into hw/kvm folderJan Kiszka3-3/+3
More KVM-specific devices will come, so let's start with moving the kvmclock into a dedicated folder. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-19msi: Generalize msix_supported to msi_supportedJan Kiszka5-9/+16
Rename msix_supported to msi_supported and control MSI and MSI-X activation this way. That was likely to original intention for this flag, but MSI support came after MSI-X. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-19lm32: Fix mixup of uint32 and uint32_tAndreas Färber1-1/+1
Commit d23948b15a9920fb7f6374b55a6db1ecff81f3ee (lm32: add Milkymist VGAFB support) introduced a stray usage of the softfloat uint32 type. Use uint32_t instead. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Michael Walle <michael@walle.cc> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2012-01-17qxl: Slot sanity check in qxl_phys2virt() is off by one, fixMarkus Armbruster1-1/+1
Spotted by Coverity. Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2012-01-17arm: make the number of GIC interrupts configurableMark Langsdorf5-49/+87
Increase the maximum number of GIC interrupts for a9mp and a11mp to 1020, and create a configurable property for each defaulting to 96 and 64 (respectively) so that device modelers can set the value appropriately for their SoC. Other ARM processors also set their maximum number of used IRQs appropriately. Set the maximum theoretical number of GIC interrupts to 1020 and update the save/restore code to only use the appropriate number for each SoC. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Reviewed-by: Andreas Färber <afaerber@suse.de> [Peter Maydell: fixed minor whitespace snafu] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-17hw/lan9118: Add save/load supportPeter Maydell1-23/+103
Implement save/load for the LAN9118. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-01-17arm: Remove incorrect comment in arm_timerMark Langsdorf1-3/+0
The current comment says that the arm_timers are restricted to between 32 KHz and 1 MHz, but sp804 TRM does not specify those limits. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-17vexpress, realview: Add (dummy) L2 cache controllerPeter Maydell2-0/+3
Instantiate the L2 cache controller on the ARM devboards which have one, since we have a dummy model of it now. Note that the only non-MP board with an L2x0 is the PB1176, which we don't model. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-17usb: link packets to endpoints not devicesGerd Hoffmann6-7/+22
Add USBEndpoint for the control endpoint to USBDevices. Link async packets to the USBEndpoint instead of the USBDevice. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2012-01-17usb: add max_packet_size to USBEndpointGerd Hoffmann3-4/+39
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2012-01-17usb/debug: add usb_ep_dumpGerd Hoffmann2-0/+41
Add function to dump endpoint data, for debugging purposes. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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