path: root/hw/sh7750.c
AgeCommit message (Expand)AuthorFilesLines
2011-11-24sh_serial: convert to memory APIBenoît Canet1-13/+15
2011-11-24sh_intc: convert interrupt controller to memory APIBenoît Canet1-1/+1
2011-11-24sh_timer: convert to memory APIBenoît Canet1-2/+2
2011-11-24sh7750: convert cache and tlb to memory APIBenoît Canet1-21/+22
2011-11-24sh7750: convert memory controller/ioport to memory APIBenoît Canet1-27/+45
2011-08-20Use glib memory allocation and free functionsAnthony Liguori1-1/+1
2011-06-26Remove exec-all.h include directivesBlue Swirl1-1/+0
2011-01-26sh4: implement missing mmaped TLB read functionsAurelien Jarno1-6/+9
2011-01-26sh4: implement missing mmaped TLB write functionsAurelien Jarno1-3/+2
2011-01-09target-sh4: implement writes to mmaped ITLBAurelien Jarno1-0/+2
2010-12-11Add endianness as io mem parameterAlexander Graf1-2/+4
2010-03-18Replace assert(0) with abort() or cpu_abort()Blue Swirl1-15/+15
2010-02-09sh7750: handle MMUCR TI bitAurelien Jarno1-2/+5
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori1-12/+12
2009-10-01Get rid of _t suffixmalc1-12/+12
2009-09-25static and inline should came before the type of the functionsJuan Quintela1-1/+1
2009-08-25Make CPURead/WriteFunc structure 'const'Blue Swirl1-4/+4
2009-06-16Remove io_index argument from cpu_register_io_memory()Avi Kivity1-4/+2
2009-05-13Include assert.h from qemu-common.hPaul Brook1-1/+0
2009-02-07SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 an...aurel321-10/+42
2008-12-13Remove unnecessary trailing newlinesblueswir11-1/+0
2008-12-07SH4: Eliminate P4 to A7 mangling (Takashi YOSHII).balrog1-0/+6
2008-12-07SH: improve the way sh7750 registers io memory (Takashi YOSHII).balrog1-8/+6
2008-12-07SH: r2d pci support (Takashi YOSHII).balrog1-0/+17
2008-12-07sh4: Add IRL (4-bit encoded interrupt input) support (Takashi YOSHII).balrog1-1/+39
2008-12-01Change MMIO callbacks to use offsets, not absolute addresses.pbrook1-1/+2
2008-11-21SH4: Switch serial emulation to qemu_irqaurel321-8/+8
2008-11-21SH4: Use qemu_irq in timer emulation.aurel321-6/+6
2008-09-02sh4: CPU versioning.aurel321-26/+17
2008-08-22[sh4] MMU bug fixaurel321-0/+4
2008-08-22[sh4] memory mapped TLB entriesaurel321-0/+110
2008-07-16Fix a bunch of type mismatch-related warnings (Jan Kiszka).balrog1-2/+2
2008-05-09SH4 serial controler improvementsaurel321-2/+12
2008-05-09SH4 MMU improvementsaurel321-0/+3
2007-12-12Adds interrupt support to the sh specific timer code (Magnus Damm).balrog1-3/+9
2007-12-02SH4: system emulator interrupt update, by Magnus Damm.ths1-0/+2
2007-11-17Break up vl.h.pbrook1-1/+3
2007-11-11removed invalid use of _INTC_ARRAYbellard1-2/+2
2007-10-04sh775x interrupt controller by Magnus Damm.balrog1-45/+178
2007-09-29Add FRQCR read support, by Magnus Damm.ths1-0/+2
2007-09-29Add INTC controller prototype, by Magnus Damm.ths1-0/+51
2007-09-29Stand-alone SCI/SCIF emulation code, by Magnus Damm.ths1-341/+4
2007-09-29Stand-alone TMU emulation code, by Magnus Damm.ths1-96/+6
2007-09-16find -type f | xargs sed -i 's/[\t ]$//g' # on most filesths1-2/+2
2007-01-27Rearrange char event handlers to fix CHR_EVENT_RESET.pbrook1-6/+4
2006-06-25C99 64 bit printfbellard1-1/+1
2006-04-27SHIX board emulation (Samuel Tardieu)bellard1-0/+836