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2011-03-07trace: Trace posix-aio-compat.c completion and cancellationStefan Hajnoczi2-0/+7
This patch adds paio_complete() and paio_cancel() trace events to complement the paio_submit() event. Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-03-07trace: Trace bdrv_aio_flush()Stefan Hajnoczi2-0/+3
Add a trace event for bdrv_aio_flush() to complement the existing bdrv_aio_readv() and bdrv_aio_writev() events. Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-03-07simpletrace: Thread-safe tracingStefan Hajnoczi5-122/+219
Trace events outside the global mutex cannot be used with the simple trace backend since it is not thread-safe. There is no check to prevent them being enabled so people sometimes learn this the hard way. This patch restructures the simple trace backend with a ring buffer suitable for multiple concurrent writers. A writeout thread empties the trace buffer when threshold fill levels are reached. Should the writeout thread be unable to keep up with trace generation, records will simply be dropped. Each time events are dropped a special record is written to the trace file indicating how many events were dropped. The event ID is 0xfffffffffffffffe and its signature is dropped(uint32_t count). Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-03-07MAINTAINERS: add LatticeMico32 maintainerMichael Walle1-0/+12
Add me as the lm32-target and machines maintainer. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07Add lm32 target to configureMichael Walle1-3/+7
Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: opcode testsuiteMichael Walle67-0/+3048
This patch creates tests/lm32 directory and adds tests for every LatticeMico32 opcode. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: todo and documentationMichael Walle2-0/+49
This patch adds general target documentation and a todo list. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: EVR32 and uclinux BSPMichael Walle3-0/+312
This patch adds support for the following two BSPs: - LM32 EVR32 BSP (as used by RTEMS) - uclinux BSP by Theobroma Systems Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: support for creating device treeMichael Walle1-0/+178
This patch adds helper functions to create a ROM, which contains a hardware description of a board. This is used in Theobromas LM32 Linux port. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: system control modelMichael Walle3-0/+165
This patch add support for a system control block. It is supposed to act as helper for the emulated program. E.g. shutting down the VM or printing test results. This model is intended for testing purposes only and doesn't fit to any real hardware. Therefore, it is not added to any board by default. Instead a user has to add it explicitly with the '-device' commandline parameter. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: uart modelMichael Walle3-0/+294
This patch add support for the LatticeMico32 UART. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: timer modelMichael Walle3-0/+229
This patch adds support for the LatticeMico32 system timer. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: pic and juart helper functionsMichael Walle1-0/+25
This patch adds init functions for the PIC and JTAG UART commonly used in the board initialization. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: juart modelMichael Walle4-0/+168
This patch adds the JTAG UART model. It is accessed through special control registers and opcodes. Therefore the translation uses callbacks to this model. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: interrupt controller modelMichael Walle4-0/+211
This patch adds the interrupt controller of the lm32. Because the PIC is accessed through special control registers and opcodes, there are callbacks from the lm32 translation code to this model. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: gdbstub supportMichael Walle1-0/+76
This patch adds lm32 support to the gdbstub. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: machine state loading/savingMichael Walle1-0/+33
This patch adds support for saving and loading the processor state. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: translation code helperMichael Walle2-0/+120
This patch adds translation helper functions. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: translation routinesMichael Walle3-0/+1654
This patch adds the main translation routine. All opcodes of the LatticeMico32 processor are supported and translated to TCG ops. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07LatticeMico32 target supportMichael Walle8-7/+319
This patch adds support for the LatticeMico32 softcore processor by Lattice Semiconductor. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07target-arm: Implement a minimal set of cp14 debug registersPeter Maydell1-0/+28
Newer ARM kernels try to probe for whether the CPU has hardware breakpoint support. For this to work QEMU has to implement a minimal set of the cp14 debug registers. The architecture requires v7 cores to implement debug and so there is no defined way to report its absence; however in practice returning a zero DBGDIDR (ie with a reserved value for "debug architecture version") should cause well-written hw debug users to do the right thing. We also implement DBGDRAR and DBGDSAR as RAZ, indicating no memory mapped debug components. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-07target-arm: Use TCG temporary leak debugging facilitiesPeter Maydell1-0/+7
Use the new TCG temporary leak debugging facilities to check that each ARM instruction does not leak temporaries. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-07target-arm: Remove ad-hoc leak checking codePeter Maydell1-360/+338
This commit removes the ad-hoc resource leak checking code from target-arm. This includes replacing all uses of new_tmp() with tcg_temp_new_i32() and all uses of dead_tmp() with tcg_temp_free_i32(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-07tcg: Add support for debugging leakage of temporariesPeter Maydell2-0/+49
Add support (if CONFIG_DEBUG_TCG is defined) for debugging leakage of temporary variables. Generally any temporaries created by a target while it is translating an instruction should be freed by the end of that instruction; otherwise carefully crafted guest code could cause TCG to run out of temporaries and assert. By calling tcg_check_temp_count() after each instruction we can check that we are not leaking temporaries in this way. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06target-arm: Integrate secondary CPU reset in arm_bootAdam Lackorzynski2-22/+15
Integrate secondary CPU reset into arm_boot, removing it from realview.c. On non-Linux systems secondary CPUs start with the same entry as the boot CPU. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06target-arm: Implement cp15 VA->PA translationAdam Lackorzynski3-3/+50
Implement VA->PA translations by cp15-c7 that went through unchanged previously. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06target-arm: Fix soft interrupt in GIC distributorAdam Lackorzynski1-2/+2
Fix selection of target list filter mode. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06target-arm: Set carry flag correctly for Thumb2 ORNSPeter Maydell1-2/+1
The code for Thumb2 ORNS (or negated and set flags) was trashing a TCG input register which was needed later for use in calculating flags, with the effect that the carry flag was always set with the wrong sense. Fix this by using the TCG orc op instead of separate not and or ops. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06ioport: Improve error outputAndreas Färber1-2/+4
When failing due to conflicting I/O port registrations, include the offending I/O port address in the message. Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06tracetool: Add optional argument to specify dtrace probe namesJes Sorensen1-6/+13
Optional feature allowing a user to generate the probe list to match the name of the binary, in case they wish to install qemu under a different name than qemu-{system,user},<arch> Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Acked-by: Stefan Hajnoczi <stefaha@linux.vnet.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06target-arm: Handle VMOV between two core and VFP single regsPeter Maydell1-5/+5
Fix two bugs in the translation of the instructions VMOV sa,sb,rx,ry and VMOV rx,ry,sa,sb (which copy between a pair of ARM core registers and a pair of VFP single precision registers): * An incorrect condition meant these instruction patterns were being treated as load/store multiple, which resulted in the generation of bad code and a runtime segfault * The order of the core register pair was reversed so the values would go to the wrong registers Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06w32: Add support for cursesStefan Weil1-1/+5
MinGW optionally includes pdcurses, so add support for it. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06target-arm: Don't decode old cp15 WFI instructions on v7 coresPeter Maydell1-5/+30
In v7 of the ARM architecture, WFI (wait for interrupt) is a first-class instruction, but in previous versions this functionality was provided via a cp15 coprocessor register. Add correct feature checks to the decoding of the cp15 WFI instructions so that they behave correctly for newer cores. In particular, the old 0,c7,c8,2 encoding used on ARM940 has been reused for VA-to-PA translation in v6 and v7. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06net: Add the missing option declaration of "vhostforce"Jason Wang1-1/+5
Signed-off-by: Jason Wang <jasowang@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06gt64xxx: remove savevm supportJuan Quintela1-21/+0
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06vmstate: remove uninorth savevm codeJuan Quintela1-21/+0
It was migrating the wrong structures, no way it would work Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06vmstate: remove grackle_pci savevm codeJuan Quintela1-19/+0
It was migrating the wrong structures, no way it would work Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06net: remove parse_host_src_port() functionJuan Quintela2-44/+0
It was deprecated, and it has no users. Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06hw/sd.c: fix sd_set_cb() crash when bdrv == NULLAurelien Jarno1-2/+2
sd_set_cb() calls bdrv_is_read_only() and bdrv_is_inserted() even if no block driver is associated with the card reader. This patch fixes the issues by not setting the irq in this case, this fixes ARM versatile crash. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06net: Use iov helper functionsBenjamin Poirier1-22/+6
Signed-off-by: Benjamin Poirier <benjamin.poirier@gmail.com> Reviewed-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com> Acked-by: Jason Wang <jasowang@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06docs: Update stderr and simple backend, add systemtap backendStefan Hajnoczi1-4/+26
The following additions to the tracing documentation are included: 1. Move "stderr" backend documentation to top-level and out of "simple" backend. Include hints on when this backend is useful. 2. Document the "simple" backend thread-safety limitation. 3. Document the "dtrace" backend for SystemTap. Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06simpletrace: Make simpletrace.py a Python moduleStefan Hajnoczi1-33/+90
The simpletrace.py script pretty-prints a binary trace file. Most of the code can be reused by trace file analysis scripts, so turn it into a module. Here is an example script that uses the new simpletrace module: #!/usr/bin/env python # Print virtqueue elements that were never returned to the guest. import simpletrace class VirtqueueRequestTracker(simpletrace.Analyzer): def __init__(self): self.elems = set() def virtqueue_pop(self, vq, elem, in_num, out_num): self.elems.add(elem) def virtqueue_fill(self, vq, elem, length, idx): self.elems.remove(elem) def end(self): for elem in self.elems: print hex(elem) simpletrace.run(VirtqueueRequestTracker()) The simpletrace API is based around the Analyzer class. Users implement an analyzer subclass and add methods for trace events they want to process. A catchall() method is invoked for trace events which do not have dedicated methods. Finally, there are also begin() and end() methods like in sed that can be used to perform setup or print statistics at the end. A binary trace file is processed either with: simpletrace.run(analyzer) # uses command-line args or with: simpletrace.process('path/to/trace-events', 'path/to/trace-file', analyzer) Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06linux-user: Fix large seeks by 32 bit guest on 64 bit hostPeter Maydell1-6/+10
When emulating a 32 bit Linux user-mode program on a 64 bit target we implement the llseek syscall in terms of lseek. Correct a bug which meant we were silently casting the result of host lseek() to a 32 bit integer as it passed through get_errno() and thus throwing away the top half. We also don't try to store the result back to userspace unless the seek succeeded; this matches the kernel behaviour. Thanks to Eoghan Sherry for identifying the problem and suggesting a solution. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06hw/realview: Wire up the MMC card statusPeter Maydell1-3/+26
Instantiate the three PL061 GPIO modules the realview boards have. Connect the MMC card status outputs of the PL181 MMC controller to both the system registers and the GPIO module which handles internal devices. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06hw/irq: Add qemu_irq_split() so one GPIO output can feed two inputsPeter Maydell2-0/+18
Add a qemu_irq_split() function which allows a board to wire a single GPIO output up to two GPIO inputs. This is needed for realview boards, where the MMC card status is visible both in a system register and via a PL061 GPIO module. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06hw/pl061.c: Implement ARM PL061 as well as Luminary onePeter Maydell2-5/+20
ARM's PL061 has a different set of ID registers to the one in the Luminary Stellaris; implement this so that the Linux driver can identify the Realview PBX PL061 correctly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06hw/arm_sysctl.c: Wire MCI register MMC card status bits to GPIO inputsPeter Maydell2-1/+50
Implement some GPIO inputs which a board can connect up to set the MMC card status bits in the MCI register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06hw/pl181: Implement GPIO output pins for card statusPeter Maydell1-0/+6
Add two GPIO output pins to the PL181 model to indicate the card present and readonly status information. On ARM boards these usually are reflected in a system register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06lsi53c895a: Update dnad when skipping MSGOUT bytesStefan Hajnoczi1-2/+9
Update not only dbc but also dnad when skipping bytes during the MSGOUT phase. Previously only dbc was updated which is probably wrong and could lead to bogus message codes being read. Tested on Linux and Windows Server 2003. Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06WIN32: Add missing include for 'struct timeval', used in vnc.hHervé Poussineau1-0/+1
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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