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-rw-r--r--CODING_STYLE12
-rw-r--r--balloon.h6
-rw-r--r--block/vvfat.c288
-rw-r--r--console.c10
-rw-r--r--console.h8
-rw-r--r--cpu-all.h22
-rw-r--r--cpu-common.h68
-rw-r--r--cpu-defs.h10
-rw-r--r--curses.c4
-rw-r--r--curses_keys.h2
-rw-r--r--darwin-user/commpage.c2
-rw-r--r--darwin-user/machload.c2
-rw-r--r--darwin-user/qemu.h2
-rw-r--r--disas.h2
-rw-r--r--dma-helpers.c8
-rw-r--r--dma.h10
-rw-r--r--dyngen-exec.h2
-rw-r--r--exec-all.h8
-rw-r--r--exec.c218
-rw-r--r--hostregs_helper.h4
-rw-r--r--hw/an5206.c4
-rw-r--r--hw/apb_pci.c26
-rw-r--r--hw/apic.c14
-rw-r--r--hw/arm-misc.h4
-rw-r--r--hw/arm_boot.c10
-rw-r--r--hw/arm_gic.c12
-rw-r--r--hw/arm_sysctl.c4
-rw-r--r--hw/arm_timer.c12
-rw-r--r--hw/armv7m.c12
-rw-r--r--hw/axis_dev88.c14
-rw-r--r--hw/boards.h2
-rw-r--r--hw/bt-hci-csr.c4
-rw-r--r--hw/bt-hci.c16
-rw-r--r--hw/bt.h78
-rw-r--r--hw/cirrus_vga.c50
-rw-r--r--hw/cs4231.c4
-rw-r--r--hw/cuda.c12
-rw-r--r--hw/dma.c4
-rw-r--r--hw/dp8393x.c18
-rw-r--r--hw/ds1225y.c32
-rw-r--r--hw/dummy_m68k.c4
-rw-r--r--hw/e1000.c18
-rw-r--r--hw/eccmemctl.c8
-rw-r--r--hw/eepro100.c54
-rw-r--r--hw/eeprom93xx.c20
-rw-r--r--hw/eeprom93xx.h12
-rw-r--r--hw/elf_ops.h2
-rw-r--r--hw/escc.c16
-rw-r--r--hw/escc.h4
-rw-r--r--hw/esp.c6
-rw-r--r--hw/etraxfs.c8
-rw-r--r--hw/etraxfs.h2
-rw-r--r--hw/etraxfs_dma.c22
-rw-r--r--hw/etraxfs_dma.h2
-rw-r--r--hw/etraxfs_eth.c6
-rw-r--r--hw/etraxfs_pic.c4
-rw-r--r--hw/etraxfs_ser.c4
-rw-r--r--hw/etraxfs_timer.c4
-rw-r--r--hw/fdc.c346
-rw-r--r--hw/fdc.h12
-rw-r--r--hw/flash.h8
-rw-r--r--hw/framebuffer.c12
-rw-r--r--hw/framebuffer.h2
-rw-r--r--hw/fw_cfg.c8
-rw-r--r--hw/fw_cfg.h2
-rw-r--r--hw/g364fb.c34
-rw-r--r--hw/grackle_pci.c6
-rw-r--r--hw/gt64xxx.c22
-rw-r--r--hw/gumstix.c4
-rw-r--r--hw/heathrow_pic.c4
-rw-r--r--hw/hpet.c12
-rw-r--r--hw/ide.h2
-rw-r--r--hw/ide/macio.c12
-rw-r--r--hw/ide/mmio.c10
-rw-r--r--hw/integratorcp.c16
-rw-r--r--hw/ioapic.c4
-rw-r--r--hw/iommu.c26
-rw-r--r--hw/isa.h4
-rw-r--r--hw/isa_mmio.c14
-rw-r--r--hw/jazz_led.c20
-rw-r--r--hw/loader.c30
-rw-r--r--hw/loader.h18
-rw-r--r--hw/lsi53c895a.c26
-rw-r--r--hw/m48t59.c72
-rw-r--r--hw/mac_dbdma.c4
-rw-r--r--hw/mac_dbdma.h2
-rw-r--r--hw/mac_nvram.c10
-rw-r--r--hw/macio.c14
-rw-r--r--hw/mainstone.c6
-rw-r--r--hw/marvell_88w8618_audio.c4
-rw-r--r--hw/mc146818rtc.c14
-rw-r--r--hw/mcf.h10
-rw-r--r--hw/mcf5206.c20
-rw-r--r--hw/mcf5208.c12
-rw-r--r--hw/mcf_fec.c6
-rw-r--r--hw/mcf_intc.c6
-rw-r--r--hw/mcf_uart.c6
-rw-r--r--hw/mips.h14
-rw-r--r--hw/mips_jazz.c16
-rw-r--r--hw/mips_malta.c24
-rw-r--r--hw/mips_mipssim.c8
-rw-r--r--hw/mips_r4k.c12
-rw-r--r--hw/mpcore.c6
-rw-r--r--hw/msix.c10
-rw-r--r--hw/msix.h2
-rw-r--r--hw/mst_fpga.c4
-rw-r--r--hw/musicpal.c36
-rw-r--r--hw/nseries.c8
-rw-r--r--hw/nvram.h38
-rw-r--r--hw/omap.h96
-rw-r--r--hw/omap1.c174
-rw-r--r--hw/omap2.c110
-rw-r--r--hw/omap_dma.c34
-rw-r--r--hw/omap_dss.c36
-rw-r--r--hw/omap_i2c.c8
-rw-r--r--hw/omap_lcdc.c14
-rw-r--r--hw/omap_mmc.c14
-rw-r--r--hw/omap_sx1.c16
-rw-r--r--hw/onenand.c10
-rw-r--r--hw/openpic.c192
-rw-r--r--hw/openpic.h2
-rw-r--r--hw/palm.c12
-rw-r--r--hw/parallel.c14
-rw-r--r--hw/pc.c30
-rw-r--r--hw/pc.h14
-rw-r--r--hw/pci.c4
-rw-r--r--hw/pci.h8
-rw-r--r--hw/pci_host.h24
-rw-r--r--hw/pckbd.c10
-rw-r--r--hw/pcnet.c58
-rw-r--r--hw/petalogix_s3adsp1800_mmu.c16
-rw-r--r--hw/pflash_cfi01.c54
-rw-r--r--hw/pflash_cfi02.c42
-rw-r--r--hw/piix_pci.c4
-rw-r--r--hw/pl011.c4
-rw-r--r--hw/pl022.c4
-rw-r--r--hw/pl031.c4
-rw-r--r--hw/pl050.c4
-rw-r--r--hw/pl061.c4
-rw-r--r--hw/pl080.c4
-rw-r--r--hw/pl110.c4
-rw-r--r--hw/pl181.c4
-rw-r--r--hw/pl190.c4
-rw-r--r--hw/ppc.c132
-rw-r--r--hw/ppc.h6
-rw-r--r--hw/ppc405.h20
-rw-r--r--hw/ppc405_boards.c52
-rw-r--r--hw/ppc405_uc.c284
-rw-r--r--hw/ppc440.c6
-rw-r--r--hw/ppc440.h2
-rw-r--r--hw/ppc440_bamboo.c12
-rw-r--r--hw/ppc4xx.h20
-rw-r--r--hw/ppc4xx_devs.c70
-rw-r--r--hw/ppc4xx_pci.c18
-rw-r--r--hw/ppc_mac.h4
-rw-r--r--hw/ppc_newworld.c8
-rw-r--r--hw/ppc_oldworld.c4
-rw-r--r--hw/ppc_prep.c78
-rw-r--r--hw/ppce500.h2
-rw-r--r--hw/ppce500_mpc8544ds.c12
-rw-r--r--hw/ppce500_pci.c12
-rw-r--r--hw/prep_pci.c16
-rw-r--r--hw/pxa.h32
-rw-r--r--hw/pxa2xx.c44
-rw-r--r--hw/pxa2xx_dma.c22
-rw-r--r--hw/pxa2xx_gpio.c6
-rw-r--r--hw/pxa2xx_keypad.c6
-rw-r--r--hw/pxa2xx_lcd.c22
-rw-r--r--hw/pxa2xx_mmci.c18
-rw-r--r--hw/pxa2xx_pcmcia.c14
-rw-r--r--hw/pxa2xx_pic.c10
-rw-r--r--hw/pxa2xx_timer.c10
-rw-r--r--hw/qdev-addr.c8
-rw-r--r--hw/qdev-addr.h4
-rw-r--r--hw/r2d.c24
-rw-r--r--hw/rc4030.c34
-rw-r--r--hw/realview.c4
-rw-r--r--hw/realview_gic.c6
-rw-r--r--hw/rtl8139.c32
-rw-r--r--hw/sbi.c4
-rw-r--r--hw/scsi.h2
-rw-r--r--hw/sd.c12
-rw-r--r--hw/sd.h2
-rw-r--r--hw/serial.c14
-rw-r--r--hw/sh.h4
-rw-r--r--hw/sh7750.c24
-rw-r--r--hw/sh7750_regnames.c4
-rw-r--r--hw/sh_intc.c4
-rw-r--r--hw/sh_pci.c34
-rw-r--r--hw/sh_serial.c6
-rw-r--r--hw/sh_timer.c10
-rw-r--r--hw/sharpsl.h4
-rw-r--r--hw/shix.c2
-rw-r--r--hw/slavio_intctl.c8
-rw-r--r--hw/slavio_misc.c32
-rw-r--r--hw/slavio_timer.c4
-rw-r--r--hw/sm501.c24
-rw-r--r--hw/smc91c111.c12
-rw-r--r--hw/soc_dma.c8
-rw-r--r--hw/soc_dma.h12
-rw-r--r--hw/sparc32_dma.c8
-rw-r--r--hw/sparc32_dma.h4
-rw-r--r--hw/spitz.c16
-rw-r--r--hw/stellaris.c20
-rw-r--r--hw/stellaris_enet.c4
-rw-r--r--hw/sun4c_intctl.c4
-rw-r--r--hw/sun4m.c118
-rw-r--r--hw/sun4m.h6
-rw-r--r--hw/sun4u.c24
-rw-r--r--hw/syborg.c4
-rw-r--r--hw/syborg_fb.c4
-rw-r--r--hw/syborg_interrupt.c4
-rw-r--r--hw/syborg_keyboard.c4
-rw-r--r--hw/syborg_pointer.c4
-rw-r--r--hw/syborg_rtc.c4
-rw-r--r--hw/syborg_serial.c4
-rw-r--r--hw/syborg_timer.c4
-rw-r--r--hw/syborg_virtio.c12
-rw-r--r--hw/sysbus.c12
-rw-r--r--hw/sysbus.h16
-rw-r--r--hw/tc58128.c4
-rw-r--r--hw/tc6393xb.c26
-rw-r--r--hw/tcx.c28
-rw-r--r--hw/tosa.c2
-rw-r--r--hw/tusb6010.c12
-rw-r--r--hw/unin_pci.c10
-rw-r--r--hw/usb-musb.c12
-rw-r--r--hw/usb-ohci.c8
-rw-r--r--hw/versatile_pci.c16
-rw-r--r--hw/versatilepb.c12
-rw-r--r--hw/vga-isa-mm.c20
-rw-r--r--hw/vga.c18
-rw-r--r--hw/vga_int.h6
-rw-r--r--hw/virtio-balloon.c8
-rw-r--r--hw/virtio-pci.c4
-rw-r--r--hw/virtio.c56
-rw-r--r--hw/virtio.h8
-rw-r--r--hw/vmware_vga.c20
-rw-r--r--hw/wdt_i6300esb.c12
-rw-r--r--hw/xen_machine_pv.c2
-rw-r--r--hw/xilinx.h6
-rw-r--r--hw/xilinx_ethlite.c4
-rw-r--r--hw/xilinx_intc.c4
-rw-r--r--hw/xilinx_timer.c6
-rw-r--r--hw/xilinx_uartlite.c4
-rw-r--r--hw/zaurus.c8
-rw-r--r--ioport-user.c12
-rw-r--r--ioport.c18
-rw-r--r--ioport.h20
-rw-r--r--keymaps.c18
-rw-r--r--keymaps.h6
-rw-r--r--kvm-all.c46
-rw-r--r--kvm.h18
-rw-r--r--linux-user/alpha/target_signal.h2
-rw-r--r--linux-user/alpha/termbits.h22
-rw-r--r--linux-user/arm/target_signal.h2
-rw-r--r--linux-user/cris/target_signal.h2
-rw-r--r--linux-user/elfload.c64
-rw-r--r--linux-user/i386/target_signal.h2
-rw-r--r--linux-user/m68k/target_signal.h2
-rw-r--r--linux-user/main.c24
-rw-r--r--linux-user/microblaze/target_signal.h2
-rw-r--r--linux-user/mips/target_signal.h2
-rw-r--r--linux-user/mips64/target_signal.h2
-rw-r--r--linux-user/mipsn32/target_signal.h2
-rw-r--r--linux-user/ppc/target_signal.h2
-rw-r--r--linux-user/qemu.h8
-rw-r--r--linux-user/sh4/target_signal.h2
-rw-r--r--linux-user/signal.c246
-rw-r--r--linux-user/sparc/target_signal.h2
-rw-r--r--linux-user/sparc64/target_signal.h2
-rw-r--r--linux-user/syscall.c36
-rw-r--r--linux-user/syscall_defs.h56
-rw-r--r--linux-user/x86_64/target_signal.h2
-rw-r--r--linux-user/x86_64/termbits.h18
-rw-r--r--m68k-semi.c14
-rw-r--r--monitor.c54
-rw-r--r--qemu-img.c8
-rw-r--r--qemu-lock.h24
-rw-r--r--sdl.c2
-rw-r--r--sdl_keysym.h2
-rw-r--r--softmmu_template.h12
-rw-r--r--tap-win32.c50
-rw-r--r--target-alpha/cpu.h6
-rw-r--r--target-alpha/helper.c4
-rw-r--r--target-alpha/op_helper.c2
-rw-r--r--target-arm/helper.c4
-rw-r--r--target-arm/op_helper.c2
-rw-r--r--target-cris/helper.c4
-rw-r--r--target-i386/helper.c22
-rw-r--r--target-i386/op_helper.c8
-rw-r--r--target-m68k/helper.c10
-rw-r--r--target-microblaze/cpu.h2
-rw-r--r--target-microblaze/helper.c4
-rw-r--r--target-microblaze/op_helper.c2
-rw-r--r--target-mips/cpu.h17
-rw-r--r--target-mips/helper.c6
-rw-r--r--target-mips/op_helper.c8
-rw-r--r--target-mips/translate.c4
-rw-r--r--target-mips/translate_init.c20
-rw-r--r--target-ppc/cpu.h88
-rw-r--r--target-ppc/helper.c116
-rw-r--r--target-ppc/helper.h2
-rw-r--r--target-ppc/op_helper.c166
-rw-r--r--target-ppc/translate.c18
-rw-r--r--target-ppc/translate_init.c78
-rw-r--r--target-sh4/cpu.h2
-rw-r--r--target-sh4/helper.c6
-rw-r--r--target-sparc/cpu.h2
-rw-r--r--target-sparc/helper.c36
-rw-r--r--target-sparc/op_helper.c36
-rw-r--r--targphys.h8
-rw-r--r--uboot_image.h2
-rw-r--r--vl.c28
-rw-r--r--vnc.h2
-rw-r--r--vnc_keysym.h2
316 files changed, 3334 insertions, 3327 deletions
diff --git a/CODING_STYLE b/CODING_STYLE
index 08af61ad1..a579cb1b5 100644
--- a/CODING_STYLE
+++ b/CODING_STYLE
@@ -40,10 +40,14 @@ Rationale:
3. Naming
-Variables are lower_case_with_underscores; easy to type and read.
-Structured type names are in CamelCase; harder to type but standing
-out. Scalar type names are a_lower_case_beginning_with_an a or an.
-Do not use _t suffix if you are including any headers.
+Variables are lower_case_with_underscores; easy to type and read. Structured
+type names are in CamelCase; harder to type but standing out. Scalar type
+names are lower_case_with_underscores_ending_with_a_t, like the POSIX
+uint64_t and family. Note that this last convention contradicts POSIX
+and is therefore likely to be changed.
+
+Typedefs are used to eliminate the redundant 'struct' keyword. It is the
+QEMU coding style.
4. Block structure
diff --git a/balloon.h b/balloon.h
index 1fc553505..60b4a5de7 100644
--- a/balloon.h
+++ b/balloon.h
@@ -16,12 +16,12 @@
#include "cpu-defs.h"
-typedef a_ram_addr (QEMUBalloonEvent)(void *opaque, a_ram_addr target);
+typedef ram_addr_t (QEMUBalloonEvent)(void *opaque, ram_addr_t target);
void qemu_add_balloon_handler(QEMUBalloonEvent *func, void *opaque);
-void qemu_balloon(a_ram_addr target);
+void qemu_balloon(ram_addr_t target);
-a_ram_addr qemu_balloon_status(void);
+ram_addr_t qemu_balloon_status(void);
#endif
diff --git a/block/vvfat.c b/block/vvfat.c
index 6677028ce..063f7318c 100644
--- a/block/vvfat.c
+++ b/block/vvfat.c
@@ -71,12 +71,12 @@ void nonono(const char* file, int line, const char* msg) {
#endif
/* dynamic array functions */
-typedef struct array {
+typedef struct array_t {
char* pointer;
unsigned int size,next,item_size;
-} an_array;
+} array_t;
-static inline void array_init(an_array* array,unsigned int item_size)
+static inline void array_init(array_t* array,unsigned int item_size)
{
array->pointer = NULL;
array->size=0;
@@ -84,7 +84,7 @@ static inline void array_init(an_array* array,unsigned int item_size)
array->item_size=item_size;
}
-static inline void array_free(an_array* array)
+static inline void array_free(array_t* array)
{
if(array->pointer)
free(array->pointer);
@@ -92,12 +92,12 @@ static inline void array_free(an_array* array)
}
/* does not automatically grow */
-static inline void* array_get(an_array* array,unsigned int index) {
+static inline void* array_get(array_t* array,unsigned int index) {
assert(index < array->next);
return array->pointer + index * array->item_size;
}
-static inline int array_ensure_allocated(an_array* array, int index)
+static inline int array_ensure_allocated(array_t* array, int index)
{
if((index + 1) * array->item_size > array->size) {
int new_size = (index + 32) * array->item_size;
@@ -111,7 +111,7 @@ static inline int array_ensure_allocated(an_array* array, int index)
return 0;
}
-static inline void* array_get_next(an_array* array) {
+static inline void* array_get_next(array_t* array) {
unsigned int next = array->next;
void* result;
@@ -124,7 +124,7 @@ static inline void* array_get_next(an_array* array) {
return result;
}
-static inline void* array_insert(an_array* array,unsigned int index,unsigned int count) {
+static inline void* array_insert(array_t* array,unsigned int index,unsigned int count) {
if((array->next+count)*array->item_size>array->size) {
int increment=count*array->item_size;
array->pointer=qemu_realloc(array->pointer,array->size+increment);
@@ -141,7 +141,7 @@ static inline void* array_insert(an_array* array,unsigned int index,unsigned int
/* this performs a "roll", so that the element which was at index_from becomes
* index_to, but the order of all other elements is preserved. */
-static inline int array_roll(an_array* array,int index_to,int index_from,int count)
+static inline int array_roll(array_t* array,int index_to,int index_from,int count)
{
char* buf;
char* from;
@@ -174,7 +174,7 @@ static inline int array_roll(an_array* array,int index_to,int index_from,int cou
return 0;
}
-static inline int array_remove_slice(an_array* array,int index, int count)
+static inline int array_remove_slice(array_t* array,int index, int count)
{
assert(index >=0);
assert(count > 0);
@@ -185,13 +185,13 @@ static inline int array_remove_slice(an_array* array,int index, int count)
return 0;
}
-static int array_remove(an_array* array,int index)
+static int array_remove(array_t* array,int index)
{
return array_remove_slice(array, index, 1);
}
/* return the index for a given member */
-static int array_index(an_array* array, void* pointer)
+static int array_index(array_t* array, void* pointer)
{
size_t offset = (char*)pointer - array->pointer;
assert((offset % array->item_size) == 0);
@@ -202,7 +202,7 @@ static int array_index(an_array* array, void* pointer)
/* These structures are used to fake a disk and the VFAT filesystem.
* For this reason we need to use __attribute__((packed)). */
-typedef struct bootsector {
+typedef struct bootsector_t {
uint8_t jump[3];
uint8_t name[8];
uint16_t sector_size;
@@ -238,32 +238,32 @@ typedef struct bootsector {
uint8_t fat_type[8];
uint8_t ignored[0x1c0];
uint8_t magic[2];
-} __attribute__((packed)) a_bootsector;
+} __attribute__((packed)) bootsector_t;
typedef struct {
uint8_t head;
uint8_t sector;
uint8_t cylinder;
-} a_mbr_chs;
+} mbr_chs_t;
-typedef struct partition {
+typedef struct partition_t {
uint8_t attributes; /* 0x80 = bootable */
- a_mbr_chs start_CHS;
+ mbr_chs_t start_CHS;
uint8_t fs_type; /* 0x1 = FAT12, 0x6 = FAT16, 0xe = FAT16_LBA, 0xb = FAT32, 0xc = FAT32_LBA */
- a_mbr_chs end_CHS;
+ mbr_chs_t end_CHS;
uint32_t start_sector_long;
uint32_t length_sector_long;
-} __attribute__((packed)) a_partition;
+} __attribute__((packed)) partition_t;
-typedef struct mbr {
+typedef struct mbr_t {
uint8_t ignored[0x1b8];
uint32_t nt_id;
uint8_t ignored2[2];
- a_partition partition[4];
+ partition_t partition[4];
uint8_t magic[2];
-} __attribute__((packed)) a_mbr;
+} __attribute__((packed)) mbr_t;
-typedef struct direntry {
+typedef struct direntry_t {
uint8_t name[8];
uint8_t extension[3];
uint8_t attributes;
@@ -276,11 +276,11 @@ typedef struct direntry {
uint16_t mdate;
uint16_t begin;
uint32_t size;
-} __attribute__((packed)) a_direntry;
+} __attribute__((packed)) direntry_t;
/* this structure are used to transparently access the files */
-typedef struct mapping {
+typedef struct mapping_t {
/* begin is the first cluster, end is the last+1 */
uint32_t begin,end;
/* as s->directory is growable, no pointer may be used here */
@@ -308,11 +308,11 @@ typedef struct mapping {
MODE_DIRECTORY = 4, MODE_FAKED = 8,
MODE_DELETED = 16, MODE_RENAMED = 32 } mode;
int read_only;
-} a_mapping;
+} mapping_t;
#ifdef DEBUG
-static void print_direntry(const struct a_direntry*);
-static void print_mapping(const struct a_mapping* mapping);
+static void print_direntry(const struct direntry_t*);
+static void print_mapping(const struct mapping_t* mapping);
#endif
/* here begins the real VVFAT driver */
@@ -323,7 +323,7 @@ typedef struct BDRVVVFATState {
unsigned char first_sectors[0x40*0x200];
int fat_type; /* 16 or 32 */
- an_array fat,directory,mapping;
+ array_t fat,directory,mapping;
unsigned int cluster_size;
unsigned int sectors_per_cluster;
@@ -336,7 +336,7 @@ typedef struct BDRVVVFATState {
uint32_t max_fat_value;
int current_fd;
- a_mapping* current_mapping;
+ mapping_t* current_mapping;
unsigned char* cluster; /* points to current cluster */
unsigned char* cluster_buffer; /* points to a buffer to hold temp data */
unsigned int current_cluster;
@@ -347,7 +347,7 @@ typedef struct BDRVVVFATState {
BlockDriverState* qcow;
void* fat2;
char* used_clusters;
- an_array commits;
+ array_t commits;
const char* path;
int downcase_short_names;
} BDRVVVFATState;
@@ -356,7 +356,7 @@ typedef struct BDRVVVFATState {
* if the position is outside the specified geometry, fill maximum value for CHS
* and return 1 to signal overflow.
*/
-static int sector2CHS(BlockDriverState* bs, a_mbr_chs * chs, int spos){
+static int sector2CHS(BlockDriverState* bs, mbr_chs_t * chs, int spos){
int head,sector;
sector = spos % (bs->secs); spos/= bs->secs;
head = spos % (bs->heads); spos/= bs->heads;
@@ -378,8 +378,8 @@ static int sector2CHS(BlockDriverState* bs, a_mbr_chs * chs, int spos){
static void init_mbr(BDRVVVFATState* s)
{
/* TODO: if the files mbr.img and bootsect.img exist, use them */
- a_mbr* real_mbr=(a_mbr*)s->first_sectors;
- a_partition* partition = &(real_mbr->partition[0]);
+ mbr_t* real_mbr=(mbr_t*)s->first_sectors;
+ partition_t* partition = &(real_mbr->partition[0]);
int lba;
memset(s->first_sectors,0,512);
@@ -425,12 +425,12 @@ static inline int short2long_name(char* dest,const char* src)
return len;
}
-static inline a_direntry* create_long_filename(BDRVVVFATState* s,const char* filename)
+static inline direntry_t* create_long_filename(BDRVVVFATState* s,const char* filename)
{
char buffer[258];
int length=short2long_name(buffer,filename),
number_of_entries=(length+25)/26,i;
- a_direntry* entry;
+ direntry_t* entry;
for(i=0;i<number_of_entries;i++) {
entry=array_get_next(&(s->directory));
@@ -450,53 +450,53 @@ static inline a_direntry* create_long_filename(BDRVVVFATState* s,const char* fil
return array_get(&(s->directory),s->directory.next-number_of_entries);
}
-static char is_free(const a_direntry* direntry)
+static char is_free(const direntry_t* direntry)
{
return direntry->name[0]==0xe5 || direntry->name[0]==0x00;
}
-static char is_volume_label(const a_direntry* direntry)
+static char is_volume_label(const direntry_t* direntry)
{
return direntry->attributes == 0x28;
}
-static char is_long_name(const a_direntry* direntry)
+static char is_long_name(const direntry_t* direntry)
{
return direntry->attributes == 0xf;
}
-static char is_short_name(const a_direntry* direntry)
+static char is_short_name(const direntry_t* direntry)
{
return !is_volume_label(direntry) && !is_long_name(direntry)
&& !is_free(direntry);
}
-static char is_directory(const a_direntry* direntry)
+static char is_directory(const direntry_t* direntry)
{
return direntry->attributes & 0x10 && direntry->name[0] != 0xe5;
}
-static inline char is_dot(const a_direntry* direntry)
+static inline char is_dot(const direntry_t* direntry)
{
return is_short_name(direntry) && direntry->name[0] == '.';
}
-static char is_file(const a_direntry* direntry)
+static char is_file(const direntry_t* direntry)
{
return is_short_name(direntry) && !is_directory(direntry);
}
-static inline uint32_t begin_of_direntry(const a_direntry* direntry)
+static inline uint32_t begin_of_direntry(const direntry_t* direntry)
{
return le16_to_cpu(direntry->begin)|(le16_to_cpu(direntry->begin_hi)<<16);
}
-static inline uint32_t filesize_of_direntry(const a_direntry* direntry)
+static inline uint32_t filesize_of_direntry(const direntry_t* direntry)
{
return le32_to_cpu(direntry->size);
}
-static void set_begin_of_direntry(a_direntry* direntry, uint32_t begin)
+static void set_begin_of_direntry(direntry_t* direntry, uint32_t begin)
{
direntry->begin = cpu_to_le16(begin & 0xffff);
direntry->begin_hi = cpu_to_le16((begin >> 16) & 0xffff);
@@ -504,7 +504,7 @@ static void set_begin_of_direntry(a_direntry* direntry, uint32_t begin)
/* fat functions */
-static inline uint8_t fat_chksum(const a_direntry* entry)
+static inline uint8_t fat_chksum(const direntry_t* entry)
{
uint8_t chksum=0;
int i;
@@ -603,12 +603,12 @@ static inline void init_fat(BDRVVVFATState* s)
/* TODO: in create_short_filename, 0xe5->0x05 is not yet handled! */
/* TODO: in parse_short_filename, 0x05->0xe5 is not yet handled! */
-static inline a_direntry* create_short_and_long_name(BDRVVVFATState* s,
+static inline direntry_t* create_short_and_long_name(BDRVVVFATState* s,
unsigned int directory_start, const char* filename, int is_dot)
{
int i,j,long_index=s->directory.next;
- a_direntry* entry = NULL;
- a_direntry* entry_long = NULL;
+ direntry_t* entry = NULL;
+ direntry_t* entry_long = NULL;
if(is_dot) {
entry=array_get_next(&(s->directory));
@@ -646,7 +646,7 @@ static inline a_direntry* create_short_and_long_name(BDRVVVFATState* s,
/* mangle duplicates */
while(1) {
- a_direntry* entry1=array_get(&(s->directory),directory_start);
+ direntry_t* entry1=array_get(&(s->directory),directory_start);
int j;
for(;entry1<entry;entry1++)
@@ -693,12 +693,12 @@ static inline a_direntry* create_short_and_long_name(BDRVVVFATState* s,
*/
static int read_directory(BDRVVVFATState* s, int mapping_index)
{
- a_mapping* mapping = array_get(&(s->mapping), mapping_index);
- a_direntry* direntry;
+ mapping_t* mapping = array_get(&(s->mapping), mapping_index);
+ direntry_t* direntry;
const char* dirname = mapping->path;
int first_cluster = mapping->begin;
int parent_index = mapping->info.dir.parent_mapping_index;
- a_mapping* parent_mapping = (a_mapping*)
+ mapping_t* parent_mapping = (mapping_t*)
(parent_index >= 0 ? array_get(&(s->mapping), parent_index) : NULL);
int first_cluster_of_parent = parent_mapping ? parent_mapping->begin : -1;
@@ -720,7 +720,7 @@ static int read_directory(BDRVVVFATState* s, int mapping_index)
while((entry=readdir(dir))) {
unsigned int length=strlen(dirname)+2+strlen(entry->d_name);
char* buffer;
- a_direntry* direntry;
+ direntry_t* direntry;
struct stat st;
int is_dot=!strcmp(entry->d_name,".");
int is_dotdot=!strcmp(entry->d_name,"..");
@@ -762,7 +762,7 @@ static int read_directory(BDRVVVFATState* s, int mapping_index)
/* create mapping for this file */
if(!is_dot && !is_dotdot && (S_ISDIR(st.st_mode) || st.st_size)) {
- s->current_mapping=(a_mapping*)array_get_next(&(s->mapping));
+ s->current_mapping=(mapping_t*)array_get_next(&(s->mapping));
s->current_mapping->begin=0;
s->current_mapping->end=st.st_size;
/*
@@ -788,8 +788,8 @@ static int read_directory(BDRVVVFATState* s, int mapping_index)
/* fill with zeroes up to the end of the cluster */
while(s->directory.next%(0x10*s->sectors_per_cluster)) {
- a_direntry* direntry=array_get_next(&(s->directory));
- memset(direntry,0,sizeof(a_direntry));
+ direntry_t* direntry=array_get_next(&(s->directory));
+ memset(direntry,0,sizeof(direntry_t));
}
/* TODO: if there are more entries, bootsector has to be adjusted! */
@@ -799,16 +799,16 @@ static int read_directory(BDRVVVFATState* s, int mapping_index)
int cur = s->directory.next;
array_ensure_allocated(&(s->directory), ROOT_ENTRIES - 1);
memset(array_get(&(s->directory), cur), 0,
- (ROOT_ENTRIES - cur) * sizeof(a_direntry));
+ (ROOT_ENTRIES - cur) * sizeof(direntry_t));
}
/* reget the mapping, since s->mapping was possibly realloc()ed */
- mapping = (a_mapping*)array_get(&(s->mapping), mapping_index);
+ mapping = (mapping_t*)array_get(&(s->mapping), mapping_index);
first_cluster += (s->directory.next - mapping->info.dir.first_dir_index)
* 0x20 / s->cluster_size;
mapping->end = first_cluster;
- direntry = (a_direntry*)array_get(&(s->directory), mapping->dir_index);
+ direntry = (direntry_t*)array_get(&(s->directory), mapping->dir_index);
set_begin_of_direntry(direntry, mapping->begin);
return 0;
@@ -830,19 +830,19 @@ static inline uint32_t sector_offset_in_cluster(BDRVVVFATState* s,off_t sector_n
}
#ifdef DBG
-static a_direntry* get_direntry_for_mapping(BDRVVVFATState* s,a_mapping* mapping)
+static direntry_t* get_direntry_for_mapping(BDRVVVFATState* s,mapping_t* mapping)
{
if(mapping->mode==MODE_UNDEFINED)
return 0;
- return (a_direntry*)(s->directory.pointer+sizeof(a_direntry)*mapping->dir_index);
+ return (direntry_t*)(s->directory.pointer+sizeof(direntry_t)*mapping->dir_index);
}
#endif
static int init_directories(BDRVVVFATState* s,
const char* dirname)
{
- a_bootsector* bootsector;
- a_mapping* mapping;
+ bootsector_t* bootsector;
+ mapping_t* mapping;
unsigned int i;
unsigned int cluster;
@@ -861,12 +861,12 @@ static int init_directories(BDRVVVFATState* s,
i = 1+s->sectors_per_cluster*0x200*8/s->fat_type;
s->sectors_per_fat=(s->sector_count+i)/i; /* round up */
- array_init(&(s->mapping),sizeof(a_mapping));
- array_init(&(s->directory),sizeof(a_direntry));
+ array_init(&(s->mapping),sizeof(mapping_t));
+ array_init(&(s->directory),sizeof(direntry_t));
/* add volume label */
{
- a_direntry* entry=array_get_next(&(s->directory));
+ direntry_t* entry=array_get_next(&(s->directory));
entry->attributes=0x28; /* archive | volume label */
snprintf((char*)entry->name,11,"QEMU VVFAT");
}
@@ -910,7 +910,7 @@ static int init_directories(BDRVVVFATState* s,
mapping->mode=MODE_NORMAL;
mapping->begin = cluster;
if (mapping->end > 0) {
- a_direntry* direntry = array_get(&(s->directory),
+ direntry_t* direntry = array_get(&(s->directory),
mapping->dir_index);
mapping->end = cluster + 1 + (mapping->end-1)/s->cluster_size;
@@ -954,7 +954,7 @@ static int init_directories(BDRVVVFATState* s,
s->current_mapping = NULL;
- bootsector=(a_bootsector*)(s->first_sectors+(s->first_sectors_number-1)*0x200);
+ bootsector=(bootsector_t*)(s->first_sectors+(s->first_sectors_number-1)*0x200);
bootsector->jump[0]=0xeb;
bootsector->jump[1]=0x3e;
bootsector->jump[2]=0x90;
@@ -1100,7 +1100,7 @@ static inline int find_mapping_for_cluster_aux(BDRVVVFATState* s,int cluster_num
{
int index3=index1+1;
while(1) {
- a_mapping* mapping;
+ mapping_t* mapping;
index3=(index1+index2)/2;
mapping=array_get(&(s->mapping),index3);
assert(mapping->begin < mapping->end);
@@ -1123,10 +1123,10 @@ static inline int find_mapping_for_cluster_aux(BDRVVVFATState* s,int cluster_num
}
}
-static inline a_mapping* find_mapping_for_cluster(BDRVVVFATState* s,int cluster_num)
+static inline mapping_t* find_mapping_for_cluster(BDRVVVFATState* s,int cluster_num)
{
int index=find_mapping_for_cluster_aux(s,cluster_num,0,s->mapping.next);
- a_mapping* mapping;
+ mapping_t* mapping;
if(index>=s->mapping.next)
return NULL;
mapping=array_get(&(s->mapping),index);
@@ -1140,13 +1140,13 @@ static inline a_mapping* find_mapping_for_cluster(BDRVVVFATState* s,int cluster_
* This function simply compares path == mapping->path. Since the mappings
* are sorted by cluster, this is expensive: O(n).
*/
-static inline a_mapping* find_mapping_for_path(BDRVVVFATState* s,
+static inline mapping_t* find_mapping_for_path(BDRVVVFATState* s,
const char* path)
{
int i;
for (i = 0; i < s->mapping.next; i++) {
- a_mapping* mapping = array_get(&(s->mapping), i);
+ mapping_t* mapping = array_get(&(s->mapping), i);
if (mapping->first_mapping_index < 0 &&
!strcmp(path, mapping->path))
return mapping;
@@ -1155,7 +1155,7 @@ static inline a_mapping* find_mapping_for_path(BDRVVVFATState* s,
return NULL;
}
-static int open_file(BDRVVVFATState* s,a_mapping* mapping)
+static int open_file(BDRVVVFATState* s,mapping_t* mapping)
{
if(!mapping)
return -1;
@@ -1182,7 +1182,7 @@ static inline int read_cluster(BDRVVVFATState *s,int cluster_num)
|| s->current_mapping->begin>cluster_num
|| s->current_mapping->end<=cluster_num) {
/* binary search of mappings for file */
- a_mapping* mapping=find_mapping_for_cluster(s,cluster_num);
+ mapping_t* mapping=find_mapping_for_cluster(s,cluster_num);
assert(!mapping || (cluster_num>=mapping->begin && cluster_num<mapping->end));
@@ -1238,7 +1238,7 @@ static void hexdump(const void* address, uint32_t len)
}
}
-static void print_direntry(const a_direntry* direntry)
+static void print_direntry(const direntry_t* direntry)
{
int j = 0;
char buffer[1024];
@@ -1270,7 +1270,7 @@ static void print_direntry(const a_direntry* direntry)
}
}
-static void print_mapping(const a_mapping* mapping)
+static void print_mapping(const mapping_t* mapping)
{
fprintf(stderr, "mapping (0x%x): begin, end = %d, %d, dir_index = %d, first_mapping_index = %d, name = %s, mode = 0x%x, " , (int)mapping, mapping->begin, mapping->end, mapping->dir_index, mapping->first_mapping_index, mapping->path, mapping->mode);
if (mapping->mode & MODE_DIRECTORY)
@@ -1346,7 +1346,7 @@ DLOG(fprintf(stderr, "sector %d not allocated\n", (int)sector_num));
*
*/
-typedef struct commit {
+typedef struct commit_t {
char* path;
union {
struct { uint32_t cluster; } rename;
@@ -1358,14 +1358,14 @@ typedef struct commit {
enum {
ACTION_RENAME, ACTION_WRITEOUT, ACTION_NEW_FILE, ACTION_MKDIR
} action;
-} a_commit;
+} commit_t;
static void clear_commits(BDRVVVFATState* s)
{
int i;
DLOG(fprintf(stderr, "clear_commits (%d commits)\n", s->commits.next));
for (i = 0; i < s->commits.next; i++) {
- a_commit* commit = array_get(&(s->commits), i);
+ commit_t* commit = array_get(&(s->commits), i);
assert(commit->path || commit->action == ACTION_WRITEOUT);
if (commit->action != ACTION_WRITEOUT) {
assert(commit->path);
@@ -1379,7 +1379,7 @@ DLOG(fprintf(stderr, "clear_commits (%d commits)\n", s->commits.next));
static void schedule_rename(BDRVVVFATState* s,
uint32_t cluster, char* new_path)
{
- a_commit* commit = array_get_next(&(s->commits));
+ commit_t* commit = array_get_next(&(s->commits));
commit->path = new_path;
commit->param.rename.cluster = cluster;
commit->action = ACTION_RENAME;
@@ -1388,7 +1388,7 @@ static void schedule_rename(BDRVVVFATState* s,
static void schedule_writeout(BDRVVVFATState* s,
int dir_index, uint32_t modified_offset)
{
- a_commit* commit = array_get_next(&(s->commits));
+ commit_t* commit = array_get_next(&(s->commits));
commit->path = NULL;
commit->param.writeout.dir_index = dir_index;
commit->param.writeout.modified_offset = modified_offset;
@@ -1398,7 +1398,7 @@ static void schedule_writeout(BDRVVVFATState* s,
static void schedule_new_file(BDRVVVFATState* s,
char* path, uint32_t first_cluster)
{
- a_commit* commit = array_get_next(&(s->commits));
+ commit_t* commit = array_get_next(&(s->commits));
commit->path = path;
commit->param.new_file.first_cluster = first_cluster;
commit->action = ACTION_NEW_FILE;
@@ -1406,7 +1406,7 @@ static void schedule_new_file(BDRVVVFATState* s,
static void schedule_mkdir(BDRVVVFATState* s, uint32_t cluster, char* path)
{
- a_commit* commit = array_get_next(&(s->commits));
+ commit_t* commit = array_get_next(&(s->commits));
commit->path = path;
commit->param.mkdir.cluster = cluster;
commit->action = ACTION_MKDIR;
@@ -1431,7 +1431,7 @@ static void lfn_init(long_file_name* lfn)
/* return 0 if parsed successfully, > 0 if no long name, < 0 if error */
static int parse_long_name(long_file_name* lfn,
- const a_direntry* direntry)
+ const direntry_t* direntry)
{
int i, j, offset;
const unsigned char* pointer = (const unsigned char*)direntry;
@@ -1474,7 +1474,7 @@ static int parse_long_name(long_file_name* lfn,
/* returns 0 if successful, >0 if no short_name, and <0 on error */
static int parse_short_name(BDRVVVFATState* s,
- long_file_name* lfn, a_direntry* direntry)
+ long_file_name* lfn, direntry_t* direntry)
{
int i, j;
@@ -1566,7 +1566,7 @@ static const char* get_basename(const char* path)
*/
typedef enum {
USED_DIRECTORY = 1, USED_FILE = 2, USED_ANY = 3, USED_ALLOCATED = 4
-} e_used;
+} used_t;
/*
* get_cluster_count_for_direntry() not only determines how many clusters
@@ -1579,7 +1579,7 @@ typedef enum {
* assumed to be *not* deleted (and *only* those).
*/
static uint32_t get_cluster_count_for_direntry(BDRVVVFATState* s,
- a_direntry* direntry, const char* path)
+ direntry_t* direntry, const char* path)
{
/*
* This is a little bit tricky:
@@ -1605,7 +1605,7 @@ static uint32_t get_cluster_count_for_direntry(BDRVVVFATState* s,
uint32_t cluster_num = begin_of_direntry(direntry);
uint32_t offset = 0;
int first_mapping_index = -1;
- a_mapping* mapping = NULL;
+ mapping_t* mapping = NULL;
const char* basename2 = NULL;
vvfat_close_current_file(s);
@@ -1730,8 +1730,8 @@ static int check_directory_consistency(BDRVVVFATState *s,
{
int ret = 0;
unsigned char* cluster = qemu_malloc(s->cluster_size);
- a_direntry* direntries = (a_direntry*)cluster;
- a_mapping* mapping = find_mapping_for_cluster(s, cluster_num);
+ direntry_t* direntries = (direntry_t*)cluster;
+ mapping_t* mapping = find_mapping_for_cluster(s, cluster_num);
long_file_name lfn;
int path_len = strlen(path);
@@ -1889,7 +1889,7 @@ DLOG(checkpoint());
* (check_directory_consistency() will unmark those still present). */
if (s->qcow)
for (i = 0; i < s->mapping.next; i++) {
- a_mapping* mapping = array_get(&(s->mapping), i);
+ mapping_t* mapping = array_get(&(s->mapping), i);
if (mapping->first_mapping_index < 0)
mapping->mode |= MODE_DELETED;
}
@@ -1929,7 +1929,7 @@ static inline void adjust_mapping_indices(BDRVVVFATState* s,
int i;
for (i = 0; i < s->mapping.next; i++) {
- a_mapping* mapping = array_get(&(s->mapping), i);
+ mapping_t* mapping = array_get(&(s->mapping), i);
#define ADJUST_MAPPING_INDEX(name) \
if (mapping->name >= offset) \
@@ -1942,7 +1942,7 @@ static inline void adjust_mapping_indices(BDRVVVFATState* s,
}
/* insert or update mapping */
-static a_mapping* insert_mapping(BDRVVVFATState* s,
+static mapping_t* insert_mapping(BDRVVVFATState* s,
uint32_t begin, uint32_t end)
{
/*
@@ -1953,8 +1953,8 @@ static a_mapping* insert_mapping(BDRVVVFATState* s,
* - replace name
*/
int index = find_mapping_for_cluster_aux(s, begin, 0, s->mapping.next);
- a_mapping* mapping = NULL;
- a_mapping* first_mapping = array_get(&(s->mapping), 0);
+ mapping_t* mapping = NULL;
+ mapping_t* first_mapping = array_get(&(s->mapping), 0);
if (index < s->mapping.next && (mapping = array_get(&(s->mapping), index))
&& mapping->begin < begin) {
@@ -1971,12 +1971,12 @@ static a_mapping* insert_mapping(BDRVVVFATState* s,
mapping->begin = begin;
mapping->end = end;
-DLOG(a_mapping* next_mapping;
+DLOG(mapping_t* next_mapping;
assert(index + 1 >= s->mapping.next ||
((next_mapping = array_get(&(s->mapping), index + 1)) &&
next_mapping->begin >= end)));
- if (s->current_mapping && first_mapping != (a_mapping*)s->mapping.pointer)
+ if (s->current_mapping && first_mapping != (mapping_t*)s->mapping.pointer)
s->current_mapping = array_get(&(s->mapping),
s->current_mapping - first_mapping);
@@ -1985,8 +1985,8 @@ assert(index + 1 >= s->mapping.next ||
static int remove_mapping(BDRVVVFATState* s, int mapping_index)
{
- a_mapping* mapping = array_get(&(s->mapping), mapping_index);
- a_mapping* first_mapping = array_get(&(s->mapping), 0);
+ mapping_t* mapping = array_get(&(s->mapping), mapping_index);
+ mapping_t* first_mapping = array_get(&(s->mapping), 0);
/* free mapping */
if (mapping->first_mapping_index < 0)
@@ -1998,7 +1998,7 @@ static int remove_mapping(BDRVVVFATState* s, int mapping_index)
/* adjust all references to mappings */
adjust_mapping_indices(s, mapping_index, -1);
- if (s->current_mapping && first_mapping != (a_mapping*)s->mapping.pointer)
+ if (s->current_mapping && first_mapping != (mapping_t*)s->mapping.pointer)
s->current_mapping = array_get(&(s->mapping),
s->current_mapping - first_mapping);
@@ -2009,7 +2009,7 @@ static void adjust_dirindices(BDRVVVFATState* s, int offset, int adjust)
{
int i;
for (i = 0; i < s->mapping.next; i++) {
- a_mapping* mapping = array_get(&(s->mapping), i);
+ mapping_t* mapping = array_get(&(s->mapping), i);
if (mapping->dir_index >= offset)
mapping->dir_index += adjust;
if ((mapping->mode & MODE_DIRECTORY) &&
@@ -2018,14 +2018,14 @@ static void adjust_dirindices(BDRVVVFATState* s, int offset, int adjust)
}
}
-static a_direntry* insert_direntries(BDRVVVFATState* s,
+static direntry_t* insert_direntries(BDRVVVFATState* s,
int dir_index, int count)
{
/*
* make room in s->directory,
* adjust_dirindices
*/
- a_direntry* result = array_insert(&(s->directory), dir_index, count);
+ direntry_t* result = array_insert(&(s->directory), dir_index, count);
if (result == NULL)
return NULL;
adjust_dirindices(s, dir_index, count);
@@ -2050,8 +2050,8 @@ static int remove_direntries(BDRVVVFATState* s, int dir_index, int count)
static int commit_mappings(BDRVVVFATState* s,
uint32_t first_cluster, int dir_index)
{
- a_mapping* mapping = find_mapping_for_cluster(s, first_cluster);
- a_direntry* direntry = array_get(&(s->directory), dir_index);
+ mapping_t* mapping = find_mapping_for_cluster(s, first_cluster);
+ direntry_t* direntry = array_get(&(s->directory), dir_index);
uint32_t cluster = first_cluster;
vvfat_close_current_file(s);
@@ -2083,7 +2083,7 @@ static int commit_mappings(BDRVVVFATState* s,
if (!fat_eof(s, c1)) {
int i = find_mapping_for_cluster_aux(s, c1, 0, s->mapping.next);
- a_mapping* next_mapping = i >= s->mapping.next ? NULL :
+ mapping_t* next_mapping = i >= s->mapping.next ? NULL :
array_get(&(s->mapping), i);
if (next_mapping == NULL || next_mapping->begin > c1) {
@@ -2127,9 +2127,9 @@ static int commit_mappings(BDRVVVFATState* s,
static int commit_direntries(BDRVVVFATState* s,
int dir_index, int parent_mapping_index)
{
- a_direntry* direntry = array_get(&(s->directory), dir_index);
+ direntry_t* direntry = array_get(&(s->directory), dir_index);
uint32_t first_cluster = dir_index == 0 ? 0 : begin_of_direntry(direntry);
- a_mapping* mapping = find_mapping_for_cluster(s, first_cluster);
+ mapping_t* mapping = find_mapping_for_cluster(s, first_cluster);
int factor = 0x10 * s->sectors_per_cluster;
int old_cluster_count, new_cluster_count;
@@ -2207,10 +2207,10 @@ DLOG(fprintf(stderr, "commit_direntries for %s, parent_mapping_index %d\n", mapp
static int commit_one_file(BDRVVVFATState* s,
int dir_index, uint32_t offset)
{
- a_direntry* direntry = array_get(&(s->directory), dir_index);
+ direntry_t* direntry = array_get(&(s->directory), dir_index);
uint32_t c = begin_of_direntry(direntry);
uint32_t first_cluster = c;
- a_mapping* mapping = find_mapping_for_cluster(s, c);
+ mapping_t* mapping = find_mapping_for_cluster(s, c);
uint32_t size = filesize_of_direntry(direntry);
char* cluster = qemu_malloc(s->cluster_size);
uint32_t i;
@@ -2268,14 +2268,14 @@ static void check1(BDRVVVFATState* s)
{
int i;
for (i = 0; i < s->mapping.next; i++) {
- a_mapping* mapping = array_get(&(s->mapping), i);
+ mapping_t* mapping = array_get(&(s->mapping), i);
if (mapping->mode & MODE_DELETED) {
fprintf(stderr, "deleted\n");
continue;
}
assert(mapping->dir_index >= 0);
assert(mapping->dir_index < s->directory.next);
- a_direntry* direntry = array_get(&(s->directory), mapping->dir_index);
+ direntry_t* direntry = array_get(&(s->directory), mapping->dir_index);
assert(mapping->begin == begin_of_direntry(direntry) || mapping->first_mapping_index >= 0);
if (mapping->mode & MODE_DIRECTORY) {
assert(mapping->info.dir.first_dir_index + 0x10 * s->sectors_per_cluster * (mapping->end - mapping->begin) <= s->directory.next);
@@ -2291,10 +2291,10 @@ static void check2(BDRVVVFATState* s)
int first_mapping = -1;
for (i = 0; i < s->directory.next; i++) {
- a_direntry* direntry = array_get(&(s->directory), i);
+ direntry_t* direntry = array_get(&(s->directory), i);
if (is_short_name(direntry) && begin_of_direntry(direntry)) {
- a_mapping* mapping = find_mapping_for_cluster(s, begin_of_direntry(direntry));
+ mapping_t* mapping = find_mapping_for_cluster(s, begin_of_direntry(direntry));
assert(mapping);
assert(mapping->dir_index == i || is_dot(direntry));
assert(mapping->begin == begin_of_direntry(direntry) || is_dot(direntry));
@@ -2305,7 +2305,7 @@ static void check2(BDRVVVFATState* s)
int j, count = 0;
for (j = 0; j < s->mapping.next; j++) {
- a_mapping* mapping = array_get(&(s->mapping), j);
+ mapping_t* mapping = array_get(&(s->mapping), j);
if (mapping->mode & MODE_DELETED)
continue;
if (mapping->mode & MODE_DIRECTORY) {
@@ -2318,7 +2318,7 @@ static void check2(BDRVVVFATState* s)
if (mapping->info.dir.parent_mapping_index < 0)
assert(j == 0);
else {
- a_mapping* parent = array_get(&(s->mapping), mapping->info.dir.parent_mapping_index);
+ mapping_t* parent = array_get(&(s->mapping), mapping->info.dir.parent_mapping_index);
assert(parent->mode & MODE_DIRECTORY);
assert(parent->info.dir.first_dir_index < mapping->info.dir.first_dir_index);
}
@@ -2339,15 +2339,15 @@ static int handle_renames_and_mkdirs(BDRVVVFATState* s)
#ifdef DEBUG
fprintf(stderr, "handle_renames\n");
for (i = 0; i < s->commits.next; i++) {
- a_commit* commit = array_get(&(s->commits), i);
+ commit_t* commit = array_get(&(s->commits), i);
fprintf(stderr, "%d, %s (%d, %d)\n", i, commit->path ? commit->path : "(null)", commit->param.rename.cluster, commit->action);
}
#endif
for (i = 0; i < s->commits.next;) {
- a_commit* commit = array_get(&(s->commits), i);
+ commit_t* commit = array_get(&(s->commits), i);
if (commit->action == ACTION_RENAME) {
- a_mapping* mapping = find_mapping_for_cluster(s,
+ mapping_t* mapping = find_mapping_for_cluster(s,
commit->param.rename.cluster);
char* old_path = mapping->path;
@@ -2360,7 +2360,7 @@ static int handle_renames_and_mkdirs(BDRVVVFATState* s)
int l1 = strlen(mapping->path);
int l2 = strlen(old_path);
int diff = l1 - l2;
- a_direntry* direntry = array_get(&(s->directory),
+ direntry_t* direntry = array_get(&(s->directory),
mapping->info.dir.first_dir_index);
uint32_t c = mapping->begin;
int i = 0;
@@ -2368,10 +2368,10 @@ static int handle_renames_and_mkdirs(BDRVVVFATState* s)
/* recurse */
while (!fat_eof(s, c)) {
do {
- a_direntry* d = direntry + i;
+ direntry_t* d = direntry + i;
if (is_file(d) || (is_directory(d) && !is_dot(d))) {
- a_mapping* m = find_mapping_for_cluster(s,
+ mapping_t* m = find_mapping_for_cluster(s,
begin_of_direntry(d));
int l = strlen(m->path);
char* new_path = qemu_malloc(l + diff + 1);
@@ -2394,7 +2394,7 @@ static int handle_renames_and_mkdirs(BDRVVVFATState* s)
array_remove(&(s->commits), i);
continue;
} else if (commit->action == ACTION_MKDIR) {
- a_mapping* mapping;
+ mapping_t* mapping;
int j, parent_path_len;
#ifdef __MINGW32__
@@ -2422,7 +2422,7 @@ static int handle_renames_and_mkdirs(BDRVVVFATState* s)
parent_path_len = strlen(commit->path)
- strlen(get_basename(commit->path)) - 1;
for (j = 0; j < s->mapping.next; j++) {
- a_mapping* m = array_get(&(s->mapping), j);
+ mapping_t* m = array_get(&(s->mapping), j);
if (m->first_mapping_index < 0 && m != mapping &&
!strncmp(m->path, mapping->path, parent_path_len) &&
strlen(m->path) == parent_path_len)
@@ -2450,17 +2450,17 @@ static int handle_commits(BDRVVVFATState* s)
vvfat_close_current_file(s);
for (i = 0; !fail && i < s->commits.next; i++) {
- a_commit* commit = array_get(&(s->commits), i);
+ commit_t* commit = array_get(&(s->commits), i);
switch(commit->action) {
case ACTION_RENAME: case ACTION_MKDIR:
assert(0);
fail = -2;
break;
case ACTION_WRITEOUT: {
- a_direntry* entry = array_get(&(s->directory),
+ direntry_t* entry = array_get(&(s->directory),
commit->param.writeout.dir_index);
uint32_t begin = begin_of_direntry(entry);
- a_mapping* mapping = find_mapping_for_cluster(s, begin);
+ mapping_t* mapping = find_mapping_for_cluster(s, begin);
assert(mapping);
assert(mapping->begin == begin);
@@ -2474,8 +2474,8 @@ static int handle_commits(BDRVVVFATState* s)
}
case ACTION_NEW_FILE: {
int begin = commit->param.new_file.first_cluster;
- a_mapping* mapping = find_mapping_for_cluster(s, begin);
- a_direntry* entry;
+ mapping_t* mapping = find_mapping_for_cluster(s, begin);
+ direntry_t* entry;
int i;
/* find direntry */
@@ -2530,9 +2530,9 @@ static int handle_deletes(BDRVVVFATState* s)
deleted = 0;
for (i = 1; i < s->mapping.next; i++) {
- a_mapping* mapping = array_get(&(s->mapping), i);
+ mapping_t* mapping = array_get(&(s->mapping), i);
if (mapping->mode & MODE_DELETED) {
- a_direntry* entry = array_get(&(s->directory),
+ direntry_t* entry = array_get(&(s->directory),
mapping->dir_index);
if (is_free(entry)) {
@@ -2550,7 +2550,7 @@ static int handle_deletes(BDRVVVFATState* s)
}
for (j = 1; j < s->mapping.next; j++) {
- a_mapping* m = array_get(&(s->mapping), j);
+ mapping_t* m = array_get(&(s->mapping), j);
if (m->mode & MODE_DIRECTORY &&
m->info.dir.first_dir_index >
first_dir_index &&
@@ -2666,7 +2666,7 @@ DLOG(checkpoint());
for (i = sector2cluster(s, sector_num);
i <= sector2cluster(s, sector_num + nb_sectors - 1);) {
- a_mapping* mapping = find_mapping_for_cluster(s, i);
+ mapping_t* mapping = find_mapping_for_cluster(s, i);
if (mapping) {
if (mapping->read_only) {
fprintf(stderr, "Tried to write to write-protected file %s\n",
@@ -2678,7 +2678,7 @@ DLOG(checkpoint());
int begin = cluster2sector(s, i);
int end = begin + s->sectors_per_cluster, k;
int dir_index;
- const a_direntry* direntries;
+ const direntry_t* direntries;
long_file_name lfn;
lfn_init(&lfn);
@@ -2689,7 +2689,7 @@ DLOG(checkpoint());
end = sector_num + nb_sectors;
dir_index = mapping->dir_index +
0x10 * (begin - mapping->begin * s->sectors_per_cluster);
- direntries = (a_direntry*)(buf + 0x200 * (begin - sector_num));
+ direntries = (direntry_t*)(buf + 0x200 * (begin - sector_num));
for (k = 0; k < (end - begin) * 0x10; k++) {
/* do not allow non-ASCII filenames */
@@ -2702,7 +2702,7 @@ DLOG(checkpoint());
(direntries[k].attributes & 1)) {
if (memcmp(direntries + k,
array_get(&(s->directory), dir_index + k),
- sizeof(a_direntry))) {
+ sizeof(direntry_t))) {
fprintf(stderr, "Warning: tried to write to write-protected file\n");
return -1;
}
@@ -2774,7 +2774,7 @@ static int enable_write_target(BDRVVVFATState *s)
int size = sector2cluster(s, s->sector_count);
s->used_clusters = calloc(size, 1);
- array_init(&(s->commits), sizeof(a_commit));
+ array_init(&(s->commits), sizeof(commit_t));
s->qcow_filename = qemu_malloc(1024);
get_tmp_filename(s->qcow_filename, 1024);
@@ -2833,15 +2833,15 @@ block_init(bdrv_vvfat_init);
#ifdef DEBUG
static void checkpoint(void) {
- assert(((a_mapping*)array_get(&(vvv->mapping), 0))->end == 2);
+ assert(((mapping_t*)array_get(&(vvv->mapping), 0))->end == 2);
check1(vvv);
check2(vvv);
assert(!vvv->current_mapping || vvv->current_fd || (vvv->current_mapping->mode & MODE_DIRECTORY));
#if 0
- if (((a_direntry*)vvv->directory.pointer)[1].attributes != 0xf)
+ if (((direntry_t*)vvv->directory.pointer)[1].attributes != 0xf)
fprintf(stderr, "Nonono!\n");
- a_mapping* mapping;
- a_direntry* direntry;
+ mapping_t* mapping;
+ direntry_t* direntry;
assert(vvv->mapping.size >= vvv->mapping.item_size * vvv->mapping.next);
assert(vvv->directory.size >= vvv->directory.item_size * vvv->directory.next);
if (vvv->mapping.next<47)
diff --git a/console.c b/console.c
index f7b5d49f7..9bbef593b 100644
--- a/console.c
+++ b/console.c
@@ -110,12 +110,12 @@ typedef enum {
GRAPHIC_CONSOLE,
TEXT_CONSOLE,
TEXT_CONSOLE_FIXED_SIZE
-} e_console_type;
+} console_type_t;
/* ??? This is mis-named.
It is used for both text and graphical consoles. */
struct TextConsole {
- e_console_type console_type;
+ console_type_t console_type;
DisplayState *ds;
/* Graphic console state. */
vga_hw_update_ptr hw_update;
@@ -183,7 +183,7 @@ void vga_hw_screen_dump(const char *filename)
active_console = previous_active_console;
}
-void vga_hw_text_update(a_console_ch *chardata)
+void vga_hw_text_update(console_ch_t *chardata)
{
if (active_console && active_console->hw_text_update)
active_console->hw_text_update(active_console->hw, chardata);
@@ -1197,7 +1197,7 @@ static void text_console_invalidate(void *opaque)
console_refresh(s);
}
-static void text_console_update(void *opaque, a_console_ch *chardata)
+static void text_console_update(void *opaque, console_ch_t *chardata)
{
TextConsole *s = (TextConsole *) opaque;
int i, j, src;
@@ -1236,7 +1236,7 @@ static TextConsole *get_graphic_console(DisplayState *ds)
return NULL;
}
-static TextConsole *new_console(DisplayState *ds, e_console_type console_type)
+static TextConsole *new_console(DisplayState *ds, console_type_t console_type)
{
TextConsole *s;
int i;
diff --git a/console.h b/console.h
index 2629e697c..9615f5636 100644
--- a/console.h
+++ b/console.h
@@ -279,8 +279,8 @@ static inline int ds_get_bytes_per_pixel(DisplayState *ds)
return ds->surface->pf.bytes_per_pixel;
}
-typedef unsigned long a_console_ch;
-static inline void console_write_ch(a_console_ch *dest, uint32_t ch)
+typedef unsigned long console_ch_t;
+static inline void console_write_ch(console_ch_t *dest, uint32_t ch)
{
cpu_to_le32wu((uint32_t *) dest, ch);
}
@@ -288,7 +288,7 @@ static inline void console_write_ch(a_console_ch *dest, uint32_t ch)
typedef void (*vga_hw_update_ptr)(void *);
typedef void (*vga_hw_invalidate_ptr)(void *);
typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
-typedef void (*vga_hw_text_update_ptr)(void *, a_console_ch *);
+typedef void (*vga_hw_text_update_ptr)(void *, console_ch_t *);
DisplayState *graphic_console_init(vga_hw_update_ptr update,
vga_hw_invalidate_ptr invalidate,
@@ -299,7 +299,7 @@ DisplayState *graphic_console_init(vga_hw_update_ptr update,
void vga_hw_update(void);
void vga_hw_invalidate(void);
void vga_hw_screen_dump(const char *filename);
-void vga_hw_text_update(a_console_ch *chardata);
+void vga_hw_text_update(console_ch_t *chardata);
int is_graphic_console(void);
int is_fixedsize_console(void);
diff --git a/cpu-all.h b/cpu-all.h
index 45e1ebff7..ebe8bfbad 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -814,7 +814,7 @@ void cpu_reset(CPUState *s);
/* Return the physical page corresponding to a virtual one. Use it
only for debugging because no protection checks are done. Return -1
if no page found. */
-a_target_phys_addr cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
+target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
#define CPU_LOG_TB_OUT_ASM (1 << 0)
#define CPU_LOG_TB_IN_ASM (1 << 1)
@@ -847,8 +847,8 @@ int cpu_str_to_log_mask(const char *str);
extern int phys_ram_fd;
extern uint8_t *phys_ram_dirty;
-extern a_ram_addr ram_size;
-extern a_ram_addr last_ram_offset;
+extern ram_addr_t ram_size;
+extern ram_addr_t last_ram_offset;
/* physical memory access */
@@ -876,23 +876,23 @@ int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
#define MIGRATION_DIRTY_FLAG 0x08
/* read dirty bit (return 0 or 1) */
-static inline int cpu_physical_memory_is_dirty(a_ram_addr addr)
+static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
{
return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
}
-static inline int cpu_physical_memory_get_dirty(a_ram_addr addr,
+static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
int dirty_flags)
{
return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
}
-static inline void cpu_physical_memory_set_dirty(a_ram_addr addr)
+static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
{
phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
}
-void cpu_physical_memory_reset_dirty(a_ram_addr start, a_ram_addr end,
+void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
int dirty_flags);
void cpu_tlb_update_dirty(CPUState *env);
@@ -900,8 +900,8 @@ int cpu_physical_memory_set_dirty_tracking(int enable);
int cpu_physical_memory_get_dirty_tracking(void);
-int cpu_physical_sync_dirty_bitmap(a_target_phys_addr start_addr,
- a_target_phys_addr end_addr);
+int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr,
+ target_phys_addr_t end_addr);
void dump_exec_info(FILE *f,
int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
@@ -911,9 +911,9 @@ void dump_exec_info(FILE *f,
* batching which can make a major impact on performance when using
* virtualization.
*/
-void qemu_register_coalesced_mmio(a_target_phys_addr addr, a_ram_addr size);
+void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
-void qemu_unregister_coalesced_mmio(a_target_phys_addr addr, a_ram_addr size);
+void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
/*******************************************/
/* host CPU ticks (if available) */
diff --git a/cpu-common.h b/cpu-common.h
index 854f629ad..630237203 100644
--- a/cpu-common.h
+++ b/cpu-common.h
@@ -10,69 +10,69 @@
#include "bswap.h"
/* address in the RAM (different from a physical address) */
-typedef unsigned long a_ram_addr;
+typedef unsigned long ram_addr_t;
/* memory API */
-typedef void CPUWriteMemoryFunc(void *opaque, a_target_phys_addr addr, uint32_t value);
-typedef uint32_t CPUReadMemoryFunc(void *opaque, a_target_phys_addr addr);
+typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
+typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
-void cpu_register_physical_memory_offset(a_target_phys_addr start_addr,
- a_ram_addr size,
- a_ram_addr phys_offset,
- a_ram_addr region_offset);
-static inline void cpu_register_physical_memory(a_target_phys_addr start_addr,
- a_ram_addr size,
- a_ram_addr phys_offset)
+void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
+ ram_addr_t size,
+ ram_addr_t phys_offset,
+ ram_addr_t region_offset);
+static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
+ ram_addr_t size,
+ ram_addr_t phys_offset)
{
cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
}
-a_ram_addr cpu_get_physical_page_desc(a_target_phys_addr addr);
-a_ram_addr qemu_ram_alloc(a_ram_addr);
-void qemu_ram_free(a_ram_addr addr);
+ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
+ram_addr_t qemu_ram_alloc(ram_addr_t);
+void qemu_ram_free(ram_addr_t addr);
/* This should only be used for ram local to a device. */
-void *qemu_get_ram_ptr(a_ram_addr addr);
+void *qemu_get_ram_ptr(ram_addr_t addr);
/* This should not be used by devices. */
-a_ram_addr qemu_ram_addr_from_host(void *ptr);
+ram_addr_t qemu_ram_addr_from_host(void *ptr);
int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
CPUWriteMemoryFunc * const *mem_write,
void *opaque);
void cpu_unregister_io_memory(int table_address);
-void cpu_physical_memory_rw(a_target_phys_addr addr, uint8_t *buf,
+void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
int len, int is_write);
-static inline void cpu_physical_memory_read(a_target_phys_addr addr,
+static inline void cpu_physical_memory_read(target_phys_addr_t addr,
uint8_t *buf, int len)
{
cpu_physical_memory_rw(addr, buf, len, 0);
}
-static inline void cpu_physical_memory_write(a_target_phys_addr addr,
+static inline void cpu_physical_memory_write(target_phys_addr_t addr,
const uint8_t *buf, int len)
{
cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
}
-void *cpu_physical_memory_map(a_target_phys_addr addr,
- a_target_phys_addr *plen,
+void *cpu_physical_memory_map(target_phys_addr_t addr,
+ target_phys_addr_t *plen,
int is_write);
-void cpu_physical_memory_unmap(void *buffer, a_target_phys_addr len,
- int is_write, a_target_phys_addr access_len);
+void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
+ int is_write, target_phys_addr_t access_len);
void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
void cpu_unregister_map_client(void *cookie);
-uint32_t ldub_phys(a_target_phys_addr addr);
-uint32_t lduw_phys(a_target_phys_addr addr);
-uint32_t ldl_phys(a_target_phys_addr addr);
-uint64_t ldq_phys(a_target_phys_addr addr);
-void stl_phys_notdirty(a_target_phys_addr addr, uint32_t val);
-void stq_phys_notdirty(a_target_phys_addr addr, uint64_t val);
-void stb_phys(a_target_phys_addr addr, uint32_t val);
-void stw_phys(a_target_phys_addr addr, uint32_t val);
-void stl_phys(a_target_phys_addr addr, uint32_t val);
-void stq_phys(a_target_phys_addr addr, uint64_t val);
-
-void cpu_physical_memory_write_rom(a_target_phys_addr addr,
+uint32_t ldub_phys(target_phys_addr_t addr);
+uint32_t lduw_phys(target_phys_addr_t addr);
+uint32_t ldl_phys(target_phys_addr_t addr);
+uint64_t ldq_phys(target_phys_addr_t addr);
+void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
+void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
+void stb_phys(target_phys_addr_t addr, uint32_t val);
+void stw_phys(target_phys_addr_t addr, uint32_t val);
+void stl_phys(target_phys_addr_t addr, uint32_t val);
+void stq_phys(target_phys_addr_t addr, uint64_t val);
+
+void cpu_physical_memory_write_rom(target_phys_addr_t addr,
const uint8_t *buf, int len);
#define IO_MEM_SHIFT 3
diff --git a/cpu-defs.h b/cpu-defs.h
index a48fb0213..95068b530 100644
--- a/cpu-defs.h
+++ b/cpu-defs.h
@@ -95,15 +95,15 @@ typedef struct CPUTLBEntry {
use the corresponding iotlb value. */
#if TARGET_PHYS_ADDR_BITS == 64
/* on i386 Linux make sure it is aligned */
- a_target_phys_addr addend __attribute__((aligned(8)));
+ target_phys_addr_t addend __attribute__((aligned(8)));
#else
- a_target_phys_addr addend;
+ target_phys_addr_t addend;
#endif
/* padding to get a power of two size */
uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
(sizeof(target_ulong) * 3 +
- ((-sizeof(target_ulong) * 3) & (sizeof(a_target_phys_addr) - 1)) +
- sizeof(a_target_phys_addr))];
+ ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) +
+ sizeof(target_phys_addr_t))];
} CPUTLBEntry;
#ifdef HOST_WORDS_BIGENDIAN
@@ -152,7 +152,7 @@ typedef struct CPUWatchpoint {
volatile sig_atomic_t exit_request; \
/* The meaning of the MMU modes is defined in the target code. */ \
CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
- a_target_phys_addr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
+ target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
/* buffer for temporaries in the code generator */ \
long temp_buf[CPU_TEMP_BUF_NLONGS]; \
diff --git a/curses.c b/curses.c
index 09ccee935..3ce12b923 100644
--- a/curses.c
+++ b/curses.c
@@ -40,7 +40,7 @@
#define FONT_HEIGHT 16
#define FONT_WIDTH 8
-static a_console_ch screen[160 * 100];
+static console_ch_t screen[160 * 100];
static WINDOW *screenpad = NULL;
static int width, height, gwidth, gheight, invalidate;
static int px, py, sminx, sminy, smaxx, smaxy;
@@ -158,7 +158,7 @@ static void curses_cursor_position(DisplayState *ds, int x, int y)
#include "curses_keys.h"
-static a_kbd_layout *kbd_layout = NULL;
+static kbd_layout_t *kbd_layout = NULL;
static int keycode2keysym[CURSES_KEYS];
static void curses_refresh(DisplayState *ds)
diff --git a/curses_keys.h b/curses_keys.h
index 210a36884..a6e41cf4e 100644
--- a/curses_keys.h
+++ b/curses_keys.h
@@ -243,7 +243,7 @@ static const int curses2keysym[CURSES_KEYS] = {
};
-static const a_name2keysym name2keysym[] = {
+static const name2keysym_t name2keysym[] = {
/* Plain ASCII */
{ "space", 0x020 },
{ "exclam", 0x021 },
diff --git a/darwin-user/commpage.c b/darwin-user/commpage.c
index 641fdb390..2b41bc5e3 100644
--- a/darwin-user/commpage.c
+++ b/darwin-user/commpage.c
@@ -109,7 +109,7 @@ static struct commpage_entry commpage_entries[] =
COMMPAGE_ENTRY(add_atomic_word64, 0, 0x1c0, unimpl_commpage, CALL_INDIRECT | HAS_PTR),
COMMPAGE_ENTRY(mach_absolute_time, 0, 0x200, unimpl_commpage, CALL_INDIRECT),
- COMMPAGE_ENTRY(a_spinlockry, 1, 0x220, unimpl_commpage, CALL_INDIRECT),
+ COMMPAGE_ENTRY(spinlock_try, 1, 0x220, unimpl_commpage, CALL_INDIRECT),
COMMPAGE_ENTRY(spinlock_lock, 1, 0x260, OSSpinLockLock, CALL_DIRECT),
COMMPAGE_ENTRY(spinlock_unlock, 1, 0x2a0, OSSpinLockUnlock, CALL_DIRECT),
COMMPAGE_ENTRY(pthread_getspecific, 0, 0x2c0, unimpl_commpage, CALL_INDIRECT),
diff --git a/darwin-user/machload.c b/darwin-user/machload.c
index 027976b45..4bb5c7276 100644
--- a/darwin-user/machload.c
+++ b/darwin-user/machload.c
@@ -101,7 +101,7 @@ typedef struct mach_i386_thread_state {
unsigned int es;
unsigned int fs;
unsigned int gs;
-};
+} mach_i386_thread_state_t;
void bswap_i386_thread_state(struct mach_i386_thread_state *ts)
{
diff --git a/darwin-user/qemu.h b/darwin-user/qemu.h
index 4084819d9..462bbdac2 100644
--- a/darwin-user/qemu.h
+++ b/darwin-user/qemu.h
@@ -10,7 +10,7 @@
#include "gdbstub.h"
-typedef siginfo_t a_target_siginfo;
+typedef siginfo_t target_siginfo_t;
#define target_sigaction sigaction
#ifdef TARGET_I386
struct target_pt_regs {
diff --git a/disas.h b/disas.h
index 9b630832c..06abab21e 100644
--- a/disas.h
+++ b/disas.h
@@ -22,7 +22,7 @@ struct syminfo;
struct elf32_sym;
struct elf64_sym;
-typedef const char *(*lookup_symbol_t)(struct syminfo *s, a_target_phys_addr orig_addr);
+typedef const char *(*lookup_symbol_t)(struct syminfo *s, target_phys_addr_t orig_addr);
struct syminfo {
lookup_symbol_t lookup_symbol;
diff --git a/dma-helpers.c b/dma-helpers.c
index 3b7323f5f..712ed897f 100644
--- a/dma-helpers.c
+++ b/dma-helpers.c
@@ -18,8 +18,8 @@ void qemu_sglist_init(QEMUSGList *qsg, int alloc_hint)
qsg->size = 0;
}
-void qemu_sglist_add(QEMUSGList *qsg, a_target_phys_addr base,
- a_target_phys_addr len)
+void qemu_sglist_add(QEMUSGList *qsg, target_phys_addr_t base,
+ target_phys_addr_t len)
{
if (qsg->nsg == qsg->nalloc) {
qsg->nalloc = 2 * qsg->nalloc + 1;
@@ -44,7 +44,7 @@ typedef struct {
uint64_t sector_num;
int is_write;
int sg_cur_index;
- a_target_phys_addr sg_cur_byte;
+ target_phys_addr_t sg_cur_byte;
QEMUIOVector iov;
QEMUBH *bh;
} DMAAIOCB;
@@ -82,7 +82,7 @@ static void dma_bdrv_unmap(DMAAIOCB *dbs)
static void dma_bdrv_cb(void *opaque, int ret)
{
DMAAIOCB *dbs = (DMAAIOCB *)opaque;
- a_target_phys_addr cur_addr, cur_len;
+ target_phys_addr_t cur_addr, cur_len;
void *mem;
dbs->acb = NULL;
diff --git a/dma.h b/dma.h
index 883d471b9..f3bb27515 100644
--- a/dma.h
+++ b/dma.h
@@ -16,20 +16,20 @@
#include "block.h"
typedef struct {
- a_target_phys_addr base;
- a_target_phys_addr len;
+ target_phys_addr_t base;
+ target_phys_addr_t len;
} ScatterGatherEntry;
typedef struct {
ScatterGatherEntry *sg;
int nsg;
int nalloc;
- a_target_phys_addr size;
+ target_phys_addr_t size;
} QEMUSGList;
void qemu_sglist_init(QEMUSGList *qsg, int alloc_hint);
-void qemu_sglist_add(QEMUSGList *qsg, a_target_phys_addr base,
- a_target_phys_addr len);
+void qemu_sglist_add(QEMUSGList *qsg, target_phys_addr_t base,
+ target_phys_addr_t len);
void qemu_sglist_destroy(QEMUSGList *qsg);
BlockDriverAIOCB *dma_bdrv_read(BlockDriverState *bs,
diff --git a/dyngen-exec.h b/dyngen-exec.h
index ae744f24f..86e61c3df 100644
--- a/dyngen-exec.h
+++ b/dyngen-exec.h
@@ -37,7 +37,7 @@
#endif
/* XXX: This may be wrong for 64-bit ILP32 hosts. */
-typedef void * a_host_reg;
+typedef void * host_reg_t;
#ifdef CONFIG_BSD
typedef struct __sFILE FILE;
diff --git a/exec-all.h b/exec-all.h
index 412b53a07..dd134a99f 100644
--- a/exec-all.h
+++ b/exec-all.h
@@ -81,16 +81,16 @@ TranslationBlock *tb_gen_code(CPUState *env,
void cpu_exec_init(CPUState *env);
void QEMU_NORETURN cpu_loop_exit(void);
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
-void tb_invalidate_phys_page_range(a_target_phys_addr start, a_target_phys_addr end,
+void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, target_ulong addr);
void tlb_flush(CPUState *env, int flush_global);
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
- a_target_phys_addr paddr, int prot,
+ target_phys_addr_t paddr, int prot,
int mmu_idx, int is_softmmu);
static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
- a_target_phys_addr paddr, int prot,
+ target_phys_addr_t paddr, int prot,
int mmu_idx, int is_softmmu)
{
if (prot & PAGE_READ)
@@ -269,7 +269,7 @@ extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
#include "qemu-lock.h"
-extern a_spinlock tb_lock;
+extern spinlock_t tb_lock;
extern int tb_invalidated_flag;
diff --git a/exec.c b/exec.c
index 93517fad9..c82e76714 100644
--- a/exec.c
+++ b/exec.c
@@ -83,7 +83,7 @@ int code_gen_max_blocks;
TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
static int nb_tbs;
/* any access to the tbs or the page table must use this lock */
-a_spinlock tb_lock = SPIN_LOCK_UNLOCKED;
+spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
#if defined(__arm__) || defined(__sparc_v9__)
/* The prologue must be reachable with a direct jump. ARM and Sparc64
@@ -115,8 +115,8 @@ static int in_migration;
typedef struct RAMBlock {
uint8_t *host;
- a_ram_addr offset;
- a_ram_addr length;
+ ram_addr_t offset;
+ ram_addr_t length;
struct RAMBlock *next;
} RAMBlock;
@@ -124,7 +124,7 @@ static RAMBlock *ram_blocks;
/* TODO: When we implement (and use) ram deallocation (e.g. for hotplug)
then we can no longer assume contiguous ram offsets, and external uses
of this variable will break. */
-a_ram_addr last_ram_offset;
+ram_addr_t last_ram_offset;
#endif
CPUState *first_cpu;
@@ -153,8 +153,8 @@ typedef struct PageDesc {
typedef struct PhysPageDesc {
/* offset in host memory of the page + io_index in the low bits */
- a_ram_addr phys_offset;
- a_ram_addr region_offset;
+ ram_addr_t phys_offset;
+ ram_addr_t region_offset;
} PhysPageDesc;
#define L2_BITS 10
@@ -203,13 +203,13 @@ static int tb_flush_count;
static int tb_phys_invalidate_count;
#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
-typedef struct subpage {
- a_target_phys_addr base;
+typedef struct subpage_t {
+ target_phys_addr_t base;
CPUReadMemoryFunc * const *mem_read[TARGET_PAGE_SIZE][4];
CPUWriteMemoryFunc * const *mem_write[TARGET_PAGE_SIZE][4];
void *opaque[TARGET_PAGE_SIZE][2][4];
- a_ram_addr region_offset[TARGET_PAGE_SIZE][2][4];
-} a_subpage;
+ ram_addr_t region_offset[TARGET_PAGE_SIZE][2][4];
+} subpage_t;
#ifdef _WIN32
static void map_exec(void *addr, long size)
@@ -346,7 +346,7 @@ static inline PageDesc *page_find(target_ulong index)
return p + (index & (L2_SIZE - 1));
}
-static PhysPageDesc *phys_page_find_alloc(a_target_phys_addr index, int alloc)
+static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
{
void **lp, **p;
PhysPageDesc *pd;
@@ -385,14 +385,14 @@ static PhysPageDesc *phys_page_find_alloc(a_target_phys_addr index, int alloc)
return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1));
}
-static inline PhysPageDesc *phys_page_find(a_target_phys_addr index)
+static inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
{
return phys_page_find_alloc(index, 0);
}
#if !defined(CONFIG_USER_ONLY)
-static void tlb_protect_code(a_ram_addr ram_addr);
-static void tlb_unprotect_code_phys(CPUState *env, a_ram_addr ram_addr,
+static void tlb_protect_code(ram_addr_t ram_addr);
+static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
target_ulong vaddr);
#define mmap_lock() do { } while(0)
#define mmap_unlock() do { } while(0)
@@ -766,7 +766,7 @@ void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr)
CPUState *env;
PageDesc *p;
unsigned int h, n1;
- a_target_phys_addr phys_pc;
+ target_phys_addr_t phys_pc;
TranslationBlock *tb1, *tb2;
/* remove the TB from the hash list */
@@ -914,7 +914,7 @@ TranslationBlock *tb_gen_code(CPUState *env,
the same physical page. 'is_cpu_write_access' should be true if called
from a real cpu write access: the virtual CPU will exit the current
TB if code is modified inside this TB. */
-void tb_invalidate_phys_page_range(a_target_phys_addr start, a_target_phys_addr end,
+void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
int is_cpu_write_access)
{
TranslationBlock *tb, *tb_next, *saved_tb;
@@ -1021,7 +1021,7 @@ void tb_invalidate_phys_page_range(a_target_phys_addr start, a_target_phys_addr
}
/* len must be <= 8 and start must be a multiple of len */
-static inline void tb_invalidate_phys_page_fast(a_target_phys_addr start, int len)
+static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
{
PageDesc *p;
int offset, b;
@@ -1048,7 +1048,7 @@ static inline void tb_invalidate_phys_page_fast(a_target_phys_addr start, int le
}
#if !defined(CONFIG_SOFTMMU)
-static void tb_invalidate_phys_page(a_target_phys_addr addr,
+static void tb_invalidate_phys_page(target_phys_addr_t addr,
unsigned long pc, void *puc)
{
TranslationBlock *tb;
@@ -1310,9 +1310,9 @@ static void tb_reset_jump_recursive(TranslationBlock *tb)
#if defined(TARGET_HAS_ICE)
static void breakpoint_invalidate(CPUState *env, target_ulong pc)
{
- a_target_phys_addr addr;
+ target_phys_addr_t addr;
target_ulong pd;
- a_ram_addr ram_addr;
+ ram_addr_t ram_addr;
PhysPageDesc *p;
addr = cpu_get_phys_page_debug(env, pc);
@@ -1533,7 +1533,7 @@ static void cpu_unlink_tb(CPUState *env)
signals are used primarily to interrupt blocking syscalls. */
#else
TranslationBlock *tb;
- static a_spinlock interrupt_lock = SPIN_LOCK_UNLOCKED;
+ static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED;
tb = env->current_tb;
/* if the cpu is currently executing code, we must unlink it and
@@ -1810,7 +1810,7 @@ void tlb_flush_page(CPUState *env, target_ulong addr)
/* update the TLBs so that writes to code in the virtual page 'addr'
can be detected */
-static void tlb_protect_code(a_ram_addr ram_addr)
+static void tlb_protect_code(ram_addr_t ram_addr)
{
cpu_physical_memory_reset_dirty(ram_addr,
ram_addr + TARGET_PAGE_SIZE,
@@ -1819,7 +1819,7 @@ static void tlb_protect_code(a_ram_addr ram_addr)
/* update the TLB so that writes in physical page 'phys_addr' are no longer
tested for self modifying code */
-static void tlb_unprotect_code_phys(CPUState *env, a_ram_addr ram_addr,
+static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
target_ulong vaddr)
{
phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG;
@@ -1838,7 +1838,7 @@ static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
}
/* Note: start and end must be within the same ram block. */
-void cpu_physical_memory_reset_dirty(a_ram_addr start, a_ram_addr end,
+void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
int dirty_flags)
{
CPUState *env;
@@ -1892,8 +1892,8 @@ int cpu_physical_memory_get_dirty_tracking(void)
return in_migration;
}
-int cpu_physical_sync_dirty_bitmap(a_target_phys_addr start_addr,
- a_target_phys_addr end_addr)
+int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr,
+ target_phys_addr_t end_addr)
{
int ret = 0;
@@ -1904,7 +1904,7 @@ int cpu_physical_sync_dirty_bitmap(a_target_phys_addr start_addr,
static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
{
- a_ram_addr ram_addr;
+ ram_addr_t ram_addr;
void *p;
if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
@@ -1952,7 +1952,7 @@ static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
(can only happen in non SOFTMMU mode for I/O pages or pages
conflicting with the host address space). */
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
- a_target_phys_addr paddr, int prot,
+ target_phys_addr_t paddr, int prot,
int mmu_idx, int is_softmmu)
{
PhysPageDesc *p;
@@ -1960,11 +1960,11 @@ int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
unsigned int index;
target_ulong address;
target_ulong code_address;
- a_target_phys_addr addend;
+ target_phys_addr_t addend;
int ret;
CPUTLBEntry *te;
CPUWatchpoint *wp;
- a_target_phys_addr iotlb;
+ target_phys_addr_t iotlb;
p = phys_page_find(paddr >> TARGET_PAGE_BITS);
if (!p) {
@@ -2061,7 +2061,7 @@ void tlb_flush_page(CPUState *env, target_ulong addr)
}
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
- a_target_phys_addr paddr, int prot,
+ target_phys_addr_t paddr, int prot,
int mmu_idx, int is_softmmu)
{
return 0;
@@ -2267,10 +2267,10 @@ static inline void tlb_set_dirty(CPUState *env,
#if !defined(CONFIG_USER_ONLY)
-static int subpage_register (a_subpage *mmio, uint32_t start, uint32_t end,
- a_ram_addr memory, a_ram_addr region_offset);
-static void *subpage_init (a_target_phys_addr base, a_ram_addr *phys,
- a_ram_addr orig_memory, a_ram_addr region_offset);
+static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
+ ram_addr_t memory, ram_addr_t region_offset);
+static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
+ ram_addr_t orig_memory, ram_addr_t region_offset);
#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
need_subpage) \
do { \
@@ -2298,15 +2298,15 @@ static void *subpage_init (a_target_phys_addr base, a_ram_addr *phys,
start_addr and region_offset are rounded down to a page boundary
before calculating this offset. This should not be a problem unless
the low bits of start_addr and region_offset differ. */
-void cpu_register_physical_memory_offset(a_target_phys_addr start_addr,
- a_ram_addr size,
- a_ram_addr phys_offset,
- a_ram_addr region_offset)
+void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
+ ram_addr_t size,
+ ram_addr_t phys_offset,
+ ram_addr_t region_offset)
{
- a_target_phys_addr addr, end_addr;
+ target_phys_addr_t addr, end_addr;
PhysPageDesc *p;
CPUState *env;
- a_ram_addr orig_size = size;
+ ram_addr_t orig_size = size;
void *subpage;
if (kvm_enabled())
@@ -2317,12 +2317,12 @@ void cpu_register_physical_memory_offset(a_target_phys_addr start_addr,
}
region_offset &= TARGET_PAGE_MASK;
size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
- end_addr = start_addr + (a_target_phys_addr)size;
+ end_addr = start_addr + (target_phys_addr_t)size;
for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
p = phys_page_find(addr >> TARGET_PAGE_BITS);
if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
- a_ram_addr orig_memory = p->phys_offset;
- a_target_phys_addr start_addr2, end_addr2;
+ ram_addr_t orig_memory = p->phys_offset;
+ target_phys_addr_t start_addr2, end_addr2;
int need_subpage = 0;
CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
@@ -2353,7 +2353,7 @@ void cpu_register_physical_memory_offset(a_target_phys_addr start_addr,
(phys_offset & IO_MEM_ROMD)) {
phys_offset += TARGET_PAGE_SIZE;
} else {
- a_target_phys_addr start_addr2, end_addr2;
+ target_phys_addr_t start_addr2, end_addr2;
int need_subpage = 0;
CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
@@ -2381,7 +2381,7 @@ void cpu_register_physical_memory_offset(a_target_phys_addr start_addr,
}
/* XXX: temporary until new memory mapping API */
-a_ram_addr cpu_get_physical_page_desc(a_target_phys_addr addr)
+ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
{
PhysPageDesc *p;
@@ -2391,19 +2391,19 @@ a_ram_addr cpu_get_physical_page_desc(a_target_phys_addr addr)
return p->phys_offset;
}
-void qemu_register_coalesced_mmio(a_target_phys_addr addr, a_ram_addr size)
+void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
{
if (kvm_enabled())
kvm_coalesce_mmio_region(addr, size);
}
-void qemu_unregister_coalesced_mmio(a_target_phys_addr addr, a_ram_addr size)
+void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
{
if (kvm_enabled())
kvm_uncoalesce_mmio_region(addr, size);
}
-a_ram_addr qemu_ram_alloc(a_ram_addr size)
+ram_addr_t qemu_ram_alloc(ram_addr_t size)
{
RAMBlock *new_block;
@@ -2430,7 +2430,7 @@ a_ram_addr qemu_ram_alloc(a_ram_addr size)
return new_block->offset;
}
-void qemu_ram_free(a_ram_addr addr)
+void qemu_ram_free(ram_addr_t addr)
{
/* TODO: implement this. */
}
@@ -2443,7 +2443,7 @@ void qemu_ram_free(a_ram_addr addr)
It should not be used for general purpose DMA.
Use cpu_physical_memory_map/cpu_physical_memory_rw instead.
*/
-void *qemu_get_ram_ptr(a_ram_addr addr)
+void *qemu_get_ram_ptr(ram_addr_t addr)
{
RAMBlock *prev;
RAMBlock **prevp;
@@ -2474,7 +2474,7 @@ void *qemu_get_ram_ptr(a_ram_addr addr)
/* Some of the softmmu routines need to translate from a host pointer
(typically a TLB entry) back to a ram offset. */
-a_ram_addr qemu_ram_addr_from_host(void *ptr)
+ram_addr_t qemu_ram_addr_from_host(void *ptr)
{
RAMBlock *prev;
RAMBlock **prevp;
@@ -2498,7 +2498,7 @@ a_ram_addr qemu_ram_addr_from_host(void *ptr)
return block->offset + (host - block->host);
}
-static uint32_t unassigned_mem_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
@@ -2509,7 +2509,7 @@ static uint32_t unassigned_mem_readb(void *opaque, a_target_phys_addr addr)
return 0;
}
-static uint32_t unassigned_mem_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
@@ -2520,7 +2520,7 @@ static uint32_t unassigned_mem_readw(void *opaque, a_target_phys_addr addr)
return 0;
}
-static uint32_t unassigned_mem_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
@@ -2531,7 +2531,7 @@ static uint32_t unassigned_mem_readl(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void unassigned_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
@@ -2541,7 +2541,7 @@ static void unassigned_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_
#endif
}
-static void unassigned_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
@@ -2551,7 +2551,7 @@ static void unassigned_mem_writew(void *opaque, a_target_phys_addr addr, uint32_
#endif
}
-static void unassigned_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
@@ -2573,7 +2573,7 @@ static CPUWriteMemoryFunc * const unassigned_mem_write[3] = {
unassigned_mem_writel,
};
-static void notdirty_mem_writeb(void *opaque, a_target_phys_addr ram_addr,
+static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr,
uint32_t val)
{
int dirty_flags;
@@ -2593,7 +2593,7 @@ static void notdirty_mem_writeb(void *opaque, a_target_phys_addr ram_addr,
tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
}
-static void notdirty_mem_writew(void *opaque, a_target_phys_addr ram_addr,
+static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr,
uint32_t val)
{
int dirty_flags;
@@ -2613,7 +2613,7 @@ static void notdirty_mem_writew(void *opaque, a_target_phys_addr ram_addr,
tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
}
-static void notdirty_mem_writel(void *opaque, a_target_phys_addr ram_addr,
+static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr,
uint32_t val)
{
int dirty_flags;
@@ -2693,39 +2693,39 @@ static void check_watchpoint(int offset, int len_mask, int flags)
/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
so these check for a hit then pass through to the normal out-of-line
phys routines. */
-static uint32_t watch_mem_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ);
return ldub_phys(addr);
}
-static uint32_t watch_mem_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ);
return lduw_phys(addr);
}
-static uint32_t watch_mem_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ);
return ldl_phys(addr);
}
-static void watch_mem_writeb(void *opaque, a_target_phys_addr addr,
+static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE);
stb_phys(addr, val);
}
-static void watch_mem_writew(void *opaque, a_target_phys_addr addr,
+static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE);
stw_phys(addr, val);
}
-static void watch_mem_writel(void *opaque, a_target_phys_addr addr,
+static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE);
@@ -2744,7 +2744,7 @@ static CPUWriteMemoryFunc * const watch_mem_write[3] = {
watch_mem_writel,
};
-static inline uint32_t subpage_readlen (a_subpage *mmio, a_target_phys_addr addr,
+static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr,
unsigned int len)
{
uint32_t ret;
@@ -2761,7 +2761,7 @@ static inline uint32_t subpage_readlen (a_subpage *mmio, a_target_phys_addr addr
return ret;
}
-static inline void subpage_writelen (a_subpage *mmio, a_target_phys_addr addr,
+static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
uint32_t value, unsigned int len)
{
unsigned int idx;
@@ -2776,7 +2776,7 @@ static inline void subpage_writelen (a_subpage *mmio, a_target_phys_addr addr,
value);
}
-static uint32_t subpage_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
{
#if defined(DEBUG_SUBPAGE)
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -2785,7 +2785,7 @@ static uint32_t subpage_readb (void *opaque, a_target_phys_addr addr)
return subpage_readlen(opaque, addr, 0);
}
-static void subpage_writeb (void *opaque, a_target_phys_addr addr,
+static void subpage_writeb (void *opaque, target_phys_addr_t addr,
uint32_t value)
{
#if defined(DEBUG_SUBPAGE)
@@ -2794,7 +2794,7 @@ static void subpage_writeb (void *opaque, a_target_phys_addr addr,
subpage_writelen(opaque, addr, value, 0);
}
-static uint32_t subpage_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
{
#if defined(DEBUG_SUBPAGE)
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -2803,7 +2803,7 @@ static uint32_t subpage_readw (void *opaque, a_target_phys_addr addr)
return subpage_readlen(opaque, addr, 1);
}
-static void subpage_writew (void *opaque, a_target_phys_addr addr,
+static void subpage_writew (void *opaque, target_phys_addr_t addr,
uint32_t value)
{
#if defined(DEBUG_SUBPAGE)
@@ -2812,7 +2812,7 @@ static void subpage_writew (void *opaque, a_target_phys_addr addr,
subpage_writelen(opaque, addr, value, 1);
}
-static uint32_t subpage_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
{
#if defined(DEBUG_SUBPAGE)
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -2822,7 +2822,7 @@ static uint32_t subpage_readl (void *opaque, a_target_phys_addr addr)
}
static void subpage_writel (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
#if defined(DEBUG_SUBPAGE)
printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
@@ -2842,8 +2842,8 @@ static CPUWriteMemoryFunc * const subpage_write[] = {
&subpage_writel,
};
-static int subpage_register (a_subpage *mmio, uint32_t start, uint32_t end,
- a_ram_addr memory, a_ram_addr region_offset)
+static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
+ ram_addr_t memory, ram_addr_t region_offset)
{
int idx, eidx;
unsigned int i;
@@ -2875,13 +2875,13 @@ static int subpage_register (a_subpage *mmio, uint32_t start, uint32_t end,
return 0;
}
-static void *subpage_init (a_target_phys_addr base, a_ram_addr *phys,
- a_ram_addr orig_memory, a_ram_addr region_offset)
+static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
+ ram_addr_t orig_memory, ram_addr_t region_offset)
{
- a_subpage *mmio;
+ subpage_t *mmio;
int subpage_memory;
- mmio = qemu_mallocz(sizeof(a_subpage));
+ mmio = qemu_mallocz(sizeof(subpage_t));
mmio->base = base;
subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio);
@@ -2981,7 +2981,7 @@ static void io_mem_init(void)
/* physical memory access (slow version, mainly for debug) */
#if defined(CONFIG_USER_ONLY)
-void cpu_physical_memory_rw(a_target_phys_addr addr, uint8_t *buf,
+void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
int len, int is_write)
{
int l, flags;
@@ -3022,13 +3022,13 @@ void cpu_physical_memory_rw(a_target_phys_addr addr, uint8_t *buf,
}
#else
-void cpu_physical_memory_rw(a_target_phys_addr addr, uint8_t *buf,
+void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
int len, int is_write)
{
int l, io_index;
uint8_t *ptr;
uint32_t val;
- a_target_phys_addr page;
+ target_phys_addr_t page;
unsigned long pd;
PhysPageDesc *p;
@@ -3046,7 +3046,7 @@ void cpu_physical_memory_rw(a_target_phys_addr addr, uint8_t *buf,
if (is_write) {
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
- a_target_phys_addr addr1 = addr;
+ target_phys_addr_t addr1 = addr;
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
if (p)
addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
@@ -3085,7 +3085,7 @@ void cpu_physical_memory_rw(a_target_phys_addr addr, uint8_t *buf,
} else {
if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
!(pd & IO_MEM_ROMD)) {
- a_target_phys_addr addr1 = addr;
+ target_phys_addr_t addr1 = addr;
/* I/O case */
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
if (p)
@@ -3120,12 +3120,12 @@ void cpu_physical_memory_rw(a_target_phys_addr addr, uint8_t *buf,
}
/* used for ROM loading : can write in RAM and ROM */
-void cpu_physical_memory_write_rom(a_target_phys_addr addr,
+void cpu_physical_memory_write_rom(target_phys_addr_t addr,
const uint8_t *buf, int len)
{
int l;
uint8_t *ptr;
- a_target_phys_addr page;
+ target_phys_addr_t page;
unsigned long pd;
PhysPageDesc *p;
@@ -3160,8 +3160,8 @@ void cpu_physical_memory_write_rom(a_target_phys_addr addr,
typedef struct {
void *buffer;
- a_target_phys_addr addr;
- a_target_phys_addr len;
+ target_phys_addr_t addr;
+ target_phys_addr_t len;
} BounceBuffer;
static BounceBuffer bounce;
@@ -3211,16 +3211,16 @@ static void cpu_notify_map_clients(void)
* Use cpu_register_map_client() to know when retrying the map operation is
* likely to succeed.
*/
-void *cpu_physical_memory_map(a_target_phys_addr addr,
- a_target_phys_addr *plen,
+void *cpu_physical_memory_map(target_phys_addr_t addr,
+ target_phys_addr_t *plen,
int is_write)
{
- a_target_phys_addr len = *plen;
- a_target_phys_addr done = 0;
+ target_phys_addr_t len = *plen;
+ target_phys_addr_t done = 0;
int l;
uint8_t *ret = NULL;
uint8_t *ptr;
- a_target_phys_addr page;
+ target_phys_addr_t page;
unsigned long pd;
PhysPageDesc *p;
unsigned long addr1;
@@ -3270,12 +3270,12 @@ void *cpu_physical_memory_map(a_target_phys_addr addr,
* Will also mark the memory as dirty if is_write == 1. access_len gives
* the amount of memory that was actually read or written by the caller.
*/
-void cpu_physical_memory_unmap(void *buffer, a_target_phys_addr len,
- int is_write, a_target_phys_addr access_len)
+void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
+ int is_write, target_phys_addr_t access_len)
{
if (buffer != bounce.buffer) {
if (is_write) {
- a_ram_addr addr1 = qemu_ram_addr_from_host(buffer);
+ ram_addr_t addr1 = qemu_ram_addr_from_host(buffer);
while (access_len) {
unsigned l;
l = TARGET_PAGE_SIZE;
@@ -3303,7 +3303,7 @@ void cpu_physical_memory_unmap(void *buffer, a_target_phys_addr len,
}
/* warning: addr must be aligned */
-uint32_t ldl_phys(a_target_phys_addr addr)
+uint32_t ldl_phys(target_phys_addr_t addr)
{
int io_index;
uint8_t *ptr;
@@ -3335,7 +3335,7 @@ uint32_t ldl_phys(a_target_phys_addr addr)
}
/* warning: addr must be aligned */
-uint64_t ldq_phys(a_target_phys_addr addr)
+uint64_t ldq_phys(target_phys_addr_t addr)
{
int io_index;
uint8_t *ptr;
@@ -3373,7 +3373,7 @@ uint64_t ldq_phys(a_target_phys_addr addr)
}
/* XXX: optimize */
-uint32_t ldub_phys(a_target_phys_addr addr)
+uint32_t ldub_phys(target_phys_addr_t addr)
{
uint8_t val;
cpu_physical_memory_read(addr, &val, 1);
@@ -3381,7 +3381,7 @@ uint32_t ldub_phys(a_target_phys_addr addr)
}
/* XXX: optimize */
-uint32_t lduw_phys(a_target_phys_addr addr)
+uint32_t lduw_phys(target_phys_addr_t addr)
{
uint16_t val;
cpu_physical_memory_read(addr, (uint8_t *)&val, 2);
@@ -3391,7 +3391,7 @@ uint32_t lduw_phys(a_target_phys_addr addr)
/* warning: addr must be aligned. The ram page is not masked as dirty
and the code inside is not invalidated. It is useful if the dirty
bits are used to track modified PTEs */
-void stl_phys_notdirty(a_target_phys_addr addr, uint32_t val)
+void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
{
int io_index;
uint8_t *ptr;
@@ -3427,7 +3427,7 @@ void stl_phys_notdirty(a_target_phys_addr addr, uint32_t val)
}
}
-void stq_phys_notdirty(a_target_phys_addr addr, uint64_t val)
+void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
{
int io_index;
uint8_t *ptr;
@@ -3460,7 +3460,7 @@ void stq_phys_notdirty(a_target_phys_addr addr, uint64_t val)
}
/* warning: addr must be aligned */
-void stl_phys(a_target_phys_addr addr, uint32_t val)
+void stl_phys(target_phys_addr_t addr, uint32_t val)
{
int io_index;
uint8_t *ptr;
@@ -3496,21 +3496,21 @@ void stl_phys(a_target_phys_addr addr, uint32_t val)
}
/* XXX: optimize */
-void stb_phys(a_target_phys_addr addr, uint32_t val)
+void stb_phys(target_phys_addr_t addr, uint32_t val)
{
uint8_t v = val;
cpu_physical_memory_write(addr, &v, 1);
}
/* XXX: optimize */
-void stw_phys(a_target_phys_addr addr, uint32_t val)
+void stw_phys(target_phys_addr_t addr, uint32_t val)
{
uint16_t v = tswap16(val);
cpu_physical_memory_write(addr, (const uint8_t *)&v, 2);
}
/* XXX: optimize */
-void stq_phys(a_target_phys_addr addr, uint64_t val)
+void stq_phys(target_phys_addr_t addr, uint64_t val)
{
val = tswap64(val);
cpu_physical_memory_write(addr, (const uint8_t *)&val, 8);
@@ -3523,7 +3523,7 @@ int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
int l;
- a_target_phys_addr phys_addr;
+ target_phys_addr_t phys_addr;
target_ulong page;
while (len > 0) {
diff --git a/hostregs_helper.h b/hostregs_helper.h
index fa94292c1..3a0bece81 100644
--- a/hostregs_helper.h
+++ b/hostregs_helper.h
@@ -27,8 +27,8 @@
#if defined(DECLARE_HOST_REGS)
#define DO_REG(REG) \
- register a_host_reg reg_AREG##REG asm(AREG##REG); \
- volatile a_host_reg saved_AREG##REG;
+ register host_reg_t reg_AREG##REG asm(AREG##REG); \
+ volatile host_reg_t saved_AREG##REG;
#elif defined(SAVE_HOST_REGS)
diff --git a/hw/an5206.c b/hw/an5206.c
index 2a458b7ef..a4b83b0f4 100644
--- a/hw/an5206.c
+++ b/hw/an5206.c
@@ -29,7 +29,7 @@ void irq_info(Monitor *mon)
/* Board init. */
-static void an5206_init(a_ram_addr ram_size,
+static void an5206_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@@ -37,7 +37,7 @@ static void an5206_init(a_ram_addr ram_size,
CPUState *env;
int kernel_size;
uint64_t elf_entry;
- a_target_phys_addr entry;
+ target_phys_addr_t entry;
if (!cpu_model)
cpu_model = "m5206";
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index 6bb032472..eb7704250 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -39,7 +39,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
#define APB_DPRINTF(fmt, ...)
#endif
-typedef a_target_phys_addr a_pci_addr;
+typedef target_phys_addr_t pci_addr_t;
#include "pci_host.h"
typedef struct APBState {
@@ -47,7 +47,7 @@ typedef struct APBState {
PCIHostState host_state;
} APBState;
-static void pci_apb_config_writel (void *opaque, a_target_phys_addr addr,
+static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
APBState *s = opaque;
@@ -61,7 +61,7 @@ static void pci_apb_config_writel (void *opaque, a_target_phys_addr addr,
}
static uint32_t pci_apb_config_readl (void *opaque,
- a_target_phys_addr addr)
+ target_phys_addr_t addr)
{
APBState *s = opaque;
uint32_t val;
@@ -87,7 +87,7 @@ static CPUReadMemoryFunc * const pci_apb_config_read[] = {
&pci_apb_config_readl,
};
-static void apb_config_writel (void *opaque, a_target_phys_addr addr,
+static void apb_config_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
//PCIBus *s = opaque;
@@ -105,7 +105,7 @@ static void apb_config_writel (void *opaque, a_target_phys_addr addr,
}
static uint32_t apb_config_readl (void *opaque,
- a_target_phys_addr addr)
+ target_phys_addr_t addr)
{
//PCIBus *s = opaque;
uint32_t val;
@@ -148,25 +148,25 @@ static CPUReadMemoryFunc * const pci_apb_read[] = {
&pci_host_data_readl,
};
-static void pci_apb_iowriteb (void *opaque, a_target_phys_addr addr,
+static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
cpu_outb(addr & IOPORTS_MASK, val);
}
-static void pci_apb_iowritew (void *opaque, a_target_phys_addr addr,
+static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
cpu_outw(addr & IOPORTS_MASK, val);
}
-static void pci_apb_iowritel (void *opaque, a_target_phys_addr addr,
+static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
cpu_outl(addr & IOPORTS_MASK, val);
}
-static uint32_t pci_apb_ioreadb (void *opaque, a_target_phys_addr addr)
+static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
@@ -174,7 +174,7 @@ static uint32_t pci_apb_ioreadb (void *opaque, a_target_phys_addr addr)
return val;
}
-static uint32_t pci_apb_ioreadw (void *opaque, a_target_phys_addr addr)
+static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
@@ -182,7 +182,7 @@ static uint32_t pci_apb_ioreadw (void *opaque, a_target_phys_addr addr)
return val;
}
-static uint32_t pci_apb_ioreadl (void *opaque, a_target_phys_addr addr)
+static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
@@ -226,8 +226,8 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
qemu_set_irq(pic[irq_num], level);
}
-PCIBus *pci_apb_init(a_target_phys_addr special_base,
- a_target_phys_addr mem_base,
+PCIBus *pci_apb_init(target_phys_addr_t special_base,
+ target_phys_addr_t mem_base,
qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
{
DeviceState *dev;
diff --git a/hw/apic.c b/hw/apic.c
index b96275e23..2c414c187 100644
--- a/hw/apic.c
+++ b/hw/apic.c
@@ -661,25 +661,25 @@ static void apic_timer(void *opaque)
apic_timer_update(s, s->next_time);
}
-static uint32_t apic_mem_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
{
return 0;
}
-static uint32_t apic_mem_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
{
return 0;
}
-static void apic_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
}
-static void apic_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
}
-static uint32_t apic_mem_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
{
CPUState *env;
APICState *s;
@@ -760,7 +760,7 @@ static uint32_t apic_mem_readl(void *opaque, a_target_phys_addr addr)
return val;
}
-static void apic_send_msi(a_target_phys_addr addr, uint32 data)
+static void apic_send_msi(target_phys_addr_t addr, uint32 data)
{
uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
@@ -771,7 +771,7 @@ static void apic_send_msi(a_target_phys_addr addr, uint32 data)
apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
}
-static void apic_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
CPUState *env;
APICState *s;
diff --git a/hw/arm-misc.h b/hw/arm-misc.h
index bc67ebde1..367dd25c0 100644
--- a/hw/arm-misc.h
+++ b/hw/arm-misc.h
@@ -26,8 +26,8 @@ struct arm_boot_info {
const char *kernel_filename;
const char *kernel_cmdline;
const char *initrd_filename;
- a_target_phys_addr loader_start;
- a_target_phys_addr smp_loader_start;
+ target_phys_addr_t loader_start;
+ target_phys_addr_t smp_loader_start;
int nb_cpus;
int board_id;
int (*atag_board)(struct arm_boot_info *info, void *p);
diff --git a/hw/arm_boot.c b/hw/arm_boot.c
index ef5d2083b..a8a38c5a3 100644
--- a/hw/arm_boot.c
+++ b/hw/arm_boot.c
@@ -61,9 +61,9 @@ static void main_cpu_reset(void *opaque)
} while (0)
static void set_kernel_args(struct arm_boot_info *info,
- int initrd_size, a_target_phys_addr base)
+ int initrd_size, target_phys_addr_t base)
{
- a_target_phys_addr p;
+ target_phys_addr_t p;
p = base + KERNEL_ARGS_ADDR;
/* ATAG_CORE */
@@ -114,9 +114,9 @@ static void set_kernel_args(struct arm_boot_info *info,
}
static void set_kernel_args_old(struct arm_boot_info *info,
- int initrd_size, a_target_phys_addr base)
+ int initrd_size, target_phys_addr_t base)
{
- a_target_phys_addr p;
+ target_phys_addr_t p;
const char *s;
@@ -193,7 +193,7 @@ void arm_load_kernel(CPUState *env, struct arm_boot_info *info)
int n;
int is_linux = 0;
uint64_t elf_entry;
- a_target_phys_addr entry;
+ target_phys_addr_t entry;
int big_endian;
/* Load the kernel. */
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index a466ba4bd..12f510992 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -238,7 +238,7 @@ static void gic_complete_irq(gic_state * s, int cpu, int irq)
}
}
-static uint32_t gic_dist_readb(void *opaque, a_target_phys_addr offset)
+static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
{
gic_state *s = (gic_state *)opaque;
uint32_t res;
@@ -348,7 +348,7 @@ bad_reg:
return 0;
}
-static uint32_t gic_dist_readw(void *opaque, a_target_phys_addr offset)
+static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
{
uint32_t val;
val = gic_dist_readb(opaque, offset);
@@ -356,7 +356,7 @@ static uint32_t gic_dist_readw(void *opaque, a_target_phys_addr offset)
return val;
}
-static uint32_t gic_dist_readl(void *opaque, a_target_phys_addr offset)
+static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
{
uint32_t val;
#ifdef NVIC
@@ -371,7 +371,7 @@ static uint32_t gic_dist_readl(void *opaque, a_target_phys_addr offset)
return val;
}
-static void gic_dist_writeb(void *opaque, a_target_phys_addr offset,
+static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
gic_state *s = (gic_state *)opaque;
@@ -509,14 +509,14 @@ bad_reg:
hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
}
-static void gic_dist_writew(void *opaque, a_target_phys_addr offset,
+static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
gic_dist_writeb(opaque, offset, value & 0xff);
gic_dist_writeb(opaque, offset + 1, value >> 8);
}
-static void gic_dist_writel(void *opaque, a_target_phys_addr offset,
+static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
gic_state *s = (gic_state *)opaque;
diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c
index 624f1128c..26300ef8a 100644
--- a/hw/arm_sysctl.c
+++ b/hw/arm_sysctl.c
@@ -27,7 +27,7 @@ typedef struct {
uint32_t resetlevel;
} arm_sysctl_state;
-static uint32_t arm_sysctl_read(void *opaque, a_target_phys_addr offset)
+static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
@@ -104,7 +104,7 @@ static uint32_t arm_sysctl_read(void *opaque, a_target_phys_addr offset)
}
}
-static void arm_sysctl_write(void *opaque, a_target_phys_addr offset,
+static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
uint32_t val)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
diff --git a/hw/arm_timer.c b/hw/arm_timer.c
index 0bb3591a9..9fef191cb 100644
--- a/hw/arm_timer.c
+++ b/hw/arm_timer.c
@@ -42,7 +42,7 @@ static void arm_timer_update(arm_timer_state *s)
}
}
-static uint32_t arm_timer_read(void *opaque, a_target_phys_addr offset)
+static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
{
arm_timer_state *s = (arm_timer_state *)opaque;
@@ -84,7 +84,7 @@ static void arm_timer_recalibrate(arm_timer_state *s, int reload)
ptimer_set_limit(s->timer, limit, reload);
}
-static void arm_timer_write(void *opaque, a_target_phys_addr offset,
+static void arm_timer_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
arm_timer_state *s = (arm_timer_state *)opaque;
@@ -199,7 +199,7 @@ static void sp804_set_irq(void *opaque, int irq, int level)
qemu_set_irq(s->irq, s->level[0] || s->level[1]);
}
-static uint32_t sp804_read(void *opaque, a_target_phys_addr offset)
+static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
{
sp804_state *s = (sp804_state *)opaque;
@@ -211,7 +211,7 @@ static uint32_t sp804_read(void *opaque, a_target_phys_addr offset)
}
}
-static void sp804_write(void *opaque, a_target_phys_addr offset,
+static void sp804_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
sp804_state *s = (sp804_state *)opaque;
@@ -283,7 +283,7 @@ typedef struct {
arm_timer_state *timer[3];
} icp_pit_state;
-static uint32_t icp_pit_read(void *opaque, a_target_phys_addr offset)
+static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
{
icp_pit_state *s = (icp_pit_state *)opaque;
int n;
@@ -297,7 +297,7 @@ static uint32_t icp_pit_read(void *opaque, a_target_phys_addr offset)
return arm_timer_read(s->timer[n], offset & 0xff);
}
-static void icp_pit_write(void *opaque, a_target_phys_addr offset,
+static void icp_pit_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
icp_pit_state *s = (icp_pit_state *)opaque;
diff --git a/hw/armv7m.c b/hw/armv7m.c
index 0f40b406c..a96288d0d 100644
--- a/hw/armv7m.c
+++ b/hw/armv7m.c
@@ -26,14 +26,14 @@ static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
}
-static uint32_t bitband_readb(void *opaque, a_target_phys_addr offset)
+static uint32_t bitband_readb(void *opaque, target_phys_addr_t offset)
{
uint8_t v;
cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
return (v & (1 << ((offset >> 2) & 7))) != 0;
}
-static void bitband_writeb(void *opaque, a_target_phys_addr offset,
+static void bitband_writeb(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
uint32_t addr;
@@ -49,7 +49,7 @@ static void bitband_writeb(void *opaque, a_target_phys_addr offset,
cpu_physical_memory_write(addr, &v, 1);
}
-static uint32_t bitband_readw(void *opaque, a_target_phys_addr offset)
+static uint32_t bitband_readw(void *opaque, target_phys_addr_t offset)
{
uint32_t addr;
uint16_t mask;
@@ -61,7 +61,7 @@ static uint32_t bitband_readw(void *opaque, a_target_phys_addr offset)
return (v & mask) != 0;
}
-static void bitband_writew(void *opaque, a_target_phys_addr offset,
+static void bitband_writew(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
uint32_t addr;
@@ -78,7 +78,7 @@ static void bitband_writew(void *opaque, a_target_phys_addr offset,
cpu_physical_memory_write(addr, (uint8_t *)&v, 2);
}
-static uint32_t bitband_readl(void *opaque, a_target_phys_addr offset)
+static uint32_t bitband_readl(void *opaque, target_phys_addr_t offset)
{
uint32_t addr;
uint32_t mask;
@@ -90,7 +90,7 @@ static uint32_t bitband_readl(void *opaque, a_target_phys_addr offset)
return (v & mask) != 0;
}
-static void bitband_writel(void *opaque, a_target_phys_addr offset,
+static void bitband_writel(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
uint32_t addr;
diff --git a/hw/axis_dev88.c b/hw/axis_dev88.c
index 5ceb65392..81a41c944 100644
--- a/hw/axis_dev88.c
+++ b/hw/axis_dev88.c
@@ -44,7 +44,7 @@ struct nand_state_t
};
static struct nand_state_t nand_state;
-static uint32_t nand_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
{
struct nand_state_t *s = opaque;
uint32_t r;
@@ -59,7 +59,7 @@ static uint32_t nand_readl (void *opaque, a_target_phys_addr addr)
}
static void
-nand_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
+nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct nand_state_t *s = opaque;
int rdy;
@@ -168,7 +168,7 @@ static struct gpio_state_t
uint32_t regs[0x5c / 4];
} gpio_state;
-static uint32_t gpio_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
{
struct gpio_state_t *s = opaque;
uint32_t r = 0;
@@ -197,7 +197,7 @@ static uint32_t gpio_readl (void *opaque, a_target_phys_addr addr)
D(printf("%s %x=%x\n", __func__, addr, r));
}
-static void gpio_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
+static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct gpio_state_t *s = opaque;
D(printf("%s %x=%x\n", __func__, addr, value));
@@ -250,7 +250,7 @@ static void main_cpu_reset(void *opaque)
}
static
-void axisdev88_init (a_ram_addr ram_size,
+void axisdev88_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@@ -265,8 +265,8 @@ void axisdev88_init (a_ram_addr ram_size,
int i;
int nand_regs;
int gpio_regs;
- a_ram_addr phys_ram;
- a_ram_addr phys_intmem;
+ ram_addr_t phys_ram;
+ ram_addr_t phys_intmem;
/* init CPUs */
if (cpu_model == NULL) {
diff --git a/hw/boards.h b/hw/boards.h
index 68414d799..d8893413d 100644
--- a/hw/boards.h
+++ b/hw/boards.h
@@ -5,7 +5,7 @@
#include "qdev.h"
-typedef void QEMUMachineInitFunc(a_ram_addr ram_size,
+typedef void QEMUMachineInitFunc(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
diff --git a/hw/bt-hci-csr.c b/hw/bt-hci-csr.c
index 892801e00..7300ea679 100644
--- a/hw/bt-hci-csr.c
+++ b/hw/bt-hci-csr.c
@@ -44,7 +44,7 @@ struct csrhci_s {
QEMUTimer *out_tm;
int64_t baud_delay;
- a_bdaddr bd_addr;
+ bdaddr_t bd_addr;
struct HCIInfo *hci;
};
@@ -398,7 +398,7 @@ static void csrhci_reset(struct csrhci_s *s)
/* After a while... (but sooner than 10ms) */
s->modem_state |= CHR_TIOCM_CTS;
- memset(&s->bd_addr, 0, sizeof(a_bdaddr));
+ memset(&s->bd_addr, 0, sizeof(bdaddr_t));
}
static void csrhci_out_tick(void *opaque)
diff --git a/hw/bt-hci.c b/hw/bt-hci.c
index f70dba0f5..669866a5c 100644
--- a/hw/bt-hci.c
+++ b/hw/bt-hci.c
@@ -62,7 +62,7 @@ struct bt_hci_s {
uint32_t role_bmp;
int last_handle;
int connecting;
- a_bdaddr awaiting_bdaddr[HCI_HANDLES_MAX];
+ bdaddr_t awaiting_bdaddr[HCI_HANDLES_MAX];
} lm;
uint8_t event_mask[8];
@@ -672,7 +672,7 @@ static void bt_hci_lmp_link_teardown(struct bt_hci_s *hci, uint16_t handle)
}
}
-static int bt_hci_connect(struct bt_hci_s *hci, a_bdaddr *bdaddr)
+static int bt_hci_connect(struct bt_hci_s *hci, bdaddr_t *bdaddr)
{
struct bt_device_s *slave;
struct bt_link_s link;
@@ -706,7 +706,7 @@ static void bt_hci_connection_reject(struct bt_hci_s *hci,
}
static void bt_hci_connection_reject_event(struct bt_hci_s *hci,
- a_bdaddr *bdaddr)
+ bdaddr_t *bdaddr)
{
evt_conn_complete params;
@@ -808,7 +808,7 @@ static void bt_hci_conn_accept_timeout(void *opaque)
* that's been cancelled by the host in the meantime and immediately
* try to detach the link and send a Connection Complete. */
static int bt_hci_lmp_connection_ready(struct bt_hci_s *hci,
- a_bdaddr *bdaddr)
+ bdaddr_t *bdaddr)
{
int i;
@@ -939,7 +939,7 @@ static void bt_hci_lmp_disconnect_slave(struct bt_link_s *btlink)
&params, EVT_DISCONN_COMPLETE_SIZE);
}
-static int bt_hci_name_req(struct bt_hci_s *hci, a_bdaddr *bdaddr)
+static int bt_hci_name_req(struct bt_hci_s *hci, bdaddr_t *bdaddr)
{
struct bt_device_s *slave;
evt_remote_name_req_complete params;
@@ -1290,7 +1290,7 @@ static inline void bt_hci_event_complete_status(struct bt_hci_s *hci,
}
static inline void bt_hci_event_complete_conn_cancel(struct bt_hci_s *hci,
- uint8_t status, a_bdaddr *bd_addr)
+ uint8_t status, bdaddr_t *bd_addr)
{
create_conn_cancel_rp params = {
.status = status,
@@ -1324,7 +1324,7 @@ static inline void bt_hci_event_encrypt_change(struct bt_hci_s *hci,
}
static inline void bt_hci_event_complete_name_cancel(struct bt_hci_s *hci,
- a_bdaddr *bd_addr)
+ bdaddr_t *bd_addr)
{
remote_name_req_cancel_rp params = {
.status = HCI_INVALID_PARAMETERS,
@@ -2134,7 +2134,7 @@ static int bt_hci_bdaddr_set(struct HCIInfo *info, const uint8_t *bd_addr)
{
struct bt_hci_s *hci = hci_from_info(info);
- bacpy(&hci->device.bd_addr, (const a_bdaddr *) bd_addr);
+ bacpy(&hci->device.bd_addr, (const bdaddr_t *) bd_addr);
return 0;
}
diff --git a/hw/bt.h b/hw/bt.h
index 076af40b5..4a702adef 100644
--- a/hw/bt.h
+++ b/hw/bt.h
@@ -26,20 +26,20 @@
/* BD Address */
typedef struct {
uint8_t b[6];
-} __attribute__((packed)) a_bdaddr;
+} __attribute__((packed)) bdaddr_t;
-#define BDADDR_ANY (&(a_bdaddr) {{0, 0, 0, 0, 0, 0}})
-#define BDADDR_ALL (&(a_bdaddr) {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}})
-#define BDADDR_LOCAL (&(a_bdaddr) {{0, 0, 0, 0xff, 0xff, 0xff}})
+#define BDADDR_ANY (&(bdaddr_t) {{0, 0, 0, 0, 0, 0}})
+#define BDADDR_ALL (&(bdaddr_t) {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}})
+#define BDADDR_LOCAL (&(bdaddr_t) {{0, 0, 0, 0xff, 0xff, 0xff}})
/* Copy, swap, convert BD Address */
-static inline int bacmp(const a_bdaddr *ba1, const a_bdaddr *ba2)
+static inline int bacmp(const bdaddr_t *ba1, const bdaddr_t *ba2)
{
- return memcmp(ba1, ba2, sizeof(a_bdaddr));
+ return memcmp(ba1, ba2, sizeof(bdaddr_t));
}
-static inline void bacpy(a_bdaddr *dst, const a_bdaddr *src)
+static inline void bacpy(bdaddr_t *dst, const bdaddr_t *src)
{
- memcpy(dst, src, sizeof(a_bdaddr));
+ memcpy(dst, src, sizeof(bdaddr_t));
}
#define BAINIT(orig) { .b = { \
@@ -71,7 +71,7 @@ struct bt_link_s {
struct bt_device_s {
int lt_addr;
- a_bdaddr bd_addr;
+ bdaddr_t bd_addr;
int mtu;
int setup;
struct bt_scatternet_s *net;
@@ -451,7 +451,7 @@ typedef struct {
typedef struct {
uint8_t status;
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
} __attribute__ ((packed)) status_bdaddr_rp;
#define STATUS_BDADDR_RP_SIZE 7
@@ -471,7 +471,7 @@ typedef struct {
#define OCF_CREATE_CONN 0x0005
typedef struct {
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint16_t pkt_type;
uint8_t pscan_rep_mode;
uint8_t pscan_mode;
@@ -497,33 +497,33 @@ typedef struct {
#define OCF_CREATE_CONN_CANCEL 0x0008
typedef struct {
uint8_t status;
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
} __attribute__ ((packed)) create_conn_cancel_cp;
#define CREATE_CONN_CANCEL_CP_SIZE 6
typedef struct {
uint8_t status;
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
} __attribute__ ((packed)) create_conn_cancel_rp;
#define CREATE_CONN_CANCEL_RP_SIZE 7
#define OCF_ACCEPT_CONN_REQ 0x0009
typedef struct {
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint8_t role;
} __attribute__ ((packed)) accept_conn_req_cp;
#define ACCEPT_CONN_REQ_CP_SIZE 7
#define OCF_REJECT_CONN_REQ 0x000A
typedef struct {
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint8_t reason;
} __attribute__ ((packed)) reject_conn_req_cp;
#define REJECT_CONN_REQ_CP_SIZE 7
#define OCF_LINK_KEY_REPLY 0x000B
typedef struct {
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint8_t link_key[16];
} __attribute__ ((packed)) link_key_reply_cp;
#define LINK_KEY_REPLY_CP_SIZE 22
@@ -532,7 +532,7 @@ typedef struct {
#define OCF_PIN_CODE_REPLY 0x000D
typedef struct {
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint8_t pin_len;
uint8_t pin_code[16];
} __attribute__ ((packed)) pin_code_reply_cp;
@@ -574,7 +574,7 @@ typedef struct {
#define OCF_REMOTE_NAME_REQ 0x0019
typedef struct {
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_mode;
uint16_t clock_offset;
@@ -583,13 +583,13 @@ typedef struct {
#define OCF_REMOTE_NAME_REQ_CANCEL 0x001A
typedef struct {
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
} __attribute__ ((packed)) remote_name_req_cancel_cp;
#define REMOTE_NAME_REQ_CANCEL_CP_SIZE 6
typedef struct {
uint8_t status;
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
} __attribute__ ((packed)) remote_name_req_cancel_rp;
#define REMOTE_NAME_REQ_CANCEL_RP_SIZE 7
@@ -646,7 +646,7 @@ typedef struct {
#define OCF_ACCEPT_SYNC_CONN_REQ 0x0029
typedef struct {
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint32_t tx_bandwith;
uint32_t rx_bandwith;
uint16_t max_latency;
@@ -658,7 +658,7 @@ typedef struct {
#define OCF_REJECT_SYNC_CONN_REQ 0x002A
typedef struct {
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint8_t reason;
} __attribute__ ((packed)) reject_sync_conn_req_cp;
#define REJECT_SYNC_CONN_REQ_CP_SIZE 7
@@ -734,7 +734,7 @@ typedef struct {
#define OCF_SWITCH_ROLE 0x000B
typedef struct {
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint8_t role;
} __attribute__ ((packed)) switch_role_cp;
#define SWITCH_ROLE_CP_SIZE 7
@@ -847,7 +847,7 @@ typedef struct {
#define OCF_READ_STORED_LINK_KEY 0x000D
typedef struct {
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint8_t read_all;
} __attribute__ ((packed)) read_stored_link_key_cp;
#define READ_STORED_LINK_KEY_CP_SIZE 7
@@ -872,7 +872,7 @@ typedef struct {
#define OCF_DELETE_STORED_LINK_KEY 0x0012
typedef struct {
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint8_t delete_all;
} __attribute__ ((packed)) delete_stored_link_key_cp;
#define DELETE_STORED_LINK_KEY_CP_SIZE 7
@@ -1238,7 +1238,7 @@ typedef struct {
#define OCF_READ_BD_ADDR 0x0009
typedef struct {
uint8_t status;
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
} __attribute__ ((packed)) read_bd_addr_rp;
#define READ_BD_ADDR_RP_SIZE 7
@@ -1317,7 +1317,7 @@ typedef struct {
#define EVT_INQUIRY_RESULT 0x02
typedef struct {
uint8_t num_responses;
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_period_mode;
uint8_t pscan_mode;
@@ -1330,7 +1330,7 @@ typedef struct {
typedef struct {
uint8_t status;
uint16_t handle;
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint8_t link_type;
uint8_t encr_mode;
} __attribute__ ((packed)) evt_conn_complete;
@@ -1338,7 +1338,7 @@ typedef struct {
#define EVT_CONN_REQUEST 0x04
typedef struct {
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint8_t dev_class[3];
uint8_t link_type;
} __attribute__ ((packed)) evt_conn_request;
@@ -1362,7 +1362,7 @@ typedef struct {
#define EVT_REMOTE_NAME_REQ_COMPLETE 0x07
typedef struct {
uint8_t status;
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
char name[248];
} __attribute__ ((packed)) evt_remote_name_req_complete;
#define EVT_REMOTE_NAME_REQ_COMPLETE_SIZE 255
@@ -1447,7 +1447,7 @@ typedef struct {
#define EVT_ROLE_CHANGE 0x12
typedef struct {
uint8_t status;
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint8_t role;
} __attribute__ ((packed)) evt_role_change;
#define EVT_ROLE_CHANGE_SIZE 8
@@ -1480,19 +1480,19 @@ typedef struct {
#define EVT_PIN_CODE_REQ 0x16
typedef struct {
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
} __attribute__ ((packed)) evt_pin_code_req;
#define EVT_PIN_CODE_REQ_SIZE 6
#define EVT_LINK_KEY_REQ 0x17
typedef struct {
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
} __attribute__ ((packed)) evt_link_key_req;
#define EVT_LINK_KEY_REQ_SIZE 6
#define EVT_LINK_KEY_NOTIFY 0x18
typedef struct {
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint8_t link_key[16];
uint8_t key_type;
} __attribute__ ((packed)) evt_link_key_notify;
@@ -1537,7 +1537,7 @@ typedef struct {
#define EVT_PSCAN_REP_MODE_CHANGE 0x20
typedef struct {
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint8_t pscan_rep_mode;
} __attribute__ ((packed)) evt_pscan_rep_mode_change;
#define EVT_PSCAN_REP_MODE_CHANGE_SIZE 7
@@ -1555,7 +1555,7 @@ typedef struct {
#define EVT_INQUIRY_RESULT_WITH_RSSI 0x22
typedef struct {
uint8_t num_responses;
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_period_mode;
uint8_t dev_class[3];
@@ -1565,7 +1565,7 @@ typedef struct {
#define INQUIRY_INFO_WITH_RSSI_SIZE 15
typedef struct {
uint8_t num_responses;
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_period_mode;
uint8_t pscan_mode;
@@ -1589,7 +1589,7 @@ typedef struct {
typedef struct {
uint8_t status;
uint16_t handle;
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint8_t link_type;
uint8_t trans_interval;
uint8_t retrans_window;
@@ -1623,7 +1623,7 @@ typedef struct {
#define EVT_EXTENDED_INQUIRY_RESULT 0x2F
typedef struct {
- a_bdaddr bdaddr;
+ bdaddr_t bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_period_mode;
uint8_t dev_class[3];
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index 09bd10cfc..7e95f10bd 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -1214,7 +1214,7 @@ static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
/* Thinking about changing bank base? First, drop the dirty bitmap information
* on the current location, otherwise we lose this pointer forever */
if (s->vga.lfb_vram_mapped) {
- a_target_phys_addr base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
+ target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
}
s->cirrus_bank_base[bank_index] = offset;
@@ -1988,7 +1988,7 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
*
***************************************/
-static uint32_t cirrus_vga_mem_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
{
CirrusVGAState *s = opaque;
unsigned bank_index;
@@ -2032,7 +2032,7 @@ static uint32_t cirrus_vga_mem_readb(void *opaque, a_target_phys_addr addr)
return val;
}
-static uint32_t cirrus_vga_mem_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -2045,7 +2045,7 @@ static uint32_t cirrus_vga_mem_readw(void *opaque, a_target_phys_addr addr)
return v;
}
-static uint32_t cirrus_vga_mem_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -2062,7 +2062,7 @@ static uint32_t cirrus_vga_mem_readl(void *opaque, a_target_phys_addr addr)
return v;
}
-static void cirrus_vga_mem_writeb(void *opaque, a_target_phys_addr addr,
+static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t mem_value)
{
CirrusVGAState *s = opaque;
@@ -2127,7 +2127,7 @@ static void cirrus_vga_mem_writeb(void *opaque, a_target_phys_addr addr,
}
}
-static void cirrus_vga_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
@@ -2138,7 +2138,7 @@ static void cirrus_vga_mem_writew(void *opaque, a_target_phys_addr addr, uint32_
#endif
}
-static void cirrus_vga_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
@@ -2341,7 +2341,7 @@ static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
*
***************************************/
-static uint32_t cirrus_linear_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
{
CirrusVGAState *s = opaque;
uint32_t ret;
@@ -2369,7 +2369,7 @@ static uint32_t cirrus_linear_readb(void *opaque, a_target_phys_addr addr)
return ret;
}
-static uint32_t cirrus_linear_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -2382,7 +2382,7 @@ static uint32_t cirrus_linear_readw(void *opaque, a_target_phys_addr addr)
return v;
}
-static uint32_t cirrus_linear_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -2399,7 +2399,7 @@ static uint32_t cirrus_linear_readl(void *opaque, a_target_phys_addr addr)
return v;
}
-static void cirrus_linear_writeb(void *opaque, a_target_phys_addr addr,
+static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
CirrusVGAState *s = opaque;
@@ -2440,7 +2440,7 @@ static void cirrus_linear_writeb(void *opaque, a_target_phys_addr addr,
}
}
-static void cirrus_linear_writew(void *opaque, a_target_phys_addr addr,
+static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@@ -2452,7 +2452,7 @@ static void cirrus_linear_writew(void *opaque, a_target_phys_addr addr,
#endif
}
-static void cirrus_linear_writel(void *opaque, a_target_phys_addr addr,
+static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@@ -2488,7 +2488,7 @@ static CPUWriteMemoryFunc * const cirrus_linear_write[3] = {
***************************************/
-static uint32_t cirrus_linear_bitblt_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
{
uint32_t ret;
@@ -2497,7 +2497,7 @@ static uint32_t cirrus_linear_bitblt_readb(void *opaque, a_target_phys_addr addr
return ret;
}
-static uint32_t cirrus_linear_bitblt_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -2510,7 +2510,7 @@ static uint32_t cirrus_linear_bitblt_readw(void *opaque, a_target_phys_addr addr
return v;
}
-static uint32_t cirrus_linear_bitblt_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -2527,7 +2527,7 @@ static uint32_t cirrus_linear_bitblt_readl(void *opaque, a_target_phys_addr addr
return v;
}
-static void cirrus_linear_bitblt_writeb(void *opaque, a_target_phys_addr addr,
+static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
CirrusVGAState *s = opaque;
@@ -2541,7 +2541,7 @@ static void cirrus_linear_bitblt_writeb(void *opaque, a_target_phys_addr addr,
}
}
-static void cirrus_linear_bitblt_writew(void *opaque, a_target_phys_addr addr,
+static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@@ -2553,7 +2553,7 @@ static void cirrus_linear_bitblt_writew(void *opaque, a_target_phys_addr addr,
#endif
}
-static void cirrus_linear_bitblt_writel(void *opaque, a_target_phys_addr addr,
+static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@@ -2855,7 +2855,7 @@ static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
*
***************************************/
-static uint32_t cirrus_mmio_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
{
CirrusVGAState *s = opaque;
@@ -2868,7 +2868,7 @@ static uint32_t cirrus_mmio_readb(void *opaque, a_target_phys_addr addr)
}
}
-static uint32_t cirrus_mmio_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -2881,7 +2881,7 @@ static uint32_t cirrus_mmio_readw(void *opaque, a_target_phys_addr addr)
return v;
}
-static uint32_t cirrus_mmio_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -2898,7 +2898,7 @@ static uint32_t cirrus_mmio_readl(void *opaque, a_target_phys_addr addr)
return v;
}
-static void cirrus_mmio_writeb(void *opaque, a_target_phys_addr addr,
+static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
CirrusVGAState *s = opaque;
@@ -2912,7 +2912,7 @@ static void cirrus_mmio_writeb(void *opaque, a_target_phys_addr addr,
}
}
-static void cirrus_mmio_writew(void *opaque, a_target_phys_addr addr,
+static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@@ -2924,7 +2924,7 @@ static void cirrus_mmio_writew(void *opaque, a_target_phys_addr addr,
#endif
}
-static void cirrus_mmio_writel(void *opaque, a_target_phys_addr addr,
+static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
diff --git a/hw/cs4231.c b/hw/cs4231.c
index e4708f877..843f86ed6 100644
--- a/hw/cs4231.c
+++ b/hw/cs4231.c
@@ -64,7 +64,7 @@ static void cs_reset(void *opaque)
s->dregs[25] = CS_VER;
}
-static uint32_t cs_mem_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
{
CSState *s = opaque;
uint32_t saddr, ret;
@@ -90,7 +90,7 @@ static uint32_t cs_mem_readl(void *opaque, a_target_phys_addr addr)
return ret;
}
-static void cs_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
CSState *s = opaque;
uint32_t saddr;
diff --git a/hw/cuda.c b/hw/cuda.c
index 1076ef936..552e422a7 100644
--- a/hw/cuda.c
+++ b/hw/cuda.c
@@ -250,7 +250,7 @@ static void cuda_timer1(void *opaque)
cuda_update_irq(s);
}
-static uint32_t cuda_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
{
CUDAState *s = opaque;
uint32_t val;
@@ -321,7 +321,7 @@ static uint32_t cuda_readb(void *opaque, a_target_phys_addr addr)
return val;
}
-static void cuda_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
CUDAState *s = opaque;
@@ -612,20 +612,20 @@ static void cuda_receive_packet_from_host(CUDAState *s,
}
}
-static void cuda_writew (void *opaque, a_target_phys_addr addr, uint32_t value)
+static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
}
-static void cuda_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
+static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
}
-static uint32_t cuda_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
{
return 0;
}
-static uint32_t cuda_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
{
return 0;
}
diff --git a/hw/dma.c b/hw/dma.c
index 3e70105af..f418e4252 100644
--- a/hw/dma.c
+++ b/hw/dma.c
@@ -401,7 +401,7 @@ void DMA_register_channel (int nchan,
int DMA_read_memory (int nchan, void *buf, int pos, int len)
{
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
- a_target_phys_addr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
+ target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
int i;
@@ -423,7 +423,7 @@ int DMA_read_memory (int nchan, void *buf, int pos, int len)
int DMA_write_memory (int nchan, void *buf, int pos, int len)
{
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
- a_target_phys_addr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
+ target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
int i;
diff --git a/hw/dp8393x.c b/hw/dp8393x.c
index a972970b7..067831d1d 100644
--- a/hw/dp8393x.c
+++ b/hw/dp8393x.c
@@ -166,7 +166,7 @@ typedef struct dp8393xState {
int loopback_packet;
/* Memory access */
- void (*memory_rw)(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write);
+ void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
void* mem_opaque;
} dp8393xState;
@@ -601,7 +601,7 @@ static void dp8393x_watchdog(void *opaque)
dp8393x_update_irq(s);
}
-static uint32_t dp8393x_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t dp8393x_readw(void *opaque, target_phys_addr_t addr)
{
dp8393xState *s = opaque;
int reg;
@@ -614,13 +614,13 @@ static uint32_t dp8393x_readw(void *opaque, a_target_phys_addr addr)
return read_register(s, reg);
}
-static uint32_t dp8393x_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t dp8393x_readb(void *opaque, target_phys_addr_t addr)
{
uint16_t v = dp8393x_readw(opaque, addr & ~0x1);
return (v >> (8 * (addr & 0x1))) & 0xff;
}
-static uint32_t dp8393x_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t dp8393x_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
v = dp8393x_readw(opaque, addr);
@@ -628,7 +628,7 @@ static uint32_t dp8393x_readl(void *opaque, a_target_phys_addr addr)
return v;
}
-static void dp8393x_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void dp8393x_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
dp8393xState *s = opaque;
int reg;
@@ -642,7 +642,7 @@ static void dp8393x_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
write_register(s, reg, (uint16_t)val);
}
-static void dp8393x_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void dp8393x_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
uint16_t old_val = dp8393x_readw(opaque, addr & ~0x1);
@@ -657,7 +657,7 @@ static void dp8393x_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
dp8393x_writew(opaque, addr & ~0x1, val);
}
-static void dp8393x_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void dp8393x_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
dp8393x_writew(opaque, addr, val & 0xffff);
dp8393x_writew(opaque, addr + 2, (val >> 16) & 0xffff);
@@ -872,9 +872,9 @@ static void nic_cleanup(VLANClientState *vc)
qemu_free(s);
}
-void dp83932_init(NICInfo *nd, a_target_phys_addr base, int it_shift,
+void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
qemu_irq irq, void* mem_opaque,
- void (*memory_rw)(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write))
+ void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write))
{
dp8393xState *s;
diff --git a/hw/ds1225y.c b/hw/ds1225y.c
index b3dbc46c8..009d12745 100644
--- a/hw/ds1225y.c
+++ b/hw/ds1225y.c
@@ -34,12 +34,12 @@ typedef struct ds1225y_t
QEMUFile *file;
uint8_t *contents;
uint8_t protection;
-} a_ds1225y;
+} ds1225y_t;
-static uint32_t nvram_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
{
- a_ds1225y *s = opaque;
+ ds1225y_t *s = opaque;
uint32_t val;
val = s->contents[addr];
@@ -50,7 +50,7 @@ static uint32_t nvram_readb (void *opaque, a_target_phys_addr addr)
return val;
}
-static uint32_t nvram_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
{
uint32_t v;
v = nvram_readb(opaque, addr);
@@ -58,7 +58,7 @@ static uint32_t nvram_readw (void *opaque, a_target_phys_addr addr)
return v;
}
-static uint32_t nvram_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t v;
v = nvram_readb(opaque, addr);
@@ -68,9 +68,9 @@ static uint32_t nvram_readl (void *opaque, a_target_phys_addr addr)
return v;
}
-static void nvram_writeb (void *opaque, a_target_phys_addr addr, uint32_t val)
+static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
{
- a_ds1225y *s = opaque;
+ ds1225y_t *s = opaque;
#ifdef DEBUG_NVRAM
printf("nvram: write 0x%x at " TARGET_FMT_lx "\n", val, addr);
@@ -84,13 +84,13 @@ static void nvram_writeb (void *opaque, a_target_phys_addr addr, uint32_t val)
}
}
-static void nvram_writew (void *opaque, a_target_phys_addr addr, uint32_t val)
+static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
{
nvram_writeb(opaque, addr, val & 0xff);
nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff);
}
-static void nvram_writel (void *opaque, a_target_phys_addr addr, uint32_t val)
+static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
{
nvram_writeb(opaque, addr, val & 0xff);
nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff);
@@ -98,9 +98,9 @@ static void nvram_writel (void *opaque, a_target_phys_addr addr, uint32_t val)
nvram_writeb(opaque, addr + 3, (val >> 24) & 0xff);
}
-static void nvram_writeb_protected (void *opaque, a_target_phys_addr addr, uint32_t val)
+static void nvram_writeb_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
{
- a_ds1225y *s = opaque;
+ ds1225y_t *s = opaque;
if (s->protection != 7) {
#ifdef DEBUG_NVRAM
@@ -112,13 +112,13 @@ static void nvram_writeb_protected (void *opaque, a_target_phys_addr addr, uint3
nvram_writeb(opaque, addr, val);
}
-static void nvram_writew_protected (void *opaque, a_target_phys_addr addr, uint32_t val)
+static void nvram_writew_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
{
nvram_writeb_protected(opaque, addr, val & 0xff);
nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff);
}
-static void nvram_writel_protected (void *opaque, a_target_phys_addr addr, uint32_t val)
+static void nvram_writel_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
{
nvram_writeb_protected(opaque, addr, val & 0xff);
nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff);
@@ -145,13 +145,13 @@ static CPUWriteMemoryFunc * const nvram_write_protected[] = {
};
/* Initialisation routine */
-void *ds1225y_init(a_target_phys_addr mem_base, const char *filename)
+void *ds1225y_init(target_phys_addr_t mem_base, const char *filename)
{
- a_ds1225y *s;
+ ds1225y_t *s;
int mem_indexRW, mem_indexRP;
QEMUFile *file;
- s = qemu_mallocz(sizeof(a_ds1225y));
+ s = qemu_mallocz(sizeof(ds1225y_t));
s->chip_size = 0x2000; /* Fixed for ds1225y chip: 8 KiB */
s->contents = qemu_mallocz(s->chip_size);
s->protection = 7;
diff --git a/hw/dummy_m68k.c b/hw/dummy_m68k.c
index 10e5741d4..ce45a597d 100644
--- a/hw/dummy_m68k.c
+++ b/hw/dummy_m68k.c
@@ -16,7 +16,7 @@
/* Board init. */
-static void dummy_m68k_init(a_ram_addr ram_size,
+static void dummy_m68k_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@@ -24,7 +24,7 @@ static void dummy_m68k_init(a_ram_addr ram_size,
CPUState *env;
int kernel_size;
uint64_t elf_entry;
- a_target_phys_addr entry;
+ target_phys_addr_t entry;
if (!cpu_model)
cpu_model = "cfv4e";
diff --git a/hw/e1000.c b/hw/e1000.c
index e4a241f4e..95c471c62 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -478,7 +478,7 @@ process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
}
static uint32_t
-txdesc_writeback(a_target_phys_addr base, struct e1000_tx_desc *dp)
+txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp)
{
uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
@@ -495,7 +495,7 @@ txdesc_writeback(a_target_phys_addr base, struct e1000_tx_desc *dp)
static void
start_xmit(E1000State *s)
{
- a_target_phys_addr base;
+ target_phys_addr_t base;
struct e1000_tx_desc desc;
uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
@@ -613,7 +613,7 @@ e1000_receive(VLANClientState *vc, const uint8_t *buf, size_t size)
{
E1000State *s = vc->opaque;
struct e1000_rx_desc desc;
- a_target_phys_addr base;
+ target_phys_addr_t base;
unsigned int n, rdt;
uint32_t rdh_start;
uint16_t vlan_special = 0;
@@ -814,7 +814,7 @@ static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
static void
-e1000_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
+e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
E1000State *s = opaque;
unsigned int index = (addr & 0x1ffff) >> 2;
@@ -832,7 +832,7 @@ e1000_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
}
static void
-e1000_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
+e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
// emulate hw without byte enables: no RMW
e1000_mmio_writel(opaque, addr & ~3,
@@ -840,7 +840,7 @@ e1000_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
}
static void
-e1000_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
+e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
// emulate hw without byte enables: no RMW
e1000_mmio_writel(opaque, addr & ~3,
@@ -848,7 +848,7 @@ e1000_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
}
static uint32_t
-e1000_mmio_readl(void *opaque, a_target_phys_addr addr)
+e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
{
E1000State *s = opaque;
unsigned int index = (addr & 0x1ffff) >> 2;
@@ -866,14 +866,14 @@ e1000_mmio_readl(void *opaque, a_target_phys_addr addr)
}
static uint32_t
-e1000_mmio_readb(void *opaque, a_target_phys_addr addr)
+e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
{
return ((e1000_mmio_readl(opaque, addr & ~3)) >>
(8 * (addr & 3))) & 0xff;
}
static uint32_t
-e1000_mmio_readw(void *opaque, a_target_phys_addr addr)
+e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
{
return ((e1000_mmio_readl(opaque, addr & ~3)) >>
(8 * (addr & 3))) & 0xffff;
diff --git a/hw/eccmemctl.c b/hw/eccmemctl.c
index 7eaa1e583..12c386b05 100644
--- a/hw/eccmemctl.c
+++ b/hw/eccmemctl.c
@@ -133,7 +133,7 @@ typedef struct ECCState {
uint32_t version;
} ECCState;
-static void ecc_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
ECCState *s = opaque;
@@ -175,7 +175,7 @@ static void ecc_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
}
}
-static uint32_t ecc_mem_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
{
ECCState *s = opaque;
uint32_t ret = 0;
@@ -233,7 +233,7 @@ static CPUWriteMemoryFunc * const ecc_mem_write[3] = {
ecc_mem_writel,
};
-static void ecc_diag_mem_writeb(void *opaque, a_target_phys_addr addr,
+static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
ECCState *s = opaque;
@@ -242,7 +242,7 @@ static void ecc_diag_mem_writeb(void *opaque, a_target_phys_addr addr,
s->diag[addr & ECC_DIAG_MASK] = val;
}
-static uint32_t ecc_diag_mem_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr)
{
ECCState *s = opaque;
uint32_t ret = s->diag[(int)addr];
diff --git a/hw/eepro100.c b/hw/eepro100.c
index aac7bdc22..3f84e26f5 100644
--- a/hw/eepro100.c
+++ b/hw/eepro100.c
@@ -144,7 +144,7 @@ typedef struct {
//~ int32_t tx_buf_size0; /* Length of Tx hdr. */
//~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
//~ int32_t tx_buf_size1; /* Length of Tx data. */
-} a_eepro100_tx;
+} eepro100_tx_t;
/* Receive frame descriptor. */
typedef struct {
@@ -155,7 +155,7 @@ typedef struct {
uint16_t count;
uint16_t size;
char packet[MAX_ETH_FRAME_SIZE + 4];
-} a_eepro100_rx;
+} eepro100_rx_t;
typedef struct {
uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
@@ -167,7 +167,7 @@ typedef struct {
uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
uint16_t xmt_tco_frames, rcv_tco_frames;
uint32_t complete;
-} a_eepro100_stats;
+} eepro100_stats_t;
typedef enum {
cu_idle = 0,
@@ -175,14 +175,14 @@ typedef enum {
cu_active = 2,
cu_lpq_active = 2,
cu_hqp_active = 3
-} a_cu_state;
+} cu_state_t;
typedef enum {
ru_idle = 0,
ru_suspended = 1,
ru_no_resources = 2,
ru_ready = 4
-} a_ru_state;
+} ru_state_t;
typedef struct {
PCIDevice dev;
@@ -213,7 +213,7 @@ typedef struct {
uint8_t macaddr[6];
uint32_t statcounter[19];
uint16_t mdimem[32];
- a_eeprom *eeprom;
+ eeprom_t *eeprom;
uint32_t device; /* device variant */
uint32_t pointer;
/* (cu_base + cu_offset) address the next command block in the command block list. */
@@ -222,8 +222,8 @@ typedef struct {
/* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
uint32_t ru_base; /* RU base address */
uint32_t ru_offset; /* RU address offset */
- uint32_t statsaddr; /* pointer to a_eepro100_stats */
- a_eepro100_stats statistics; /* statistical counters */
+ uint32_t statsaddr; /* pointer to eepro100_stats_t */
+ eepro100_stats_t statistics; /* statistical counters */
#if 0
uint16_t status;
#endif
@@ -600,22 +600,22 @@ enum commands {
CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
};
-static a_cu_state get_cu_state(EEPRO100State * s)
+static cu_state_t get_cu_state(EEPRO100State * s)
{
return ((s->mem[SCBStatus] >> 6) & 0x03);
}
-static void set_cu_state(EEPRO100State * s, a_cu_state state)
+static void set_cu_state(EEPRO100State * s, cu_state_t state)
{
s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6);
}
-static a_ru_state get_ru_state(EEPRO100State * s)
+static ru_state_t get_ru_state(EEPRO100State * s)
{
return ((s->mem[SCBStatus] >> 2) & 0x0f);
}
-static void set_ru_state(EEPRO100State * s, a_ru_state state)
+static void set_ru_state(EEPRO100State * s, ru_state_t state)
{
s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2);
}
@@ -639,7 +639,7 @@ static void dump_statistics(EEPRO100State * s)
static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
{
- a_eepro100_tx tx;
+ eepro100_tx_t tx;
uint32_t cb_address;
switch (val) {
case CU_NOP:
@@ -915,7 +915,7 @@ static uint16_t eepro100_read_eeprom(EEPRO100State * s)
return val;
}
-static void eepro100_write_eeprom(a_eeprom * eeprom, uint8_t val)
+static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
{
TRACE(EEPROM, logout("val=0x%02x\n", val));
@@ -1099,7 +1099,7 @@ static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
typedef struct {
uint32_t st_sign; /* Self Test Signature */
uint32_t st_result; /* Self Test Results */
-} a_eepro100_selftest;
+} eepro100_selftest_t;
static uint32_t eepro100_read_port(EEPRO100State * s)
{
@@ -1117,7 +1117,7 @@ static void eepro100_write_port(EEPRO100State * s, uint32_t val)
break;
case PORT_SELFTEST:
TRACE(OTHER, logout("selftest address=0x%08x\n", address));
- a_eepro100_selftest data;
+ eepro100_selftest_t data;
cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
data.st_sign = 0xffffffff;
data.st_result = 0;
@@ -1398,42 +1398,42 @@ static void pci_map(PCIDevice * pci_dev, int region_num,
*
****************************************************************************/
-static void pci_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
eepro100_write1(s, addr, val);
}
-static void pci_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
eepro100_write2(s, addr, val);
}
-static void pci_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
eepro100_write4(s, addr, val);
}
-static uint32_t pci_mmio_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s\n", regname(addr));
return eepro100_read1(s, addr);
}
-static uint32_t pci_mmio_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s\n", regname(addr));
return eepro100_read2(s, addr);
}
-static uint32_t pci_mmio_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s\n", regname(addr));
@@ -1541,9 +1541,9 @@ static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size
}
//~ !!!
//~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
- a_eepro100_rx rx;
+ eepro100_rx_t rx;
cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
- offsetof(a_eepro100_rx, packet));
+ offsetof(eepro100_rx_t, packet));
uint16_t rfd_command = le16_to_cpu(rx.command);
uint16_t rfd_size = le16_to_cpu(rx.size);
assert(size <= rfd_size);
@@ -1552,9 +1552,9 @@ static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size
}
TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
- stw_phys(s->ru_base + s->ru_offset + offsetof(a_eepro100_rx, status),
+ stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
rfd_status);
- stw_phys(s->ru_base + s->ru_offset + offsetof(a_eepro100_rx, count), size);
+ stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
/* Early receive interrupt not supported. */
//~ eepro100_er_interrupt(s);
/* Receive CRC Transfer not supported. */
@@ -1562,7 +1562,7 @@ static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size
/* TODO: check stripping enable bit. */
//~ assert(!(s->configuration[17] & 1));
cpu_physical_memory_write(s->ru_base + s->ru_offset +
- offsetof(a_eepro100_rx, packet), buf, size);
+ offsetof(eepro100_rx_t, packet), buf, size);
s->statistics.rx_good_frames++;
eepro100_fr_interrupt(s);
s->ru_offset = le32_to_cpu(rx.link);
diff --git a/hw/eeprom93xx.c b/hw/eeprom93xx.c
index f3ac81611..66dfc43d5 100644
--- a/hw/eeprom93xx.c
+++ b/hw/eeprom93xx.c
@@ -71,7 +71,7 @@ static const char *opstring[] = {
};
#endif
-struct eeprom {
+struct _eeprom_t {
uint8_t tick;
uint8_t address;
uint8_t command;
@@ -93,7 +93,7 @@ static void eeprom_save(QEMUFile *f, void *opaque)
{
/* Save EEPROM data. */
unsigned address;
- a_eeprom *eeprom = (a_eeprom *)opaque;
+ eeprom_t *eeprom = (eeprom_t *)opaque;
qemu_put_byte(f, eeprom->tick);
qemu_put_byte(f, eeprom->address);
@@ -116,7 +116,7 @@ static int eeprom_load(QEMUFile *f, void *opaque, int version_id)
{
/* Load EEPROM data from saved data if version and EEPROM size
of data and current EEPROM are identical. */
- a_eeprom *eeprom = (a_eeprom *)opaque;
+ eeprom_t *eeprom = (eeprom_t *)opaque;
int result = -EINVAL;
if (version_id >= OLD_EEPROM_VERSION) {
unsigned address;
@@ -150,7 +150,7 @@ static int eeprom_load(QEMUFile *f, void *opaque, int version_id)
return result;
}
-void eeprom93xx_write(a_eeprom *eeprom, int eecs, int eesk, int eedi)
+void eeprom93xx_write(eeprom_t *eeprom, int eecs, int eesk, int eedi)
{
uint8_t tick = eeprom->tick;
uint8_t eedo = eeprom->eedo;
@@ -275,7 +275,7 @@ void eeprom93xx_write(a_eeprom *eeprom, int eecs, int eesk, int eedi)
eeprom->command = command;
}
-uint16_t eeprom93xx_read(a_eeprom *eeprom)
+uint16_t eeprom93xx_read(eeprom_t *eeprom)
{
/* Return status of pin DO (0 or 1). */
logout("CS=%u DO=%u\n", eeprom->eecs, eeprom->eedo);
@@ -292,10 +292,10 @@ void eeprom93xx_reset(eeprom_t *eeprom)
}
#endif
-a_eeprom *eeprom93xx_new(uint16_t nwords)
+eeprom_t *eeprom93xx_new(uint16_t nwords)
{
/* Add a new EEPROM (with 16, 64 or 256 words). */
- a_eeprom *eeprom;
+ eeprom_t *eeprom;
uint8_t addrbits;
switch (nwords) {
@@ -313,7 +313,7 @@ a_eeprom *eeprom93xx_new(uint16_t nwords)
addrbits = 6;
}
- eeprom = (a_eeprom *)qemu_mallocz(sizeof(*eeprom) + nwords * 2);
+ eeprom = (eeprom_t *)qemu_mallocz(sizeof(*eeprom) + nwords * 2);
eeprom->size = nwords;
eeprom->addrbits = addrbits;
/* Output DO is tristate, read results in 1. */
@@ -324,7 +324,7 @@ a_eeprom *eeprom93xx_new(uint16_t nwords)
return eeprom;
}
-void eeprom93xx_free(a_eeprom *eeprom)
+void eeprom93xx_free(eeprom_t *eeprom)
{
/* Destroy EEPROM. */
logout("eeprom = 0x%p\n", eeprom);
@@ -332,7 +332,7 @@ void eeprom93xx_free(a_eeprom *eeprom)
qemu_free(eeprom);
}
-uint16_t *eeprom93xx_data(a_eeprom *eeprom)
+uint16_t *eeprom93xx_data(eeprom_t *eeprom)
{
/* Get EEPROM data array. */
return &eeprom->contents[0];
diff --git a/hw/eeprom93xx.h b/hw/eeprom93xx.h
index 72a7c81ef..47282d381 100644
--- a/hw/eeprom93xx.h
+++ b/hw/eeprom93xx.h
@@ -20,21 +20,21 @@
#ifndef EEPROM93XX_H
#define EEPROM93XX_H
-typedef struct eeprom a_eeprom;
+typedef struct _eeprom_t eeprom_t;
/* Create a new EEPROM with (nwords * 2) bytes. */
-a_eeprom *eeprom93xx_new(uint16_t nwords);
+eeprom_t *eeprom93xx_new(uint16_t nwords);
/* Destroy an existing EEPROM. */
-void eeprom93xx_free(a_eeprom *eeprom);
+void eeprom93xx_free(eeprom_t *eeprom);
/* Read from the EEPROM. */
-uint16_t eeprom93xx_read(a_eeprom *eeprom);
+uint16_t eeprom93xx_read(eeprom_t *eeprom);
/* Write to the EEPROM. */
-void eeprom93xx_write(a_eeprom *eeprom, int eecs, int eesk, int eedi);
+void eeprom93xx_write(eeprom_t *eeprom, int eecs, int eesk, int eedi);
/* Get EEPROM data array. */
-uint16_t *eeprom93xx_data(a_eeprom *eeprom);
+uint16_t *eeprom93xx_data(eeprom_t *eeprom);
#endif /* EEPROM93XX_H */
diff --git a/hw/elf_ops.h b/hw/elf_ops.h
index 7eac22552..8376465a1 100644
--- a/hw/elf_ops.h
+++ b/hw/elf_ops.h
@@ -74,7 +74,7 @@ static int glue(symfind, SZ)(const void *s0, const void *s1)
}
static const char *glue(lookup_symbol, SZ)(struct syminfo *s,
- a_target_phys_addr orig_addr)
+ target_phys_addr_t orig_addr)
{
struct elf_sym *syms = glue(s->disas_symtab.elf, SZ);
struct elf_sym key;
diff --git a/hw/escc.c b/hw/escc.c
index 1597f3636..382719ded 100644
--- a/hw/escc.c
+++ b/hw/escc.c
@@ -84,13 +84,13 @@
typedef enum {
chn_a, chn_b,
-} e_chn_id;
+} chn_id_t;
#define CHN_C(s) ((s)->chn == chn_b? 'b' : 'a')
typedef enum {
ser, kbd, mouse,
-} e_chn_type;
+} chn_type_t;
#define SERIO_QUEUE_SIZE 256
@@ -104,8 +104,8 @@ typedef struct ChannelState {
qemu_irq irq;
uint32_t reg;
uint32_t rxint, txint, rxint_under_svc, txint_under_svc;
- e_chn_id chn; // this channel, A (base+4) or B (base+0)
- e_chn_type type;
+ chn_id_t chn; // this channel, A (base+4) or B (base+0)
+ chn_type_t type;
struct ChannelState *otherchn;
uint8_t rx, tx, wregs[SERIAL_REGS], rregs[SERIAL_REGS];
SERIOQueue queue;
@@ -481,7 +481,7 @@ static void escc_update_parameters(ChannelState *s)
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
-static void escc_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void escc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
SerialState *serial = opaque;
ChannelState *s;
@@ -578,7 +578,7 @@ static void escc_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
}
}
-static uint32_t escc_mem_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t escc_mem_readb(void *opaque, target_phys_addr_t addr)
{
SerialState *serial = opaque;
ChannelState *s;
@@ -725,7 +725,7 @@ static int escc_load(QEMUFile *f, void *opaque, int version_id)
}
-int escc_init(a_target_phys_addr base, qemu_irq irqA, qemu_irq irqB,
+int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
CharDriverState *chrA, CharDriverState *chrB,
int clock, int it_shift)
{
@@ -890,7 +890,7 @@ static void sunmouse_event(void *opaque,
put_queue(s, 0);
}
-void slavio_serial_ms_kbd_init(a_target_phys_addr base, qemu_irq irq,
+void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
int disabled, int clock, int it_shift)
{
DeviceState *dev;
diff --git a/hw/escc.h b/hw/escc.h
index fe461f6e5..015b9d008 100644
--- a/hw/escc.h
+++ b/hw/escc.h
@@ -1,8 +1,8 @@
/* escc.c */
#define ESCC_SIZE 4
-int escc_init(a_target_phys_addr base, qemu_irq irqA, qemu_irq irqB,
+int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
CharDriverState *chrA, CharDriverState *chrB,
int clock, int it_shift);
-void slavio_serial_ms_kbd_init(a_target_phys_addr base, qemu_irq irq,
+void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
int disabled, int clock, int it_shift);
diff --git a/hw/esp.c b/hw/esp.c
index a8965e95d..9a5a8fbf7 100644
--- a/hw/esp.c
+++ b/hw/esp.c
@@ -439,7 +439,7 @@ static void parent_esp_reset(void *opaque, int irq, int level)
esp_reset(opaque);
}
-static uint32_t esp_mem_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
{
ESPState *s = opaque;
uint32_t saddr, old_val;
@@ -480,7 +480,7 @@ static uint32_t esp_mem_readb(void *opaque, a_target_phys_addr addr)
return s->rregs[saddr];
}
-static void esp_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
ESPState *s = opaque;
uint32_t saddr;
@@ -632,7 +632,7 @@ static const VMStateDescription vmstate_esp = {
}
};
-void esp_init(a_target_phys_addr espaddr, int it_shift,
+void esp_init(target_phys_addr_t espaddr, int it_shift,
espdma_memory_read_write dma_memory_read,
espdma_memory_read_write dma_memory_write,
void *dma_opaque, qemu_irq irq, qemu_irq *reset)
diff --git a/hw/etraxfs.c b/hw/etraxfs.c
index 50d9eb3e3..4f451c54c 100644
--- a/hw/etraxfs.c
+++ b/hw/etraxfs.c
@@ -45,7 +45,7 @@ static void main_cpu_reset(void *opaque)
}
static
-void bareetraxfs_init (a_ram_addr ram_size,
+void bareetraxfs_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@@ -59,9 +59,9 @@ void bareetraxfs_init (a_ram_addr ram_size,
int kernel_size;
DriveInfo *dinfo;
int i;
- a_ram_addr phys_ram;
- a_ram_addr phys_flash;
- a_ram_addr phys_intmem;
+ ram_addr_t phys_ram;
+ ram_addr_t phys_flash;
+ ram_addr_t phys_intmem;
/* init CPUs */
if (cpu_model == NULL) {
diff --git a/hw/etraxfs.h b/hw/etraxfs.h
index b3b122222..01fb9d3e8 100644
--- a/hw/etraxfs.h
+++ b/hw/etraxfs.h
@@ -25,4 +25,4 @@
#include "etraxfs_dma.h"
qemu_irq *cris_pic_init_cpu(CPUState *env);
-void *etraxfs_eth_init(NICInfo *nd, a_target_phys_addr base, int phyaddr);
+void *etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr);
diff --git a/hw/etraxfs_dma.c b/hw/etraxfs_dma.c
index 4b96cf815..15c8ad3dc 100644
--- a/hw/etraxfs_dma.c
+++ b/hw/etraxfs_dma.c
@@ -211,7 +211,7 @@ static inline int channel_en(struct fs_dma_ctrl *ctrl, int c)
&& ctrl->channels[c].client;
}
-static inline int fs_channel(a_target_phys_addr addr)
+static inline int fs_channel(target_phys_addr_t addr)
{
/* Every channel has a 0x2000 ctrl register map. */
return addr >> 13;
@@ -220,7 +220,7 @@ static inline int fs_channel(a_target_phys_addr addr)
#ifdef USE_THIS_DEAD_CODE
static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
{
- a_target_phys_addr addr = channel_reg(ctrl, c, RW_GROUP);
+ target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);
/* Load and decode. FIXME: handle endianness. */
cpu_physical_memory_read (addr,
@@ -252,7 +252,7 @@ static void dump_d(int ch, struct dma_descr_data *d)
static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
{
- a_target_phys_addr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
+ target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
/* Load and decode. FIXME: handle endianness. */
cpu_physical_memory_read (addr,
@@ -269,7 +269,7 @@ static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
{
- a_target_phys_addr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
+ target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
/* Load and decode. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
@@ -283,7 +283,7 @@ static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
{
- a_target_phys_addr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
+ target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
/* Encode and store. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
@@ -295,7 +295,7 @@ static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
{
- a_target_phys_addr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
+ target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
/* Encode and store. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
@@ -556,14 +556,14 @@ static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c)
return 0;
}
-static uint32_t dma_rinvalid (void *opaque, a_target_phys_addr addr)
+static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
{
hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr);
return 0;
}
static uint32_t
-dma_readl (void *opaque, a_target_phys_addr addr)
+dma_readl (void *opaque, target_phys_addr_t addr)
{
struct fs_dma_ctrl *ctrl = opaque;
int c;
@@ -591,7 +591,7 @@ dma_readl (void *opaque, a_target_phys_addr addr)
}
static void
-dma_winvalid (void *opaque, a_target_phys_addr addr, uint32_t value)
+dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
{
hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr);
}
@@ -608,7 +608,7 @@ dma_update_state(struct fs_dma_ctrl *ctrl, int c)
}
static void
-dma_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
+dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct fs_dma_ctrl *ctrl = opaque;
int c;
@@ -739,7 +739,7 @@ static void DMA_run(void *opaque)
qemu_bh_schedule_idle(etraxfs_dmac->bh);
}
-void *etraxfs_dmac_init(a_target_phys_addr base, int nr_channels)
+void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels)
{
struct fs_dma_ctrl *ctrl = NULL;
diff --git a/hw/etraxfs_dma.h b/hw/etraxfs_dma.h
index 4bca2d2d6..96408abab 100644
--- a/hw/etraxfs_dma.h
+++ b/hw/etraxfs_dma.h
@@ -13,7 +13,7 @@ struct etraxfs_dma_client
} client;
};
-void *etraxfs_dmac_init(a_target_phys_addr base, int nr_channels);
+void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels);
void etraxfs_dmac_connect(void *opaque, int channel, qemu_irq *line,
int input);
void etraxfs_dmac_connect_client(void *opaque, int c,
diff --git a/hw/etraxfs_eth.c b/hw/etraxfs_eth.c
index 853752875..54786c5e9 100644
--- a/hw/etraxfs_eth.c
+++ b/hw/etraxfs_eth.c
@@ -365,7 +365,7 @@ static void eth_validate_duplex(struct fs_eth *eth)
}
}
-static uint32_t eth_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
{
struct fs_eth *eth = opaque;
uint32_t r = 0;
@@ -409,7 +409,7 @@ static void eth_update_ma(struct fs_eth *eth, int ma)
}
static void
-eth_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
+eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct fs_eth *eth = opaque;
@@ -564,7 +564,7 @@ static void eth_cleanup(VLANClientState *vc)
qemu_free(eth);
}
-void *etraxfs_eth_init(NICInfo *nd, a_target_phys_addr base, int phyaddr)
+void *etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr)
{
struct etraxfs_dma_client *dma = NULL;
struct fs_eth *eth = NULL;
diff --git a/hw/etraxfs_pic.c b/hw/etraxfs_pic.c
index 9140caad8..b2c485994 100644
--- a/hw/etraxfs_pic.c
+++ b/hw/etraxfs_pic.c
@@ -77,7 +77,7 @@ static void pic_update(struct etrax_pic *fs)
qemu_set_irq(fs->parent_irq, !!vector);
}
-static uint32_t pic_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
{
struct etrax_pic *fs = opaque;
uint32_t rval;
@@ -88,7 +88,7 @@ static uint32_t pic_readl (void *opaque, a_target_phys_addr addr)
}
static void
-pic_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
+pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct etrax_pic *fs = opaque;
D(printf("%s addr=%x val=%x\n", __func__, addr, value));
diff --git a/hw/etraxfs_ser.c b/hw/etraxfs_ser.c
index 9bfbc12a9..e1f96158f 100644
--- a/hw/etraxfs_ser.c
+++ b/hw/etraxfs_ser.c
@@ -65,7 +65,7 @@ static void ser_update_irq(struct etrax_serial *s)
s->regs[RW_ACK_INTR] = 0;
}
-static uint32_t ser_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
{
struct etrax_serial *s = opaque;
D(CPUState *env = s->env);
@@ -91,7 +91,7 @@ static uint32_t ser_readl (void *opaque, a_target_phys_addr addr)
}
static void
-ser_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
+ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct etrax_serial *s = opaque;
unsigned char ch = value;
diff --git a/hw/etraxfs_timer.c b/hw/etraxfs_timer.c
index 272b3e675..87700d4cd 100644
--- a/hw/etraxfs_timer.c
+++ b/hw/etraxfs_timer.c
@@ -72,7 +72,7 @@ struct etrax_timer {
uint32_t r_masked_intr;
};
-static uint32_t timer_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
{
struct etrax_timer *t = opaque;
uint32_t r = 0;
@@ -243,7 +243,7 @@ static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value)
}
static void
-timer_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
+timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct etrax_timer *t = opaque;
diff --git a/hw/fdc.c b/hw/fdc.c
index 1580d3d86..389d9e6a0 100644
--- a/hw/fdc.c
+++ b/hw/fdc.c
@@ -61,43 +61,43 @@
#define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
/* Floppy disk drive emulation */
-typedef enum fdisk_type {
+typedef enum fdisk_type_t {
FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */
FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */
FDRIVE_DISK_720 = 0x03, /* 720 kB disk */
FDRIVE_DISK_USER = 0x04, /* User defined geometry */
FDRIVE_DISK_NONE = 0x05, /* No disk */
-} e_fdisk_type;
+} fdisk_type_t;
-typedef enum fdrive_type {
+typedef enum fdrive_type_t {
FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
FDRIVE_DRV_NONE = 0x03, /* No drive connected */
-} e_fdrive_type;
+} fdrive_type_t;
-typedef enum fdisk_flags {
+typedef enum fdisk_flags_t {
FDISK_DBL_SIDES = 0x01,
-} e_fdisk_flags;
+} fdisk_flags_t;
-typedef struct fdrive {
+typedef struct fdrive_t {
BlockDriverState *bs;
/* Drive status */
- e_fdrive_type drive;
+ fdrive_type_t drive;
uint8_t perpendicular; /* 2.88 MB access mode */
/* Position */
uint8_t head;
uint8_t track;
uint8_t sect;
/* Media */
- e_fdisk_flags flags;
+ fdisk_flags_t flags;
uint8_t last_sect; /* Nb sector per track */
uint8_t max_track; /* Nb of tracks */
uint16_t bps; /* Bytes per sector */
uint8_t ro; /* Is read-only */
-} a_fdrive;
+} fdrive_t;
-static void fd_init (a_fdrive *drv, BlockDriverState *bs)
+static void fd_init (fdrive_t *drv, BlockDriverState *bs)
{
/* Drive */
drv->bs = bs;
@@ -115,7 +115,7 @@ static int _fd_sector (uint8_t head, uint8_t track,
}
/* Returns current position, in sectors, for given drive */
-static int fd_sector (a_fdrive *drv)
+static int fd_sector (fdrive_t *drv)
{
return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
}
@@ -127,7 +127,7 @@ static int fd_sector (a_fdrive *drv)
* returns 3 if sector is invalid
* returns 4 if seek is disabled
*/
-static int fd_seek (a_fdrive *drv, uint8_t head, uint8_t track, uint8_t sect,
+static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
int enable_seek)
{
uint32_t sector;
@@ -169,7 +169,7 @@ static int fd_seek (a_fdrive *drv, uint8_t head, uint8_t track, uint8_t sect,
}
/* Set drive back to track 0 */
-static void fd_recalibrate (a_fdrive *drv)
+static void fd_recalibrate (fdrive_t *drv)
{
FLOPPY_DPRINTF("recalibrate\n");
drv->head = 0;
@@ -178,16 +178,16 @@ static void fd_recalibrate (a_fdrive *drv)
}
/* Recognize floppy formats */
-typedef struct fd_format {
- e_fdrive_type drive;
- e_fdisk_type disk;
+typedef struct fd_format_t {
+ fdrive_type_t drive;
+ fdisk_type_t disk;
uint8_t last_sect;
uint8_t max_track;
uint8_t max_head;
const char *str;
-} a_fd_format;
+} fd_format_t;
-static const a_fd_format fd_formats[] = {
+static const fd_format_t fd_formats[] = {
/* First entry is default format */
/* 1.44 MB 3"1/2 floppy disks */
{ FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
@@ -235,9 +235,9 @@ static const a_fd_format fd_formats[] = {
};
/* Revalidate a disk drive after a disk change */
-static void fd_revalidate (a_fdrive *drv)
+static void fd_revalidate (fdrive_t *drv)
{
- const a_fd_format *parse;
+ const fd_format_t *parse;
uint64_t nb_sectors, size;
int i, first_match, match;
int nb_heads, max_track, last_sect, ro;
@@ -302,23 +302,23 @@ static void fd_revalidate (a_fdrive *drv)
/********************************************************/
/* Intel 82078 floppy disk controller emulation */
-static void fdctrl_reset (a_fdctrl *fdctrl, int do_irq);
-static void fdctrl_reset_fifo (a_fdctrl *fdctrl);
+static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
+static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
static int fdctrl_transfer_handler (void *opaque, int nchan,
- int dma_pos, int dma_len);
-static void fdctrl_raise_irq (a_fdctrl *fdctrl, uint8_t status0);
-
-static uint32_t fdctrl_read_statusA (a_fdctrl *fdctrl);
-static uint32_t fdctrl_read_statusB (a_fdctrl *fdctrl);
-static uint32_t fdctrl_read_dor (a_fdctrl *fdctrl);
-static void fdctrl_write_dor (a_fdctrl *fdctrl, uint32_t value);
-static uint32_t fdctrl_read_tape (a_fdctrl *fdctrl);
-static void fdctrl_write_tape (a_fdctrl *fdctrl, uint32_t value);
-static uint32_t fdctrl_read_main_status (a_fdctrl *fdctrl);
-static void fdctrl_write_rate (a_fdctrl *fdctrl, uint32_t value);
-static uint32_t fdctrl_read_data (a_fdctrl *fdctrl);
-static void fdctrl_write_data (a_fdctrl *fdctrl, uint32_t value);
-static uint32_t fdctrl_read_dir (a_fdctrl *fdctrl);
+ int dma_pos, int dma_len);
+static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0);
+
+static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
+static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
+static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
+static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
+static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
+static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
+static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
+static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
+static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
+static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
+static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
enum {
FD_DIR_WRITE = 0,
@@ -470,7 +470,7 @@ enum {
#define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
-struct fdctrl {
+struct fdctrl_t {
/* Controller's identification */
uint8_t version;
/* HW */
@@ -511,23 +511,23 @@ struct fdctrl {
int sun4m;
/* Floppy drives */
uint8_t num_floppies;
- a_fdrive drives[MAX_FD];
+ fdrive_t drives[MAX_FD];
int reset_sensei;
};
-typedef struct fdctrl_sysbus {
+typedef struct fdctrl_sysbus_t {
SysBusDevice busdev;
- struct fdctrl state;
-} a_fdctrl_sysbus;
+ struct fdctrl_t state;
+} fdctrl_sysbus_t;
-typedef struct fdctrl_isabus {
+typedef struct fdctrl_isabus_t {
ISADevice busdev;
- struct fdctrl state;
-} a_fdctrl_isabus;
+ struct fdctrl_t state;
+} fdctrl_isabus_t;
static uint32_t fdctrl_read (void *opaque, uint32_t reg)
{
- a_fdctrl *fdctrl = opaque;
+ fdctrl_t *fdctrl = opaque;
uint32_t retval;
switch (reg) {
@@ -563,7 +563,7 @@ static uint32_t fdctrl_read (void *opaque, uint32_t reg)
static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
{
- a_fdctrl *fdctrl = opaque;
+ fdctrl_t *fdctrl = opaque;
FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
@@ -595,13 +595,13 @@ static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
fdctrl_write(opaque, reg & 7, value);
}
-static uint32_t fdctrl_read_mem (void *opaque, a_target_phys_addr reg)
+static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
{
return fdctrl_read(opaque, (uint32_t)reg);
}
static void fdctrl_write_mem (void *opaque,
- a_target_phys_addr reg, uint32_t value)
+ target_phys_addr_t reg, uint32_t value)
{
fdctrl_write(opaque, (uint32_t)reg, value);
}
@@ -636,23 +636,23 @@ static const VMStateDescription vmstate_fdrive = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
- VMSTATE_UINT8(head, a_fdrive),
- VMSTATE_UINT8(track, a_fdrive),
- VMSTATE_UINT8(sect, a_fdrive),
+ VMSTATE_UINT8(head, fdrive_t),
+ VMSTATE_UINT8(track, fdrive_t),
+ VMSTATE_UINT8(sect, fdrive_t),
VMSTATE_END_OF_LIST()
}
};
static void fdc_pre_save(const void *opaque)
{
- a_fdctrl *s = (void *)opaque;
+ fdctrl_t *s = (void *)opaque;
s->dor_vmstate = s->dor | GET_CUR_DRV(s);
}
static int fdc_post_load(void *opaque)
{
- a_fdctrl *s = opaque;
+ fdctrl_t *s = opaque;
SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
@@ -668,46 +668,46 @@ static const VMStateDescription vmstate_fdc = {
.post_load = fdc_post_load,
.fields = (VMStateField []) {
/* Controller State */
- VMSTATE_UINT8(sra, a_fdctrl),
- VMSTATE_UINT8(srb, a_fdctrl),
- VMSTATE_UINT8(dor_vmstate, a_fdctrl),
- VMSTATE_UINT8(tdr, a_fdctrl),
- VMSTATE_UINT8(dsr, a_fdctrl),
- VMSTATE_UINT8(msr, a_fdctrl),
- VMSTATE_UINT8(status0, a_fdctrl),
- VMSTATE_UINT8(status1, a_fdctrl),
- VMSTATE_UINT8(status2, a_fdctrl),
+ VMSTATE_UINT8(sra, fdctrl_t),
+ VMSTATE_UINT8(srb, fdctrl_t),
+ VMSTATE_UINT8(dor_vmstate, fdctrl_t),
+ VMSTATE_UINT8(tdr, fdctrl_t),
+ VMSTATE_UINT8(dsr, fdctrl_t),
+ VMSTATE_UINT8(msr, fdctrl_t),
+ VMSTATE_UINT8(status0, fdctrl_t),
+ VMSTATE_UINT8(status1, fdctrl_t),
+ VMSTATE_UINT8(status2, fdctrl_t),
/* Command FIFO */
- VMSTATE_VARRAY(fifo, a_fdctrl, fifo_size, 0, vmstate_info_uint8, uint8),
- VMSTATE_UINT32(data_pos, a_fdctrl),
- VMSTATE_UINT32(data_len, a_fdctrl),
- VMSTATE_UINT8(data_state, a_fdctrl),
- VMSTATE_UINT8(data_dir, a_fdctrl),
- VMSTATE_UINT8(eot, a_fdctrl),
+ VMSTATE_VARRAY(fifo, fdctrl_t, fifo_size, 0, vmstate_info_uint8, uint8),
+ VMSTATE_UINT32(data_pos, fdctrl_t),
+ VMSTATE_UINT32(data_len, fdctrl_t),
+ VMSTATE_UINT8(data_state, fdctrl_t),
+ VMSTATE_UINT8(data_dir, fdctrl_t),
+ VMSTATE_UINT8(eot, fdctrl_t),
/* States kept only to be returned back */
- VMSTATE_UINT8(timer0, a_fdctrl),
- VMSTATE_UINT8(timer1, a_fdctrl),
- VMSTATE_UINT8(precomp_trk, a_fdctrl),
- VMSTATE_UINT8(config, a_fdctrl),
- VMSTATE_UINT8(lock, a_fdctrl),
- VMSTATE_UINT8(pwrd, a_fdctrl),
- VMSTATE_UINT8_EQUAL(num_floppies, a_fdctrl),
- VMSTATE_STRUCT_ARRAY(drives, a_fdctrl, MAX_FD, 1,
- vmstate_fdrive, a_fdrive),
+ VMSTATE_UINT8(timer0, fdctrl_t),
+ VMSTATE_UINT8(timer1, fdctrl_t),
+ VMSTATE_UINT8(precomp_trk, fdctrl_t),
+ VMSTATE_UINT8(config, fdctrl_t),
+ VMSTATE_UINT8(lock, fdctrl_t),
+ VMSTATE_UINT8(pwrd, fdctrl_t),
+ VMSTATE_UINT8_EQUAL(num_floppies, fdctrl_t),
+ VMSTATE_STRUCT_ARRAY(drives, fdctrl_t, MAX_FD, 1,
+ vmstate_fdrive, fdrive_t),
VMSTATE_END_OF_LIST()
}
};
static void fdctrl_external_reset(void *opaque)
{
- a_fdctrl *s = opaque;
+ fdctrl_t *s = opaque;
fdctrl_reset(s, 0);
}
static void fdctrl_handle_tc(void *opaque, int irq, int level)
{
- //a_fdctrl *s = opaque;
+ //fdctrl_t *s = opaque;
if (level) {
// XXX
@@ -716,13 +716,13 @@ static void fdctrl_handle_tc(void *opaque, int irq, int level)
}
/* XXX: may change if moved to bdrv */
-int fdctrl_get_drive_type(a_fdctrl *fdctrl, int drive_num)
+int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
{
return fdctrl->drives[drive_num].drive;
}
/* Change IRQ state */
-static void fdctrl_reset_irq (a_fdctrl *fdctrl)
+static void fdctrl_reset_irq (fdctrl_t *fdctrl)
{
if (!(fdctrl->sra & FD_SRA_INTPEND))
return;
@@ -731,7 +731,7 @@ static void fdctrl_reset_irq (a_fdctrl *fdctrl)
fdctrl->sra &= ~FD_SRA_INTPEND;
}
-static void fdctrl_raise_irq (a_fdctrl *fdctrl, uint8_t status0)
+static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
{
/* Sparc mutation */
if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
@@ -751,7 +751,7 @@ static void fdctrl_raise_irq (a_fdctrl *fdctrl, uint8_t status0)
}
/* Reset controller */
-static void fdctrl_reset (a_fdctrl *fdctrl, int do_irq)
+static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
{
int i;
@@ -780,12 +780,12 @@ static void fdctrl_reset (a_fdctrl *fdctrl, int do_irq)
}
}
-static inline a_fdrive *drv0 (a_fdctrl *fdctrl)
+static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
{
return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
}
-static inline a_fdrive *drv1 (a_fdctrl *fdctrl)
+static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
{
if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
return &fdctrl->drives[1];
@@ -794,7 +794,7 @@ static inline a_fdrive *drv1 (a_fdctrl *fdctrl)
}
#if MAX_FD == 4
-static inline a_fdrive *drv2 (a_fdctrl *fdctrl)
+static inline fdrive_t *drv2 (fdctrl_t *fdctrl)
{
if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
return &fdctrl->drives[2];
@@ -802,7 +802,7 @@ static inline a_fdrive *drv2 (a_fdctrl *fdctrl)
return &fdctrl->drives[1];
}
-static inline a_fdrive *drv3 (a_fdctrl *fdctrl)
+static inline fdrive_t *drv3 (fdctrl_t *fdctrl)
{
if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
return &fdctrl->drives[3];
@@ -811,7 +811,7 @@ static inline a_fdrive *drv3 (a_fdctrl *fdctrl)
}
#endif
-static a_fdrive *get_cur_drv (a_fdctrl *fdctrl)
+static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
{
switch (fdctrl->cur_drv) {
case 0: return drv0(fdctrl);
@@ -825,7 +825,7 @@ static a_fdrive *get_cur_drv (a_fdctrl *fdctrl)
}
/* Status A register : 0x00 (read-only) */
-static uint32_t fdctrl_read_statusA (a_fdctrl *fdctrl)
+static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
{
uint32_t retval = fdctrl->sra;
@@ -835,7 +835,7 @@ static uint32_t fdctrl_read_statusA (a_fdctrl *fdctrl)
}
/* Status B register : 0x01 (read-only) */
-static uint32_t fdctrl_read_statusB (a_fdctrl *fdctrl)
+static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
{
uint32_t retval = fdctrl->srb;
@@ -845,7 +845,7 @@ static uint32_t fdctrl_read_statusB (a_fdctrl *fdctrl)
}
/* Digital output register : 0x02 */
-static uint32_t fdctrl_read_dor (a_fdctrl *fdctrl)
+static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
{
uint32_t retval = fdctrl->dor;
@@ -856,7 +856,7 @@ static uint32_t fdctrl_read_dor (a_fdctrl *fdctrl)
return retval;
}
-static void fdctrl_write_dor (a_fdctrl *fdctrl, uint32_t value)
+static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
{
FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
@@ -895,7 +895,7 @@ static void fdctrl_write_dor (a_fdctrl *fdctrl, uint32_t value)
}
/* Tape drive register : 0x03 */
-static uint32_t fdctrl_read_tape (a_fdctrl *fdctrl)
+static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
{
uint32_t retval = fdctrl->tdr;
@@ -904,7 +904,7 @@ static uint32_t fdctrl_read_tape (a_fdctrl *fdctrl)
return retval;
}
-static void fdctrl_write_tape (a_fdctrl *fdctrl, uint32_t value)
+static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
{
/* Reset mode */
if (!(fdctrl->dor & FD_DOR_nRESET)) {
@@ -918,7 +918,7 @@ static void fdctrl_write_tape (a_fdctrl *fdctrl, uint32_t value)
}
/* Main status register : 0x04 (read) */
-static uint32_t fdctrl_read_main_status (a_fdctrl *fdctrl)
+static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
{
uint32_t retval = fdctrl->msr;
@@ -931,7 +931,7 @@ static uint32_t fdctrl_read_main_status (a_fdctrl *fdctrl)
}
/* Data select rate register : 0x04 (write) */
-static void fdctrl_write_rate (a_fdctrl *fdctrl, uint32_t value)
+static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
{
/* Reset mode */
if (!(fdctrl->dor & FD_DOR_nRESET)) {
@@ -951,7 +951,7 @@ static void fdctrl_write_rate (a_fdctrl *fdctrl, uint32_t value)
fdctrl->dsr = value;
}
-static int fdctrl_media_changed(a_fdrive *drv)
+static int fdctrl_media_changed(fdrive_t *drv)
{
int ret;
@@ -965,7 +965,7 @@ static int fdctrl_media_changed(a_fdrive *drv)
}
/* Digital input register : 0x07 (read-only) */
-static uint32_t fdctrl_read_dir (a_fdctrl *fdctrl)
+static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
{
uint32_t retval = 0;
@@ -984,7 +984,7 @@ static uint32_t fdctrl_read_dir (a_fdctrl *fdctrl)
}
/* FIFO state control */
-static void fdctrl_reset_fifo (a_fdctrl *fdctrl)
+static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
{
fdctrl->data_dir = FD_DIR_WRITE;
fdctrl->data_pos = 0;
@@ -992,7 +992,7 @@ static void fdctrl_reset_fifo (a_fdctrl *fdctrl)
}
/* Set FIFO status for the host to read */
-static void fdctrl_set_fifo (a_fdctrl *fdctrl, int fifo_len, int do_irq)
+static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
{
fdctrl->data_dir = FD_DIR_READ;
fdctrl->data_len = fifo_len;
@@ -1003,7 +1003,7 @@ static void fdctrl_set_fifo (a_fdctrl *fdctrl, int fifo_len, int do_irq)
}
/* Set an error: unimplemented/unknown command */
-static void fdctrl_unimplemented (a_fdctrl *fdctrl, int direction)
+static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
{
FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
fdctrl->fifo[0] = FD_SR0_INVCMD;
@@ -1011,7 +1011,7 @@ static void fdctrl_unimplemented (a_fdctrl *fdctrl, int direction)
}
/* Seek to next sector */
-static int fdctrl_seek_to_next_sect (a_fdctrl *fdctrl, a_fdrive *cur_drv)
+static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
{
FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
cur_drv->head, cur_drv->track, cur_drv->sect,
@@ -1045,10 +1045,10 @@ static int fdctrl_seek_to_next_sect (a_fdctrl *fdctrl, a_fdrive *cur_drv)
}
/* Callback for transfer end (stop or abort) */
-static void fdctrl_stop_transfer (a_fdctrl *fdctrl, uint8_t status0,
+static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
uint8_t status1, uint8_t status2)
{
- a_fdrive *cur_drv;
+ fdrive_t *cur_drv;
cur_drv = get_cur_drv(fdctrl);
FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
@@ -1071,9 +1071,9 @@ static void fdctrl_stop_transfer (a_fdctrl *fdctrl, uint8_t status0,
}
/* Prepare a data transfer (either DMA or FIFO) */
-static void fdctrl_start_transfer (a_fdctrl *fdctrl, int direction)
+static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
{
- a_fdrive *cur_drv;
+ fdrive_t *cur_drv;
uint8_t kh, kt, ks;
int did_seek = 0;
@@ -1173,7 +1173,7 @@ static void fdctrl_start_transfer (a_fdctrl *fdctrl, int direction)
}
/* Prepare a transfer of deleted data */
-static void fdctrl_start_transfer_del (a_fdctrl *fdctrl, int direction)
+static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
{
FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
@@ -1187,8 +1187,8 @@ static void fdctrl_start_transfer_del (a_fdctrl *fdctrl, int direction)
static int fdctrl_transfer_handler (void *opaque, int nchan,
int dma_pos, int dma_len)
{
- a_fdctrl *fdctrl;
- a_fdrive *cur_drv;
+ fdctrl_t *fdctrl;
+ fdrive_t *cur_drv;
int len, start_pos, rel_pos;
uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
@@ -1294,9 +1294,9 @@ static int fdctrl_transfer_handler (void *opaque, int nchan,
}
/* Data register : 0x05 */
-static uint32_t fdctrl_read_data (a_fdctrl *fdctrl)
+static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
{
- a_fdrive *cur_drv;
+ fdrive_t *cur_drv;
uint32_t retval = 0;
int pos;
@@ -1342,9 +1342,9 @@ static uint32_t fdctrl_read_data (a_fdctrl *fdctrl)
return retval;
}
-static void fdctrl_format_sector (a_fdctrl *fdctrl)
+static void fdctrl_format_sector (fdctrl_t *fdctrl)
{
- a_fdrive *cur_drv;
+ fdrive_t *cur_drv;
uint8_t kh, kt, ks;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
@@ -1404,16 +1404,16 @@ static void fdctrl_format_sector (a_fdctrl *fdctrl)
}
}
-static void fdctrl_handle_lock (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
{
fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
fdctrl->fifo[0] = fdctrl->lock << 4;
fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
}
-static void fdctrl_handle_dumpreg (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
{
- a_fdrive *cur_drv = get_cur_drv(fdctrl);
+ fdrive_t *cur_drv = get_cur_drv(fdctrl);
/* Drives position */
fdctrl->fifo[0] = drv0(fdctrl)->track;
@@ -1436,22 +1436,22 @@ static void fdctrl_handle_dumpreg (a_fdctrl *fdctrl, int direction)
fdctrl_set_fifo(fdctrl, 10, 0);
}
-static void fdctrl_handle_version (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
{
/* Controller's version */
fdctrl->fifo[0] = fdctrl->version;
fdctrl_set_fifo(fdctrl, 1, 1);
}
-static void fdctrl_handle_partid (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
{
fdctrl->fifo[0] = 0x41; /* Stepping 1 */
fdctrl_set_fifo(fdctrl, 1, 0);
}
-static void fdctrl_handle_restore (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
{
- a_fdrive *cur_drv = get_cur_drv(fdctrl);
+ fdrive_t *cur_drv = get_cur_drv(fdctrl);
/* Drives position */
drv0(fdctrl)->track = fdctrl->fifo[3];
@@ -1472,9 +1472,9 @@ static void fdctrl_handle_restore (a_fdctrl *fdctrl, int direction)
fdctrl_reset_fifo(fdctrl);
}
-static void fdctrl_handle_save (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
{
- a_fdrive *cur_drv = get_cur_drv(fdctrl);
+ fdrive_t *cur_drv = get_cur_drv(fdctrl);
fdctrl->fifo[0] = 0;
fdctrl->fifo[1] = 0;
@@ -1502,9 +1502,9 @@ static void fdctrl_handle_save (a_fdctrl *fdctrl, int direction)
fdctrl_set_fifo(fdctrl, 15, 1);
}
-static void fdctrl_handle_readid (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
{
- a_fdrive *cur_drv = get_cur_drv(fdctrl);
+ fdrive_t *cur_drv = get_cur_drv(fdctrl);
/* XXX: should set main status register to busy */
cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
@@ -1512,9 +1512,9 @@ static void fdctrl_handle_readid (a_fdctrl *fdctrl, int direction)
qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
}
-static void fdctrl_handle_format_track (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
{
- a_fdrive *cur_drv;
+ fdrive_t *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
@@ -1541,7 +1541,7 @@ static void fdctrl_handle_format_track (a_fdctrl *fdctrl, int direction)
fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
}
-static void fdctrl_handle_specify (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
{
fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
fdctrl->timer1 = fdctrl->fifo[2] >> 1;
@@ -1553,9 +1553,9 @@ static void fdctrl_handle_specify (a_fdctrl *fdctrl, int direction)
fdctrl_reset_fifo(fdctrl);
}
-static void fdctrl_handle_sense_drive_status (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
{
- a_fdrive *cur_drv;
+ fdrive_t *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
@@ -1569,9 +1569,9 @@ static void fdctrl_handle_sense_drive_status (a_fdctrl *fdctrl, int direction)
fdctrl_set_fifo(fdctrl, 1, 0);
}
-static void fdctrl_handle_recalibrate (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
{
- a_fdrive *cur_drv;
+ fdrive_t *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
@@ -1581,9 +1581,9 @@ static void fdctrl_handle_recalibrate (a_fdctrl *fdctrl, int direction)
fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
}
-static void fdctrl_handle_sense_interrupt_status (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
{
- a_fdrive *cur_drv = get_cur_drv(fdctrl);
+ fdrive_t *cur_drv = get_cur_drv(fdctrl);
if(fdctrl->reset_sensei > 0) {
fdctrl->fifo[0] =
@@ -1603,9 +1603,9 @@ static void fdctrl_handle_sense_interrupt_status (a_fdctrl *fdctrl, int directio
fdctrl->status0 = FD_SR0_RDYCHG;
}
-static void fdctrl_handle_seek (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
{
- a_fdrive *cur_drv;
+ fdrive_t *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
@@ -1619,9 +1619,9 @@ static void fdctrl_handle_seek (a_fdctrl *fdctrl, int direction)
}
}
-static void fdctrl_handle_perpendicular_mode (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
{
- a_fdrive *cur_drv = get_cur_drv(fdctrl);
+ fdrive_t *cur_drv = get_cur_drv(fdctrl);
if (fdctrl->fifo[1] & 0x80)
cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
@@ -1629,7 +1629,7 @@ static void fdctrl_handle_perpendicular_mode (a_fdctrl *fdctrl, int direction)
fdctrl_reset_fifo(fdctrl);
}
-static void fdctrl_handle_configure (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
{
fdctrl->config = fdctrl->fifo[2];
fdctrl->precomp_trk = fdctrl->fifo[3];
@@ -1637,22 +1637,22 @@ static void fdctrl_handle_configure (a_fdctrl *fdctrl, int direction)
fdctrl_reset_fifo(fdctrl);
}
-static void fdctrl_handle_powerdown_mode (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
{
fdctrl->pwrd = fdctrl->fifo[1];
fdctrl->fifo[0] = fdctrl->fifo[1];
fdctrl_set_fifo(fdctrl, 1, 1);
}
-static void fdctrl_handle_option (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
{
/* No result back */
fdctrl_reset_fifo(fdctrl);
}
-static void fdctrl_handle_drive_specification_command (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
{
- a_fdrive *cur_drv = get_cur_drv(fdctrl);
+ fdrive_t *cur_drv = get_cur_drv(fdctrl);
if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
/* Command parameters done */
@@ -1672,9 +1672,9 @@ static void fdctrl_handle_drive_specification_command (a_fdctrl *fdctrl, int dir
}
}
-static void fdctrl_handle_relative_seek_out (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
{
- a_fdrive *cur_drv;
+ fdrive_t *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
@@ -1688,9 +1688,9 @@ static void fdctrl_handle_relative_seek_out (a_fdctrl *fdctrl, int direction)
fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
}
-static void fdctrl_handle_relative_seek_in (a_fdctrl *fdctrl, int direction)
+static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
{
- a_fdrive *cur_drv;
+ fdrive_t *cur_drv;
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
@@ -1709,7 +1709,7 @@ static const struct {
uint8_t mask;
const char* name;
int parameters;
- void (*handler)(a_fdctrl *fdctrl, int direction);
+ void (*handler)(fdctrl_t *fdctrl, int direction);
int direction;
} handlers[] = {
{ FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
@@ -1748,9 +1748,9 @@ static const struct {
/* Associate command to an index in the 'handlers' array */
static uint8_t command_to_handler[256];
-static void fdctrl_write_data (a_fdctrl *fdctrl, uint32_t value)
+static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
{
- a_fdrive *cur_drv;
+ fdrive_t *cur_drv;
int pos;
/* Reset mode */
@@ -1815,8 +1815,8 @@ static void fdctrl_write_data (a_fdctrl *fdctrl, uint32_t value)
static void fdctrl_result_timer(void *opaque)
{
- a_fdctrl *fdctrl = opaque;
- a_fdrive *cur_drv = get_cur_drv(fdctrl);
+ fdctrl_t *fdctrl = opaque;
+ fdrive_t *cur_drv = get_cur_drv(fdctrl);
/* Pretend we are spinning.
* This is needed for Coherent, which uses READ ID to check for
@@ -1829,7 +1829,7 @@ static void fdctrl_result_timer(void *opaque)
}
/* Init functions */
-static void fdctrl_connect_drives(a_fdctrl *fdctrl, BlockDriverState **fds)
+static void fdctrl_connect_drives(fdctrl_t *fdctrl, BlockDriverState **fds)
{
unsigned int i;
@@ -1839,14 +1839,14 @@ static void fdctrl_connect_drives(a_fdctrl *fdctrl, BlockDriverState **fds)
}
}
-a_fdctrl *fdctrl_init_isa(BlockDriverState **fds)
+fdctrl_t *fdctrl_init_isa(BlockDriverState **fds)
{
- a_fdctrl *fdctrl;
+ fdctrl_t *fdctrl;
ISADevice *dev;
int dma_chann = 2;
dev = isa_create_simple("isa-fdc");
- fdctrl = &(DO_UPCAST(a_fdctrl_isabus, busdev, dev)->state);
+ fdctrl = &(DO_UPCAST(fdctrl_isabus_t, busdev, dev)->state);
fdctrl->dma_chann = dma_chann;
DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
@@ -1856,17 +1856,17 @@ a_fdctrl *fdctrl_init_isa(BlockDriverState **fds)
return fdctrl;
}
-a_fdctrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
- a_target_phys_addr mmio_base,
+fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
+ target_phys_addr_t mmio_base,
BlockDriverState **fds)
{
- a_fdctrl *fdctrl;
+ fdctrl_t *fdctrl;
DeviceState *dev;
- a_fdctrl_sysbus *sys;
+ fdctrl_sysbus_t *sys;
dev = qdev_create(NULL, "sysbus-fdc");
qdev_init(dev);
- sys = DO_UPCAST(a_fdctrl_sysbus, busdev.qdev, dev);
+ sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
fdctrl = &sys->state;
sysbus_connect_irq(&sys->busdev, 0, irq);
sysbus_mmio_map(&sys->busdev, 0, mmio_base);
@@ -1878,16 +1878,16 @@ a_fdctrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
return fdctrl;
}
-a_fdctrl *sun4m_fdctrl_init (qemu_irq irq, a_target_phys_addr io_base,
+fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
BlockDriverState **fds, qemu_irq *fdc_tc)
{
DeviceState *dev;
- a_fdctrl_sysbus *sys;
- a_fdctrl *fdctrl;
+ fdctrl_sysbus_t *sys;
+ fdctrl_t *fdctrl;
dev = qdev_create(NULL, "SUNW,fdtwo");
qdev_init(dev);
- sys = DO_UPCAST(a_fdctrl_sysbus, busdev.qdev, dev);
+ sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
fdctrl = &sys->state;
sysbus_connect_irq(&sys->busdev, 0, irq);
sysbus_mmio_map(&sys->busdev, 0, io_base);
@@ -1900,7 +1900,7 @@ a_fdctrl *sun4m_fdctrl_init (qemu_irq irq, a_target_phys_addr io_base,
return fdctrl;
}
-static int fdctrl_init_common(a_fdctrl *fdctrl)
+static int fdctrl_init_common(fdctrl_t *fdctrl)
{
int i, j;
static int command_tables_inited = 0;
@@ -1935,8 +1935,8 @@ static int fdctrl_init_common(a_fdctrl *fdctrl)
static int isabus_fdc_init1(ISADevice *dev)
{
- a_fdctrl_isabus *isa = DO_UPCAST(a_fdctrl_isabus, busdev, dev);
- a_fdctrl *fdctrl = &isa->state;
+ fdctrl_isabus_t *isa = DO_UPCAST(fdctrl_isabus_t, busdev, dev);
+ fdctrl_t *fdctrl = &isa->state;
int iobase = 0x3f0;
int isairq = 6;
@@ -1955,7 +1955,7 @@ static int isabus_fdc_init1(ISADevice *dev)
static int sysbus_fdc_init1(SysBusDevice *dev)
{
- a_fdctrl *fdctrl = &(FROM_SYSBUS(a_fdctrl_sysbus, dev)->state);
+ fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state);
int io;
io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl);
@@ -1968,7 +1968,7 @@ static int sysbus_fdc_init1(SysBusDevice *dev)
static int sun4m_fdc_init1(SysBusDevice *dev)
{
- a_fdctrl *fdctrl = &(FROM_SYSBUS(a_fdctrl_sysbus, dev)->state);
+ fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state);
int io;
io = cpu_register_io_memory(fdctrl_mem_read_strict,
@@ -1984,19 +1984,19 @@ static int sun4m_fdc_init1(SysBusDevice *dev)
static ISADeviceInfo isa_fdc_info = {
.init = isabus_fdc_init1,
.qdev.name = "isa-fdc",
- .qdev.size = sizeof(a_fdctrl_isabus),
+ .qdev.size = sizeof(fdctrl_isabus_t),
};
static SysBusDeviceInfo sysbus_fdc_info = {
.init = sysbus_fdc_init1,
.qdev.name = "sysbus-fdc",
- .qdev.size = sizeof(a_fdctrl_sysbus),
+ .qdev.size = sizeof(fdctrl_sysbus_t),
};
static SysBusDeviceInfo sun4m_fdc_info = {
.init = sun4m_fdc_init1,
.qdev.name = "SUNW,fdtwo",
- .qdev.size = sizeof(a_fdctrl_sysbus),
+ .qdev.size = sizeof(fdctrl_sysbus_t),
};
static void fdc_register_devices(void)
diff --git a/hw/fdc.h b/hw/fdc.h
index 38e8278a6..1b81ec1db 100644
--- a/hw/fdc.h
+++ b/hw/fdc.h
@@ -1,12 +1,12 @@
/* fdc.c */
#define MAX_FD 2
-typedef struct fdctrl a_fdctrl;
+typedef struct fdctrl_t fdctrl_t;
-a_fdctrl *fdctrl_init_isa(BlockDriverState **fds);
-a_fdctrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
- a_target_phys_addr mmio_base,
+fdctrl_t *fdctrl_init_isa(BlockDriverState **fds);
+fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
+ target_phys_addr_t mmio_base,
BlockDriverState **fds);
-a_fdctrl *sun4m_fdctrl_init (qemu_irq irq, a_target_phys_addr io_base,
+fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
BlockDriverState **fds, qemu_irq *fdc_tc);
-int fdctrl_get_drive_type(a_fdctrl *fdctrl, int drive_num);
+int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
diff --git a/hw/flash.h b/hw/flash.h
index ac1c325ec..69aef8ce2 100644
--- a/hw/flash.h
+++ b/hw/flash.h
@@ -1,15 +1,15 @@
/* NOR flash devices */
-typedef struct pflash a_pflash;
+typedef struct pflash_t pflash_t;
/* pflash_cfi01.c */
-a_pflash *pflash_cfi01_register(a_target_phys_addr base, a_ram_addr off,
+pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
BlockDriverState *bs,
uint32_t sector_len, int nb_blocs, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3);
/* pflash_cfi02.c */
-a_pflash *pflash_cfi02_register(a_target_phys_addr base, a_ram_addr off,
+pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1,
@@ -36,7 +36,7 @@ uint8_t nand_getio(NANDFlashState *s);
#define NAND_MFR_MICRON 0x2c
/* onenand.c */
-void onenand_base_update(void *opaque, a_target_phys_addr new);
+void onenand_base_update(void *opaque, target_phys_addr_t new);
void onenand_base_unmap(void *opaque);
void *onenand_init(uint32_t id, int regshift, qemu_irq irq);
void *onenand_raw_otp(void *opaque);
diff --git a/hw/framebuffer.c b/hw/framebuffer.c
index f60beff64..24cdf25d0 100644
--- a/hw/framebuffer.c
+++ b/hw/framebuffer.c
@@ -22,7 +22,7 @@
void framebuffer_update_display(
DisplayState *ds,
- a_target_phys_addr base,
+ target_phys_addr_t base,
int cols, /* Width in pixels. */
int rows, /* Leight in pixels. */
int src_width, /* Length of source line, in bytes. */
@@ -34,16 +34,16 @@ void framebuffer_update_display(
int *first_row, /* Input and output. */
int *last_row /* Output only */)
{
- a_target_phys_addr src_len;
+ target_phys_addr_t src_len;
uint8_t *dest;
uint8_t *src;
uint8_t *src_base;
int first, last = 0;
int dirty;
int i;
- a_ram_addr addr;
- a_ram_addr pd;
- a_ram_addr pd2;
+ ram_addr_t addr;
+ ram_addr_t pd;
+ ram_addr_t pd2;
i = *first_row;
*first_row = -1;
@@ -86,7 +86,7 @@ void framebuffer_update_display(
dest += i * dest_row_pitch;
for (; i < rows; i++) {
- a_target_phys_addr dirty_offset;
+ target_phys_addr_t dirty_offset;
dirty = 0;
dirty_offset = 0;
while (addr + dirty_offset < TARGET_PAGE_ALIGN(addr + src_width)) {
diff --git a/hw/framebuffer.h b/hw/framebuffer.h
index 22d57350d..a3a214649 100644
--- a/hw/framebuffer.h
+++ b/hw/framebuffer.h
@@ -7,7 +7,7 @@ typedef void (*drawfn)(void *, uint8_t *, const uint8_t *, int, int);
void framebuffer_update_display(
DisplayState *ds,
- a_target_phys_addr base,
+ target_phys_addr_t base,
int cols,
int rows,
int src_width,
diff --git a/hw/fw_cfg.c b/hw/fw_cfg.c
index bd57416f9..37fe3b358 100644
--- a/hw/fw_cfg.c
+++ b/hw/fw_cfg.c
@@ -116,18 +116,18 @@ static void fw_cfg_io_writew(void *opaque, uint32_t addr, uint32_t value)
fw_cfg_select(opaque, (uint16_t)value);
}
-static uint32_t fw_cfg_mem_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t fw_cfg_mem_readb(void *opaque, target_phys_addr_t addr)
{
return fw_cfg_read(opaque);
}
-static void fw_cfg_mem_writeb(void *opaque, a_target_phys_addr addr,
+static void fw_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
fw_cfg_write(opaque, (uint8_t)value);
}
-static void fw_cfg_mem_writew(void *opaque, a_target_phys_addr addr,
+static void fw_cfg_mem_writew(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
fw_cfg_select(opaque, (uint16_t)value);
@@ -242,7 +242,7 @@ int fw_cfg_add_callback(void *opaque, uint16_t key, FWCfgCallback callback,
}
void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
- a_target_phys_addr ctl_addr, a_target_phys_addr data_addr)
+ target_phys_addr_t ctl_addr, target_phys_addr_t data_addr)
{
FWCfgState *s;
int io_ctl_memory, io_data_memory;
diff --git a/hw/fw_cfg.h b/hw/fw_cfg.h
index db835d04b..30dfec7c6 100644
--- a/hw/fw_cfg.h
+++ b/hw/fw_cfg.h
@@ -35,7 +35,7 @@ int fw_cfg_add_i64(void *opaque, uint16_t key, uint64_t value);
int fw_cfg_add_callback(void *opaque, uint16_t key, FWCfgCallback callback,
void *callback_opaque, uint8_t *data, size_t len);
void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
- a_target_phys_addr crl_addr, a_target_phys_addr data_addr);
+ target_phys_addr_t crl_addr, target_phys_addr_t data_addr);
#endif /* NO_QEMU_PROTOS */
diff --git a/hw/g364fb.c b/hw/g364fb.c
index 548f67577..d1d2c12d6 100644
--- a/hw/g364fb.c
+++ b/hw/g364fb.c
@@ -36,7 +36,7 @@ do { fprintf(stderr, "g364 ERROR: " fmt , ## __VA_ARGS__);} while (0)
typedef struct G364State {
/* hardware */
uint8_t *vram;
- a_ram_addr vram_offset;
+ ram_addr_t vram_offset;
int vram_size;
qemu_irq irq;
/* registers */
@@ -68,13 +68,13 @@ typedef struct G364State {
#define CTLA_FORCE_BLANK 0x00000400
#define CTLA_NO_CURSOR 0x00800000
-static inline int check_dirty(a_ram_addr page)
+static inline int check_dirty(ram_addr_t page)
{
return cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
}
static inline void reset_dirty(G364State *s,
- a_ram_addr page_min, a_ram_addr page_max)
+ ram_addr_t page_min, ram_addr_t page_max)
{
cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE - 1,
VGA_DIRTY_FLAG);
@@ -85,7 +85,7 @@ static void g364fb_draw_graphic8(G364State *s)
int i, w;
uint8_t *vram;
uint8_t *data_display, *dd;
- a_ram_addr page, page_min, page_max;
+ ram_addr_t page, page_min, page_max;
int x, y;
int xmin, xmax;
int ymin, ymax;
@@ -115,7 +115,7 @@ static void g364fb_draw_graphic8(G364State *s)
}
page = s->vram_offset;
- page_min = (a_ram_addr)-1;
+ page_min = (ram_addr_t)-1;
page_max = 0;
x = y = 0;
@@ -138,7 +138,7 @@ static void g364fb_draw_graphic8(G364State *s)
if (check_dirty(page)) {
if (y < ymin)
ymin = ymax = y;
- if (page_min == (a_ram_addr)-1)
+ if (page_min == (ram_addr_t)-1)
page_min = page;
page_max = page;
if (x < xmin)
@@ -197,9 +197,9 @@ static void g364fb_draw_graphic8(G364State *s)
ymax = y;
} else {
int dy;
- if (page_min != (a_ram_addr)-1) {
+ if (page_min != (ram_addr_t)-1) {
reset_dirty(s, page_min, page_max);
- page_min = (a_ram_addr)-1;
+ page_min = (ram_addr_t)-1;
page_max = 0;
dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
xmin = s->width;
@@ -219,7 +219,7 @@ static void g364fb_draw_graphic8(G364State *s)
}
done:
- if (page_min != (a_ram_addr)-1) {
+ if (page_min != (ram_addr_t)-1) {
dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
reset_dirty(s, page_min, page_max);
}
@@ -336,7 +336,7 @@ static void g364fb_screen_dump(void *opaque, const char *filename)
}
/* called for accesses to io ports */
-static uint32_t g364fb_ctrl_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t g364fb_ctrl_readl(void *opaque, target_phys_addr_t addr)
{
G364State *s = opaque;
uint32_t val;
@@ -379,7 +379,7 @@ static uint32_t g364fb_ctrl_readl(void *opaque, a_target_phys_addr addr)
return val;
}
-static uint32_t g364fb_ctrl_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t g364fb_ctrl_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t v = g364fb_ctrl_readl(opaque, addr & ~0x3);
if (addr & 0x2)
@@ -388,7 +388,7 @@ static uint32_t g364fb_ctrl_readw(void *opaque, a_target_phys_addr addr)
return v & 0xffff;
}
-static uint32_t g364fb_ctrl_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t g364fb_ctrl_readb(void *opaque, target_phys_addr_t addr)
{
uint32_t v = g364fb_ctrl_readl(opaque, addr & ~0x3);
return (v >> (8 * (addr & 0x3))) & 0xff;
@@ -415,7 +415,7 @@ static void g364_invalidate_cursor_position(G364State *s)
}
}
-static void g364fb_ctrl_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void g364fb_ctrl_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
G364State *s = opaque;
@@ -490,7 +490,7 @@ static void g364fb_ctrl_writel(void *opaque, a_target_phys_addr addr, uint32_t v
qemu_irq_lower(s->irq);
}
-static void g364fb_ctrl_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
uint32_t old_val = g364fb_ctrl_readl(opaque, addr & ~0x3);
@@ -501,7 +501,7 @@ static void g364fb_ctrl_writew(void *opaque, a_target_phys_addr addr, uint32_t v
g364fb_ctrl_writel(opaque, addr & ~0x3, val);
}
-static void g364fb_ctrl_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
uint32_t old_val = g364fb_ctrl_readl(opaque, addr & ~0x3);
@@ -583,8 +583,8 @@ static void g364fb_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, s->height);
}
-int g364fb_mm_init(a_target_phys_addr vram_base,
- a_target_phys_addr ctrl_base, int it_shift,
+int g364fb_mm_init(target_phys_addr_t vram_base,
+ target_phys_addr_t ctrl_base, int it_shift,
qemu_irq irq)
{
G364State *s;
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index 555abd5c4..d878cf674 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -37,7 +37,7 @@
#define GRACKLE_DPRINTF(fmt, ...)
#endif
-typedef a_target_phys_addr a_pci_addr;
+typedef target_phys_addr_t pci_addr_t;
#include "pci_host.h"
typedef struct GrackleState {
@@ -45,7 +45,7 @@ typedef struct GrackleState {
PCIHostState host_state;
} GrackleState;
-static void pci_grackle_config_writel (void *opaque, a_target_phys_addr addr,
+static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
GrackleState *s = opaque;
@@ -58,7 +58,7 @@ static void pci_grackle_config_writel (void *opaque, a_target_phys_addr addr,
s->host_state.config_reg = val;
}
-static uint32_t pci_grackle_config_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
{
GrackleState *s = opaque;
uint32_t val;
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index 87d13f998..8f9ae4a20 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -27,7 +27,7 @@
#include "pci.h"
#include "pc.h"
-typedef a_target_phys_addr a_pci_addr;
+typedef target_phys_addr_t pci_addr_t;
#include "pci_host.h"
//#define DEBUG
@@ -229,8 +229,8 @@ typedef a_target_phys_addr a_pci_addr;
typedef PCIHostState GT64120PCIState;
#define PCI_MAPPING_ENTRY(regname) \
- a_target_phys_addr regname ##_start; \
- a_target_phys_addr regname ##_length; \
+ target_phys_addr_t regname ##_start; \
+ target_phys_addr_t regname ##_length; \
int regname ##_handle
typedef struct GT64120State {
@@ -243,11 +243,11 @@ typedef struct GT64120State {
/* Adjust range to avoid touching space which isn't mappable via PCI */
/* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
0x1fc00000 - 0x1fd00000 */
-static void check_reserved_space (a_target_phys_addr *start,
- a_target_phys_addr *length)
+static void check_reserved_space (target_phys_addr_t *start,
+ target_phys_addr_t *length)
{
- a_target_phys_addr begin = *start;
- a_target_phys_addr end = *start + *length;
+ target_phys_addr_t begin = *start;
+ target_phys_addr_t end = *start + *length;
if (end >= 0x1e000000LL && end < 0x1f100000LL)
end = 0x1e000000LL;
@@ -269,8 +269,8 @@ static void check_reserved_space (a_target_phys_addr *start,
static void gt64120_isd_mapping(GT64120State *s)
{
- a_target_phys_addr start = s->regs[GT_ISD] << 21;
- a_target_phys_addr length = 0x1000;
+ target_phys_addr_t start = s->regs[GT_ISD] << 21;
+ target_phys_addr_t length = 0x1000;
if (s->ISD_length)
cpu_register_physical_memory(s->ISD_start, s->ISD_length,
@@ -303,7 +303,7 @@ static void gt64120_pci_mapping(GT64120State *s)
}
}
-static void gt64120_writel (void *opaque, a_target_phys_addr addr,
+static void gt64120_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
GT64120State *s = opaque;
@@ -583,7 +583,7 @@ static void gt64120_writel (void *opaque, a_target_phys_addr addr,
}
static uint32_t gt64120_readl (void *opaque,
- a_target_phys_addr addr)
+ target_phys_addr_t addr)
{
GT64120State *s = opaque;
uint32_t val;
diff --git a/hw/gumstix.c b/hw/gumstix.c
index c3f214859..8fbf64c0f 100644
--- a/hw/gumstix.c
+++ b/hw/gumstix.c
@@ -41,7 +41,7 @@
static const int sector_len = 128 * 1024;
-static void connex_init(a_ram_addr ram_size,
+static void connex_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@@ -75,7 +75,7 @@ static void connex_init(a_ram_addr ram_size,
pxa2xx_gpio_in_get(cpu->gpio)[36]);
}
-static void verdex_init(a_ram_addr ram_size,
+static void verdex_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
diff --git a/hw/heathrow_pic.c b/hw/heathrow_pic.c
index c3c8db615..500b9f19b 100644
--- a/hw/heathrow_pic.c
+++ b/hw/heathrow_pic.c
@@ -62,7 +62,7 @@ static void heathrow_pic_update(HeathrowPICS *s)
}
}
-static void pic_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
+static void pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
HeathrowPICS *s = opaque;
HeathrowPIC *pic;
@@ -92,7 +92,7 @@ static void pic_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
}
}
-static uint32_t pic_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
{
HeathrowPICS *s = opaque;
HeathrowPIC *pic;
diff --git a/hw/hpet.c b/hw/hpet.c
index a51741305..c1ead3444 100644
--- a/hw/hpet.c
+++ b/hw/hpet.c
@@ -270,20 +270,20 @@ static void hpet_del_timer(HPETTimer *t)
}
#ifdef HPET_DEBUG
-static uint32_t hpet_ram_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
{
printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
return 0;
}
-static uint32_t hpet_ram_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
{
printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
return 0;
}
#endif
-static uint32_t hpet_ram_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
{
HPETState *s = (HPETState *)opaque;
uint64_t cur_tick, index;
@@ -350,14 +350,14 @@ static uint32_t hpet_ram_readl(void *opaque, a_target_phys_addr addr)
}
#ifdef HPET_DEBUG
-static void hpet_ram_writeb(void *opaque, a_target_phys_addr addr,
+static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
addr, value);
}
-static void hpet_ram_writew(void *opaque, a_target_phys_addr addr,
+static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
@@ -365,7 +365,7 @@ static void hpet_ram_writew(void *opaque, a_target_phys_addr addr,
}
#endif
-static void hpet_ram_writel(void *opaque, a_target_phys_addr addr,
+static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
int i;
diff --git a/hw/ide.h b/hw/ide.h
index 774c09b42..0e7d540bd 100644
--- a/hw/ide.h
+++ b/hw/ide.h
@@ -18,7 +18,7 @@ int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
void *dbdma, int channel, qemu_irq dma_irq);
/* ide-mmio.c */
-void mmio_ide_init (a_target_phys_addr membase, a_target_phys_addr membase2,
+void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
qemu_irq irq, int shift,
DriveInfo *hd0, DriveInfo *hd1);
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index 692023d42..a11223e6f 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -178,7 +178,7 @@ static void pmac_ide_flush(DBDMA_io *io)
/* PowerMac IDE memory IO */
static void pmac_ide_writeb (void *opaque,
- a_target_phys_addr addr, uint32_t val)
+ target_phys_addr_t addr, uint32_t val)
{
MACIOIDEState *d = opaque;
@@ -196,7 +196,7 @@ static void pmac_ide_writeb (void *opaque,
}
}
-static uint32_t pmac_ide_readb (void *opaque,a_target_phys_addr addr)
+static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
{
uint8_t retval;
MACIOIDEState *d = opaque;
@@ -218,7 +218,7 @@ static uint32_t pmac_ide_readb (void *opaque,a_target_phys_addr addr)
}
static void pmac_ide_writew (void *opaque,
- a_target_phys_addr addr, uint32_t val)
+ target_phys_addr_t addr, uint32_t val)
{
MACIOIDEState *d = opaque;
@@ -231,7 +231,7 @@ static void pmac_ide_writew (void *opaque,
}
}
-static uint32_t pmac_ide_readw (void *opaque,a_target_phys_addr addr)
+static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
{
uint16_t retval;
MACIOIDEState *d = opaque;
@@ -249,7 +249,7 @@ static uint32_t pmac_ide_readw (void *opaque,a_target_phys_addr addr)
}
static void pmac_ide_writel (void *opaque,
- a_target_phys_addr addr, uint32_t val)
+ target_phys_addr_t addr, uint32_t val)
{
MACIOIDEState *d = opaque;
@@ -262,7 +262,7 @@ static void pmac_ide_writel (void *opaque,
}
}
-static uint32_t pmac_ide_readl (void *opaque,a_target_phys_addr addr)
+static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
{
uint32_t retval;
MACIOIDEState *d = opaque;
diff --git a/hw/ide/mmio.c b/hw/ide/mmio.c
index a1a760629..acaa900c8 100644
--- a/hw/ide/mmio.c
+++ b/hw/ide/mmio.c
@@ -41,7 +41,7 @@ typedef struct {
int shift;
} MMIOState;
-static uint32_t mmio_ide_read (void *opaque, a_target_phys_addr addr)
+static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
{
MMIOState *s = (MMIOState*)opaque;
IDEBus *bus = s->bus;
@@ -52,7 +52,7 @@ static uint32_t mmio_ide_read (void *opaque, a_target_phys_addr addr)
return ide_data_readw(bus, 0);
}
-static void mmio_ide_write (void *opaque, a_target_phys_addr addr,
+static void mmio_ide_write (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
MMIOState *s = (MMIOState*)opaque;
@@ -76,14 +76,14 @@ static CPUWriteMemoryFunc * const mmio_ide_writes[] = {
mmio_ide_write,
};
-static uint32_t mmio_ide_status_read (void *opaque, a_target_phys_addr addr)
+static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr)
{
MMIOState *s= (MMIOState*)opaque;
IDEBus *bus = s->bus;
return ide_status_read(bus, 0);
}
-static void mmio_ide_cmd_write (void *opaque, a_target_phys_addr addr,
+static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
MMIOState *s = (MMIOState*)opaque;
@@ -122,7 +122,7 @@ static int mmio_ide_load(QEMUFile* f, void *opaque, int version_id)
return 0;
}
-void mmio_ide_init (a_target_phys_addr membase, a_target_phys_addr membase2,
+void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
qemu_irq irq, int shift,
DriveInfo *hd0, DriveInfo *hd1)
{
diff --git a/hw/integratorcp.c b/hw/integratorcp.c
index 2f3e44d4d..21e7712a6 100644
--- a/hw/integratorcp.c
+++ b/hw/integratorcp.c
@@ -37,7 +37,7 @@ static uint8_t integrator_spd[128] = {
0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
};
-static uint32_t integratorcm_read(void *opaque, a_target_phys_addr offset)
+static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
{
integratorcm_state *s = (integratorcm_state *)opaque;
if (offset >= 0x100 && offset < 0x200) {
@@ -138,7 +138,7 @@ static void integratorcm_update(integratorcm_state *s)
hw_error("Core module interrupt\n");
}
-static void integratorcm_write(void *opaque, a_target_phys_addr offset,
+static void integratorcm_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
integratorcm_state *s = (integratorcm_state *)opaque;
@@ -296,7 +296,7 @@ static void icp_pic_set_irq(void *opaque, int irq, int level)
icp_pic_update(s);
}
-static uint32_t icp_pic_read(void *opaque, a_target_phys_addr offset)
+static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset)
{
icp_pic_state *s = (icp_pic_state *)opaque;
@@ -324,7 +324,7 @@ static uint32_t icp_pic_read(void *opaque, a_target_phys_addr offset)
}
}
-static void icp_pic_write(void *opaque, a_target_phys_addr offset,
+static void icp_pic_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
icp_pic_state *s = (icp_pic_state *)opaque;
@@ -388,7 +388,7 @@ static int icp_pic_init(SysBusDevice *dev)
}
/* CP control registers. */
-static uint32_t icp_control_read(void *opaque, a_target_phys_addr offset)
+static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
{
switch (offset >> 2) {
case 0: /* CP_IDFIELD */
@@ -405,7 +405,7 @@ static uint32_t icp_control_read(void *opaque, a_target_phys_addr offset)
}
}
-static void icp_control_write(void *opaque, a_target_phys_addr offset,
+static void icp_control_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
switch (offset >> 2) {
@@ -448,13 +448,13 @@ static struct arm_boot_info integrator_binfo = {
.board_id = 0x113,
};
-static void integratorcp_init(a_ram_addr ram_size,
+static void integratorcp_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
- a_ram_addr ram_offset;
+ ram_addr_t ram_offset;
qemu_irq pic[32];
qemu_irq *cpu_pic;
DeviceState *dev;
diff --git a/hw/ioapic.c b/hw/ioapic.c
index 1186a18bb..b0ad78f24 100644
--- a/hw/ioapic.c
+++ b/hw/ioapic.c
@@ -119,7 +119,7 @@ void ioapic_set_irq(void *opaque, int vector, int level)
}
}
-static uint32_t ioapic_mem_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
{
IOAPICState *s = opaque;
int index;
@@ -155,7 +155,7 @@ static uint32_t ioapic_mem_readl(void *opaque, a_target_phys_addr addr)
return val;
}
-static void ioapic_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
IOAPICState *s = opaque;
int index;
diff --git a/hw/iommu.c b/hw/iommu.c
index 3fe039700..20da7ab96 100644
--- a/hw/iommu.c
+++ b/hw/iommu.c
@@ -130,15 +130,15 @@
typedef struct IOMMUState {
SysBusDevice busdev;
uint32_t regs[IOMMU_NREGS];
- a_target_phys_addr iostart;
+ target_phys_addr_t iostart;
uint32_t version;
qemu_irq irq;
} IOMMUState;
-static uint32_t iommu_mem_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr)
{
IOMMUState *s = opaque;
- a_target_phys_addr saddr;
+ target_phys_addr_t saddr;
uint32_t ret;
saddr = addr >> 2;
@@ -156,11 +156,11 @@ static uint32_t iommu_mem_readl(void *opaque, a_target_phys_addr addr)
return ret;
}
-static void iommu_mem_writel(void *opaque, a_target_phys_addr addr,
+static void iommu_mem_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
IOMMUState *s = opaque;
- a_target_phys_addr saddr;
+ target_phys_addr_t saddr;
saddr = addr >> 2;
DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
@@ -250,12 +250,12 @@ static CPUWriteMemoryFunc * const iommu_mem_write[3] = {
iommu_mem_writel,
};
-static uint32_t iommu_page_get_flags(IOMMUState *s, a_target_phys_addr addr)
+static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
{
uint32_t ret;
- a_target_phys_addr iopte;
+ target_phys_addr_t iopte;
#ifdef DEBUG_IOMMU
- a_target_phys_addr pa = addr;
+ target_phys_addr_t pa = addr;
#endif
iopte = s->regs[IOMMU_BASE] << 4;
@@ -269,11 +269,11 @@ static uint32_t iommu_page_get_flags(IOMMUState *s, a_target_phys_addr addr)
return ret;
}
-static a_target_phys_addr iommu_translate_pa(a_target_phys_addr addr,
+static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
uint32_t pte)
{
uint32_t tmppte;
- a_target_phys_addr pa;
+ target_phys_addr_t pa;
tmppte = pte;
pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
@@ -283,7 +283,7 @@ static a_target_phys_addr iommu_translate_pa(a_target_phys_addr addr,
return pa;
}
-static void iommu_bad_addr(IOMMUState *s, a_target_phys_addr addr,
+static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
int is_write)
{
DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
@@ -295,12 +295,12 @@ static void iommu_bad_addr(IOMMUState *s, a_target_phys_addr addr,
qemu_irq_raise(s->irq);
}
-void sparc_iommu_memory_rw(void *opaque, a_target_phys_addr addr,
+void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
uint8_t *buf, int len, int is_write)
{
int l;
uint32_t flags;
- a_target_phys_addr page, phys_addr;
+ target_phys_addr_t page, phys_addr;
while (len > 0) {
page = addr & IOMMU_PAGE_MASK;
diff --git a/hw/isa.h b/hw/isa.h
index 1644a120a..655ad62c1 100644
--- a/hw/isa.h
+++ b/hw/isa.h
@@ -30,9 +30,9 @@ void isa_qdev_register(ISADeviceInfo *info);
ISADevice *isa_create(const char *name);
ISADevice *isa_create_simple(const char *name);
-extern a_target_phys_addr isa_mem_base;
+extern target_phys_addr_t isa_mem_base;
-void isa_mmio_init(a_target_phys_addr base, a_target_phys_addr size);
+void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
/* dma.c */
int DMA_get_channel_mode (int nchan);
diff --git a/hw/isa_mmio.c b/hw/isa_mmio.c
index 6a1967bab..ed0e189c8 100644
--- a/hw/isa_mmio.c
+++ b/hw/isa_mmio.c
@@ -25,13 +25,13 @@
#include "hw.h"
#include "isa.h"
-static void isa_mmio_writeb (void *opaque, a_target_phys_addr addr,
+static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
cpu_outb(addr & IOPORTS_MASK, val);
}
-static void isa_mmio_writew (void *opaque, a_target_phys_addr addr,
+static void isa_mmio_writew (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@@ -40,7 +40,7 @@ static void isa_mmio_writew (void *opaque, a_target_phys_addr addr,
cpu_outw(addr & IOPORTS_MASK, val);
}
-static void isa_mmio_writel (void *opaque, a_target_phys_addr addr,
+static void isa_mmio_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
@@ -49,7 +49,7 @@ static void isa_mmio_writel (void *opaque, a_target_phys_addr addr,
cpu_outl(addr & IOPORTS_MASK, val);
}
-static uint32_t isa_mmio_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
@@ -57,7 +57,7 @@ static uint32_t isa_mmio_readb (void *opaque, a_target_phys_addr addr)
return val;
}
-static uint32_t isa_mmio_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t isa_mmio_readw (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
@@ -68,7 +68,7 @@ static uint32_t isa_mmio_readw (void *opaque, a_target_phys_addr addr)
return val;
}
-static uint32_t isa_mmio_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t isa_mmio_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
@@ -93,7 +93,7 @@ static CPUReadMemoryFunc * const isa_mmio_read[] = {
static int isa_mmio_iomemtype = 0;
-void isa_mmio_init(a_target_phys_addr base, a_target_phys_addr size)
+void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size)
{
if (!isa_mmio_iomemtype) {
isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read,
diff --git a/hw/jazz_led.c b/hw/jazz_led.c
index 2df0e7f44..18780e937 100644
--- a/hw/jazz_led.c
+++ b/hw/jazz_led.c
@@ -31,15 +31,15 @@
typedef enum {
REDRAW_NONE = 0, REDRAW_SEGMENTS = 1, REDRAW_BACKGROUND = 2,
-} e_screen_state;
+} screen_state_t;
typedef struct LedState {
uint8_t segments;
DisplayState *ds;
- e_screen_state state;
+ screen_state_t state;
} LedState;
-static uint32_t led_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t led_readb(void *opaque, target_phys_addr_t addr)
{
LedState *s = opaque;
uint32_t val;
@@ -58,7 +58,7 @@ static uint32_t led_readb(void *opaque, a_target_phys_addr addr)
return val;
}
-static uint32_t led_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t led_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -71,7 +71,7 @@ static uint32_t led_readw(void *opaque, a_target_phys_addr addr)
return v;
}
-static uint32_t led_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t led_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -88,7 +88,7 @@ static uint32_t led_readl(void *opaque, a_target_phys_addr addr)
return v;
}
-static void led_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void led_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
LedState *s = opaque;
@@ -105,7 +105,7 @@ static void led_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
}
}
-static void led_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void led_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
led_writeb(opaque, addr, (val >> 8) & 0xff);
@@ -116,7 +116,7 @@ static void led_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
#endif
}
-static void led_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void led_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
led_writeb(opaque, addr, (val >> 24) & 0xff);
@@ -282,7 +282,7 @@ static void jazz_led_screen_dump(void *opaque, const char *filename)
printf("jazz_led_screen_dump() not implemented\n");
}
-static void jazz_led_text_update(void *opaque, a_console_ch *chardata)
+static void jazz_led_text_update(void *opaque, console_ch_t *chardata)
{
LedState *s = opaque;
char buf[2];
@@ -298,7 +298,7 @@ static void jazz_led_text_update(void *opaque, a_console_ch *chardata)
dpy_update(s->ds, 0, 0, 2, 1);
}
-void jazz_led_init(a_target_phys_addr base)
+void jazz_led_init(target_phys_addr_t base)
{
LedState *s;
int io;
diff --git a/hw/loader.c b/hw/loader.c
index 16ea3f648..5d83a6604 100644
--- a/hw/loader.c
+++ b/hw/loader.c
@@ -81,10 +81,10 @@ int load_image(const char *filename, uint8_t *addr)
}
/* return the amount read, just like fread. 0 may mean error or eof */
-int fread_targphys(a_target_phys_addr dst_addr, size_t nbytes, FILE *f)
+int fread_targphys(target_phys_addr_t dst_addr, size_t nbytes, FILE *f)
{
uint8_t buf[4096];
- a_target_phys_addr dst_begin = dst_addr;
+ target_phys_addr_t dst_begin = dst_addr;
size_t want, did;
while (nbytes) {
@@ -101,16 +101,16 @@ int fread_targphys(a_target_phys_addr dst_addr, size_t nbytes, FILE *f)
}
/* returns 0 on error, 1 if ok */
-int fread_targphys_ok(a_target_phys_addr dst_addr, size_t nbytes, FILE *f)
+int fread_targphys_ok(target_phys_addr_t dst_addr, size_t nbytes, FILE *f)
{
return fread_targphys(dst_addr, nbytes, f) == nbytes;
}
/* read()-like version */
-int read_targphys(int fd, a_target_phys_addr dst_addr, size_t nbytes)
+int read_targphys(int fd, target_phys_addr_t dst_addr, size_t nbytes)
{
uint8_t buf[4096];
- a_target_phys_addr dst_begin = dst_addr;
+ target_phys_addr_t dst_begin = dst_addr;
size_t want, did;
while (nbytes) {
@@ -127,7 +127,7 @@ int read_targphys(int fd, a_target_phys_addr dst_addr, size_t nbytes)
/* return the size or -1 if error */
int load_image_targphys(const char *filename,
- a_target_phys_addr addr, int max_sz)
+ target_phys_addr_t addr, int max_sz)
{
FILE *f;
size_t got;
@@ -142,7 +142,7 @@ int load_image_targphys(const char *filename,
return got;
}
-void pstrcpy_targphys(a_target_phys_addr dest, int buf_size,
+void pstrcpy_targphys(target_phys_addr_t dest, int buf_size,
const char *source)
{
static const uint8_t nul_byte = 0;
@@ -204,8 +204,8 @@ static void bswap_ahdr(struct exec *e)
: (_N_SEGMENT_ROUND (_N_TXTENDADDR(x, target_page_size), target_page_size)))
-int load_aout(const char *filename, a_target_phys_addr addr, int max_sz,
- int bswap_needed, a_target_phys_addr target_page_size)
+int load_aout(const char *filename, target_phys_addr_t addr, int max_sz,
+ int bswap_needed, target_phys_addr_t target_page_size)
{
int fd, size, ret;
struct exec e;
@@ -358,7 +358,7 @@ int load_elf(const char *filename, int64_t address_offset,
return -1;
}
-static void bswap_uboot_header(an_uboot_image_header *hdr)
+static void bswap_uboot_header(uboot_image_header_t *hdr)
{
#ifndef HOST_WORDS_BIGENDIAN
bswap32s(&hdr->ih_magic);
@@ -457,13 +457,13 @@ static ssize_t gunzip(void *dst, size_t dstlen, uint8_t *src,
}
/* Load a U-Boot image. */
-int load_uimage(const char *filename, a_target_phys_addr *ep,
- a_target_phys_addr *loadaddr, int *is_linux)
+int load_uimage(const char *filename, target_phys_addr_t *ep,
+ target_phys_addr_t *loadaddr, int *is_linux)
{
int fd;
int size;
- an_uboot_image_header h;
- an_uboot_image_header *hdr = &h;
+ uboot_image_header_t h;
+ uboot_image_header_t *hdr = &h;
uint8_t *data = NULL;
int ret = -1;
@@ -471,7 +471,7 @@ int load_uimage(const char *filename, a_target_phys_addr *ep,
if (fd < 0)
return -1;
- size = read(fd, hdr, sizeof(an_uboot_image_header));
+ size = read(fd, hdr, sizeof(uboot_image_header_t));
if (size < 0)
goto out;
diff --git a/hw/loader.h b/hw/loader.h
index 23443b284..363200892 100644
--- a/hw/loader.h
+++ b/hw/loader.h
@@ -4,18 +4,18 @@
/* loader.c */
int get_image_size(const char *filename);
int load_image(const char *filename, uint8_t *addr); /* deprecated */
-int load_image_targphys(const char *filename, a_target_phys_addr, int max_sz);
+int load_image_targphys(const char *filename, target_phys_addr_t, int max_sz);
int load_elf(const char *filename, int64_t address_offset,
uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr,
int big_endian, int elf_machine, int clear_lsb);
-int load_aout(const char *filename, a_target_phys_addr addr, int max_sz,
- int bswap_needed, a_target_phys_addr target_page_size);
-int load_uimage(const char *filename, a_target_phys_addr *ep,
- a_target_phys_addr *loadaddr, int *is_linux);
+int load_aout(const char *filename, target_phys_addr_t addr, int max_sz,
+ int bswap_needed, target_phys_addr_t target_page_size);
+int load_uimage(const char *filename, target_phys_addr_t *ep,
+ target_phys_addr_t *loadaddr, int *is_linux);
-int fread_targphys(a_target_phys_addr dst_addr, size_t nbytes, FILE *f);
-int fread_targphys_ok(a_target_phys_addr dst_addr, size_t nbytes, FILE *f);
-int read_targphys(int fd, a_target_phys_addr dst_addr, size_t nbytes);
-void pstrcpy_targphys(a_target_phys_addr dest, int buf_size,
+int fread_targphys(target_phys_addr_t dst_addr, size_t nbytes, FILE *f);
+int fread_targphys_ok(target_phys_addr_t dst_addr, size_t nbytes, FILE *f);
+int read_targphys(int fd, target_phys_addr_t dst_addr, size_t nbytes);
+void pstrcpy_targphys(target_phys_addr_t dest, int buf_size,
const char *source);
#endif
diff --git a/hw/lsi53c895a.c b/hw/lsi53c895a.c
index e47c16481..62bdca803 100644
--- a/hw/lsi53c895a.c
+++ b/hw/lsi53c895a.c
@@ -484,7 +484,7 @@ static void lsi_resume_script(LSIState *s)
static void lsi_do_dma(LSIState *s, int out)
{
uint32_t count;
- a_target_phys_addr addr;
+ target_phys_addr_t addr;
if (!s->current_dma_len) {
/* Wait until data is available. */
@@ -1723,14 +1723,14 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
#undef CASE_SET_REG32
}
-static void lsi_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
LSIState *s = opaque;
lsi_reg_writeb(s, addr & 0xff, val);
}
-static void lsi_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
LSIState *s = opaque;
@@ -1739,7 +1739,7 @@ static void lsi_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
}
-static void lsi_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
LSIState *s = opaque;
@@ -1750,14 +1750,14 @@ static void lsi_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
}
-static uint32_t lsi_mmio_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr)
{
LSIState *s = opaque;
return lsi_reg_readb(s, addr & 0xff);
}
-static uint32_t lsi_mmio_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr)
{
LSIState *s = opaque;
uint32_t val;
@@ -1768,7 +1768,7 @@ static uint32_t lsi_mmio_readw(void *opaque, a_target_phys_addr addr)
return val;
}
-static uint32_t lsi_mmio_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr)
{
LSIState *s = opaque;
uint32_t val;
@@ -1792,7 +1792,7 @@ static CPUWriteMemoryFunc * const lsi_mmio_writefn[3] = {
lsi_mmio_writel,
};
-static void lsi_ram_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
LSIState *s = opaque;
uint32_t newval;
@@ -1806,7 +1806,7 @@ static void lsi_ram_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
s->script_ram[addr >> 2] = newval;
}
-static void lsi_ram_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
LSIState *s = opaque;
uint32_t newval;
@@ -1822,7 +1822,7 @@ static void lsi_ram_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
}
-static void lsi_ram_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
LSIState *s = opaque;
@@ -1830,7 +1830,7 @@ static void lsi_ram_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
s->script_ram[addr >> 2] = val;
}
-static uint32_t lsi_ram_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr)
{
LSIState *s = opaque;
uint32_t val;
@@ -1841,7 +1841,7 @@ static uint32_t lsi_ram_readb(void *opaque, a_target_phys_addr addr)
return val & 0xff;
}
-static uint32_t lsi_ram_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr)
{
LSIState *s = opaque;
uint32_t val;
@@ -1853,7 +1853,7 @@ static uint32_t lsi_ram_readw(void *opaque, a_target_phys_addr addr)
return le16_to_cpu(val);
}
-static uint32_t lsi_ram_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr)
{
LSIState *s = opaque;
diff --git a/hw/m48t59.c b/hw/m48t59.c
index b8ad5b8a0..b9892cc1f 100644
--- a/hw/m48t59.c
+++ b/hw/m48t59.c
@@ -41,7 +41,7 @@
* alarm and a watchdog timer and related control registers. In the
* PPC platform there is also a nvram lock function.
*/
-struct m48t59 {
+struct m48t59_t {
/* Model parameters */
uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
/* Hardware parameters */
@@ -63,12 +63,12 @@ struct m48t59 {
typedef struct M48t59ISAState {
ISADevice busdev;
- a_m48t59 state;
+ m48t59_t state;
} M48t59ISAState;
typedef struct M48t59SysBusState {
SysBusDevice busdev;
- a_m48t59 state;
+ m48t59_t state;
} M48t59SysBusState;
/* Fake timer functions */
@@ -88,7 +88,7 @@ static void alarm_cb (void *opaque)
{
struct tm tm;
uint64_t next_time;
- a_m48t59 *NVRAM = opaque;
+ m48t59_t *NVRAM = opaque;
qemu_set_irq(NVRAM->IRQ, 1);
if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
@@ -130,7 +130,7 @@ static void alarm_cb (void *opaque)
qemu_set_irq(NVRAM->IRQ, 0);
}
-static void set_alarm (a_m48t59 *NVRAM)
+static void set_alarm (m48t59_t *NVRAM)
{
int diff;
if (NVRAM->alrm_timer != NULL) {
@@ -142,12 +142,12 @@ static void set_alarm (a_m48t59 *NVRAM)
}
/* RTC management helpers */
-static inline void get_time (a_m48t59 *NVRAM, struct tm *tm)
+static inline void get_time (m48t59_t *NVRAM, struct tm *tm)
{
qemu_get_timedate(tm, NVRAM->time_offset);
}
-static void set_time (a_m48t59 *NVRAM, struct tm *tm)
+static void set_time (m48t59_t *NVRAM, struct tm *tm)
{
NVRAM->time_offset = qemu_timedate_diff(tm);
set_alarm(NVRAM);
@@ -156,7 +156,7 @@ static void set_time (a_m48t59 *NVRAM, struct tm *tm)
/* Watchdog management */
static void watchdog_cb (void *opaque)
{
- a_m48t59 *NVRAM = opaque;
+ m48t59_t *NVRAM = opaque;
NVRAM->buffer[0x1FF0] |= 0x80;
if (NVRAM->buffer[0x1FF7] & 0x80) {
@@ -170,7 +170,7 @@ static void watchdog_cb (void *opaque)
}
}
-static void set_up_watchdog (a_m48t59 *NVRAM, uint8_t value)
+static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
{
uint64_t interval; /* in 1/16 seconds */
@@ -188,7 +188,7 @@ static void set_up_watchdog (a_m48t59 *NVRAM, uint8_t value)
/* Direct access to NVRAM */
void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
{
- a_m48t59 *NVRAM = opaque;
+ m48t59_t *NVRAM = opaque;
struct tm tm;
int tmp;
@@ -356,7 +356,7 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
uint32_t m48t59_read (void *opaque, uint32_t addr)
{
- a_m48t59 *NVRAM = opaque;
+ m48t59_t *NVRAM = opaque;
struct tm tm;
uint32_t retval = 0xFF;
@@ -463,14 +463,14 @@ uint32_t m48t59_read (void *opaque, uint32_t addr)
void m48t59_set_addr (void *opaque, uint32_t addr)
{
- a_m48t59 *NVRAM = opaque;
+ m48t59_t *NVRAM = opaque;
NVRAM->addr = addr;
}
void m48t59_toggle_lock (void *opaque, int lock)
{
- a_m48t59 *NVRAM = opaque;
+ m48t59_t *NVRAM = opaque;
NVRAM->lock ^= 1 << lock;
}
@@ -478,7 +478,7 @@ void m48t59_toggle_lock (void *opaque, int lock)
/* IO access to NVRAM */
static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
{
- a_m48t59 *NVRAM = opaque;
+ m48t59_t *NVRAM = opaque;
addr -= NVRAM->io_base;
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
@@ -502,7 +502,7 @@ static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
{
- a_m48t59 *NVRAM = opaque;
+ m48t59_t *NVRAM = opaque;
uint32_t retval;
addr -= NVRAM->io_base;
@@ -519,24 +519,24 @@ static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
return retval;
}
-static void nvram_writeb (void *opaque, a_target_phys_addr addr, uint32_t value)
+static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
- a_m48t59 *NVRAM = opaque;
+ m48t59_t *NVRAM = opaque;
m48t59_write(NVRAM, addr, value & 0xff);
}
-static void nvram_writew (void *opaque, a_target_phys_addr addr, uint32_t value)
+static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
- a_m48t59 *NVRAM = opaque;
+ m48t59_t *NVRAM = opaque;
m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
m48t59_write(NVRAM, addr + 1, value & 0xff);
}
-static void nvram_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
+static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
- a_m48t59 *NVRAM = opaque;
+ m48t59_t *NVRAM = opaque;
m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
@@ -544,18 +544,18 @@ static void nvram_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
m48t59_write(NVRAM, addr + 3, value & 0xff);
}
-static uint32_t nvram_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
{
- a_m48t59 *NVRAM = opaque;
+ m48t59_t *NVRAM = opaque;
uint32_t retval;
retval = m48t59_read(NVRAM, addr);
return retval;
}
-static uint32_t nvram_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
{
- a_m48t59 *NVRAM = opaque;
+ m48t59_t *NVRAM = opaque;
uint32_t retval;
retval = m48t59_read(NVRAM, addr) << 8;
@@ -563,9 +563,9 @@ static uint32_t nvram_readw (void *opaque, a_target_phys_addr addr)
return retval;
}
-static uint32_t nvram_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
{
- a_m48t59 *NVRAM = opaque;
+ m48t59_t *NVRAM = opaque;
uint32_t retval;
retval = m48t59_read(NVRAM, addr) << 24;
@@ -589,7 +589,7 @@ static CPUReadMemoryFunc * const nvram_read[] = {
static void m48t59_save(QEMUFile *f, void *opaque)
{
- a_m48t59 *s = opaque;
+ m48t59_t *s = opaque;
qemu_put_8s(f, &s->lock);
qemu_put_be16s(f, &s->addr);
@@ -598,7 +598,7 @@ static void m48t59_save(QEMUFile *f, void *opaque)
static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
{
- a_m48t59 *s = opaque;
+ m48t59_t *s = opaque;
if (version_id != 1)
return -EINVAL;
@@ -612,7 +612,7 @@ static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
static void m48t59_reset(void *opaque)
{
- a_m48t59 *NVRAM = opaque;
+ m48t59_t *NVRAM = opaque;
NVRAM->addr = 0;
NVRAM->lock = 0;
@@ -624,7 +624,7 @@ static void m48t59_reset(void *opaque)
}
/* Initialisation routine */
-a_m48t59 *m48t59_init (qemu_irq IRQ, a_target_phys_addr mem_base,
+m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
uint32_t io_base, uint16_t size,
int type)
{
@@ -652,11 +652,11 @@ a_m48t59 *m48t59_init (qemu_irq IRQ, a_target_phys_addr mem_base,
return &d->state;
}
-a_m48t59 *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
+m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
{
M48t59ISAState *d;
ISADevice *dev;
- a_m48t59 *s;
+ m48t59_t *s;
dev = isa_create("m48t59_isa");
qdev_prop_set_uint32(&dev->qdev, "type", type);
@@ -674,7 +674,7 @@ a_m48t59 *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
return s;
}
-static void m48t59_init_common(a_m48t59 *s)
+static void m48t59_init_common(m48t59_t *s)
{
s->buffer = qemu_mallocz(s->size);
if (s->type == 59) {
@@ -690,7 +690,7 @@ static void m48t59_init_common(a_m48t59 *s)
static int m48t59_init_isa1(ISADevice *dev)
{
M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev);
- a_m48t59 *s = &d->state;
+ m48t59_t *s = &d->state;
isa_init_irq(dev, &s->IRQ, 8);
m48t59_init_common(s);
@@ -701,7 +701,7 @@ static int m48t59_init_isa1(ISADevice *dev)
static int m48t59_init1(SysBusDevice *dev)
{
M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev);
- a_m48t59 *s = &d->state;
+ m48t59_t *s = &d->state;
int mem_index;
sysbus_init_irq(dev, &s->IRQ);
diff --git a/hw/mac_dbdma.c b/hw/mac_dbdma.c
index f44b90b33..c88ba2b8d 100644
--- a/hw/mac_dbdma.c
+++ b/hw/mac_dbdma.c
@@ -693,7 +693,7 @@ dbdma_control_write(DBDMA_channel *ch)
}
static void dbdma_writel (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
int channel = addr >> DBDMA_CHANNEL_SHIFT;
DBDMA_channel *ch = (DBDMA_channel *)opaque + channel;
@@ -741,7 +741,7 @@ static void dbdma_writel (void *opaque,
}
}
-static uint32_t dbdma_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t value;
int channel = addr >> DBDMA_CHANNEL_SHIFT;
diff --git a/hw/mac_dbdma.h b/hw/mac_dbdma.h
index c8c82af2d..d236c5b3f 100644
--- a/hw/mac_dbdma.h
+++ b/hw/mac_dbdma.h
@@ -28,7 +28,7 @@ typedef void (*DBDMA_end)(DBDMA_io *io);
struct DBDMA_io {
void *opaque;
void *channel;
- a_target_phys_addr addr;
+ target_phys_addr_t addr;
int len;
int is_last;
int is_dma_out;
diff --git a/hw/mac_nvram.c b/hw/mac_nvram.c
index 60cc56ef3..0c91b3f1b 100644
--- a/hw/mac_nvram.c
+++ b/hw/mac_nvram.c
@@ -38,7 +38,7 @@
#endif
struct MacIONVRAMState {
- a_target_phys_addr size;
+ target_phys_addr_t size;
int mem_index;
unsigned int it_shift;
uint8_t *data;
@@ -72,7 +72,7 @@ void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val)
/* macio style NVRAM device */
static void macio_nvram_writeb (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
MacIONVRAMState *s = opaque;
@@ -81,7 +81,7 @@ static void macio_nvram_writeb (void *opaque,
NVR_DPRINTF("writeb addr %04x val %x\n", (int)addr, value);
}
-static uint32_t macio_nvram_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
{
MacIONVRAMState *s = opaque;
uint32_t value;
@@ -128,7 +128,7 @@ static void macio_nvram_reset(void *opaque)
{
}
-MacIONVRAMState *macio_nvram_init (int *mem_index, a_target_phys_addr size,
+MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size,
unsigned int it_shift)
{
MacIONVRAMState *s;
@@ -148,7 +148,7 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, a_target_phys_addr size,
return s;
}
-void macio_nvram_map (void *opaque, a_target_phys_addr mem_base)
+void macio_nvram_map (void *opaque, target_phys_addr_t mem_base)
{
MacIONVRAMState *s;
diff --git a/hw/macio.c b/hw/macio.c
index 52d05d8e7..8cfadfc5e 100644
--- a/hw/macio.c
+++ b/hw/macio.c
@@ -27,8 +27,8 @@
#include "pci.h"
#include "escc.h"
-typedef struct macio_state a_macio_state;
-struct macio_state {
+typedef struct macio_state_t macio_state_t;
+struct macio_state_t {
int is_oldworld;
int pic_mem_index;
int dbdma_mem_index;
@@ -42,10 +42,10 @@ struct macio_state {
static void macio_map (PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
- a_macio_state *macio_state;
+ macio_state_t *macio_state;
int i;
- macio_state = (a_macio_state *)(pci_dev + 1);
+ macio_state = (macio_state_t *)(pci_dev + 1);
if (macio_state->pic_mem_index >= 0) {
if (macio_state->is_oldworld) {
/* Heathrow PIC */
@@ -84,13 +84,13 @@ void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
int nb_ide, int *ide_mem_index, int escc_mem_index)
{
PCIDevice *d;
- a_macio_state *macio_state;
+ macio_state_t *macio_state;
int i;
d = pci_register_device(bus, "macio",
- sizeof(PCIDevice) + sizeof(a_macio_state),
+ sizeof(PCIDevice) + sizeof(macio_state_t),
-1, NULL, NULL);
- macio_state = (a_macio_state *)(d + 1);
+ macio_state = (macio_state_t *)(d + 1);
macio_state->is_oldworld = is_oldworld;
macio_state->pic_mem_index = pic_mem_index;
macio_state->dbdma_mem_index = dbdma_mem_index;
diff --git a/hw/mainstone.c b/hw/mainstone.c
index 74d81021d..3e517f070 100644
--- a/hw/mainstone.c
+++ b/hw/mainstone.c
@@ -68,13 +68,13 @@ static struct arm_boot_info mainstone_binfo = {
.ram_size = 0x04000000,
};
-static void mainstone_common_init(a_ram_addr ram_size,
+static void mainstone_common_init(ram_addr_t ram_size,
const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, enum mainstone_model_e model, int arm_id)
{
uint32_t sector_len = 256 * 1024;
- a_target_phys_addr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
+ target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
PXA2xxState *cpu;
qemu_irq *mst_irq;
DriveInfo *dinfo;
@@ -127,7 +127,7 @@ static void mainstone_common_init(a_ram_addr ram_size,
arm_load_kernel(cpu->env, &mainstone_binfo);
}
-static void mainstone_init(a_ram_addr ram_size,
+static void mainstone_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
diff --git a/hw/marvell_88w8618_audio.c b/hw/marvell_88w8618_audio.c
index a3777350e..1c68da3c7 100644
--- a/hw/marvell_88w8618_audio.c
+++ b/hw/marvell_88w8618_audio.c
@@ -133,7 +133,7 @@ static void mv88w8618_audio_clock_update(mv88w8618_audio_state *s)
wm8750_set_bclk_in(s->wm, rate);
}
-static uint32_t mv88w8618_audio_read(void *opaque, a_target_phys_addr offset)
+static uint32_t mv88w8618_audio_read(void *opaque, target_phys_addr_t offset)
{
mv88w8618_audio_state *s = opaque;
@@ -158,7 +158,7 @@ static uint32_t mv88w8618_audio_read(void *opaque, a_target_phys_addr offset)
}
}
-static void mv88w8618_audio_write(void *opaque, a_target_phys_addr offset,
+static void mv88w8618_audio_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
mv88w8618_audio_state *s = opaque;
diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c
index cef813eb1..9d6a62751 100644
--- a/hw/mc146818rtc.c
+++ b/hw/mc146818rtc.c
@@ -659,7 +659,7 @@ static void mc146818rtc_register(void)
device_init(mc146818rtc_register)
/* Memory mapped interface */
-static uint32_t cmos_mm_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
{
RTCState *s = opaque;
@@ -667,14 +667,14 @@ static uint32_t cmos_mm_readb (void *opaque, a_target_phys_addr addr)
}
static void cmos_mm_writeb (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
RTCState *s = opaque;
cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF);
}
-static uint32_t cmos_mm_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
{
RTCState *s = opaque;
uint32_t val;
@@ -687,7 +687,7 @@ static uint32_t cmos_mm_readw (void *opaque, a_target_phys_addr addr)
}
static void cmos_mm_writew (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
RTCState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -696,7 +696,7 @@ static void cmos_mm_writew (void *opaque,
cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
}
-static uint32_t cmos_mm_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
{
RTCState *s = opaque;
uint32_t val;
@@ -709,7 +709,7 @@ static uint32_t cmos_mm_readl (void *opaque, a_target_phys_addr addr)
}
static void cmos_mm_writel (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
RTCState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -730,7 +730,7 @@ static CPUWriteMemoryFunc * const rtc_mm_write[] = {
&cmos_mm_writel,
};
-RTCState *rtc_mm_init(a_target_phys_addr base, int it_shift, qemu_irq irq,
+RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
int base_year)
{
RTCState *s;
diff --git a/hw/mcf.h b/hw/mcf.h
index edf25754b..91f2821f1 100644
--- a/hw/mcf.h
+++ b/hw/mcf.h
@@ -3,17 +3,17 @@
/* Motorola ColdFire device prototypes. */
/* mcf_uart.c */
-uint32_t mcf_uart_read(void *opaque, a_target_phys_addr addr);
-void mcf_uart_write(void *opaque, a_target_phys_addr addr, uint32_t val);
+uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
+void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
-void mcf_uart_mm_init(a_target_phys_addr base, qemu_irq irq,
+void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
CharDriverState *chr);
/* mcf_intc.c */
-qemu_irq *mcf_intc_init(a_target_phys_addr base, CPUState *env);
+qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
/* mcf_fec.c */
-void mcf_fec_init(NICInfo *nd, a_target_phys_addr base, qemu_irq *irq);
+void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
/* mcf5206.c */
qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
diff --git a/hw/mcf5206.c b/hw/mcf5206.c
index b9930d87c..c107de8c6 100644
--- a/hw/mcf5206.c
+++ b/hw/mcf5206.c
@@ -367,10 +367,10 @@ static const int m5206_mbar_width[] =
/* 1c0-200 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
};
-static uint32_t m5206_mbar_readw(void *opaque, a_target_phys_addr offset);
-static uint32_t m5206_mbar_readl(void *opaque, a_target_phys_addr offset);
+static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset);
+static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset);
-static uint32_t m5206_mbar_readb(void *opaque, a_target_phys_addr offset)
+static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
offset &= 0x3ff;
@@ -388,7 +388,7 @@ static uint32_t m5206_mbar_readb(void *opaque, a_target_phys_addr offset)
return m5206_mbar_read(s, offset);
}
-static uint32_t m5206_mbar_readw(void *opaque, a_target_phys_addr offset)
+static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
int width;
@@ -412,7 +412,7 @@ static uint32_t m5206_mbar_readw(void *opaque, a_target_phys_addr offset)
return m5206_mbar_read(s, offset);
}
-static uint32_t m5206_mbar_readl(void *opaque, a_target_phys_addr offset)
+static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
int width;
@@ -430,12 +430,12 @@ static uint32_t m5206_mbar_readl(void *opaque, a_target_phys_addr offset)
return m5206_mbar_read(s, offset);
}
-static void m5206_mbar_writew(void *opaque, a_target_phys_addr offset,
+static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
uint32_t value);
-static void m5206_mbar_writel(void *opaque, a_target_phys_addr offset,
+static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
uint32_t value);
-static void m5206_mbar_writeb(void *opaque, a_target_phys_addr offset,
+static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
@@ -459,7 +459,7 @@ static void m5206_mbar_writeb(void *opaque, a_target_phys_addr offset,
m5206_mbar_write(s, offset, value);
}
-static void m5206_mbar_writew(void *opaque, a_target_phys_addr offset,
+static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
@@ -487,7 +487,7 @@ static void m5206_mbar_writew(void *opaque, a_target_phys_addr offset,
m5206_mbar_write(s, offset, value);
}
-static void m5206_mbar_writel(void *opaque, a_target_phys_addr offset,
+static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
diff --git a/hw/mcf5208.c b/hw/mcf5208.c
index 46bcfe75a..559861146 100644
--- a/hw/mcf5208.c
+++ b/hw/mcf5208.c
@@ -42,7 +42,7 @@ static void m5208_timer_update(m5208_timer_state *s)
qemu_irq_lower(s->irq);
}
-static void m5208_timer_write(void *opaque, a_target_phys_addr offset,
+static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
@@ -104,7 +104,7 @@ static void m5208_timer_trigger(void *opaque)
m5208_timer_update(s);
}
-static uint32_t m5208_timer_read(void *opaque, a_target_phys_addr addr)
+static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
switch (addr) {
@@ -132,7 +132,7 @@ static CPUWriteMemoryFunc * const m5208_timer_writefn[] = {
m5208_timer_write
};
-static uint32_t m5208_sys_read(void *opaque, a_target_phys_addr addr)
+static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
{
switch (addr) {
case 0x110: /* SDCS0 */
@@ -153,7 +153,7 @@ static uint32_t m5208_sys_read(void *opaque, a_target_phys_addr addr)
}
}
-static void m5208_sys_write(void *opaque, a_target_phys_addr addr,
+static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
@@ -195,7 +195,7 @@ static void mcf5208_sys_init(qemu_irq *pic)
}
}
-static void mcf5208evb_init(a_ram_addr ram_size,
+static void mcf5208evb_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@@ -203,7 +203,7 @@ static void mcf5208evb_init(a_ram_addr ram_size,
CPUState *env;
int kernel_size;
uint64_t elf_entry;
- a_target_phys_addr entry;
+ target_phys_addr_t entry;
qemu_irq *pic;
if (!cpu_model)
diff --git a/hw/mcf_fec.c b/hw/mcf_fec.c
index e21af42e3..f6d2bab12 100644
--- a/hw/mcf_fec.c
+++ b/hw/mcf_fec.c
@@ -214,7 +214,7 @@ static void mcf_fec_reset(mcf_fec_state *s)
s->rfsr = 0x500;
}
-static uint32_t mcf_fec_read(void *opaque, a_target_phys_addr addr)
+static uint32_t mcf_fec_read(void *opaque, target_phys_addr_t addr)
{
mcf_fec_state *s = (mcf_fec_state *)opaque;
switch (addr & 0x3ff) {
@@ -251,7 +251,7 @@ static uint32_t mcf_fec_read(void *opaque, a_target_phys_addr addr)
}
}
-static void mcf_fec_write(void *opaque, a_target_phys_addr addr, uint32_t value)
+static void mcf_fec_write(void *opaque, target_phys_addr_t addr, uint32_t value)
{
mcf_fec_state *s = (mcf_fec_state *)opaque;
switch (addr & 0x3ff) {
@@ -450,7 +450,7 @@ static void mcf_fec_cleanup(VLANClientState *vc)
qemu_free(s);
}
-void mcf_fec_init(NICInfo *nd, a_target_phys_addr base, qemu_irq *irq)
+void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq)
{
mcf_fec_state *s;
diff --git a/hw/mcf_intc.c b/hw/mcf_intc.c
index 35a42dc9b..f01bd320a 100644
--- a/hw/mcf_intc.c
+++ b/hw/mcf_intc.c
@@ -41,7 +41,7 @@ static void mcf_intc_update(mcf_intc_state *s)
m68k_set_irq_level(s->env, best_level, s->active_vector);
}
-static uint32_t mcf_intc_read(void *opaque, a_target_phys_addr addr)
+static uint32_t mcf_intc_read(void *opaque, target_phys_addr_t addr)
{
int offset;
mcf_intc_state *s = (mcf_intc_state *)opaque;
@@ -73,7 +73,7 @@ static uint32_t mcf_intc_read(void *opaque, a_target_phys_addr addr)
}
}
-static void mcf_intc_write(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void mcf_intc_write(void *opaque, target_phys_addr_t addr, uint32_t val)
{
int offset;
mcf_intc_state *s = (mcf_intc_state *)opaque;
@@ -139,7 +139,7 @@ static CPUWriteMemoryFunc * const mcf_intc_writefn[] = {
mcf_intc_write
};
-qemu_irq *mcf_intc_init(a_target_phys_addr base, CPUState *env)
+qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env)
{
mcf_intc_state *s;
int iomemtype;
diff --git a/hw/mcf_uart.c b/hw/mcf_uart.c
index 68e6cf6a5..d16bac733 100644
--- a/hw/mcf_uart.c
+++ b/hw/mcf_uart.c
@@ -64,7 +64,7 @@ static void mcf_uart_update(mcf_uart_state *s)
qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
}
-uint32_t mcf_uart_read(void *opaque, a_target_phys_addr addr)
+uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr)
{
mcf_uart_state *s = (mcf_uart_state *)opaque;
switch (addr & 0x3f) {
@@ -182,7 +182,7 @@ static void mcf_do_command(mcf_uart_state *s, uint8_t cmd)
}
}
-void mcf_uart_write(void *opaque, a_target_phys_addr addr, uint32_t val)
+void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val)
{
mcf_uart_state *s = (mcf_uart_state *)opaque;
switch (addr & 0x3f) {
@@ -296,7 +296,7 @@ static CPUWriteMemoryFunc * const mcf_uart_writefn[] = {
mcf_uart_write
};
-void mcf_uart_mm_init(a_target_phys_addr base, qemu_irq irq,
+void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
CharDriverState *chr)
{
mcf_uart_state *s;
diff --git a/hw/mips.h b/hw/mips.h
index e75fea722..5fd72bb02 100644
--- a/hw/mips.h
+++ b/hw/mips.h
@@ -6,19 +6,19 @@
PCIBus *pci_gt64120_init(qemu_irq *pic);
/* ds1225y.c */
-void *ds1225y_init(a_target_phys_addr mem_base, const char *filename);
+void *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
void ds1225y_set_protection(void *opaque, int protection);
/* g364fb.c */
-int g364fb_mm_init(a_target_phys_addr vram_base,
- a_target_phys_addr ctrl_base, int it_shift,
+int g364fb_mm_init(target_phys_addr_t vram_base,
+ target_phys_addr_t ctrl_base, int it_shift,
qemu_irq irq);
/* mipsnet.c */
void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
/* jazz_led.c */
-extern void jazz_led_init(a_target_phys_addr base);
+extern void jazz_led_init(target_phys_addr_t base);
/* mips_int.c */
extern void cpu_mips_irq_init_cpu(CPUState *env);
@@ -28,7 +28,7 @@ extern void cpu_mips_clock_init(CPUState *);
/* rc4030.c */
typedef struct rc4030DMAState *rc4030_dma;
-void rc4030_dma_memory_rw(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write);
+void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
void rc4030_dma_read(void *dma, uint8_t *buf, int len);
void rc4030_dma_write(void *dma, uint8_t *buf, int len);
@@ -36,8 +36,8 @@ void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
qemu_irq **irqs, rc4030_dma **dmas);
/* dp8393x.c */
-void dp83932_init(NICInfo *nd, a_target_phys_addr base, int it_shift,
+void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
qemu_irq irq, void* mem_opaque,
- void (*memory_rw)(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write));
+ void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write));
#endif
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index 9d0f0ecc3..2a70b8bec 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -47,12 +47,12 @@ static void main_cpu_reset(void *opaque)
cpu_reset(env);
}
-static uint32_t rtc_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
{
return cpu_inw(0x71);
}
-static void rtc_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
cpu_outw(0x71, val & 0xff);
}
@@ -69,7 +69,7 @@ static CPUWriteMemoryFunc * const rtc_write[3] = {
rtc_writeb,
};
-static void dma_dummy_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
/* Nothing to do. That is only to ensure that
* the current DMA acknowledge cycle is completed. */
@@ -113,7 +113,7 @@ static void audio_init(qemu_irq *pic)
#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
static
-void mips_jazz_init (a_ram_addr ram_size,
+void mips_jazz_init (ram_addr_t ram_size,
const char *cpu_model,
enum jazz_model_e jazz_model)
{
@@ -128,8 +128,8 @@ void mips_jazz_init (a_ram_addr ram_size,
PITState *pit;
BlockDriverState *fds[MAX_FD];
qemu_irq esp_reset;
- a_ram_addr ram_offset;
- a_ram_addr bios_offset;
+ ram_addr_t ram_offset;
+ ram_addr_t bios_offset;
/* init CPUs */
if (cpu_model == NULL) {
@@ -271,7 +271,7 @@ void mips_jazz_init (a_ram_addr ram_size,
}
static
-void mips_magnum_init (a_ram_addr ram_size,
+void mips_magnum_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@@ -280,7 +280,7 @@ void mips_magnum_init (a_ram_addr ram_size,
}
static
-void mips_pica61_init (a_ram_addr ram_size,
+void mips_pica61_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 748c07897..e09e971b3 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -117,7 +117,7 @@ static void malta_fpga_update_display(void *opaque)
# define logout(fmt, ...) ((void)0)
#endif
-struct eeprom24c0x {
+struct _eeprom24c0x_t {
uint8_t tick;
uint8_t address;
uint8_t command;
@@ -129,9 +129,9 @@ struct eeprom24c0x {
uint8_t contents[256];
};
-typedef struct eeprom24c0x a_eeprom24c0x;
+typedef struct _eeprom24c0x_t eeprom24c0x_t;
-static a_eeprom24c0x eeprom = {
+static eeprom24c0x_t eeprom = {
.contents = {
/* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00,
/* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
@@ -217,7 +217,7 @@ static void eeprom24c0x_write(int scl, int sda)
eeprom.sda = sda;
}
-static uint32_t malta_fpga_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
{
MaltaFPGAState *s = opaque;
uint32_t val = 0;
@@ -304,7 +304,7 @@ static uint32_t malta_fpga_readl(void *opaque, a_target_phys_addr addr)
return val;
}
-static void malta_fpga_writel(void *opaque, a_target_phys_addr addr,
+static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
MaltaFPGAState *s = opaque;
@@ -431,7 +431,7 @@ static void malta_fpga_led_init(CharDriverState *chr)
qemu_chr_printf(chr, "+--------+\r\n");
}
-static MaltaFPGAState *malta_fpga_init(a_target_phys_addr base, qemu_irq uart_irq, CharDriverState *uart_chr)
+static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_irq, CharDriverState *uart_chr)
{
MaltaFPGAState *s;
int malta;
@@ -658,7 +658,7 @@ static void write_bootloader (CPUState *env, uint8_t *base,
static void prom_set(int index, const char *string, ...)
{
char buf[ENVP_ENTRY_SIZE];
- a_target_phys_addr p;
+ target_phys_addr_t p;
va_list ap;
int32_t table_addr;
@@ -688,7 +688,7 @@ static int64_t load_kernel (CPUState *env)
int64_t kernel_entry, kernel_low, kernel_high;
int index = 0;
long initrd_size;
- a_ram_addr initrd_offset;
+ ram_addr_t initrd_offset;
int big_endian;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -763,21 +763,21 @@ static void main_cpu_reset(void *opaque)
}
static
-void mips_malta_init (a_ram_addr ram_size,
+void mips_malta_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
char *filename;
- a_ram_addr ram_offset;
- a_ram_addr bios_offset;
+ ram_addr_t ram_offset;
+ ram_addr_t bios_offset;
target_long bios_size;
int64_t kernel_entry;
PCIBus *pci_bus;
ISADevice *isa_dev;
CPUState *env;
RTCState *rtc_state;
- a_fdctrl *floppy_controller;
+ fdctrl_t *floppy_controller;
MaltaFPGAState *malta_fpga;
qemu_irq *i8259;
int piix4_devfn;
diff --git a/hw/mips_mipssim.c b/hw/mips_mipssim.c
index 05751f1f5..9aed40e1b 100644
--- a/hw/mips_mipssim.c
+++ b/hw/mips_mipssim.c
@@ -55,7 +55,7 @@ static void load_kernel (CPUState *env)
int64_t entry, kernel_low, kernel_high;
long kernel_size;
long initrd_size;
- a_ram_addr initrd_offset;
+ ram_addr_t initrd_offset;
int big_endian;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -111,14 +111,14 @@ static void main_cpu_reset(void *opaque)
}
static void
-mips_mipssim_init (a_ram_addr ram_size,
+mips_mipssim_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
char *filename;
- a_ram_addr ram_offset;
- a_ram_addr bios_offset;
+ ram_addr_t ram_offset;
+ ram_addr_t bios_offset;
CPUState *env;
int bios_size;
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
index e10d5002d..b3abc6155 100644
--- a/hw/mips_r4k.c
+++ b/hw/mips_r4k.c
@@ -45,7 +45,7 @@ static struct _loaderparams {
const char *initrd_filename;
} loaderparams;
-static void mips_qemu_writel (void *opaque, a_target_phys_addr addr,
+static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
if ((addr & 0xffff) == 0 && val == 42)
@@ -54,7 +54,7 @@ static void mips_qemu_writel (void *opaque, a_target_phys_addr addr,
qemu_system_shutdown_request ();
}
-static uint32_t mips_qemu_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
{
return 0;
}
@@ -77,7 +77,7 @@ static void load_kernel (CPUState *env)
{
int64_t entry, kernel_low, kernel_high;
long kernel_size, initrd_size;
- a_ram_addr initrd_offset;
+ ram_addr_t initrd_offset;
int ret;
int big_endian;
@@ -151,14 +151,14 @@ static void main_cpu_reset(void *opaque)
static const int sector_len = 32 * 1024;
static
-void mips_r4k_init (a_ram_addr ram_size,
+void mips_r4k_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
char *filename;
- a_ram_addr ram_offset;
- a_ram_addr bios_offset;
+ ram_addr_t ram_offset;
+ ram_addr_t bios_offset;
int bios_size;
CPUState *env;
RTCState *rtc_state;
diff --git a/hw/mpcore.c b/hw/mpcore.c
index c8d307c57..46c2b9d99 100644
--- a/hw/mpcore.c
+++ b/hw/mpcore.c
@@ -155,7 +155,7 @@ static void mpcore_timer_init(mpcore_priv_state *mpcore,
/* Per-CPU private memory mapped IO. */
-static uint32_t mpcore_priv_read(void *opaque, a_target_phys_addr offset)
+static uint32_t mpcore_priv_read(void *opaque, target_phys_addr_t offset)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
int id;
@@ -199,7 +199,7 @@ bad_reg:
return 0;
}
-static void mpcore_priv_write(void *opaque, a_target_phys_addr offset,
+static void mpcore_priv_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
@@ -255,7 +255,7 @@ static CPUWriteMemoryFunc * const mpcore_priv_writefn[] = {
mpcore_priv_write
};
-static void mpcore_priv_map(SysBusDevice *dev, a_target_phys_addr base)
+static void mpcore_priv_map(SysBusDevice *dev, target_phys_addr_t base)
{
mpcore_priv_state *s = FROM_SYSBUSGIC(mpcore_priv_state, dev);
cpu_register_physical_memory(base, 0x1000, s->iomemtype);
diff --git a/hw/msix.c b/hw/msix.c
index 80f22095a..3782994ca 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -123,7 +123,7 @@ void msix_write_config(PCIDevice *dev, uint32_t addr,
qemu_set_irq(dev->irq[0], 0);
}
-static uint32_t msix_mmio_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
{
PCIDevice *dev = opaque;
unsigned int offset = addr & (dev->msix_page_size - 1);
@@ -135,7 +135,7 @@ static uint32_t msix_mmio_readl(void *opaque, a_target_phys_addr addr)
return val;
}
-static uint32_t msix_mmio_read_unallowed(void *opaque, a_target_phys_addr addr)
+static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
{
fprintf(stderr, "MSI-X: only dword read is allowed!\n");
return 0;
@@ -172,7 +172,7 @@ static int msix_is_masked(PCIDevice *dev, int vector)
return dev->msix_table_page[offset] & MSIX_VECTOR_MASK;
}
-static void msix_mmio_writel(void *opaque, a_target_phys_addr addr,
+static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
PCIDevice *dev = opaque;
@@ -185,7 +185,7 @@ static void msix_mmio_writel(void *opaque, a_target_phys_addr addr,
}
}
-static void msix_mmio_write_unallowed(void *opaque, a_target_phys_addr addr,
+static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
fprintf(stderr, "MSI-X: only dword write is allowed!\n");
@@ -221,7 +221,7 @@ void msix_mmio_map(PCIDevice *d, int region_num,
/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
* modified, it should be retrieved with msix_bar_size. */
int msix_init(struct PCIDevice *dev, unsigned short nentries,
- unsigned bar_nr, unsigned bar_size, a_target_phys_addr page_size)
+ unsigned bar_nr, unsigned bar_size, target_phys_addr_t page_size)
{
int ret;
/* Nothing to do if MSI is not supported by interrupt controller */
diff --git a/hw/msix.h b/hw/msix.h
index 76f1c97fe..9367ba38f 100644
--- a/hw/msix.h
+++ b/hw/msix.h
@@ -5,7 +5,7 @@
int msix_init(struct PCIDevice *dev, unsigned short nentries,
unsigned bar_nr, unsigned bar_size,
- a_target_phys_addr page_size);
+ target_phys_addr_t page_size);
void msix_write_config(PCIDevice *pci_dev, uint32_t address,
uint32_t val, int len);
diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c
index fc255b4eb..1b6cb7765 100644
--- a/hw/mst_fpga.c
+++ b/hw/mst_fpga.c
@@ -78,7 +78,7 @@ mst_fpga_set_irq(void *opaque, int irq, int level)
static uint32_t
-mst_fpga_readb(void *opaque, a_target_phys_addr addr)
+mst_fpga_readb(void *opaque, target_phys_addr_t addr)
{
mst_irq_state *s = (mst_irq_state *) opaque;
@@ -115,7 +115,7 @@ mst_fpga_readb(void *opaque, a_target_phys_addr addr)
}
static void
-mst_fpga_writeb(void *opaque, a_target_phys_addr addr, uint32_t value)
+mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
{
mst_irq_state *s = (mst_irq_state *) opaque;
value &= 0xffffffff;
diff --git a/hw/musicpal.c b/hw/musicpal.c
index 230c7de96..1c4f17cb9 100644
--- a/hw/musicpal.c
+++ b/hw/musicpal.c
@@ -255,7 +255,7 @@ static void eth_send(mv88w8618_eth_state *s, int queue_index)
} while (desc_addr != s->tx_queue[queue_index]);
}
-static uint32_t mv88w8618_eth_read(void *opaque, a_target_phys_addr offset)
+static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
{
mv88w8618_eth_state *s = opaque;
@@ -296,7 +296,7 @@ static uint32_t mv88w8618_eth_read(void *opaque, a_target_phys_addr offset)
}
}
-static void mv88w8618_eth_write(void *opaque, a_target_phys_addr offset,
+static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
mv88w8618_eth_state *s = opaque;
@@ -481,7 +481,7 @@ static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
s->brightness |= level << irq;
}
-static uint32_t musicpal_lcd_read(void *opaque, a_target_phys_addr offset)
+static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
{
musicpal_lcd_state *s = opaque;
@@ -494,7 +494,7 @@ static uint32_t musicpal_lcd_read(void *opaque, a_target_phys_addr offset)
}
}
-static void musicpal_lcd_write(void *opaque, a_target_phys_addr offset,
+static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
musicpal_lcd_state *s = opaque;
@@ -594,7 +594,7 @@ static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
mv88w8618_pic_update(s);
}
-static uint32_t mv88w8618_pic_read(void *opaque, a_target_phys_addr offset)
+static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
{
mv88w8618_pic_state *s = opaque;
@@ -607,7 +607,7 @@ static uint32_t mv88w8618_pic_read(void *opaque, a_target_phys_addr offset)
}
}
-static void mv88w8618_pic_write(void *opaque, a_target_phys_addr offset,
+static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
mv88w8618_pic_state *s = opaque;
@@ -705,7 +705,7 @@ static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
s->ptimer = ptimer_init(bh);
}
-static uint32_t mv88w8618_pit_read(void *opaque, a_target_phys_addr offset)
+static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
{
mv88w8618_pit_state *s = opaque;
mv88w8618_timer_state *t;
@@ -720,7 +720,7 @@ static uint32_t mv88w8618_pit_read(void *opaque, a_target_phys_addr offset)
}
}
-static void mv88w8618_pit_write(void *opaque, a_target_phys_addr offset,
+static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
mv88w8618_pit_state *s = opaque;
@@ -792,7 +792,7 @@ typedef struct mv88w8618_flashcfg_state {
} mv88w8618_flashcfg_state;
static uint32_t mv88w8618_flashcfg_read(void *opaque,
- a_target_phys_addr offset)
+ target_phys_addr_t offset)
{
mv88w8618_flashcfg_state *s = opaque;
@@ -805,7 +805,7 @@ static uint32_t mv88w8618_flashcfg_read(void *opaque,
}
}
-static void mv88w8618_flashcfg_write(void *opaque, a_target_phys_addr offset,
+static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
mv88w8618_flashcfg_state *s = opaque;
@@ -846,7 +846,7 @@ static int mv88w8618_flashcfg_init(SysBusDevice *dev)
#define MP_BOARD_REVISION 0x31
-static uint32_t musicpal_misc_read(void *opaque, a_target_phys_addr offset)
+static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
{
switch (offset) {
case MP_MISC_BOARD_REVISION:
@@ -857,7 +857,7 @@ static uint32_t musicpal_misc_read(void *opaque, a_target_phys_addr offset)
}
}
-static void musicpal_misc_write(void *opaque, a_target_phys_addr offset,
+static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
}
@@ -887,7 +887,7 @@ static void musicpal_misc_init(void)
#define MP_WLAN_MAGIC1 0x11c
#define MP_WLAN_MAGIC2 0x124
-static uint32_t mv88w8618_wlan_read(void *opaque, a_target_phys_addr offset)
+static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
{
switch (offset) {
/* Workaround to allow loading the binary-only wlandrv.ko crap
@@ -902,7 +902,7 @@ static uint32_t mv88w8618_wlan_read(void *opaque, a_target_phys_addr offset)
}
}
-static void mv88w8618_wlan_write(void *opaque, a_target_phys_addr offset,
+static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
}
@@ -1049,7 +1049,7 @@ static void musicpal_gpio_irq(void *opaque, int irq, int level)
musicpal_gpio_keys_update(s);
}
-static uint32_t musicpal_gpio_read(void *opaque, a_target_phys_addr offset)
+static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
{
musicpal_gpio_state *s = (musicpal_gpio_state *) opaque;
@@ -1080,7 +1080,7 @@ static uint32_t musicpal_gpio_read(void *opaque, a_target_phys_addr offset)
}
}
-static void musicpal_gpio_write(void *opaque, a_target_phys_addr offset,
+static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
musicpal_gpio_state *s = (musicpal_gpio_state *) opaque;
@@ -1275,7 +1275,7 @@ static struct arm_boot_info musicpal_binfo = {
.board_id = 0x20e,
};
-static void musicpal_init(a_ram_addr ram_size,
+static void musicpal_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@@ -1295,7 +1295,7 @@ static void musicpal_init(a_ram_addr ram_size,
int i;
unsigned long flash_size;
DriveInfo *dinfo;
- a_ram_addr sram_off;
+ ram_addr_t sram_off;
if (!cpu_model)
cpu_model = "arm926";
diff --git a/hw/nseries.c b/hw/nseries.c
index 2b8e362da..79f7387ff 100644
--- a/hw/nseries.c
+++ b/hw/nseries.c
@@ -1094,7 +1094,7 @@ static struct omap_partition_info_s {
{ 0, 0, 0, NULL }
};
-static a_bdaddr n8x0_bd_addr = {{ N8X0_BD_ADDR }};
+static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
static int n8x0_atag_setup(void *p, int model)
{
@@ -1265,7 +1265,7 @@ static int n810_atag_setup(struct arm_boot_info *info, void *p)
return n8x0_atag_setup(p, 810);
}
-static void n8x0_init(a_ram_addr ram_size, const char *boot_device,
+static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, struct arm_boot_info *binfo, int model)
@@ -1383,7 +1383,7 @@ static struct arm_boot_info n810_binfo = {
.atag_board = n810_atag_setup,
};
-static void n800_init(a_ram_addr ram_size,
+static void n800_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@@ -1393,7 +1393,7 @@ static void n800_init(a_ram_addr ram_size,
cpu_model, &n800_binfo, 800);
}
-static void n810_init(a_ram_addr ram_size,
+static void n810_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
diff --git a/hw/nvram.h b/hw/nvram.h
index 180de8855..c63fd5f09 100644
--- a/hw/nvram.h
+++ b/hw/nvram.h
@@ -2,26 +2,26 @@
#define NVRAM_H
/* NVRAM helpers */
-typedef uint32_t (*a_nvram_read)(void *private, uint32_t addr);
-typedef void (*a_nvram_write)(void *private, uint32_t addr, uint32_t val);
-typedef struct nvram {
+typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr);
+typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val);
+typedef struct nvram_t {
void *opaque;
- a_nvram_read read_fn;
- a_nvram_write write_fn;
-} a_nvram;
+ nvram_read_t read_fn;
+ nvram_write_t write_fn;
+} nvram_t;
-void NVRAM_set_byte (a_nvram *nvram, uint32_t addr, uint8_t value);
-uint8_t NVRAM_get_byte (a_nvram *nvram, uint32_t addr);
-void NVRAM_set_word (a_nvram *nvram, uint32_t addr, uint16_t value);
-uint16_t NVRAM_get_word (a_nvram *nvram, uint32_t addr);
-void NVRAM_set_lword (a_nvram *nvram, uint32_t addr, uint32_t value);
-uint32_t NVRAM_get_lword (a_nvram *nvram, uint32_t addr);
-void NVRAM_set_string (a_nvram *nvram, uint32_t addr,
+void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value);
+uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr);
+void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value);
+uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr);
+void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value);
+uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr);
+void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
const char *str, uint32_t max);
-int NVRAM_get_string (a_nvram *nvram, uint8_t *dst, uint16_t addr, int max);
-void NVRAM_set_crc (a_nvram *nvram, uint32_t addr,
+int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max);
+void NVRAM_set_crc (nvram_t *nvram, uint32_t addr,
uint32_t start, uint32_t count);
-int PPC_NVRAM_set_params (a_nvram *nvram, uint16_t NVRAM_size,
+int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
const char *arch,
uint32_t RAM_size, int boot_device,
uint32_t kernel_image, uint32_t kernel_size,
@@ -29,13 +29,13 @@ int PPC_NVRAM_set_params (a_nvram *nvram, uint16_t NVRAM_size,
uint32_t initrd_image, uint32_t initrd_size,
uint32_t NVRAM_image,
int width, int height, int depth);
-typedef struct m48t59 a_m48t59;
+typedef struct m48t59_t m48t59_t;
void m48t59_write (void *private, uint32_t addr, uint32_t val);
uint32_t m48t59_read (void *private, uint32_t addr);
void m48t59_toggle_lock (void *private, int lock);
-a_m48t59 *m48t59_init_isa(uint32_t io_base, uint16_t size, int type);
-a_m48t59 *m48t59_init (qemu_irq IRQ, a_target_phys_addr mem_base,
+m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type);
+m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
uint32_t io_base, uint16_t size,
int type);
void m48t59_set_addr (void *opaque, uint32_t addr);
diff --git a/hw/omap.h b/hw/omap.h
index fb021add9..d3057799a 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -63,19 +63,19 @@ void omap_clk_reparent(omap_clk clk, omap_clk parent);
/* omap[123].c */
struct omap_l4_s;
-struct omap_l4_s *omap_l4_init(a_target_phys_addr base, int ta_num);
+struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num);
struct omap_target_agent_s;
struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs);
-a_target_phys_addr omap_l4_attach(struct omap_target_agent_s *ta, int region,
+target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
int iotype);
# define l4_register_io_memory cpu_register_io_memory
struct omap_intr_handler_s;
-struct omap_intr_handler_s *omap_inth_init(a_target_phys_addr base,
+struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
unsigned long size, unsigned char nbanks, qemu_irq **pins,
qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk);
-struct omap_intr_handler_s *omap2_inth_init(a_target_phys_addr base,
+struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
int size, int nbanks, qemu_irq **pins,
qemu_irq parent_irq, qemu_irq parent_fiq,
omap_clk fclk, omap_clk iclk);
@@ -91,12 +91,12 @@ struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
omap_clk iclk, struct omap_mpu_state_s *mpu);
struct omap_sdrc_s;
-struct omap_sdrc_s *omap_sdrc_init(a_target_phys_addr base);
+struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
struct omap_gpmc_s;
-struct omap_gpmc_s *omap_gpmc_init(a_target_phys_addr base, qemu_irq irq);
+struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
- void (*base_upd)(void *opaque, a_target_phys_addr new),
+ void (*base_upd)(void *opaque, target_phys_addr_t new),
void (*unmap)(void *opaque), void *opaque);
/*
@@ -416,10 +416,10 @@ enum omap_dma_model {
};
struct soc_dma_s;
-struct soc_dma_s *omap_dma_init(a_target_phys_addr base, qemu_irq *irqs,
+struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
enum omap_dma_model model);
-struct soc_dma_s *omap_dma4_init(a_target_phys_addr base, qemu_irq *irqs,
+struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
struct omap_mpu_state_s *mpu, int fifo,
int chans, omap_clk iclk, omap_clk fclk);
void omap_dma_reset(struct soc_dma_s *s);
@@ -445,15 +445,15 @@ typedef enum {
post_incremented,
single_index,
double_index,
-} e_omap_dma_addressing;
+} omap_dma_addressing_t;
/* Only used in OMAP DMA 3.x gigacells */
struct omap_dma_lcd_channel_s {
enum omap_dma_port src;
- a_target_phys_addr src_f1_top;
- a_target_phys_addr src_f1_bottom;
- a_target_phys_addr src_f2_top;
- a_target_phys_addr src_f2_bottom;
+ target_phys_addr_t src_f1_top;
+ target_phys_addr_t src_f1_bottom;
+ target_phys_addr_t src_f2_top;
+ target_phys_addr_t src_f2_bottom;
/* Used in OMAP DMA 3.2 gigacell */
unsigned char brust_f1;
@@ -480,8 +480,8 @@ struct omap_dma_lcd_channel_s {
uint16_t frames_f1;
uint16_t elements_f2;
uint16_t frames_f2;
- e_omap_dma_addressing mode_f1;
- e_omap_dma_addressing mode_f2;
+ omap_dma_addressing_t mode_f1;
+ omap_dma_addressing_t mode_f2;
/* Destination port is fixed. */
int interrupts;
@@ -489,7 +489,7 @@ struct omap_dma_lcd_channel_s {
int dual;
int current_frame;
- a_target_phys_addr phys_framebuffer[2];
+ target_phys_addr_t phys_framebuffer[2];
qemu_irq irq;
struct omap_mpu_state_s *mpu;
} *omap_dma_get_lcdch(struct soc_dma_s *s);
@@ -628,7 +628,7 @@ struct omap_dma_lcd_channel_s {
/* omap[123].c */
struct omap_mpu_timer_s;
-struct omap_mpu_timer_s *omap_mpu_timer_init(a_target_phys_addr base,
+struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
qemu_irq irq, omap_clk clk);
struct omap_gp_timer_s;
@@ -636,22 +636,22 @@ struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
qemu_irq irq, omap_clk fclk, omap_clk iclk);
struct omap_watchdog_timer_s;
-struct omap_watchdog_timer_s *omap_wd_timer_init(a_target_phys_addr base,
+struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
qemu_irq irq, omap_clk clk);
struct omap_32khz_timer_s;
-struct omap_32khz_timer_s *omap_os_timer_init(a_target_phys_addr base,
+struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
qemu_irq irq, omap_clk clk);
void omap_synctimer_init(struct omap_target_agent_s *ta,
struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
struct omap_tipb_bridge_s;
-struct omap_tipb_bridge_s *omap_tipb_bridge_init(a_target_phys_addr base,
+struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
qemu_irq abort_irq, omap_clk clk);
struct omap_uart_s;
-struct omap_uart_s *omap_uart_init(a_target_phys_addr base,
+struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr);
struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
@@ -661,7 +661,7 @@ void omap_uart_reset(struct omap_uart_s *s);
void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);
struct omap_mpuio_s;
-struct omap_mpuio_s *omap_mpuio_init(a_target_phys_addr base,
+struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
omap_clk clk);
qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
@@ -669,7 +669,7 @@ void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
struct omap_gpio_s;
-struct omap_gpio_s *omap_gpio_init(a_target_phys_addr base,
+struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
qemu_irq irq, omap_clk clk);
qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s);
void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler);
@@ -686,7 +686,7 @@ struct uWireSlave {
void *opaque;
};
struct omap_uwire_s;
-struct omap_uwire_s *omap_uwire_init(a_target_phys_addr base,
+struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
qemu_irq *irq, qemu_irq dma, omap_clk clk);
void omap_uwire_attach(struct omap_uwire_s *s,
uWireSlave *slave, int chipselect);
@@ -699,7 +699,7 @@ void omap_mcspi_attach(struct omap_mcspi_s *s,
int chipselect);
struct omap_rtc_s;
-struct omap_rtc_s *omap_rtc_init(a_target_phys_addr base,
+struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
qemu_irq *irq, omap_clk clk);
struct I2SCodec {
@@ -727,12 +727,12 @@ struct I2SCodec {
} in, out;
};
struct omap_mcbsp_s;
-struct omap_mcbsp_s *omap_mcbsp_init(a_target_phys_addr base,
+struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
qemu_irq *irq, qemu_irq *dma, omap_clk clk);
void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
struct omap_lpg_s;
-struct omap_lpg_s *omap_lpg_init(a_target_phys_addr base, omap_clk clk);
+struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk);
void omap_tap_init(struct omap_target_agent_s *ta,
struct omap_mpu_state_s *mpu);
@@ -744,9 +744,9 @@ struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
/* omap_lcdc.c */
struct omap_lcd_panel_s;
void omap_lcdc_reset(struct omap_lcd_panel_s *s);
-struct omap_lcd_panel_s *omap_lcdc_init(a_target_phys_addr base, qemu_irq irq,
+struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
struct omap_dma_lcd_channel_s *dma,
- a_ram_addr imif_base, a_ram_addr emiff_base, omap_clk clk);
+ ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
/* omap_dss.c */
struct rfbi_chip_s {
@@ -758,7 +758,7 @@ struct rfbi_chip_s {
struct omap_dss_s;
void omap_dss_reset(struct omap_dss_s *s);
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
- a_target_phys_addr l3_base,
+ target_phys_addr_t l3_base,
qemu_irq irq, qemu_irq drq,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
omap_clk ick1, omap_clk ick2);
@@ -766,7 +766,7 @@ void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
/* omap_mmc.c */
struct omap_mmc_s;
-struct omap_mmc_s *omap_mmc_init(a_target_phys_addr base,
+struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
BlockDriverState *bd,
qemu_irq irq, qemu_irq dma[], omap_clk clk);
struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
@@ -778,7 +778,7 @@ void omap_mmc_enable(struct omap_mmc_s *s, int enable);
/* omap_i2c.c */
struct omap_i2c_s;
-struct omap_i2c_s *omap_i2c_init(a_target_phys_addr base,
+struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
qemu_irq irq, qemu_irq *dma, omap_clk clk);
struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk);
@@ -829,11 +829,11 @@ struct omap_mpu_state_s {
struct omap_dma_port_if_s {
uint32_t (*read[3])(struct omap_mpu_state_s *s,
- a_target_phys_addr offset);
+ target_phys_addr_t offset);
void (*write[3])(struct omap_mpu_state_s *s,
- a_target_phys_addr offset, uint32_t value);
+ target_phys_addr_t offset, uint32_t value);
int (*addr_valid)(struct omap_mpu_state_s *s,
- a_target_phys_addr addr);
+ target_phys_addr_t addr);
} port[__omap_dma_port_last];
unsigned long sdram_size;
@@ -969,14 +969,14 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
# error TARGET_PHYS_ADDR_BITS undefined
# endif
-uint32_t omap_badwidth_read8(void *opaque, a_target_phys_addr addr);
-void omap_badwidth_write8(void *opaque, a_target_phys_addr addr,
+uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
+void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
uint32_t value);
-uint32_t omap_badwidth_read16(void *opaque, a_target_phys_addr addr);
-void omap_badwidth_write16(void *opaque, a_target_phys_addr addr,
+uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
+void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
uint32_t value);
-uint32_t omap_badwidth_read32(void *opaque, a_target_phys_addr addr);
-void omap_badwidth_write32(void *opaque, a_target_phys_addr addr,
+uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
+void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
uint32_t value);
void omap_mpu_wakeup(void *opaque, int irq, int req);
@@ -1045,7 +1045,7 @@ struct io_fn {
int in;
};
-static uint32_t io_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t io_readb(void *opaque, target_phys_addr_t addr)
{
struct io_fn *s = opaque;
uint32_t ret;
@@ -1057,7 +1057,7 @@ static uint32_t io_readb(void *opaque, a_target_phys_addr addr)
fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
return ret;
}
-static uint32_t io_readh(void *opaque, a_target_phys_addr addr)
+static uint32_t io_readh(void *opaque, target_phys_addr_t addr)
{
struct io_fn *s = opaque;
uint32_t ret;
@@ -1069,7 +1069,7 @@ static uint32_t io_readh(void *opaque, a_target_phys_addr addr)
fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
return ret;
}
-static uint32_t io_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t io_readw(void *opaque, target_phys_addr_t addr)
{
struct io_fn *s = opaque;
uint32_t ret;
@@ -1081,7 +1081,7 @@ static uint32_t io_readw(void *opaque, a_target_phys_addr addr)
fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
return ret;
}
-static void io_writeb(void *opaque, a_target_phys_addr addr, uint32_t value)
+static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct io_fn *s = opaque;
@@ -1091,7 +1091,7 @@ static void io_writeb(void *opaque, a_target_phys_addr addr, uint32_t value)
s->mem_write[0](s->opaque, addr, value);
s->in --;
}
-static void io_writeh(void *opaque, a_target_phys_addr addr, uint32_t value)
+static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct io_fn *s = opaque;
@@ -1101,7 +1101,7 @@ static void io_writeh(void *opaque, a_target_phys_addr addr, uint32_t value)
s->mem_write[1](s->opaque, addr, value);
s->in --;
}
-static void io_writew(void *opaque, a_target_phys_addr addr, uint32_t value)
+static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct io_fn *s = opaque;
diff --git a/hw/omap1.c b/hw/omap1.c
index 79c976879..e9676ecc8 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -27,7 +27,7 @@
#include "pc.h"
/* Should signal the TCMI/GPMC */
-uint32_t omap_badwidth_read8(void *opaque, a_target_phys_addr addr)
+uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
{
uint8_t ret;
@@ -36,7 +36,7 @@ uint32_t omap_badwidth_read8(void *opaque, a_target_phys_addr addr)
return ret;
}
-void omap_badwidth_write8(void *opaque, a_target_phys_addr addr,
+void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
uint8_t val8 = value;
@@ -45,7 +45,7 @@ void omap_badwidth_write8(void *opaque, a_target_phys_addr addr,
cpu_physical_memory_write(addr, (void *) &val8, 1);
}
-uint32_t omap_badwidth_read16(void *opaque, a_target_phys_addr addr)
+uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
{
uint16_t ret;
@@ -54,7 +54,7 @@ uint32_t omap_badwidth_read16(void *opaque, a_target_phys_addr addr)
return ret;
}
-void omap_badwidth_write16(void *opaque, a_target_phys_addr addr,
+void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
uint16_t val16 = value;
@@ -63,7 +63,7 @@ void omap_badwidth_write16(void *opaque, a_target_phys_addr addr,
cpu_physical_memory_write(addr, (void *) &val16, 2);
}
-uint32_t omap_badwidth_read32(void *opaque, a_target_phys_addr addr)
+uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
{
uint32_t ret;
@@ -72,7 +72,7 @@ uint32_t omap_badwidth_read32(void *opaque, a_target_phys_addr addr)
return ret;
}
-void omap_badwidth_write32(void *opaque, a_target_phys_addr addr,
+void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
OMAP_32B_REG(addr);
@@ -196,7 +196,7 @@ static void omap_set_intr_noedge(void *opaque, int irq, int req)
bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
}
-static uint32_t omap_inth_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
int i, offset = addr;
@@ -273,7 +273,7 @@ static uint32_t omap_inth_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_inth_write(void *opaque, a_target_phys_addr addr,
+static void omap_inth_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
@@ -406,7 +406,7 @@ void omap_inth_reset(struct omap_intr_handler_s *s)
qemu_set_irq(s->parent_intr[1], 0);
}
-struct omap_intr_handler_s *omap_inth_init(a_target_phys_addr base,
+struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
unsigned long size, unsigned char nbanks, qemu_irq **pins,
qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk)
{
@@ -431,7 +431,7 @@ struct omap_intr_handler_s *omap_inth_init(a_target_phys_addr base,
return s;
}
-static uint32_t omap2_inth_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
int offset = addr;
@@ -508,7 +508,7 @@ static uint32_t omap2_inth_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap2_inth_write(void *opaque, a_target_phys_addr addr,
+static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
@@ -624,7 +624,7 @@ static CPUWriteMemoryFunc * const omap2_inth_writefn[] = {
omap2_inth_write,
};
-struct omap_intr_handler_s *omap2_inth_init(a_target_phys_addr base,
+struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
int size, int nbanks, qemu_irq **pins,
qemu_irq parent_irq, qemu_irq parent_fiq,
omap_clk fclk, omap_clk iclk)
@@ -748,7 +748,7 @@ static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
timer->rate = omap_clk_getrate(timer->clk);
}
-static uint32_t omap_mpu_timer_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
@@ -767,7 +767,7 @@ static uint32_t omap_mpu_timer_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_mpu_timer_write(void *opaque, a_target_phys_addr addr,
+static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
@@ -819,7 +819,7 @@ static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
s->it_ena = 1;
}
-struct omap_mpu_timer_s *omap_mpu_timer_init(a_target_phys_addr base,
+struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
qemu_irq irq, omap_clk clk)
{
int iomemtype;
@@ -849,7 +849,7 @@ struct omap_watchdog_timer_s {
int reset;
};
-static uint32_t omap_wd_timer_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
@@ -869,7 +869,7 @@ static uint32_t omap_wd_timer_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_wd_timer_write(void *opaque, a_target_phys_addr addr,
+static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
@@ -943,7 +943,7 @@ static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
omap_timer_update(&s->timer);
}
-struct omap_watchdog_timer_s *omap_wd_timer_init(a_target_phys_addr base,
+struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
qemu_irq irq, omap_clk clk)
{
int iomemtype;
@@ -968,7 +968,7 @@ struct omap_32khz_timer_s {
struct omap_mpu_timer_s timer;
};
-static uint32_t omap_os_timer_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@@ -990,7 +990,7 @@ static uint32_t omap_os_timer_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_os_timer_write(void *opaque, a_target_phys_addr addr,
+static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
@@ -1045,7 +1045,7 @@ static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
s->timer.ar = 1;
}
-struct omap_32khz_timer_s *omap_os_timer_init(a_target_phys_addr base,
+struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
qemu_irq irq, omap_clk clk)
{
int iomemtype;
@@ -1066,7 +1066,7 @@ struct omap_32khz_timer_s *omap_os_timer_init(a_target_phys_addr base,
}
/* Ultra Low-Power Device Module */
-static uint32_t omap_ulpd_pm_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint16_t ret;
@@ -1128,7 +1128,7 @@ static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
}
-static void omap_ulpd_pm_write(void *opaque, a_target_phys_addr addr,
+static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1282,7 +1282,7 @@ static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
}
-static void omap_ulpd_pm_init(a_target_phys_addr base,
+static void omap_ulpd_pm_init(target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_ulpd_pm_readfn,
@@ -1293,7 +1293,7 @@ static void omap_ulpd_pm_init(a_target_phys_addr base,
}
/* OMAP Pin Configuration */
-static uint32_t omap_pin_cfg_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1395,7 +1395,7 @@ static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
}
-static void omap_pin_cfg_write(void *opaque, a_target_phys_addr addr,
+static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1497,7 +1497,7 @@ static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
}
-static void omap_pin_cfg_init(a_target_phys_addr base,
+static void omap_pin_cfg_init(target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_pin_cfg_readfn,
@@ -1508,7 +1508,7 @@ static void omap_pin_cfg_init(a_target_phys_addr base,
}
/* Device Identification, Die Identification */
-static uint32_t omap_id_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1550,7 +1550,7 @@ static uint32_t omap_id_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_id_write(void *opaque, a_target_phys_addr addr,
+static void omap_id_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
OMAP_BAD_REG(addr);
@@ -1579,7 +1579,7 @@ static void omap_id_init(struct omap_mpu_state_s *mpu)
}
/* MPUI Control (Dummy) */
-static uint32_t omap_mpui_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1607,7 +1607,7 @@ static uint32_t omap_mpui_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_mpui_write(void *opaque, a_target_phys_addr addr,
+static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1650,7 +1650,7 @@ static void omap_mpui_reset(struct omap_mpu_state_s *s)
s->mpui_ctrl = 0x0003ff1b;
}
-static void omap_mpui_init(a_target_phys_addr base,
+static void omap_mpui_init(target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_mpui_readfn,
@@ -1672,7 +1672,7 @@ struct omap_tipb_bridge_s {
uint16_t enh_control;
};
-static uint32_t omap_tipb_bridge_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
@@ -1697,7 +1697,7 @@ static uint32_t omap_tipb_bridge_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_tipb_bridge_write(void *opaque, a_target_phys_addr addr,
+static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
@@ -1752,7 +1752,7 @@ static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
s->enh_control = 0x000f;
}
-struct omap_tipb_bridge_s *omap_tipb_bridge_init(a_target_phys_addr base,
+struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
qemu_irq abort_irq, omap_clk clk)
{
int iomemtype;
@@ -1770,7 +1770,7 @@ struct omap_tipb_bridge_s *omap_tipb_bridge_init(a_target_phys_addr base,
}
/* Dummy Traffic Controller's Memory Interface */
-static uint32_t omap_tcmi_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
uint32_t ret;
@@ -1803,7 +1803,7 @@ static uint32_t omap_tcmi_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_tcmi_write(void *opaque, a_target_phys_addr addr,
+static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1865,7 +1865,7 @@ static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
}
-static void omap_tcmi_init(a_target_phys_addr base,
+static void omap_tcmi_init(target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_tcmi_readfn,
@@ -1876,7 +1876,7 @@ static void omap_tcmi_init(a_target_phys_addr base,
}
/* Digital phase-locked loops control */
-static uint32_t omap_dpll_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
@@ -1887,7 +1887,7 @@ static uint32_t omap_dpll_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_dpll_write(void *opaque, a_target_phys_addr addr,
+static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
@@ -1938,7 +1938,7 @@ static void omap_dpll_reset(struct dpll_ctl_s *s)
omap_clk_setrate(s->dpll, 1, 1);
}
-static void omap_dpll_init(struct dpll_ctl_s *s, a_target_phys_addr base,
+static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
omap_clk clk)
{
int iomemtype = cpu_register_io_memory(omap_dpll_readfn,
@@ -1952,7 +1952,7 @@ static void omap_dpll_init(struct dpll_ctl_s *s, a_target_phys_addr base,
/* UARTs */
struct omap_uart_s {
- a_target_phys_addr base;
+ target_phys_addr_t base;
SerialState *serial; /* TODO */
struct omap_target_agent_s *ta;
omap_clk fclk;
@@ -1976,7 +1976,7 @@ void omap_uart_reset(struct omap_uart_s *s)
s->clksel = 0;
}
-struct omap_uart_s *omap_uart_init(a_target_phys_addr base,
+struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
{
@@ -1992,7 +1992,7 @@ struct omap_uart_s *omap_uart_init(a_target_phys_addr base,
return s;
}
-static uint32_t omap_uart_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
{
struct omap_uart_s *s = (struct omap_uart_s *) opaque;
@@ -2026,7 +2026,7 @@ static uint32_t omap_uart_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_uart_write(void *opaque, a_target_phys_addr addr,
+static void omap_uart_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_uart_s *s = (struct omap_uart_s *) opaque;
@@ -2085,7 +2085,7 @@ struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
{
- a_target_phys_addr base = omap_l4_attach(ta, 0, 0);
+ target_phys_addr_t base = omap_l4_attach(ta, 0, 0);
struct omap_uart_s *s = omap_uart_init(base, irq,
fclk, iclk, txdma, rxdma, chr);
int iomemtype = cpu_register_io_memory(omap_uart_readfn,
@@ -2107,7 +2107,7 @@ void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr)
}
/* MPU Clock/Reset/Power Mode Control */
-static uint32_t omap_clkm_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -2303,7 +2303,7 @@ static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
}
}
-static void omap_clkm_write(void *opaque, a_target_phys_addr addr,
+static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -2393,7 +2393,7 @@ static CPUWriteMemoryFunc * const omap_clkm_writefn[] = {
omap_badwidth_write16,
};
-static uint32_t omap_clkdsp_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -2432,7 +2432,7 @@ static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
}
-static void omap_clkdsp_write(void *opaque, a_target_phys_addr addr,
+static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -2499,8 +2499,8 @@ static void omap_clkm_reset(struct omap_mpu_state_s *s)
s->clkm.dsp_rstct2 = 0x0000;
}
-static void omap_clkm_init(a_target_phys_addr mpu_base,
- a_target_phys_addr dsp_base, struct omap_mpu_state_s *s)
+static void omap_clkm_init(target_phys_addr_t mpu_base,
+ target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
{
int iomemtype[2] = {
cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s),
@@ -2578,7 +2578,7 @@ static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
s->row_latch = ~rows;
}
-static uint32_t omap_mpuio_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@@ -2633,7 +2633,7 @@ static uint32_t omap_mpuio_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_mpuio_write(void *opaque, a_target_phys_addr addr,
+static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
@@ -2743,7 +2743,7 @@ static void omap_mpuio_onoff(void *opaque, int line, int on)
omap_mpuio_kbd_update(s);
}
-struct omap_mpuio_s *omap_mpuio_init(a_target_phys_addr base,
+struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
omap_clk clk)
{
@@ -2823,7 +2823,7 @@ static void omap_gpio_set(void *opaque, int line, int level)
}
}
-static uint32_t omap_gpio_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr)
{
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@@ -2856,7 +2856,7 @@ static uint32_t omap_gpio_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_gpio_write(void *opaque, a_target_phys_addr addr,
+static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
@@ -2942,7 +2942,7 @@ static void omap_gpio_reset(struct omap_gpio_s *s)
s->pins = ~0;
}
-struct omap_gpio_s *omap_gpio_init(a_target_phys_addr base,
+struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
qemu_irq irq, omap_clk clk)
{
int iomemtype;
@@ -3011,7 +3011,7 @@ static void omap_uwire_transfer_start(struct omap_uwire_s *s)
}
}
-static uint32_t omap_uwire_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@@ -3040,7 +3040,7 @@ static uint32_t omap_uwire_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_uwire_write(void *opaque, a_target_phys_addr addr,
+static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
@@ -3111,7 +3111,7 @@ static void omap_uwire_reset(struct omap_uwire_s *s)
s->setup[4] = 0;
}
-struct omap_uwire_s *omap_uwire_init(a_target_phys_addr base,
+struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
qemu_irq *irq, qemu_irq dma, omap_clk clk)
{
int iomemtype;
@@ -3152,7 +3152,7 @@ static void omap_pwl_update(struct omap_mpu_state_s *s)
}
}
-static uint32_t omap_pwl_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@@ -3167,7 +3167,7 @@ static uint32_t omap_pwl_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_pwl_write(void *opaque, a_target_phys_addr addr,
+static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -3217,7 +3217,7 @@ static void omap_pwl_clk_update(void *opaque, int line, int on)
omap_pwl_update(s);
}
-static void omap_pwl_init(a_target_phys_addr base, struct omap_mpu_state_s *s,
+static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
omap_clk clk)
{
int iomemtype;
@@ -3232,7 +3232,7 @@ static void omap_pwl_init(a_target_phys_addr base, struct omap_mpu_state_s *s,
}
/* Pulse-Width Tone module */
-static uint32_t omap_pwt_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@@ -3249,7 +3249,7 @@ static uint32_t omap_pwt_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_pwt_write(void *opaque, a_target_phys_addr addr,
+static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -3311,7 +3311,7 @@ static void omap_pwt_reset(struct omap_mpu_state_s *s)
s->pwt.gcr = 0;
}
-static void omap_pwt_init(a_target_phys_addr base, struct omap_mpu_state_s *s,
+static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
omap_clk clk)
{
int iomemtype;
@@ -3368,7 +3368,7 @@ static inline int omap_rtc_bin(uint8_t num)
return (num & 15) + 10 * (num >> 4);
}
-static uint32_t omap_rtc_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@@ -3445,7 +3445,7 @@ static uint32_t omap_rtc_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_rtc_write(void *opaque, a_target_phys_addr addr,
+static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
@@ -3729,7 +3729,7 @@ static void omap_rtc_reset(struct omap_rtc_s *s)
omap_rtc_tick(s);
}
-struct omap_rtc_s *omap_rtc_init(a_target_phys_addr base,
+struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
qemu_irq *irq, omap_clk clk)
{
int iomemtype;
@@ -3956,7 +3956,7 @@ static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
omap_mcbsp_rx_stop(s);
}
-static uint32_t omap_mcbsp_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@@ -4049,7 +4049,7 @@ static uint32_t omap_mcbsp_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_mcbsp_writeh(void *opaque, a_target_phys_addr addr,
+static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
@@ -4187,7 +4187,7 @@ static void omap_mcbsp_writeh(void *opaque, a_target_phys_addr addr,
OMAP_BAD_REG(addr);
}
-static void omap_mcbsp_writew(void *opaque, a_target_phys_addr addr,
+static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
@@ -4249,7 +4249,7 @@ static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
qemu_del_timer(s->sink_timer);
}
-struct omap_mcbsp_s *omap_mcbsp_init(a_target_phys_addr base,
+struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
qemu_irq *irq, qemu_irq *dma, omap_clk clk)
{
int iomemtype;
@@ -4364,7 +4364,7 @@ static void omap_lpg_reset(struct omap_lpg_s *s)
omap_lpg_update(s);
}
-static uint32_t omap_lpg_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr)
{
struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@@ -4381,7 +4381,7 @@ static uint32_t omap_lpg_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_lpg_write(void *opaque, a_target_phys_addr addr,
+static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
@@ -4426,7 +4426,7 @@ static void omap_lpg_clk_update(void *opaque, int line, int on)
omap_lpg_update(s);
}
-struct omap_lpg_s *omap_lpg_init(a_target_phys_addr base, omap_clk clk)
+struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
{
int iomemtype;
struct omap_lpg_s *s = (struct omap_lpg_s *)
@@ -4446,7 +4446,7 @@ struct omap_lpg_s *omap_lpg_init(a_target_phys_addr base, omap_clk clk)
}
/* MPUI Peripheral Bridge configuration */
-static uint32_t omap_mpui_io_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr)
{
if (addr == OMAP_MPUI_BASE) /* CMR */
return 0xfe4d;
@@ -4517,8 +4517,8 @@ static void omap1_mpu_reset(void *opaque)
}
static const struct omap_map_s {
- a_target_phys_addr phys_dsp;
- a_target_phys_addr phys_mpu;
+ target_phys_addr_t phys_dsp;
+ target_phys_addr_t phys_mpu;
uint32_t size;
const char *name;
} omap15xx_dsp_mm[] = {
@@ -4586,37 +4586,37 @@ static const struct dma_irq_map omap1_dma_irq_map[] = {
/* DMA ports for OMAP1 */
static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
- a_target_phys_addr addr)
+ target_phys_addr_t addr)
{
return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
}
static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
- a_target_phys_addr addr)
+ target_phys_addr_t addr)
{
return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
}
static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
- a_target_phys_addr addr)
+ target_phys_addr_t addr)
{
return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
}
static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
- a_target_phys_addr addr)
+ target_phys_addr_t addr)
{
return addr >= 0xfffb0000 && addr < 0xffff0000;
}
static int omap_validate_local_addr(struct omap_mpu_state_s *s,
- a_target_phys_addr addr)
+ target_phys_addr_t addr)
{
return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000;
}
static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
- a_target_phys_addr addr)
+ target_phys_addr_t addr)
{
return addr >= 0xe1010000 && addr < 0xe1020004;
}
@@ -4627,7 +4627,7 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
int i;
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
qemu_mallocz(sizeof(struct omap_mpu_state_s));
- a_ram_addr imif_base, emiff_base;
+ ram_addr_t imif_base, emiff_base;
qemu_irq *cpu_irq;
qemu_irq dma_irqs[6];
DriveInfo *dinfo;
diff --git a/hw/omap2.c b/hw/omap2.c
index 700823c1a..a3fa89d3e 100644
--- a/hw/omap2.c
+++ b/hw/omap2.c
@@ -263,7 +263,7 @@ static void omap_gp_timer_reset(struct omap_gp_timer_s *s)
omap_gp_timer_update(s);
}
-static uint32_t omap_gp_timer_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
@@ -329,7 +329,7 @@ static uint32_t omap_gp_timer_readw(void *opaque, a_target_phys_addr addr)
return 0;
}
-static uint32_t omap_gp_timer_readh(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
uint32_t ret;
@@ -349,7 +349,7 @@ static CPUReadMemoryFunc * const omap_gp_timer_readfn[] = {
omap_gp_timer_readw,
};
-static void omap_gp_timer_write(void *opaque, a_target_phys_addr addr,
+static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
@@ -449,7 +449,7 @@ static void omap_gp_timer_write(void *opaque, a_target_phys_addr addr,
}
}
-static void omap_gp_timer_writeh(void *opaque, a_target_phys_addr addr,
+static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
@@ -499,7 +499,7 @@ static void omap_synctimer_reset(struct omap_synctimer_s *s)
s->val = omap_synctimer_read(s);
}
-static uint32_t omap_synctimer_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr)
{
struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
@@ -515,7 +515,7 @@ static uint32_t omap_synctimer_readw(void *opaque, a_target_phys_addr addr)
return 0;
}
-static uint32_t omap_synctimer_readh(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr)
{
struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
uint32_t ret;
@@ -535,7 +535,7 @@ static CPUReadMemoryFunc * const omap_synctimer_readfn[] = {
omap_synctimer_readw,
};
-static void omap_synctimer_write(void *opaque, a_target_phys_addr addr,
+static void omap_synctimer_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
OMAP_BAD_REG(addr);
@@ -658,7 +658,7 @@ static void omap_gpio_module_reset(struct omap2_gpio_s *s)
s->delay = 0;
}
-static uint32_t omap_gpio_module_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_gpio_module_read(void *opaque, target_phys_addr_t addr)
{
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
@@ -730,7 +730,7 @@ static uint32_t omap_gpio_module_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_gpio_module_write(void *opaque, a_target_phys_addr addr,
+static void omap_gpio_module_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
@@ -872,12 +872,12 @@ static void omap_gpio_module_write(void *opaque, a_target_phys_addr addr,
}
}
-static uint32_t omap_gpio_module_readp(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_gpio_module_readp(void *opaque, target_phys_addr_t addr)
{
return omap_gpio_module_readp(opaque, addr) >> ((addr & 3) << 3);
}
-static void omap_gpio_module_writep(void *opaque, a_target_phys_addr addr,
+static void omap_gpio_module_writep(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
uint32_t cur = 0;
@@ -975,7 +975,7 @@ static void omap_gpif_reset(struct omap_gpif_s *s)
s->gpo = 0;
}
-static uint32_t omap_gpif_top_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr)
{
struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
@@ -1003,7 +1003,7 @@ static uint32_t omap_gpif_top_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_gpif_top_write(void *opaque, a_target_phys_addr addr,
+static void omap_gpif_top_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
@@ -1187,7 +1187,7 @@ static void omap_mcspi_reset(struct omap_mcspi_s *s)
omap_mcspi_interrupt_update(s);
}
-static uint32_t omap_mcspi_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
int ch = 0;
@@ -1256,7 +1256,7 @@ static uint32_t omap_mcspi_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_mcspi_write(void *opaque, a_target_phys_addr addr,
+static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
@@ -1696,7 +1696,7 @@ static void omap_eac_reset(struct omap_eac_s *s)
omap_eac_interrupt_update(s);
}
-static uint32_t omap_eac_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
uint32_t ret;
@@ -1807,7 +1807,7 @@ static uint32_t omap_eac_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_eac_write(void *opaque, a_target_phys_addr addr,
+static void omap_eac_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
@@ -2014,7 +2014,7 @@ static void omap_sti_reset(struct omap_sti_s *s)
omap_sti_interrupt_update(s);
}
-static uint32_t omap_sti_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
@@ -2050,7 +2050,7 @@ static uint32_t omap_sti_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_sti_write(void *opaque, a_target_phys_addr addr,
+static void omap_sti_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
@@ -2108,13 +2108,13 @@ static CPUWriteMemoryFunc * const omap_sti_writefn[] = {
omap_sti_write,
};
-static uint32_t omap_sti_fifo_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr)
{
OMAP_BAD_REG(addr);
return 0;
}
-static void omap_sti_fifo_write(void *opaque, a_target_phys_addr addr,
+static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
@@ -2147,7 +2147,7 @@ static CPUWriteMemoryFunc * const omap_sti_fifo_writefn[] = {
};
static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
- a_target_phys_addr channel_base, qemu_irq irq, omap_clk clk,
+ target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
CharDriverState *chr)
{
int iomemtype;
@@ -2175,14 +2175,14 @@ struct omap_target_agent_s {
struct omap_l4_s *bus;
int regions;
struct omap_l4_region_s *start;
- a_target_phys_addr base;
+ target_phys_addr_t base;
uint32_t component;
uint32_t control;
uint32_t status;
};
struct omap_l4_s {
- a_target_phys_addr base;
+ target_phys_addr_t base;
int ta_num;
struct omap_target_agent_s ta[0];
};
@@ -2213,28 +2213,28 @@ int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
return omap_l4_io_entries ++;
}
-static uint32_t omap_l4_io_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr)
{
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr);
}
-static uint32_t omap_l4_io_readh(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr)
{
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr);
}
-static uint32_t omap_l4_io_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr)
{
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr);
}
-static void omap_l4_io_writeb(void *opaque, a_target_phys_addr addr,
+static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
@@ -2242,7 +2242,7 @@ static void omap_l4_io_writeb(void *opaque, a_target_phys_addr addr,
return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value);
}
-static void omap_l4_io_writeh(void *opaque, a_target_phys_addr addr,
+static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
@@ -2250,7 +2250,7 @@ static void omap_l4_io_writeh(void *opaque, a_target_phys_addr addr,
return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value);
}
-static void omap_l4_io_writew(void *opaque, a_target_phys_addr addr,
+static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
@@ -2271,7 +2271,7 @@ static CPUWriteMemoryFunc * const omap_l4_io_writefn[] = {
};
#endif
-struct omap_l4_s *omap_l4_init(a_target_phys_addr base, int ta_num)
+struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
{
struct omap_l4_s *bus = qemu_mallocz(
sizeof(*bus) + ta_num * sizeof(*bus->ta));
@@ -2299,7 +2299,7 @@ struct omap_l4_s *omap_l4_init(a_target_phys_addr base, int ta_num)
return bus;
}
-static uint32_t omap_l4ta_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
{
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
@@ -2318,7 +2318,7 @@ static uint32_t omap_l4ta_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_l4ta_write(void *opaque, a_target_phys_addr addr,
+static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
@@ -2356,7 +2356,7 @@ static CPUWriteMemoryFunc * const omap_l4ta_writefn[] = {
#define L4TAO(n) ((n) + 39)
static struct omap_l4_region_s {
- a_target_phys_addr offset;
+ target_phys_addr_t offset;
size_t size;
int access;
} omap_l4_region[125] = {
@@ -2584,10 +2584,10 @@ struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs)
return ta;
}
-a_target_phys_addr omap_l4_attach(struct omap_target_agent_s *ta, int region,
+target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
int iotype)
{
- a_target_phys_addr base;
+ target_phys_addr_t base;
ssize_t size;
#ifdef L4_MUX_HACK
int i;
@@ -2622,7 +2622,7 @@ a_target_phys_addr omap_l4_attach(struct omap_target_agent_s *ta, int region,
}
/* TEST-Chip-level TAP */
-static uint32_t omap_tap_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -2686,7 +2686,7 @@ static uint32_t omap_tap_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_tap_write(void *opaque, a_target_phys_addr addr,
+static void omap_tap_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
OMAP_BAD_REG(addr);
@@ -2753,7 +2753,7 @@ static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
/* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
}
-static uint32_t omap_prcm_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
{
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
uint32_t ret;
@@ -3060,7 +3060,7 @@ static void omap_prcm_dpll_update(struct omap_prcm_s *s)
}
}
-static void omap_prcm_write(void *opaque, a_target_phys_addr addr,
+static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
@@ -3540,7 +3540,7 @@ struct omap_sysctl_s {
uint32_t msuspendmux[5];
};
-static uint32_t omap_sysctl_read8(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
@@ -3565,7 +3565,7 @@ static uint32_t omap_sysctl_read8(void *opaque, a_target_phys_addr addr)
return 0;
}
-static uint32_t omap_sysctl_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
@@ -3665,7 +3665,7 @@ static uint32_t omap_sysctl_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_sysctl_write8(void *opaque, a_target_phys_addr addr,
+static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
@@ -3689,7 +3689,7 @@ static void omap_sysctl_write8(void *opaque, a_target_phys_addr addr,
}
}
-static void omap_sysctl_write(void *opaque, a_target_phys_addr addr,
+static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
@@ -3907,7 +3907,7 @@ static void omap_sdrc_reset(struct omap_sdrc_s *s)
s->config = 0x10;
}
-static uint32_t omap_sdrc_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr)
{
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
@@ -3957,7 +3957,7 @@ static uint32_t omap_sdrc_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_sdrc_write(void *opaque, a_target_phys_addr addr,
+static void omap_sdrc_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
@@ -4026,7 +4026,7 @@ static CPUWriteMemoryFunc * const omap_sdrc_writefn[] = {
omap_sdrc_write,
};
-struct omap_sdrc_s *omap_sdrc_init(a_target_phys_addr base)
+struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base)
{
int iomemtype;
struct omap_sdrc_s *s = (struct omap_sdrc_s *)
@@ -4056,10 +4056,10 @@ struct omap_gpmc_s {
int prefcount;
struct omap_gpmc_cs_file_s {
uint32_t config[7];
- a_target_phys_addr base;
+ target_phys_addr_t base;
size_t size;
int iomemtype;
- void (*base_update)(void *opaque, a_target_phys_addr new);
+ void (*base_update)(void *opaque, target_phys_addr_t new);
void (*unmap)(void *opaque);
void *opaque;
} cs_file[8];
@@ -4151,7 +4151,7 @@ static void omap_gpmc_reset(struct omap_gpmc_s *s)
ecc_reset(&s->ecc[i]);
}
-static uint32_t omap_gpmc_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
int cs;
@@ -4248,7 +4248,7 @@ static uint32_t omap_gpmc_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_gpmc_write(void *opaque, a_target_phys_addr addr,
+static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
@@ -4400,7 +4400,7 @@ static CPUWriteMemoryFunc * const omap_gpmc_writefn[] = {
omap_gpmc_write,
};
-struct omap_gpmc_s *omap_gpmc_init(a_target_phys_addr base, qemu_irq irq)
+struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
{
int iomemtype;
struct omap_gpmc_s *s = (struct omap_gpmc_s *)
@@ -4416,7 +4416,7 @@ struct omap_gpmc_s *omap_gpmc_init(a_target_phys_addr base, qemu_irq irq)
}
void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
- void (*base_upd)(void *opaque, a_target_phys_addr new),
+ void (*base_upd)(void *opaque, target_phys_addr_t new),
void (*unmap)(void *opaque), void *opaque)
{
struct omap_gpmc_cs_file_s *f;
@@ -4475,7 +4475,7 @@ static void omap2_mpu_reset(void *opaque)
}
static int omap2_validate_addr(struct omap_mpu_state_s *s,
- a_target_phys_addr addr)
+ target_phys_addr_t addr)
{
return 1;
}
@@ -4492,7 +4492,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
qemu_mallocz(sizeof(struct omap_mpu_state_s));
- a_ram_addr sram_base, q2_base;
+ ram_addr_t sram_base, q2_base;
qemu_irq *cpu_irq;
qemu_irq dma_irqs[4];
omap_clk gpio_clks[4];
diff --git a/hw/omap_dma.c b/hw/omap_dma.c
index 99e4306f3..205d01039 100644
--- a/hw/omap_dma.c
+++ b/hw/omap_dma.c
@@ -31,8 +31,8 @@ struct omap_dma_channel_s {
int endian_lock[2];
int translate[2];
enum omap_dma_port port[2];
- a_target_phys_addr addr[2];
- e_omap_dma_addressing mode[2];
+ target_phys_addr_t addr[2];
+ omap_dma_addressing_t mode[2];
uint32_t elements;
uint16_t frames;
int32_t frame_index[2];
@@ -78,7 +78,7 @@ struct omap_dma_channel_s {
struct omap_dma_channel_s *sibling;
struct omap_dma_reg_set_s {
- a_target_phys_addr src, dest;
+ target_phys_addr_t src, dest;
int frame;
int element;
int pck_element;
@@ -885,8 +885,8 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
break;
case 0x02: /* SYS_DMA_CCR_CH0 */
- ch->mode[1] = (e_omap_dma_addressing) ((value & 0xc000) >> 14);
- ch->mode[0] = (e_omap_dma_addressing) ((value & 0x3000) >> 12);
+ ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
+ ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
ch->end_prog = (value & 0x0800) >> 11;
if (s->model >= omap_dma_3_2)
ch->omap_3_1_compatible_disable = (value >> 10) & 0x1;
@@ -911,7 +911,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
break;
case 0x06: /* SYS_DMA_CSR_CH0 */
- OMAP_RO_REG((a_target_phys_addr) reg);
+ OMAP_RO_REG((target_phys_addr_t) reg);
break;
case 0x08: /* SYS_DMA_CSSA_L_CH0 */
@@ -951,7 +951,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
break;
case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
- OMAP_RO_REG((a_target_phys_addr) reg);
+ OMAP_RO_REG((target_phys_addr_t) reg);
break;
case 0x1c: /* DMA_CDEI */
@@ -1443,7 +1443,7 @@ static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
return 0;
}
-static uint32_t omap_dma_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
int reg, ch;
@@ -1486,7 +1486,7 @@ static uint32_t omap_dma_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_dma_write(void *opaque, a_target_phys_addr addr,
+static void omap_dma_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
@@ -1612,7 +1612,7 @@ static void omap_dma_setcaps(struct omap_dma_s *s)
}
}
-struct soc_dma_s *omap_dma_init(a_target_phys_addr base, qemu_irq *irqs,
+struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
enum omap_dma_model model)
{
@@ -1686,7 +1686,7 @@ static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
qemu_irq_raise(s->irq[3]);
}
-static uint32_t omap_dma4_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
int irqn = 0, chnum;
@@ -1831,7 +1831,7 @@ static uint32_t omap_dma4_read(void *opaque, a_target_phys_addr addr)
}
}
-static void omap_dma4_write(void *opaque, a_target_phys_addr addr,
+static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
@@ -1908,8 +1908,8 @@ static void omap_dma4_write(void *opaque, a_target_phys_addr addr,
ch->bs = (value >> 18) & 1;
ch->transparent_copy = (value >> 17) & 1;
ch->constant_fill = (value >> 16) & 1;
- ch->mode[1] = (e_omap_dma_addressing) ((value & 0xc000) >> 14);
- ch->mode[0] = (e_omap_dma_addressing) ((value & 0x3000) >> 12);
+ ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
+ ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
ch->suspend = (value & 0x0100) >> 8;
ch->priority = (value & 0x0040) >> 6;
ch->fs = (value & 0x0020) >> 5;
@@ -1973,12 +1973,12 @@ static void omap_dma4_write(void *opaque, a_target_phys_addr addr,
break;
case 0x1c: /* DMA4_CSSA */
- ch->addr[0] = (a_target_phys_addr) (uint32_t) value;
+ ch->addr[0] = (target_phys_addr_t) (uint32_t) value;
ch->set_update = 1;
break;
case 0x20: /* DMA4_CDSA */
- ch->addr[1] = (a_target_phys_addr) (uint32_t) value;
+ ch->addr[1] = (target_phys_addr_t) (uint32_t) value;
ch->set_update = 1;
break;
@@ -2031,7 +2031,7 @@ static CPUWriteMemoryFunc * const omap_dma4_writefn[] = {
omap_dma4_write,
};
-struct soc_dma_s *omap_dma4_init(a_target_phys_addr base, qemu_irq *irqs,
+struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
struct omap_mpu_state_s *mpu, int fifo,
int chans, omap_clk iclk, omap_clk fclk)
{
diff --git a/hw/omap_dss.c b/hw/omap_dss.c
index 12d288052..044f2d242 100644
--- a/hw/omap_dss.c
+++ b/hw/omap_dss.c
@@ -59,7 +59,7 @@ struct omap_dss_s {
int nx;
int ny;
- a_target_phys_addr addr[3];
+ target_phys_addr_t addr[3];
uint32_t attr;
uint32_t tresh;
@@ -167,7 +167,7 @@ void omap_dss_reset(struct omap_dss_s *s)
omap_dispc_interrupt_update(s);
}
-static uint32_t omap_diss_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_diss_read(void *opaque, target_phys_addr_t addr)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -200,7 +200,7 @@ static uint32_t omap_diss_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_diss_write(void *opaque, a_target_phys_addr addr,
+static void omap_diss_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -242,7 +242,7 @@ static CPUWriteMemoryFunc * const omap_diss1_writefn[] = {
omap_diss_write,
};
-static uint32_t omap_disc_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_disc_read(void *opaque, target_phys_addr_t addr)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -362,7 +362,7 @@ static uint32_t omap_disc_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_disc_write(void *opaque, a_target_phys_addr addr,
+static void omap_disc_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -488,11 +488,11 @@ static void omap_disc_write(void *opaque, a_target_phys_addr addr,
s->dispc.invalidate = 1;
break;
case 0x080: /* DISPC_GFX_BA0 */
- s->dispc.l[0].addr[0] = (a_target_phys_addr) value;
+ s->dispc.l[0].addr[0] = (target_phys_addr_t) value;
s->dispc.invalidate = 1;
break;
case 0x084: /* DISPC_GFX_BA1 */
- s->dispc.l[0].addr[1] = (a_target_phys_addr) value;
+ s->dispc.l[0].addr[1] = (target_phys_addr_t) value;
s->dispc.invalidate = 1;
break;
case 0x088: /* DISPC_GFX_POSITION */
@@ -529,7 +529,7 @@ static void omap_disc_write(void *opaque, a_target_phys_addr addr,
s->dispc.l[0].wininc = value;
break;
case 0x0b8: /* DISPC_GFX_TABLE_BA */
- s->dispc.l[0].addr[2] = (a_target_phys_addr) value;
+ s->dispc.l[0].addr[2] = (target_phys_addr_t) value;
s->dispc.invalidate = 1;
break;
@@ -594,11 +594,11 @@ static void omap_rfbi_transfer_stop(struct omap_dss_s *s)
static void omap_rfbi_transfer_start(struct omap_dss_s *s)
{
void *data;
- a_target_phys_addr len;
- a_target_phys_addr data_addr;
+ target_phys_addr_t len;
+ target_phys_addr_t data_addr;
int pitch;
static void *bounce_buffer;
- static a_target_phys_addr bounce_len;
+ static target_phys_addr_t bounce_len;
if (!s->rfbi.enable || s->rfbi.busy)
return;
@@ -655,7 +655,7 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
omap_dispc_interrupt_update(s);
}
-static uint32_t omap_rfbi_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_rfbi_read(void *opaque, target_phys_addr_t addr)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -717,7 +717,7 @@ static uint32_t omap_rfbi_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_rfbi_write(void *opaque, a_target_phys_addr addr,
+static void omap_rfbi_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -853,7 +853,7 @@ static CPUWriteMemoryFunc * const omap_rfbi1_writefn[] = {
omap_rfbi_write,
};
-static uint32_t omap_venc_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_venc_read(void *opaque, target_phys_addr_t addr)
{
switch (addr) {
case 0x00: /* REV_ID */
@@ -908,7 +908,7 @@ static uint32_t omap_venc_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_venc_write(void *opaque, a_target_phys_addr addr,
+static void omap_venc_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
switch (addr) {
@@ -972,7 +972,7 @@ static CPUWriteMemoryFunc * const omap_venc1_writefn[] = {
omap_venc_write,
};
-static uint32_t omap_im3_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_im3_read(void *opaque, target_phys_addr_t addr)
{
switch (addr) {
case 0x0a8: /* SBIMERRLOGA */
@@ -993,7 +993,7 @@ static uint32_t omap_im3_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_im3_write(void *opaque, a_target_phys_addr addr,
+static void omap_im3_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
switch (addr) {
@@ -1023,7 +1023,7 @@ static CPUWriteMemoryFunc * const omap_im3_writefn[] = {
};
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
- a_target_phys_addr l3_base,
+ target_phys_addr_t l3_base,
qemu_irq irq, qemu_irq drq,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
omap_clk ick1, omap_clk ick2)
diff --git a/hw/omap_i2c.c b/hw/omap_i2c.c
index 570db9f03..d7c18882d 100644
--- a/hw/omap_i2c.c
+++ b/hw/omap_i2c.c
@@ -140,7 +140,7 @@ void omap_i2c_reset(struct omap_i2c_s *s)
s->test = 0;
}
-static uint32_t omap_i2c_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
{
struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@@ -238,7 +238,7 @@ static uint32_t omap_i2c_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_i2c_write(void *opaque, a_target_phys_addr addr,
+static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
@@ -380,7 +380,7 @@ static void omap_i2c_write(void *opaque, a_target_phys_addr addr,
}
}
-static void omap_i2c_writeb(void *opaque, a_target_phys_addr addr,
+static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
@@ -420,7 +420,7 @@ static CPUWriteMemoryFunc * const omap_i2c_writefn[] = {
omap_badwidth_write16,
};
-struct omap_i2c_s *omap_i2c_init(a_target_phys_addr base,
+struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
qemu_irq irq, qemu_irq *dma, omap_clk clk)
{
int iomemtype;
diff --git a/hw/omap_lcdc.c b/hw/omap_lcdc.c
index d762f9121..6affef67b 100644
--- a/hw/omap_lcdc.c
+++ b/hw/omap_lcdc.c
@@ -24,8 +24,8 @@
struct omap_lcd_panel_s {
qemu_irq irq;
DisplayState *state;
- a_ram_addr imif_base;
- a_ram_addr emiff_base;
+ ram_addr_t imif_base;
+ ram_addr_t emiff_base;
int plm;
int tft;
@@ -117,7 +117,7 @@ static void omap_update_display(void *opaque)
draw_line_func draw_line;
int size, height, first, last;
int width, linesize, step, bpp, frame_offset;
- a_target_phys_addr frame_base;
+ target_phys_addr_t frame_base;
if (!omap_lcd || omap_lcd->plm == 1 ||
!omap_lcd->enable || !ds_get_bits_per_pixel(omap_lcd->state))
@@ -325,7 +325,7 @@ static void omap_lcd_update(struct omap_lcd_panel_s *s) {
}
}
-static uint32_t omap_lcdc_read(void *opaque, a_target_phys_addr addr)
+static uint32_t omap_lcdc_read(void *opaque, target_phys_addr_t addr)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
@@ -357,7 +357,7 @@ static uint32_t omap_lcdc_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void omap_lcdc_write(void *opaque, a_target_phys_addr addr,
+static void omap_lcdc_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
@@ -435,9 +435,9 @@ void omap_lcdc_reset(struct omap_lcd_panel_s *s)
s->ctrl = 0;
}
-struct omap_lcd_panel_s *omap_lcdc_init(a_target_phys_addr base, qemu_irq irq,
+struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
struct omap_dma_lcd_channel_s *dma,
- a_ram_addr imif_base, a_ram_addr emiff_base, omap_clk clk)
+ ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk)
{
int iomemtype;
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *)
diff --git a/hw/omap_mmc.c b/hw/omap_mmc.c
index 7edfba5cb..15cbf06c8 100644
--- a/hw/omap_mmc.c
+++ b/hw/omap_mmc.c
@@ -104,10 +104,10 @@ typedef enum {
sd_r3, /* OCR register */
sd_r6 = 6, /* Published RCA response */
sd_r1b = -1,
-} e_sd_rsp_type;
+} sd_rsp_type_t;
static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
- e_sd_cmd_type type, int busy, e_sd_rsp_type resptype, int init)
+ sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
{
uint32_t rspstatus, mask;
int rsplen, timeout;
@@ -305,7 +305,7 @@ void omap_mmc_reset(struct omap_mmc_s *host)
host->clkdiv = 0;
}
-static uint32_t omap_mmc_read(void *opaque, a_target_phys_addr offset)
+static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset)
{
uint16_t i;
struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
@@ -394,7 +394,7 @@ static uint32_t omap_mmc_read(void *opaque, a_target_phys_addr offset)
return 0;
}
-static void omap_mmc_write(void *opaque, a_target_phys_addr offset,
+static void omap_mmc_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
int i;
@@ -410,9 +410,9 @@ static void omap_mmc_write(void *opaque, a_target_phys_addr offset,
for (i = 0; i < 8; i ++)
s->rsp[i] = 0x0000;
omap_mmc_command(s, value & 63, (value >> 15) & 1,
- (e_sd_cmd_type) ((value >> 12) & 3),
+ (sd_cmd_type_t) ((value >> 12) & 3),
(value >> 11) & 1,
- (e_sd_rsp_type) ((value >> 8) & 7),
+ (sd_rsp_type_t) ((value >> 8) & 7),
(value >> 7) & 1);
omap_mmc_update(s);
break;
@@ -569,7 +569,7 @@ static void omap_mmc_cover_cb(void *opaque, int line, int level)
}
}
-struct omap_mmc_s *omap_mmc_init(a_target_phys_addr base,
+struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
BlockDriverState *bd,
qemu_irq irq, qemu_irq dma[], omap_clk clk)
{
diff --git a/hw/omap_sx1.c b/hw/omap_sx1.c
index 99744c548..255dcbd74 100644
--- a/hw/omap_sx1.c
+++ b/hw/omap_sx1.c
@@ -58,28 +58,28 @@
* - 1 RTC
*/
-static uint32_t static_readb(void *opaque, a_target_phys_addr offset)
+static uint32_t static_readb(void *opaque, target_phys_addr_t offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 3) << 3);
}
-static uint32_t static_readh(void *opaque, a_target_phys_addr offset)
+static uint32_t static_readh(void *opaque, target_phys_addr_t offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 1) << 3);
}
-static uint32_t static_readw(void *opaque, a_target_phys_addr offset)
+static uint32_t static_readw(void *opaque, target_phys_addr_t offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 0) << 3);
}
-static void static_write(void *opaque, a_target_phys_addr offset,
+static void static_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
#ifdef SPY
@@ -114,7 +114,7 @@ static struct arm_boot_info sx1_binfo = {
.board_id = 0x265,
};
-static void sx1_init(a_ram_addr ram_size,
+static void sx1_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model,
@@ -126,7 +126,7 @@ static void sx1_init(a_ram_addr ram_size,
static uint32_t cs1val = 0x00215070;
static uint32_t cs2val = 0x00001139;
static uint32_t cs3val = 0x00001139;
- a_ram_addr phys_flash;
+ ram_addr_t phys_flash;
DriveInfo *dinfo;
int fl_idx;
uint32_t flash_size = flash0_size;
@@ -204,7 +204,7 @@ static void sx1_init(a_ram_addr ram_size,
//~ qemu_console_resize(ds, 640, 480);
}
-static void sx1_init_v1(a_ram_addr ram_size,
+static void sx1_init_v1(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@@ -213,7 +213,7 @@ static void sx1_init_v1(a_ram_addr ram_size,
kernel_cmdline, initrd_filename, cpu_model, 1);
}
-static void sx1_init_v2(a_ram_addr ram_size,
+static void sx1_init_v2(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
diff --git a/hw/onenand.c b/hw/onenand.c
index 46fabedcc..c1e7e4d60 100644
--- a/hw/onenand.c
+++ b/hw/onenand.c
@@ -33,7 +33,7 @@
typedef struct {
uint32_t id;
int shift;
- a_target_phys_addr base;
+ target_phys_addr_t base;
qemu_irq intr;
qemu_irq rdy;
BlockDriverState *bdrv;
@@ -41,7 +41,7 @@ typedef struct {
uint8_t *image;
uint8_t *otp;
uint8_t *current;
- a_ram_addr ram;
+ ram_addr_t ram;
uint8_t *boot[2];
uint8_t *data[2][2];
int iomemtype;
@@ -96,7 +96,7 @@ enum {
ONEN_LOCK_UNLOCKED = 1 << 2,
};
-void onenand_base_update(void *opaque, a_target_phys_addr new)
+void onenand_base_update(void *opaque, target_phys_addr_t new)
{
OneNANDState *s = (OneNANDState *) opaque;
@@ -443,7 +443,7 @@ static void onenand_command(OneNANDState *s, int cmd)
onenand_intr_update(s);
}
-static uint32_t onenand_read(void *opaque, a_target_phys_addr addr)
+static uint32_t onenand_read(void *opaque, target_phys_addr_t addr)
{
OneNANDState *s = (OneNANDState *) opaque;
int offset = addr >> s->shift;
@@ -507,7 +507,7 @@ static uint32_t onenand_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void onenand_write(void *opaque, a_target_phys_addr addr,
+static void onenand_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
OneNANDState *s = (OneNANDState *) opaque;
diff --git a/hw/openpic.c b/hw/openpic.c
index eea3e309d..74dde6d1c 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -166,19 +166,19 @@ enum {
IRQ_SPECIAL = 0x08,
};
-typedef struct IRQ_queue {
+typedef struct IRQ_queue_t {
uint32_t queue[BF_WIDTH(MAX_IRQ)];
int next;
int priority;
-} a_IRQ_queue;
+} IRQ_queue_t;
-typedef struct IRQ_src {
+typedef struct IRQ_src_t {
uint32_t ipvp; /* IRQ vector/priority register */
uint32_t ide; /* IRQ destination register */
int type;
int last_cpu;
int pending; /* TRUE if IRQ is pending */
-} a_IRQ_src;
+} IRQ_src_t;
enum IPVP_bits {
IPVP_MASK = 31,
@@ -192,16 +192,16 @@ enum IPVP_bits {
#define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1)
#define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
-typedef struct IRQ_dst {
+typedef struct IRQ_dst_t {
uint32_t tfrr;
uint32_t pctp; /* CPU current task priority */
uint32_t pcsr; /* CPU sensitivity register */
- a_IRQ_queue raised;
- a_IRQ_queue servicing;
+ IRQ_queue_t raised;
+ IRQ_queue_t servicing;
qemu_irq *irqs;
-} a_IRQ_dst;
+} IRQ_dst_t;
-typedef struct openpic {
+typedef struct openpic_t {
PCIDevice pci_dev;
int mem_index;
/* Global registers */
@@ -213,9 +213,9 @@ typedef struct openpic {
uint32_t spve; /* Spurious vector register */
uint32_t tifr; /* Timer frequency reporting register */
/* Source registers */
- a_IRQ_src src[MAX_IRQ];
+ IRQ_src_t src[MAX_IRQ];
/* Local registers per output pin */
- a_IRQ_dst dst[MAX_CPU];
+ IRQ_dst_t dst[MAX_CPU];
int nb_cpus;
/* Timer registers */
struct {
@@ -242,10 +242,10 @@ typedef struct openpic {
int irq_tim0;
int need_swap;
void (*reset) (void *);
- void (*irq_raise) (struct openpic *, int, a_IRQ_src *);
-} a_openpic;
+ void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *);
+} openpic_t;
-static inline uint32_t openpic_swap32(a_openpic *opp, uint32_t val)
+static inline uint32_t openpic_swap32(openpic_t *opp, uint32_t val)
{
if (opp->need_swap)
return bswap32(val);
@@ -253,22 +253,22 @@ static inline uint32_t openpic_swap32(a_openpic *opp, uint32_t val)
return val;
}
-static inline void IRQ_setbit (a_IRQ_queue *q, int n_IRQ)
+static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
{
set_bit(q->queue, n_IRQ);
}
-static inline void IRQ_resetbit (a_IRQ_queue *q, int n_IRQ)
+static inline void IRQ_resetbit (IRQ_queue_t *q, int n_IRQ)
{
reset_bit(q->queue, n_IRQ);
}
-static inline int IRQ_testbit (a_IRQ_queue *q, int n_IRQ)
+static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ)
{
return test_bit(q->queue, n_IRQ);
}
-static void IRQ_check (a_openpic *opp, a_IRQ_queue *q)
+static void IRQ_check (openpic_t *opp, IRQ_queue_t *q)
{
int next, i;
int priority;
@@ -289,7 +289,7 @@ static void IRQ_check (a_openpic *opp, a_IRQ_queue *q)
q->priority = priority;
}
-static int IRQ_get_next (a_openpic *opp, a_IRQ_queue *q)
+static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q)
{
if (q->next == -1) {
/* XXX: optimize */
@@ -299,10 +299,10 @@ static int IRQ_get_next (a_openpic *opp, a_IRQ_queue *q)
return q->next;
}
-static void IRQ_local_pipe (a_openpic *opp, int n_CPU, int n_IRQ)
+static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ)
{
- a_IRQ_dst *dst;
- a_IRQ_src *src;
+ IRQ_dst_t *dst;
+ IRQ_src_t *src;
int priority;
dst = &opp->dst[n_CPU];
@@ -341,9 +341,9 @@ static void IRQ_local_pipe (a_openpic *opp, int n_CPU, int n_IRQ)
}
/* update pic state because registers for n_IRQ have changed value */
-static void openpic_update_irq(a_openpic *opp, int n_IRQ)
+static void openpic_update_irq(openpic_t *opp, int n_IRQ)
{
- a_IRQ_src *src;
+ IRQ_src_t *src;
int i;
src = &opp->src[n_IRQ];
@@ -399,8 +399,8 @@ static void openpic_update_irq(a_openpic *opp, int n_IRQ)
static void openpic_set_irq(void *opaque, int n_IRQ, int level)
{
- a_openpic *opp = opaque;
- a_IRQ_src *src;
+ openpic_t *opp = opaque;
+ IRQ_src_t *src;
src = &opp->src[n_IRQ];
DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
@@ -420,7 +420,7 @@ static void openpic_set_irq(void *opaque, int n_IRQ, int level)
static void openpic_reset (void *opaque)
{
- a_openpic *opp = (a_openpic *)opaque;
+ openpic_t *opp = (openpic_t *)opaque;
int i;
opp->glbc = 0x80000000;
@@ -441,8 +441,8 @@ static void openpic_reset (void *opaque)
for (i = 0; i < MAX_CPU; i++) {
opp->dst[i].pctp = 0x0000000F;
opp->dst[i].pcsr = 0x00000000;
- memset(&opp->dst[i].raised, 0, sizeof(a_IRQ_queue));
- memset(&opp->dst[i].servicing, 0, sizeof(a_IRQ_queue));
+ memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t));
+ memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
}
/* Initialise timers */
for (i = 0; i < MAX_TMR; i++) {
@@ -466,7 +466,7 @@ static void openpic_reset (void *opaque)
opp->glbc = 0x00000000;
}
-static inline uint32_t read_IRQreg (a_openpic *opp, int n_IRQ, uint32_t reg)
+static inline uint32_t read_IRQreg (openpic_t *opp, int n_IRQ, uint32_t reg)
{
uint32_t retval;
@@ -482,7 +482,7 @@ static inline uint32_t read_IRQreg (a_openpic *opp, int n_IRQ, uint32_t reg)
return retval;
}
-static inline void write_IRQreg (a_openpic *opp, int n_IRQ,
+static inline void write_IRQreg (openpic_t *opp, int n_IRQ,
uint32_t reg, uint32_t val)
{
uint32_t tmp;
@@ -510,7 +510,7 @@ static inline void write_IRQreg (a_openpic *opp, int n_IRQ,
#if 0 // Code provision for Intel model
#if MAX_DBL > 0
-static uint32_t read_doorbell_register (a_openpic *opp,
+static uint32_t read_doorbell_register (openpic_t *opp,
int n_dbl, uint32_t offset)
{
uint32_t retval;
@@ -548,7 +548,7 @@ static void write_doorbell_register (penpic_t *opp, int n_dbl,
#endif
#if MAX_MBX > 0
-static uint32_t read_mailbox_register (a_openpic *opp,
+static uint32_t read_mailbox_register (openpic_t *opp,
int n_mbx, uint32_t offset)
{
uint32_t retval;
@@ -568,7 +568,7 @@ static uint32_t read_mailbox_register (a_openpic *opp,
return retval;
}
-static void write_mailbox_register (a_openpic *opp, int n_mbx,
+static void write_mailbox_register (openpic_t *opp, int n_mbx,
uint32_t address, uint32_t value)
{
switch (offset) {
@@ -586,10 +586,10 @@ static void write_mailbox_register (a_openpic *opp, int n_mbx,
#endif
#endif /* 0 : Code provision for Intel model */
-static void openpic_gbl_write (void *opaque, a_target_phys_addr addr, uint32_t val)
+static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t val)
{
- a_openpic *opp = opaque;
- a_IRQ_dst *dst;
+ openpic_t *opp = opaque;
+ IRQ_dst_t *dst;
int idx;
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
@@ -646,9 +646,9 @@ static void openpic_gbl_write (void *opaque, a_target_phys_addr addr, uint32_t v
}
}
-static uint32_t openpic_gbl_read (void *opaque, a_target_phys_addr addr)
+static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr)
{
- a_openpic *opp = opaque;
+ openpic_t *opp = opaque;
uint32_t retval;
DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -700,7 +700,7 @@ static uint32_t openpic_gbl_read (void *opaque, a_target_phys_addr addr)
static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val)
{
- a_openpic *opp = opaque;
+ openpic_t *opp = opaque;
int idx;
DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
@@ -734,7 +734,7 @@ static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val)
static uint32_t openpic_timer_read (void *opaque, uint32_t addr)
{
- a_openpic *opp = opaque;
+ openpic_t *opp = opaque;
uint32_t retval;
int idx;
@@ -770,7 +770,7 @@ static uint32_t openpic_timer_read (void *opaque, uint32_t addr)
static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val)
{
- a_openpic *opp = opaque;
+ openpic_t *opp = opaque;
int idx;
DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
@@ -792,7 +792,7 @@ static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val)
static uint32_t openpic_src_read (void *opaque, uint32_t addr)
{
- a_openpic *opp = opaque;
+ openpic_t *opp = opaque;
uint32_t retval;
int idx;
@@ -817,11 +817,11 @@ static uint32_t openpic_src_read (void *opaque, uint32_t addr)
return retval;
}
-static void openpic_cpu_write (void *opaque, a_target_phys_addr addr, uint32_t val)
+static void openpic_cpu_write (void *opaque, target_phys_addr_t addr, uint32_t val)
{
- a_openpic *opp = opaque;
- a_IRQ_src *src;
- a_IRQ_dst *dst;
+ openpic_t *opp = opaque;
+ IRQ_src_t *src;
+ IRQ_dst_t *dst;
int idx, s_IRQ, n_IRQ;
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
@@ -878,11 +878,11 @@ static void openpic_cpu_write (void *opaque, a_target_phys_addr addr, uint32_t v
}
}
-static uint32_t openpic_cpu_read (void *opaque, a_target_phys_addr addr)
+static uint32_t openpic_cpu_read (void *opaque, target_phys_addr_t addr)
{
- a_openpic *opp = opaque;
- a_IRQ_src *src;
- a_IRQ_dst *dst;
+ openpic_t *opp = opaque;
+ IRQ_src_t *src;
+ IRQ_dst_t *dst;
uint32_t retval;
int idx, n_IRQ;
@@ -955,12 +955,12 @@ static uint32_t openpic_cpu_read (void *opaque, a_target_phys_addr addr)
}
static void openpic_buggy_write (void *opaque,
- a_target_phys_addr addr, uint32_t val)
+ target_phys_addr_t addr, uint32_t val)
{
printf("Invalid OPENPIC write access !\n");
}
-static uint32_t openpic_buggy_read (void *opaque, a_target_phys_addr addr)
+static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr)
{
printf("Invalid OPENPIC read access !\n");
@@ -968,9 +968,9 @@ static uint32_t openpic_buggy_read (void *opaque, a_target_phys_addr addr)
}
static void openpic_writel (void *opaque,
- a_target_phys_addr addr, uint32_t val)
+ target_phys_addr_t addr, uint32_t val)
{
- a_openpic *opp = opaque;
+ openpic_t *opp = opaque;
addr &= 0x3FFFF;
DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val);
@@ -989,9 +989,9 @@ static void openpic_writel (void *opaque,
}
}
-static uint32_t openpic_readl (void *opaque,a_target_phys_addr addr)
+static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr)
{
- a_openpic *opp = opaque;
+ openpic_t *opp = opaque;
uint32_t retval;
addr &= 0x3FFFF;
@@ -1028,10 +1028,10 @@ static CPUReadMemoryFunc * const openpic_read[] = {
static void openpic_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
- a_openpic *opp;
+ openpic_t *opp;
DPRINTF("Map OpenPIC\n");
- opp = (a_openpic *)pci_dev;
+ opp = (openpic_t *)pci_dev;
/* Global registers */
DPRINTF("Register OPENPIC gbl %08x => %08x\n",
addr + 0x1000, addr + 0x1000 + 0x100);
@@ -1053,7 +1053,7 @@ static void openpic_map(PCIDevice *pci_dev, int region_num,
#endif
}
-static void openpic_save_IRQ_queue(QEMUFile* f, a_IRQ_queue *q)
+static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
{
unsigned int i;
@@ -1066,7 +1066,7 @@ static void openpic_save_IRQ_queue(QEMUFile* f, a_IRQ_queue *q)
static void openpic_save(QEMUFile* f, void *opaque)
{
- a_openpic *opp = (a_openpic *)opaque;
+ openpic_t *opp = (openpic_t *)opaque;
unsigned int i;
qemu_put_be32s(f, &opp->frep);
@@ -1117,7 +1117,7 @@ static void openpic_save(QEMUFile* f, void *opaque)
pci_device_save(&opp->pci_dev, f);
}
-static void openpic_load_IRQ_queue(QEMUFile* f, a_IRQ_queue *q)
+static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
{
unsigned int i;
@@ -1130,7 +1130,7 @@ static void openpic_load_IRQ_queue(QEMUFile* f, a_IRQ_queue *q)
static int openpic_load(QEMUFile* f, void *opaque, int version_id)
{
- a_openpic *opp = (a_openpic *)opaque;
+ openpic_t *opp = (openpic_t *)opaque;
unsigned int i;
if (version_id != 1)
@@ -1184,7 +1184,7 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
return pci_device_load(&opp->pci_dev, f);
}
-static void openpic_irq_raise(a_openpic *opp, int n_CPU, a_IRQ_src *src)
+static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src)
{
qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
}
@@ -1192,7 +1192,7 @@ static void openpic_irq_raise(a_openpic *opp, int n_CPU, a_IRQ_src *src)
qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
qemu_irq **irqs, qemu_irq irq_out)
{
- a_openpic *opp;
+ openpic_t *opp;
uint8_t *pci_conf;
int i, m;
@@ -1200,7 +1200,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
if (nb_cpus != 1)
return NULL;
if (bus) {
- opp = (a_openpic *)pci_register_device(bus, "OpenPIC", sizeof(a_openpic),
+ opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t),
-1, NULL, NULL);
if (opp == NULL)
return NULL;
@@ -1215,7 +1215,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
pci_register_bar((PCIDevice *)opp, 0, 0x40000,
PCI_ADDRESS_SPACE_MEM, &openpic_map);
} else {
- opp = qemu_mallocz(sizeof(a_openpic));
+ opp = qemu_mallocz(sizeof(openpic_t));
}
opp->mem_index = cpu_register_io_memory(openpic_read,
openpic_write, opp);
@@ -1261,7 +1261,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq);
}
-static void mpic_irq_raise(a_openpic *mpp, int n_CPU, a_IRQ_src *src)
+static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src)
{
int n_ci = IDR_CI0 - n_CPU;
@@ -1275,7 +1275,7 @@ static void mpic_irq_raise(a_openpic *mpp, int n_CPU, a_IRQ_src *src)
static void mpic_reset (void *opaque)
{
- a_openpic *mpp = (a_openpic *)opaque;
+ openpic_t *mpp = (openpic_t *)opaque;
int i;
mpp->glbc = 0x80000000;
@@ -1293,9 +1293,9 @@ static void mpic_reset (void *opaque)
for (i = 0; i < MAX_CPU; i++) {
mpp->dst[i].pctp = 0x0000000F;
mpp->dst[i].tfrr = 0x00000000;
- memset(&mpp->dst[i].raised, 0, sizeof(a_IRQ_queue));
+ memset(&mpp->dst[i].raised, 0, sizeof(IRQ_queue_t));
mpp->dst[i].raised.next = -1;
- memset(&mpp->dst[i].servicing, 0, sizeof(a_IRQ_queue));
+ memset(&mpp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
mpp->dst[i].servicing.next = -1;
}
/* Initialise timers */
@@ -1307,9 +1307,9 @@ static void mpic_reset (void *opaque)
mpp->glbc = 0x00000000;
}
-static void mpic_timer_write (void *opaque, a_target_phys_addr addr, uint32_t val)
+static void mpic_timer_write (void *opaque, target_phys_addr_t addr, uint32_t val)
{
- a_openpic *mpp = opaque;
+ openpic_t *mpp = opaque;
int idx, cpu;
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
@@ -1340,9 +1340,9 @@ static void mpic_timer_write (void *opaque, a_target_phys_addr addr, uint32_t va
}
}
-static uint32_t mpic_timer_read (void *opaque, a_target_phys_addr addr)
+static uint32_t mpic_timer_read (void *opaque, target_phys_addr_t addr)
{
- a_openpic *mpp = opaque;
+ openpic_t *mpp = opaque;
uint32_t retval;
int idx, cpu;
@@ -1375,10 +1375,10 @@ static uint32_t mpic_timer_read (void *opaque, a_target_phys_addr addr)
return retval;
}
-static void mpic_src_ext_write (void *opaque, a_target_phys_addr addr,
+static void mpic_src_ext_write (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
- a_openpic *mpp = opaque;
+ openpic_t *mpp = opaque;
int idx = MPIC_EXT_IRQ;
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
@@ -1398,9 +1398,9 @@ static void mpic_src_ext_write (void *opaque, a_target_phys_addr addr,
}
}
-static uint32_t mpic_src_ext_read (void *opaque, a_target_phys_addr addr)
+static uint32_t mpic_src_ext_read (void *opaque, target_phys_addr_t addr)
{
- a_openpic *mpp = opaque;
+ openpic_t *mpp = opaque;
uint32_t retval;
int idx = MPIC_EXT_IRQ;
@@ -1425,10 +1425,10 @@ static uint32_t mpic_src_ext_read (void *opaque, a_target_phys_addr addr)
return retval;
}
-static void mpic_src_int_write (void *opaque, a_target_phys_addr addr,
+static void mpic_src_int_write (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
- a_openpic *mpp = opaque;
+ openpic_t *mpp = opaque;
int idx = MPIC_INT_IRQ;
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
@@ -1448,9 +1448,9 @@ static void mpic_src_int_write (void *opaque, a_target_phys_addr addr,
}
}
-static uint32_t mpic_src_int_read (void *opaque, a_target_phys_addr addr)
+static uint32_t mpic_src_int_read (void *opaque, target_phys_addr_t addr)
{
- a_openpic *mpp = opaque;
+ openpic_t *mpp = opaque;
uint32_t retval;
int idx = MPIC_INT_IRQ;
@@ -1475,10 +1475,10 @@ static uint32_t mpic_src_int_read (void *opaque, a_target_phys_addr addr)
return retval;
}
-static void mpic_src_msg_write (void *opaque, a_target_phys_addr addr,
+static void mpic_src_msg_write (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
- a_openpic *mpp = opaque;
+ openpic_t *mpp = opaque;
int idx = MPIC_MSG_IRQ;
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
@@ -1498,9 +1498,9 @@ static void mpic_src_msg_write (void *opaque, a_target_phys_addr addr,
}
}
-static uint32_t mpic_src_msg_read (void *opaque, a_target_phys_addr addr)
+static uint32_t mpic_src_msg_read (void *opaque, target_phys_addr_t addr)
{
- a_openpic *mpp = opaque;
+ openpic_t *mpp = opaque;
uint32_t retval;
int idx = MPIC_MSG_IRQ;
@@ -1525,10 +1525,10 @@ static uint32_t mpic_src_msg_read (void *opaque, a_target_phys_addr addr)
return retval;
}
-static void mpic_src_msi_write (void *opaque, a_target_phys_addr addr,
+static void mpic_src_msi_write (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
- a_openpic *mpp = opaque;
+ openpic_t *mpp = opaque;
int idx = MPIC_MSI_IRQ;
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
@@ -1547,9 +1547,9 @@ static void mpic_src_msi_write (void *opaque, a_target_phys_addr addr,
}
}
}
-static uint32_t mpic_src_msi_read (void *opaque, a_target_phys_addr addr)
+static uint32_t mpic_src_msi_read (void *opaque, target_phys_addr_t addr)
{
- a_openpic *mpp = opaque;
+ openpic_t *mpp = opaque;
uint32_t retval;
int idx = MPIC_MSI_IRQ;
@@ -1657,16 +1657,16 @@ static CPUReadMemoryFunc * const mpic_msi_read[] = {
&mpic_src_msi_read,
};
-qemu_irq *mpic_init (a_target_phys_addr base, int nb_cpus,
+qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
qemu_irq **irqs, qemu_irq irq_out)
{
- a_openpic *mpp;
+ openpic_t *mpp;
int i;
struct {
CPUReadMemoryFunc * const *read;
CPUWriteMemoryFunc * const *write;
- a_target_phys_addr start_addr;
- a_ram_addr size;
+ target_phys_addr_t start_addr;
+ ram_addr_t size;
} const list[] = {
{mpic_glb_read, mpic_glb_write, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
{mpic_tmr_read, mpic_tmr_write, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
@@ -1681,7 +1681,7 @@ qemu_irq *mpic_init (a_target_phys_addr base, int nb_cpus,
if (nb_cpus != 1)
return NULL;
- mpp = qemu_mallocz(sizeof(a_openpic));
+ mpp = qemu_mallocz(sizeof(openpic_t));
for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
int mem_index;
diff --git a/hw/openpic.h b/hw/openpic.h
index 1ab010a9e..0957c1ff0 100644
--- a/hw/openpic.h
+++ b/hw/openpic.h
@@ -13,6 +13,6 @@ enum {
qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
qemu_irq **irqs, qemu_irq irq_out);
-qemu_irq *mpic_init (a_target_phys_addr base, int nb_cpus,
+qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
qemu_irq **irqs, qemu_irq irq_out);
#endif /* __OPENPIC_H__ */
diff --git a/hw/palm.c b/hw/palm.c
index a895001e2..6d1916751 100644
--- a/hw/palm.c
+++ b/hw/palm.c
@@ -26,25 +26,25 @@
#include "devices.h"
#include "loader.h"
-static uint32_t static_readb(void *opaque, a_target_phys_addr offset)
+static uint32_t static_readb(void *opaque, target_phys_addr_t offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 3) << 3);
}
-static uint32_t static_readh(void *opaque, a_target_phys_addr offset)
+static uint32_t static_readh(void *opaque, target_phys_addr_t offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 1) << 3);
}
-static uint32_t static_readw(void *opaque, a_target_phys_addr offset)
+static uint32_t static_readw(void *opaque, target_phys_addr_t offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 0) << 3);
}
-static void static_write(void *opaque, a_target_phys_addr offset,
+static void static_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
#ifdef SPY
@@ -193,7 +193,7 @@ static struct arm_boot_info palmte_binfo = {
.board_id = 0x331,
};
-static void palmte_init(a_ram_addr ram_size,
+static void palmte_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@@ -206,7 +206,7 @@ static void palmte_init(a_ram_addr ram_size,
static uint32_t cs1val = 0x0000e1a0;
static uint32_t cs2val = 0x0000e1a0;
static uint32_t cs3val = 0xe1a0e1a0;
- a_ram_addr phys_flash;
+ ram_addr_t phys_flash;
int rom_size, rom_loaded = 0;
DisplayState *ds = get_displaystate();
diff --git a/hw/parallel.c b/hw/parallel.c
index 12fe25bbb..faaaa0d9e 100644
--- a/hw/parallel.c
+++ b/hw/parallel.c
@@ -473,7 +473,7 @@ ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
}
/* Memory mapped interface */
-static uint32_t parallel_mm_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
{
ParallelState *s = opaque;
@@ -481,14 +481,14 @@ static uint32_t parallel_mm_readb (void *opaque, a_target_phys_addr addr)
}
static void parallel_mm_writeb (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
ParallelState *s = opaque;
parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
}
-static uint32_t parallel_mm_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
{
ParallelState *s = opaque;
@@ -496,14 +496,14 @@ static uint32_t parallel_mm_readw (void *opaque, a_target_phys_addr addr)
}
static void parallel_mm_writew (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
ParallelState *s = opaque;
parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
}
-static uint32_t parallel_mm_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
{
ParallelState *s = opaque;
@@ -511,7 +511,7 @@ static uint32_t parallel_mm_readl (void *opaque, a_target_phys_addr addr)
}
static void parallel_mm_writel (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
ParallelState *s = opaque;
@@ -531,7 +531,7 @@ static CPUWriteMemoryFunc * const parallel_mm_write_sw[] = {
};
/* If fd is zero, it means that the parallel device uses the console */
-ParallelState *parallel_mm_init(a_target_phys_addr base, int it_shift, qemu_irq irq, CharDriverState *chr)
+ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr)
{
ParallelState *s;
int io_sw;
diff --git a/hw/pc.c b/hw/pc.c
index 66ec10796..bc2875e36 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -61,14 +61,14 @@
#define MAX_IDE_BUS 2
-static a_fdctrl *floppy_controller;
+static fdctrl_t *floppy_controller;
static RTCState *rtc_state;
static PITState *pit;
static PCII440FXState *i440fx_state;
typedef struct rom_reset_data {
uint8_t *data;
- a_target_phys_addr addr;
+ target_phys_addr_t addr;
unsigned size;
} RomResetData;
@@ -79,7 +79,7 @@ static void option_rom_reset(void *_rrd)
cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size);
}
-static void option_rom_setup_reset(a_target_phys_addr addr, unsigned size)
+static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size)
{
RomResetData *rrd = qemu_malloc(sizeof *rrd);
@@ -266,7 +266,7 @@ static int pc_boot_set(void *opaque, const char *boot_device)
}
/* hd_table must contain 4 block drivers */
-static void cmos_init(a_ram_addr ram_size, a_ram_addr above_4g_mem_size,
+static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
const char *boot_device, DriveInfo **hd_table)
{
RTCState *s = rtc_state;
@@ -515,7 +515,7 @@ static void *bochs_bios_init(void)
/* Generate an initial boot sector which sets state and jump to
a specified vector */
-static void generate_bootsect(a_target_phys_addr option_rom,
+static void generate_bootsect(target_phys_addr_t option_rom,
uint32_t gpr[8], uint16_t segs[6], uint16_t ip)
{
uint8_t rom[512], *p, *reloc;
@@ -819,11 +819,11 @@ static int load_multiboot(void *fw_cfg,
}
static void load_linux(void *fw_cfg,
- a_target_phys_addr option_rom,
+ target_phys_addr_t option_rom,
const char *kernel_filename,
const char *initrd_filename,
const char *kernel_cmdline,
- a_target_phys_addr max_ram_size)
+ target_phys_addr_t max_ram_size)
{
uint16_t protocol;
uint32_t gpr[8];
@@ -832,7 +832,7 @@ static void load_linux(void *fw_cfg,
int setup_size, kernel_size, initrd_size = 0, cmdline_size;
uint32_t initrd_max;
uint8_t header[8192];
- a_target_phys_addr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
+ target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
FILE *f, *fi;
char *vmode;
@@ -1058,8 +1058,8 @@ static void pc_init_ne2k_isa(NICInfo *nd)
nb_ne2k++;
}
-static int load_option_rom(const char *oprom, a_target_phys_addr start,
- a_target_phys_addr end)
+static int load_option_rom(const char *oprom, target_phys_addr_t start,
+ target_phys_addr_t end)
{
int size;
char *filename;
@@ -1112,7 +1112,7 @@ static CPUState *pc_new_cpu(const char *cpu_model)
}
/* PC hardware initialisation */
-static void pc_init1(a_ram_addr ram_size,
+static void pc_init1(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
@@ -1122,8 +1122,8 @@ static void pc_init1(a_ram_addr ram_size,
{
char *filename;
int ret, linux_boot, i;
- a_ram_addr ram_addr, bios_offset, option_rom_offset;
- a_ram_addr below_4g_mem_size, above_4g_mem_size = 0;
+ ram_addr_t ram_addr, bios_offset, option_rom_offset;
+ ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
int bios_size, isa_bios_size, oprom_area_size;
PCIBus *pci_bus;
ISADevice *isa_dev;
@@ -1432,7 +1432,7 @@ static void pc_init1(a_ram_addr ram_size,
}
}
-static void pc_init_pci(a_ram_addr ram_size,
+static void pc_init_pci(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
@@ -1444,7 +1444,7 @@ static void pc_init_pci(a_ram_addr ram_size,
initrd_filename, cpu_model, 1);
}
-static void pc_init_isa(a_ram_addr ram_size,
+static void pc_init_isa(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
diff --git a/hw/pc.h b/hw/pc.h
index 7474d188b..c9cdd4a8f 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -9,7 +9,7 @@
SerialState *serial_init(int base, qemu_irq irq, int baudbase,
CharDriverState *chr);
-SerialState *serial_mm_init (a_target_phys_addr base, int it_shift,
+SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
qemu_irq irq, int baudbase,
CharDriverState *chr, int ioregister);
@@ -17,7 +17,7 @@ SerialState *serial_mm_init (a_target_phys_addr base, int it_shift,
typedef struct ParallelState ParallelState;
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
-ParallelState *parallel_mm_init(a_target_phys_addr base, int it_shift, qemu_irq irq, CharDriverState *chr);
+ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
/* i8259.c */
@@ -74,15 +74,15 @@ void *vmmouse_init(void *m);
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
- a_target_phys_addr base, a_ram_addr size,
- a_target_phys_addr mask);
+ target_phys_addr_t base, ram_addr_t size,
+ target_phys_addr_t mask);
/* mc146818rtc.c */
typedef struct RTCState RTCState;
RTCState *rtc_init(int base_year);
-RTCState *rtc_mm_init(a_target_phys_addr base, int it_shift, qemu_irq irq,
+RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
int base_year);
void rtc_set_memory(RTCState *s, int addr, int val);
void rtc_set_date(RTCState *s, const struct tm *tm);
@@ -138,8 +138,8 @@ extern enum vga_retrace_method vga_retrace_method;
int isa_vga_init(void);
int pci_vga_init(PCIBus *bus,
unsigned long vga_bios_offset, int vga_bios_size);
-int isa_vga_mm_init(a_target_phys_addr vram_base,
- a_target_phys_addr ctrl_base, int it_shift);
+int isa_vga_mm_init(target_phys_addr_t vram_base,
+ target_phys_addr_t ctrl_base, int it_shift);
/* cirrus_vga.c */
void pci_cirrus_vga_init(PCIBus *bus);
diff --git a/hw/pci.c b/hw/pci.c
index 8c61dc534..64d70ed23 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -66,7 +66,7 @@ static struct BusInfo pci_bus_info = {
static void pci_update_mappings(PCIDevice *d);
static void pci_set_irq(void *opaque, int irq_num, int level);
-a_target_phys_addr pci_mem_base;
+target_phys_addr_t pci_mem_base;
static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
static PCIBus *first_bus;
@@ -354,7 +354,7 @@ PCIDevice *pci_register_device(PCIBus *bus, const char *name,
config_read, config_write);
return pci_dev;
}
-static a_target_phys_addr pci_to_cpu_addr(a_target_phys_addr addr)
+static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
{
return addr + pci_mem_base;
}
diff --git a/hw/pci.h b/hw/pci.h
index 37d2ae0a3..caba5c851 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -10,7 +10,7 @@
/* PCI bus */
-extern a_target_phys_addr pci_mem_base;
+extern target_phys_addr_t pci_mem_base;
#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
@@ -217,7 +217,7 @@ struct PCIDevice {
* a 4K aligned region all by itself. Align it to
* target pages so that drivers can do passthrough
* on the rest of the region. */
- a_target_phys_addr msix_page_size;
+ target_phys_addr_t msix_page_size;
};
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
@@ -354,8 +354,8 @@ void usb_ohci_init_pci(struct PCIBus *bus, int devfn);
PCIBus *pci_prep_init(qemu_irq *pic);
/* apb_pci.c */
-PCIBus *pci_apb_init(a_target_phys_addr special_base,
- a_target_phys_addr mem_base,
+PCIBus *pci_apb_init(target_phys_addr_t special_base,
+ target_phys_addr_t mem_base,
qemu_irq *pic, PCIBus **bus2, PCIBus **bus3);
/* sh_pci.c */
diff --git a/hw/pci_host.h b/hw/pci_host.h
index 608e8c63d..48862b508 100644
--- a/hw/pci_host.h
+++ b/hw/pci_host.h
@@ -43,41 +43,41 @@ typedef struct {
PCIBus *bus;
} PCIHostState;
-static void pci_host_data_writeb(void* opaque, a_pci_addr addr, uint32_t val)
+static void pci_host_data_writeb(void* opaque, pci_addr_t addr, uint32_t val)
{
PCIHostState *s = opaque;
PCI_DPRINTF("writeb addr " TARGET_FMT_plx " val %x\n",
- (a_target_phys_addr)addr, val);
+ (target_phys_addr_t)addr, val);
if (s->config_reg & (1u << 31))
pci_data_write(s->bus, s->config_reg | (addr & 3), val, 1);
}
-static void pci_host_data_writew(void* opaque, a_pci_addr addr, uint32_t val)
+static void pci_host_data_writew(void* opaque, pci_addr_t addr, uint32_t val)
{
PCIHostState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap16(val);
#endif
PCI_DPRINTF("writew addr " TARGET_FMT_plx " val %x\n",
- (a_target_phys_addr)addr, val);
+ (target_phys_addr_t)addr, val);
if (s->config_reg & (1u << 31))
pci_data_write(s->bus, s->config_reg | (addr & 3), val, 2);
}
-static void pci_host_data_writel(void* opaque, a_pci_addr addr, uint32_t val)
+static void pci_host_data_writel(void* opaque, pci_addr_t addr, uint32_t val)
{
PCIHostState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
#endif
PCI_DPRINTF("writel addr " TARGET_FMT_plx " val %x\n",
- (a_target_phys_addr)addr, val);
+ (target_phys_addr_t)addr, val);
if (s->config_reg & (1u << 31))
pci_data_write(s->bus, s->config_reg, val, 4);
}
-static uint32_t pci_host_data_readb(void* opaque, a_pci_addr addr)
+static uint32_t pci_host_data_readb(void* opaque, pci_addr_t addr)
{
PCIHostState *s = opaque;
uint32_t val;
@@ -86,11 +86,11 @@ static uint32_t pci_host_data_readb(void* opaque, a_pci_addr addr)
return 0xff;
val = pci_data_read(s->bus, s->config_reg | (addr & 3), 1);
PCI_DPRINTF("readb addr " TARGET_FMT_plx " val %x\n",
- (a_target_phys_addr)addr, val);
+ (target_phys_addr_t)addr, val);
return val;
}
-static uint32_t pci_host_data_readw(void* opaque, a_pci_addr addr)
+static uint32_t pci_host_data_readw(void* opaque, pci_addr_t addr)
{
PCIHostState *s = opaque;
uint32_t val;
@@ -98,14 +98,14 @@ static uint32_t pci_host_data_readw(void* opaque, a_pci_addr addr)
return 0xffff;
val = pci_data_read(s->bus, s->config_reg | (addr & 3), 2);
PCI_DPRINTF("readw addr " TARGET_FMT_plx " val %x\n",
- (a_target_phys_addr)addr, val);
+ (target_phys_addr_t)addr, val);
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap16(val);
#endif
return val;
}
-static uint32_t pci_host_data_readl(void* opaque, a_pci_addr addr)
+static uint32_t pci_host_data_readl(void* opaque, pci_addr_t addr)
{
PCIHostState *s = opaque;
uint32_t val;
@@ -113,7 +113,7 @@ static uint32_t pci_host_data_readl(void* opaque, a_pci_addr addr)
return 0xffffffff;
val = pci_data_read(s->bus, s->config_reg | (addr & 3), 4);
PCI_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n",
- (a_target_phys_addr)addr, val);
+ (target_phys_addr_t)addr, val);
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
#endif
diff --git a/hw/pckbd.c b/hw/pckbd.c
index 57f6668bb..c049047ae 100644
--- a/hw/pckbd.c
+++ b/hw/pckbd.c
@@ -123,7 +123,7 @@ typedef struct KBDState {
qemu_irq irq_kbd;
qemu_irq irq_mouse;
- a_target_phys_addr mask;
+ target_phys_addr_t mask;
} KBDState;
static KBDState kbd_state;
@@ -354,7 +354,7 @@ static const VMStateDescription vmstate_kbd = {
};
/* Memory mapped interface */
-static uint32_t kbd_mm_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr)
{
KBDState *s = opaque;
@@ -364,7 +364,7 @@ static uint32_t kbd_mm_readb (void *opaque, a_target_phys_addr addr)
return kbd_read_data(s, 0) & 0xff;
}
-static void kbd_mm_writeb (void *opaque, a_target_phys_addr addr, uint32_t value)
+static void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
KBDState *s = opaque;
@@ -387,8 +387,8 @@ static CPUWriteMemoryFunc * const kbd_mm_write[] = {
};
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
- a_target_phys_addr base, a_ram_addr size,
- a_target_phys_addr mask)
+ target_phys_addr_t base, ram_addr_t size,
+ target_phys_addr_t mask)
{
KBDState *s = &kbd_state;
int s_io_memory;
diff --git a/hw/pcnet.c b/hw/pcnet.c
index c9d823da2..ae98a201d 100644
--- a/hw/pcnet.c
+++ b/hw/pcnet.c
@@ -73,9 +73,9 @@ struct PCNetState_st {
uint8_t buffer[4096];
int tx_busy;
qemu_irq irq;
- void (*phys_mem_read)(void *dma_opaque, a_target_phys_addr addr,
+ void (*phys_mem_read)(void *dma_opaque, target_phys_addr_t addr,
uint8_t *buf, int len, int do_bswap);
- void (*phys_mem_write)(void *dma_opaque, a_target_phys_addr addr,
+ void (*phys_mem_write)(void *dma_opaque, target_phys_addr_t addr,
uint8_t *buf, int len, int do_bswap);
void *dma_opaque;
int looptest;
@@ -349,7 +349,7 @@ struct pcnet_RMD {
GET_FIELD((R)->msg_length, RMDM, ZEROS))
static inline void pcnet_tmd_load(PCNetState *s, struct pcnet_TMD *tmd,
- a_target_phys_addr addr)
+ target_phys_addr_t addr)
{
if (!BCR_SSIZE32(s)) {
struct {
@@ -379,7 +379,7 @@ static inline void pcnet_tmd_load(PCNetState *s, struct pcnet_TMD *tmd,
}
static inline void pcnet_tmd_store(PCNetState *s, const struct pcnet_TMD *tmd,
- a_target_phys_addr addr)
+ target_phys_addr_t addr)
{
if (!BCR_SSIZE32(s)) {
struct {
@@ -415,7 +415,7 @@ static inline void pcnet_tmd_store(PCNetState *s, const struct pcnet_TMD *tmd,
}
static inline void pcnet_rmd_load(PCNetState *s, struct pcnet_RMD *rmd,
- a_target_phys_addr addr)
+ target_phys_addr_t addr)
{
if (!BCR_SSIZE32(s)) {
struct {
@@ -445,7 +445,7 @@ static inline void pcnet_rmd_load(PCNetState *s, struct pcnet_RMD *rmd,
}
static inline void pcnet_rmd_store(PCNetState *s, struct pcnet_RMD *rmd,
- a_target_phys_addr addr)
+ target_phys_addr_t addr)
{
if (!BCR_SSIZE32(s)) {
struct {
@@ -716,7 +716,7 @@ static inline int ladr_match(PCNetState *s, const uint8_t *buf, int size)
return 0;
}
-static inline a_target_phys_addr pcnet_rdra_addr(PCNetState *s, int idx)
+static inline target_phys_addr_t pcnet_rdra_addr(PCNetState *s, int idx)
{
while (idx < 1) idx += CSR_RCVRL(s);
return s->rdra + ((CSR_RCVRL(s) - idx) * (BCR_SWSTYLE(s) ? 16 : 8));
@@ -955,19 +955,19 @@ static void pcnet_rdte_poll(PCNetState *s)
if (s->rdra) {
int bad = 0;
#if 1
- a_target_phys_addr crda = pcnet_rdra_addr(s, CSR_RCVRC(s));
- a_target_phys_addr nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s));
- a_target_phys_addr nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s));
+ target_phys_addr_t crda = pcnet_rdra_addr(s, CSR_RCVRC(s));
+ target_phys_addr_t nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s));
+ target_phys_addr_t nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s));
#else
- a_target_phys_addr crda = s->rdra +
+ target_phys_addr_t crda = s->rdra +
(CSR_RCVRL(s) - CSR_RCVRC(s)) *
(BCR_SWSTYLE(s) ? 16 : 8 );
int nrdc = CSR_RCVRC(s)<=1 ? CSR_RCVRL(s) : CSR_RCVRC(s)-1;
- a_target_phys_addr nrda = s->rdra +
+ target_phys_addr_t nrda = s->rdra +
(CSR_RCVRL(s) - nrdc) *
(BCR_SWSTYLE(s) ? 16 : 8 );
int nnrc = nrdc<=1 ? CSR_RCVRL(s) : nrdc-1;
- a_target_phys_addr nnrd = s->rdra +
+ target_phys_addr_t nnrd = s->rdra +
(CSR_RCVRL(s) - nnrc) *
(BCR_SWSTYLE(s) ? 16 : 8 );
#endif
@@ -1027,7 +1027,7 @@ static int pcnet_tdte_poll(PCNetState *s)
{
s->csr[34] = s->csr[35] = 0;
if (s->tdra) {
- a_target_phys_addr cxda = s->tdra +
+ target_phys_addr_t cxda = s->tdra +
(CSR_XMTRL(s) - CSR_XMTRC(s)) *
(BCR_SWSTYLE(s) ? 16 : 8);
int bad = 0;
@@ -1109,7 +1109,7 @@ static ssize_t pcnet_receive(VLANClientState *vc, const uint8_t *buf, size_t siz
if (!(CSR_CRST(s) & 0x8000) && s->rdra) {
struct pcnet_RMD rmd;
int rcvrc = CSR_RCVRC(s)-1,i;
- a_target_phys_addr nrda;
+ target_phys_addr_t nrda;
for (i = CSR_RCVRL(s)-1; i > 0; i--, rcvrc--) {
if (rcvrc <= 1)
rcvrc = CSR_RCVRL(s);
@@ -1137,7 +1137,7 @@ static ssize_t pcnet_receive(VLANClientState *vc, const uint8_t *buf, size_t siz
CSR_MISSC(s)++;
} else {
uint8_t *src = s->buffer;
- a_target_phys_addr crda = CSR_CRDA(s);
+ target_phys_addr_t crda = CSR_CRDA(s);
struct pcnet_RMD rmd;
int pktcount = 0;
@@ -1177,7 +1177,7 @@ static ssize_t pcnet_receive(VLANClientState *vc, const uint8_t *buf, size_t siz
#define PCNET_RECV_STORE() do { \
int count = MIN(4096 - GET_FIELD(rmd.buf_length, RMDL, BCNT),remaining); \
- a_target_phys_addr rbadr = PHYSADDR(s, rmd.rbadr); \
+ target_phys_addr_t rbadr = PHYSADDR(s, rmd.rbadr); \
s->phys_mem_write(s->dma_opaque, rbadr, src, count, CSR_BSWP(s)); \
src += count; remaining -= count; \
SET_FIELD(&rmd.status, RMDS, OWN, 0); \
@@ -1188,7 +1188,7 @@ static ssize_t pcnet_receive(VLANClientState *vc, const uint8_t *buf, size_t siz
remaining = size;
PCNET_RECV_STORE();
if ((remaining > 0) && CSR_NRDA(s)) {
- a_target_phys_addr nrda = CSR_NRDA(s);
+ target_phys_addr_t nrda = CSR_NRDA(s);
#ifdef PCNET_DEBUG_RMD
PRINT_RMD(&rmd);
#endif
@@ -1258,7 +1258,7 @@ static ssize_t pcnet_receive(VLANClientState *vc, const uint8_t *buf, size_t siz
static void pcnet_transmit(PCNetState *s)
{
- a_target_phys_addr xmit_cxda = 0;
+ target_phys_addr_t xmit_cxda = 0;
int count = CSR_XMTRL(s)-1;
int add_crc = 0;
@@ -1778,7 +1778,7 @@ static void pcnet_ioport_map(PCIDevice *pci_dev, int region_num,
register_ioport_read(addr + 0x10, 0x10, 4, pcnet_ioport_readl, d);
}
-static void pcnet_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
@@ -1789,7 +1789,7 @@ static void pcnet_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t va
pcnet_aprom_writeb(d, addr & 0x0f, val);
}
-static uint32_t pcnet_mmio_readb(void *opaque, a_target_phys_addr addr)
+static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr)
{
PCNetState *d = opaque;
uint32_t val = -1;
@@ -1802,7 +1802,7 @@ static uint32_t pcnet_mmio_readb(void *opaque, a_target_phys_addr addr)
return val;
}
-static void pcnet_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void pcnet_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
@@ -1818,7 +1818,7 @@ static void pcnet_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t va
}
}
-static uint32_t pcnet_mmio_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr)
{
PCNetState *d = opaque;
uint32_t val = -1;
@@ -1837,7 +1837,7 @@ static uint32_t pcnet_mmio_readw(void *opaque, a_target_phys_addr addr)
return val;
}
-static void pcnet_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void pcnet_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
@@ -1855,7 +1855,7 @@ static void pcnet_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t va
}
}
-static uint32_t pcnet_mmio_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr)
{
PCNetState *d = opaque;
uint32_t val;
@@ -2000,13 +2000,13 @@ static void pcnet_mmio_map(PCIDevice *pci_dev, int region_num,
cpu_register_physical_memory(addr, PCNET_PNPMMIO_SIZE, d->state.mmio_index);
}
-static void pci_physical_memory_write(void *dma_opaque, a_target_phys_addr addr,
+static void pci_physical_memory_write(void *dma_opaque, target_phys_addr_t addr,
uint8_t *buf, int len, int do_bswap)
{
cpu_physical_memory_write(addr, buf, len);
}
-static void pci_physical_memory_read(void *dma_opaque, a_target_phys_addr addr,
+static void pci_physical_memory_read(void *dma_opaque, target_phys_addr_t addr,
uint8_t *buf, int len, int do_bswap)
{
cpu_physical_memory_read(addr, buf, len);
@@ -2089,7 +2089,7 @@ static void parent_lance_reset(void *opaque, int irq, int level)
pcnet_h_reset(&d->state);
}
-static void lance_mem_writew(void *opaque, a_target_phys_addr addr,
+static void lance_mem_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
SysBusPCNetState *d = opaque;
@@ -2100,7 +2100,7 @@ static void lance_mem_writew(void *opaque, a_target_phys_addr addr,
pcnet_ioport_writew(&d->state, addr, val & 0xffff);
}
-static uint32_t lance_mem_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
{
SysBusPCNetState *d = opaque;
uint32_t val;
diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.c
index 0ff0ade0b..f343dbf7b 100644
--- a/hw/petalogix_s3adsp1800_mmu.c
+++ b/hw/petalogix_s3adsp1800_mmu.c
@@ -48,10 +48,10 @@ static void main_cpu_reset(void *opaque)
}
#define BINARY_DEVICE_TREE_FILE "petalogix-s3adsp1800.dtb"
-static int petalogix_load_device_tree(a_target_phys_addr addr,
+static int petalogix_load_device_tree(target_phys_addr_t addr,
uint32_t ramsize,
- a_target_phys_addr initrd_base,
- a_target_phys_addr initrd_size,
+ target_phys_addr_t initrd_base,
+ target_phys_addr_t initrd_size,
const char *kernel_cmdline)
{
char *path;
@@ -97,7 +97,7 @@ static int petalogix_load_device_tree(a_target_phys_addr addr,
}
static void
-petalogix_s3adsp1800_init(a_ram_addr ram_size,
+petalogix_s3adsp1800_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
@@ -108,10 +108,10 @@ petalogix_s3adsp1800_init(a_ram_addr ram_size,
int kernel_size;
DriveInfo *dinfo;
int i;
- a_target_phys_addr ddr_base = 0x90000000;
- a_ram_addr phys_lmb_bram;
- a_ram_addr phys_ram;
- a_ram_addr phys_flash;
+ target_phys_addr_t ddr_base = 0x90000000;
+ ram_addr_t phys_lmb_bram;
+ ram_addr_t phys_ram;
+ ram_addr_t phys_flash;
qemu_irq irq[32], *cpu_irq;
/* init CPUs */
diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c
index b45f0c20e..dfdced97b 100644
--- a/hw/pflash_cfi01.c
+++ b/hw/pflash_cfi01.c
@@ -57,11 +57,11 @@ do { \
#define DPRINTF(fmt, ...) do { } while (0)
#endif
-struct pflash {
+struct pflash_t {
BlockDriverState *bs;
- a_target_phys_addr base;
- a_target_phys_addr sector_len;
- a_target_phys_addr total_len;
+ target_phys_addr_t base;
+ target_phys_addr_t sector_len;
+ target_phys_addr_t total_len;
int width;
int wcycle; /* if 0, the flash is read normally */
int bypass;
@@ -71,16 +71,16 @@ struct pflash {
uint16_t ident[4];
uint8_t cfi_len;
uint8_t cfi_table[0x52];
- a_target_phys_addr counter;
+ target_phys_addr_t counter;
QEMUTimer *timer;
- a_ram_addr off;
+ ram_addr_t off;
int fl_mem;
void *storage;
};
static void pflash_timer (void *opaque)
{
- a_pflash *pfl = opaque;
+ pflash_t *pfl = opaque;
DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
/* Reset flash */
@@ -95,10 +95,10 @@ static void pflash_timer (void *opaque)
pfl->cmd = 0;
}
-static uint32_t pflash_read (a_pflash *pfl, a_target_phys_addr offset,
+static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
int width)
{
- a_target_phys_addr boff;
+ target_phys_addr_t boff;
uint32_t ret;
uint8_t *p;
@@ -181,7 +181,7 @@ static uint32_t pflash_read (a_pflash *pfl, a_target_phys_addr offset,
}
/* update flash content on disk */
-static void pflash_update(a_pflash *pfl, int offset,
+static void pflash_update(pflash_t *pfl, int offset,
int size)
{
int offset_end;
@@ -195,7 +195,7 @@ static void pflash_update(a_pflash *pfl, int offset,
}
}
-static inline void pflash_data_write(a_pflash *pfl, a_target_phys_addr offset,
+static inline void pflash_data_write(pflash_t *pfl, target_phys_addr_t offset,
uint32_t value, int width)
{
uint8_t *p = pfl->storage;
@@ -236,10 +236,10 @@ static inline void pflash_data_write(a_pflash *pfl, a_target_phys_addr offset,
}
-static void pflash_write(a_pflash *pfl, a_target_phys_addr offset,
+static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
uint32_t value, int width)
{
- a_target_phys_addr boff;
+ target_phys_addr_t boff;
uint8_t *p;
uint8_t cmd;
@@ -413,43 +413,43 @@ static void pflash_write(a_pflash *pfl, a_target_phys_addr offset,
}
-static uint32_t pflash_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr)
{
return pflash_read(opaque, addr, 1);
}
-static uint32_t pflash_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr)
{
- a_pflash *pfl = opaque;
+ pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 2);
}
-static uint32_t pflash_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr)
{
- a_pflash *pfl = opaque;
+ pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 4);
}
-static void pflash_writeb (void *opaque, a_target_phys_addr addr,
+static void pflash_writeb (void *opaque, target_phys_addr_t addr,
uint32_t value)
{
pflash_write(opaque, addr, value, 1);
}
-static void pflash_writew (void *opaque, a_target_phys_addr addr,
+static void pflash_writew (void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- a_pflash *pfl = opaque;
+ pflash_t *pfl = opaque;
pflash_write(pfl, addr, value, 2);
}
-static void pflash_writel (void *opaque, a_target_phys_addr addr,
+static void pflash_writel (void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- a_pflash *pfl = opaque;
+ pflash_t *pfl = opaque;
pflash_write(pfl, addr, value, 4);
}
@@ -500,14 +500,14 @@ static int ctz32 (uint32_t n)
return ret;
}
-a_pflash *pflash_cfi01_register(a_target_phys_addr base, a_ram_addr off,
+pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3)
{
- a_pflash *pfl;
- a_target_phys_addr total_len;
+ pflash_t *pfl;
+ target_phys_addr_t total_len;
int ret;
total_len = sector_len * nb_blocs;
@@ -519,7 +519,7 @@ a_pflash *pflash_cfi01_register(a_target_phys_addr base, a_ram_addr off,
return NULL;
#endif
- pfl = qemu_mallocz(sizeof(a_pflash));
+ pfl = qemu_mallocz(sizeof(pflash_t));
/* FIXME: Allocate ram ourselves. */
pfl->storage = qemu_get_ram_ptr(off);
diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c
index 2836a897c..135c85079 100644
--- a/hw/pflash_cfi02.c
+++ b/hw/pflash_cfi02.c
@@ -50,9 +50,9 @@ do { \
#define DPRINTF(fmt, ...) do { } while (0)
#endif
-struct pflash {
+struct pflash_t {
BlockDriverState *bs;
- a_target_phys_addr base;
+ target_phys_addr_t base;
uint32_t sector_len;
uint32_t chip_len;
int mappings;
@@ -67,13 +67,13 @@ struct pflash {
uint8_t cfi_len;
uint8_t cfi_table[0x52];
QEMUTimer *timer;
- a_ram_addr off;
+ ram_addr_t off;
int fl_mem;
int rom_mode;
void *storage;
};
-static void pflash_register_memory(a_pflash *pfl, int rom_mode)
+static void pflash_register_memory(pflash_t *pfl, int rom_mode)
{
unsigned long phys_offset = pfl->fl_mem;
int i;
@@ -89,7 +89,7 @@ static void pflash_register_memory(a_pflash *pfl, int rom_mode)
static void pflash_timer (void *opaque)
{
- a_pflash *pfl = opaque;
+ pflash_t *pfl = opaque;
DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
/* Reset flash */
@@ -103,7 +103,7 @@ static void pflash_timer (void *opaque)
pfl->cmd = 0;
}
-static uint32_t pflash_read (a_pflash *pfl, uint32_t offset, int width)
+static uint32_t pflash_read (pflash_t *pfl, uint32_t offset, int width)
{
uint32_t boff;
uint32_t ret;
@@ -208,7 +208,7 @@ static uint32_t pflash_read (a_pflash *pfl, uint32_t offset, int width)
}
/* update flash content on disk */
-static void pflash_update(a_pflash *pfl, int offset,
+static void pflash_update(pflash_t *pfl, int offset,
int size)
{
int offset_end;
@@ -222,7 +222,7 @@ static void pflash_update(a_pflash *pfl, int offset,
}
}
-static void pflash_write (a_pflash *pfl, uint32_t offset, uint32_t value,
+static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
int width)
{
uint32_t boff;
@@ -451,43 +451,43 @@ static void pflash_write (a_pflash *pfl, uint32_t offset, uint32_t value,
}
-static uint32_t pflash_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr)
{
return pflash_read(opaque, addr, 1);
}
-static uint32_t pflash_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr)
{
- a_pflash *pfl = opaque;
+ pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 2);
}
-static uint32_t pflash_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr)
{
- a_pflash *pfl = opaque;
+ pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 4);
}
-static void pflash_writeb (void *opaque, a_target_phys_addr addr,
+static void pflash_writeb (void *opaque, target_phys_addr_t addr,
uint32_t value)
{
pflash_write(opaque, addr, value, 1);
}
-static void pflash_writew (void *opaque, a_target_phys_addr addr,
+static void pflash_writew (void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- a_pflash *pfl = opaque;
+ pflash_t *pfl = opaque;
pflash_write(pfl, addr, value, 2);
}
-static void pflash_writel (void *opaque, a_target_phys_addr addr,
+static void pflash_writel (void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- a_pflash *pfl = opaque;
+ pflash_t *pfl = opaque;
pflash_write(pfl, addr, value, 4);
}
@@ -538,14 +538,14 @@ static int ctz32 (uint32_t n)
return ret;
}
-a_pflash *pflash_cfi02_register(a_target_phys_addr base, a_ram_addr off,
+pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3,
uint16_t unlock_addr0, uint16_t unlock_addr1)
{
- a_pflash *pfl;
+ pflash_t *pfl;
int32_t chip_len;
int ret;
@@ -556,7 +556,7 @@ a_pflash *pflash_cfi02_register(a_target_phys_addr base, a_ram_addr off,
total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
return NULL;
#endif
- pfl = qemu_mallocz(sizeof(a_pflash));
+ pfl = qemu_mallocz(sizeof(pflash_t));
/* FIXME: Allocate ram ourselves. */
pfl->storage = qemu_get_ram_ptr(off);
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops, pflash_write_ops,
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index ef313ce32..edd6df07e 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -28,7 +28,7 @@
#include "isa.h"
#include "sysbus.h"
-typedef uint32_t a_pci_addr;
+typedef uint32_t pci_addr_t;
#include "pci_host.h"
typedef PCIHostState I440FXState;
@@ -45,7 +45,7 @@ typedef struct PIIX3IrqState {
struct PCII440FXState {
PCIDevice dev;
- a_target_phys_addr isa_page_descs[384 / 4];
+ target_phys_addr_t isa_page_descs[384 / 4];
uint8_t smm_enabled;
PIIX3IrqState *irq_state;
};
diff --git a/hw/pl011.c b/hw/pl011.c
index 14c00eb00..81de91e4c 100644
--- a/hw/pl011.c
+++ b/hw/pl011.c
@@ -53,7 +53,7 @@ static void pl011_update(pl011_state *s)
qemu_set_irq(s->irq, flags != 0);
}
-static uint32_t pl011_read(void *opaque, a_target_phys_addr offset)
+static uint32_t pl011_read(void *opaque, target_phys_addr_t offset)
{
pl011_state *s = (pl011_state *)opaque;
uint32_t c;
@@ -122,7 +122,7 @@ static void pl011_set_read_trigger(pl011_state *s)
s->read_trigger = 1;
}
-static void pl011_write(void *opaque, a_target_phys_addr offset,
+static void pl011_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
pl011_state *s = (pl011_state *)opaque;
diff --git a/hw/pl022.c b/hw/pl022.c
index 0cb3f3bce..c2e2ddafe 100644
--- a/hw/pl022.c
+++ b/hw/pl022.c
@@ -130,7 +130,7 @@ static void pl022_xfer(pl022_state *s)
pl022_update(s);
}
-static uint32_t pl022_read(void *opaque, a_target_phys_addr offset)
+static uint32_t pl022_read(void *opaque, target_phys_addr_t offset)
{
pl022_state *s = (pl022_state *)opaque;
int val;
@@ -172,7 +172,7 @@ static uint32_t pl022_read(void *opaque, a_target_phys_addr offset)
}
}
-static void pl022_write(void *opaque, a_target_phys_addr offset,
+static void pl022_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
pl022_state *s = (pl022_state *)opaque;
diff --git a/hw/pl031.c b/hw/pl031.c
index 807718735..45b7032c5 100644
--- a/hw/pl031.c
+++ b/hw/pl031.c
@@ -90,7 +90,7 @@ static void pl031_set_alarm(pl031_state *s)
}
}
-static uint32_t pl031_read(void *opaque, a_target_phys_addr offset)
+static uint32_t pl031_read(void *opaque, target_phys_addr_t offset)
{
pl031_state *s = (pl031_state *)opaque;
@@ -125,7 +125,7 @@ static uint32_t pl031_read(void *opaque, a_target_phys_addr offset)
return 0;
}
-static void pl031_write(void * opaque, a_target_phys_addr offset,
+static void pl031_write(void * opaque, target_phys_addr_t offset,
uint32_t value)
{
pl031_state *s = (pl031_state *)opaque;
diff --git a/hw/pl050.c b/hw/pl050.c
index c89456fa7..a47786cb0 100644
--- a/hw/pl050.c
+++ b/hw/pl050.c
@@ -43,7 +43,7 @@ static void pl050_update(void *opaque, int level)
qemu_set_irq(s->irq, raise);
}
-static uint32_t pl050_read(void *opaque, a_target_phys_addr offset)
+static uint32_t pl050_read(void *opaque, target_phys_addr_t offset)
{
pl050_state *s = (pl050_state *)opaque;
if (offset >= 0xfe0 && offset < 0x1000)
@@ -84,7 +84,7 @@ static uint32_t pl050_read(void *opaque, a_target_phys_addr offset)
}
}
-static void pl050_write(void *opaque, a_target_phys_addr offset,
+static void pl050_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
pl050_state *s = (pl050_state *)opaque;
diff --git a/hw/pl061.c b/hw/pl061.c
index 3cea71d9c..7b1b636e9 100644
--- a/hw/pl061.c
+++ b/hw/pl061.c
@@ -78,7 +78,7 @@ static void pl061_update(pl061_state *s)
/* FIXME: Implement input interrupts. */
}
-static uint32_t pl061_read(void *opaque, a_target_phys_addr offset)
+static uint32_t pl061_read(void *opaque, target_phys_addr_t offset)
{
pl061_state *s = (pl061_state *)opaque;
@@ -131,7 +131,7 @@ static uint32_t pl061_read(void *opaque, a_target_phys_addr offset)
}
}
-static void pl061_write(void *opaque, a_target_phys_addr offset,
+static void pl061_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
pl061_state *s = (pl061_state *)opaque;
diff --git a/hw/pl080.c b/hw/pl080.c
index 4abc319a6..2df65fab9 100644
--- a/hw/pl080.c
+++ b/hw/pl080.c
@@ -180,7 +180,7 @@ again:
}
}
-static uint32_t pl080_read(void *opaque, a_target_phys_addr offset)
+static uint32_t pl080_read(void *opaque, target_phys_addr_t offset)
{
pl080_state *s = (pl080_state *)opaque;
uint32_t i;
@@ -247,7 +247,7 @@ static uint32_t pl080_read(void *opaque, a_target_phys_addr offset)
}
}
-static void pl080_write(void *opaque, a_target_phys_addr offset,
+static void pl080_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
pl080_state *s = (pl080_state *)opaque;
diff --git a/hw/pl110.c b/hw/pl110.c
index 41ae88db2..173458a7c 100644
--- a/hw/pl110.c
+++ b/hw/pl110.c
@@ -226,7 +226,7 @@ static void pl110_update(pl110_state *s)
/* TODO: Implement interrupts. */
}
-static uint32_t pl110_read(void *opaque, a_target_phys_addr offset)
+static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
{
pl110_state *s = (pl110_state *)opaque;
@@ -275,7 +275,7 @@ static uint32_t pl110_read(void *opaque, a_target_phys_addr offset)
}
}
-static void pl110_write(void *opaque, a_target_phys_addr offset,
+static void pl110_write(void *opaque, target_phys_addr_t offset,
uint32_t val)
{
pl110_state *s = (pl110_state *)opaque;
diff --git a/hw/pl181.c b/hw/pl181.c
index d92bad6eb..728205305 100644
--- a/hw/pl181.c
+++ b/hw/pl181.c
@@ -256,7 +256,7 @@ static void pl181_fifo_run(pl181_state *s)
}
}
-static uint32_t pl181_read(void *opaque, a_target_phys_addr offset)
+static uint32_t pl181_read(void *opaque, target_phys_addr_t offset)
{
pl181_state *s = (pl181_state *)opaque;
uint32_t tmp;
@@ -338,7 +338,7 @@ static uint32_t pl181_read(void *opaque, a_target_phys_addr offset)
}
}
-static void pl181_write(void *opaque, a_target_phys_addr offset,
+static void pl181_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
pl181_state *s = (pl181_state *)opaque;
diff --git a/hw/pl190.c b/hw/pl190.c
index 1e8ab9ee2..a4bc9c15e 100644
--- a/hw/pl190.c
+++ b/hw/pl190.c
@@ -85,7 +85,7 @@ static void pl190_update_vectors(pl190_state *s)
pl190_update(s);
}
-static uint32_t pl190_read(void *opaque, a_target_phys_addr offset)
+static uint32_t pl190_read(void *opaque, target_phys_addr_t offset)
{
pl190_state *s = (pl190_state *)opaque;
int i;
@@ -141,7 +141,7 @@ static uint32_t pl190_read(void *opaque, a_target_phys_addr offset)
}
}
-static void pl190_write(void *opaque, a_target_phys_addr offset, uint32_t val)
+static void pl190_write(void *opaque, target_phys_addr_t offset, uint32_t val)
{
pl190_state *s = (pl190_state *)opaque;
diff --git a/hw/ppc.c b/hw/ppc.c
index dca259fa5..09ee2e46d 100644
--- a/hw/ppc.c
+++ b/hw/ppc.c
@@ -377,7 +377,7 @@ void ppce500_irq_init (CPUState *env)
}
/*****************************************************************************/
/* PowerPC time base and decrementer emulation */
-struct ppc_tb {
+struct ppc_tb_t {
/* Time base management */
int64_t tb_offset; /* Compensation */
int64_t atb_offset; /* Compensation */
@@ -394,7 +394,7 @@ struct ppc_tb {
void *opaque;
};
-static inline uint64_t cpu_ppc_get_tb(a_ppc_tb *tb_env, uint64_t vmclk,
+static inline uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk,
int64_t tb_offset)
{
/* TB time in tb periods */
@@ -403,7 +403,7 @@ static inline uint64_t cpu_ppc_get_tb(a_ppc_tb *tb_env, uint64_t vmclk,
uint32_t cpu_ppc_load_tbl (CPUState *env)
{
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
@@ -414,7 +414,7 @@ uint32_t cpu_ppc_load_tbl (CPUState *env)
static inline uint32_t _cpu_ppc_load_tbu(CPUState *env)
{
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
@@ -428,7 +428,7 @@ uint32_t cpu_ppc_load_tbu (CPUState *env)
return _cpu_ppc_load_tbu(env);
}
-static inline void cpu_ppc_store_tb(a_ppc_tb *tb_env, uint64_t vmclk,
+static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk,
int64_t *tb_offsetp, uint64_t value)
{
*tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec());
@@ -438,7 +438,7 @@ static inline void cpu_ppc_store_tb(a_ppc_tb *tb_env, uint64_t vmclk,
void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
{
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
@@ -449,7 +449,7 @@ void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value)
{
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
@@ -465,7 +465,7 @@ void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
uint32_t cpu_ppc_load_atbl (CPUState *env)
{
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
@@ -476,7 +476,7 @@ uint32_t cpu_ppc_load_atbl (CPUState *env)
uint32_t cpu_ppc_load_atbu (CPUState *env)
{
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
@@ -487,7 +487,7 @@ uint32_t cpu_ppc_load_atbu (CPUState *env)
void cpu_ppc_store_atbl (CPUState *env, uint32_t value)
{
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
@@ -498,7 +498,7 @@ void cpu_ppc_store_atbl (CPUState *env, uint32_t value)
void cpu_ppc_store_atbu (CPUState *env, uint32_t value)
{
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
@@ -509,7 +509,7 @@ void cpu_ppc_store_atbu (CPUState *env, uint32_t value)
static void cpu_ppc_tb_stop (CPUState *env)
{
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
uint64_t tb, atb, vmclk;
/* If the time base is already frozen, do nothing */
@@ -531,7 +531,7 @@ static void cpu_ppc_tb_stop (CPUState *env)
static void cpu_ppc_tb_start (CPUState *env)
{
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
uint64_t tb, atb, vmclk;
/* If the time base is not frozen, do nothing */
@@ -552,7 +552,7 @@ static void cpu_ppc_tb_start (CPUState *env)
static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next)
{
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
uint32_t decr;
int64_t diff;
@@ -568,21 +568,21 @@ static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next)
uint32_t cpu_ppc_load_decr (CPUState *env)
{
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
return _cpu_ppc_load_decr(env, tb_env->decr_next);
}
uint32_t cpu_ppc_load_hdecr (CPUState *env)
{
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
return _cpu_ppc_load_decr(env, tb_env->hdecr_next);
}
uint64_t cpu_ppc_load_purr (CPUState *env)
{
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
uint64_t diff;
diff = qemu_get_clock(vm_clock) - tb_env->purr_start;
@@ -613,7 +613,7 @@ static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
uint32_t decr, uint32_t value,
int is_excp)
{
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
uint64_t now, next;
LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,
@@ -637,7 +637,7 @@ static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr,
uint32_t value, int is_excp)
{
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
__cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer,
&cpu_ppc_decr_excp, decr, value, is_excp);
@@ -656,7 +656,7 @@ static void cpu_ppc_decr_cb (void *opaque)
static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr,
uint32_t value, int is_excp)
{
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
if (tb_env->hdecr_timer != NULL) {
__cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer,
@@ -676,7 +676,7 @@ static void cpu_ppc_hdecr_cb (void *opaque)
void cpu_ppc_store_purr (CPUState *env, uint64_t value)
{
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
tb_env->purr_load = value;
tb_env->purr_start = qemu_get_clock(vm_clock);
@@ -685,7 +685,7 @@ void cpu_ppc_store_purr (CPUState *env, uint64_t value)
static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
{
CPUState *env = opaque;
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
tb_env->tb_freq = freq;
tb_env->decr_freq = freq;
@@ -701,9 +701,9 @@ static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
/* Set up (once) timebase frequency (in Hz) */
clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq)
{
- a_ppc_tb *tb_env;
+ ppc_tb_t *tb_env;
- tb_env = qemu_mallocz(sizeof(a_ppc_tb));
+ tb_env = qemu_mallocz(sizeof(ppc_tb_t));
env->tb_env = tb_env;
/* Create new timer */
tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
@@ -751,8 +751,8 @@ uint32_t cpu_ppc601_load_rtcl (CPUState *env)
/* Embedded PowerPC timers */
/* PIT, FIT & WDT */
-typedef struct ppcemb_timer a_ppcemb_timer;
-struct ppcemb_timer {
+typedef struct ppcemb_timer_t ppcemb_timer_t;
+struct ppcemb_timer_t {
uint64_t pit_reload; /* PIT auto-reload value */
uint64_t fit_next; /* Tick for next FIT interrupt */
struct QEMUTimer *fit_timer;
@@ -764,8 +764,8 @@ struct ppcemb_timer {
static void cpu_4xx_fit_cb (void *opaque)
{
CPUState *env;
- a_ppc_tb *tb_env;
- a_ppcemb_timer *ppcemb_timer;
+ ppc_tb_t *tb_env;
+ ppcemb_timer_t *ppcemb_timer;
uint64_t now, next;
env = opaque;
@@ -802,9 +802,9 @@ static void cpu_4xx_fit_cb (void *opaque)
}
/* Programmable interval timer */
-static void start_stop_pit (CPUState *env, a_ppc_tb *tb_env, int is_excp)
+static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp)
{
- a_ppcemb_timer *ppcemb_timer;
+ ppcemb_timer_t *ppcemb_timer;
uint64_t now, next;
ppcemb_timer = tb_env->opaque;
@@ -832,8 +832,8 @@ static void start_stop_pit (CPUState *env, a_ppc_tb *tb_env, int is_excp)
static void cpu_4xx_pit_cb (void *opaque)
{
CPUState *env;
- a_ppc_tb *tb_env;
- a_ppcemb_timer *ppcemb_timer;
+ ppc_tb_t *tb_env;
+ ppcemb_timer_t *ppcemb_timer;
env = opaque;
tb_env = env->tb_env;
@@ -854,8 +854,8 @@ static void cpu_4xx_pit_cb (void *opaque)
static void cpu_4xx_wdt_cb (void *opaque)
{
CPUState *env;
- a_ppc_tb *tb_env;
- a_ppcemb_timer *ppcemb_timer;
+ ppc_tb_t *tb_env;
+ ppcemb_timer_t *ppcemb_timer;
uint64_t now, next;
env = opaque;
@@ -920,8 +920,8 @@ static void cpu_4xx_wdt_cb (void *opaque)
void store_40x_pit (CPUState *env, target_ulong val)
{
- a_ppc_tb *tb_env;
- a_ppcemb_timer *ppcemb_timer;
+ ppc_tb_t *tb_env;
+ ppcemb_timer_t *ppcemb_timer;
tb_env = env->tb_env;
ppcemb_timer = tb_env->opaque;
@@ -945,7 +945,7 @@ void store_booke_tsr (CPUState *env, target_ulong val)
void store_booke_tcr (CPUState *env, target_ulong val)
{
- a_ppc_tb *tb_env;
+ ppc_tb_t *tb_env;
tb_env = env->tb_env;
LOG_TB("%s: val " TARGET_FMT_lx "\n", __func__, val);
@@ -957,7 +957,7 @@ void store_booke_tcr (CPUState *env, target_ulong val)
static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq)
{
CPUState *env = opaque;
- a_ppc_tb *tb_env = env->tb_env;
+ ppc_tb_t *tb_env = env->tb_env;
LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__,
freq);
@@ -968,12 +968,12 @@ static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq)
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq)
{
- a_ppc_tb *tb_env;
- a_ppcemb_timer *ppcemb_timer;
+ ppc_tb_t *tb_env;
+ ppcemb_timer_t *ppcemb_timer;
- tb_env = qemu_mallocz(sizeof(a_ppc_tb));
+ tb_env = qemu_mallocz(sizeof(ppc_tb_t));
env->tb_env = tb_env;
- ppcemb_timer = qemu_mallocz(sizeof(a_ppcemb_timer));
+ ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
tb_env->tb_freq = freq;
tb_env->decr_freq = freq;
tb_env->opaque = ppcemb_timer;
@@ -992,8 +992,8 @@ clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq)
/*****************************************************************************/
/* Embedded PowerPC Device Control Registers */
-typedef struct ppc_dcrn a_ppc_dcrn;
-struct ppc_dcrn {
+typedef struct ppc_dcrn_t ppc_dcrn_t;
+struct ppc_dcrn_t {
dcr_read_cb dcr_read;
dcr_write_cb dcr_write;
void *opaque;
@@ -1003,15 +1003,15 @@ struct ppc_dcrn {
* using DCRIPR to get the 22 upper bits of the DCR address
*/
#define DCRN_NB 1024
-struct ppc_dcr {
- a_ppc_dcrn dcrn[DCRN_NB];
+struct ppc_dcr_t {
+ ppc_dcrn_t dcrn[DCRN_NB];
int (*read_error)(int dcrn);
int (*write_error)(int dcrn);
};
-int ppc_dcr_read (a_ppc_dcr *dcr_env, int dcrn, target_ulong *valp)
+int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
{
- a_ppc_dcrn *dcr;
+ ppc_dcrn_t *dcr;
if (dcrn < 0 || dcrn >= DCRN_NB)
goto error;
@@ -1029,9 +1029,9 @@ int ppc_dcr_read (a_ppc_dcr *dcr_env, int dcrn, target_ulong *valp)
return -1;
}
-int ppc_dcr_write (a_ppc_dcr *dcr_env, int dcrn, target_ulong val)
+int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
{
- a_ppc_dcrn *dcr;
+ ppc_dcrn_t *dcr;
if (dcrn < 0 || dcrn >= DCRN_NB)
goto error;
@@ -1052,8 +1052,8 @@ int ppc_dcr_write (a_ppc_dcr *dcr_env, int dcrn, target_ulong val)
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
dcr_read_cb dcr_read, dcr_write_cb dcr_write)
{
- a_ppc_dcr *dcr_env;
- a_ppc_dcrn *dcr;
+ ppc_dcr_t *dcr_env;
+ ppc_dcrn_t *dcr;
dcr_env = env->dcr_env;
if (dcr_env == NULL)
@@ -1075,9 +1075,9 @@ int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn),
int (*write_error)(int dcrn))
{
- a_ppc_dcr *dcr_env;
+ ppc_dcr_t *dcr_env;
- dcr_env = qemu_mallocz(sizeof(a_ppc_dcr));
+ dcr_env = qemu_mallocz(sizeof(ppc_dcr_t));
dcr_env->read_error = read_error;
dcr_env->write_error = write_error;
env->dcr_env = dcr_env;
@@ -1117,33 +1117,33 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
/*****************************************************************************/
/* NVRAM helpers */
-static inline uint32_t nvram_read (a_nvram *nvram, uint32_t addr)
+static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr)
{
return (*nvram->read_fn)(nvram->opaque, addr);;
}
-static inline void nvram_write (a_nvram *nvram, uint32_t addr, uint32_t val)
+static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val)
{
(*nvram->write_fn)(nvram->opaque, addr, val);
}
-void NVRAM_set_byte (a_nvram *nvram, uint32_t addr, uint8_t value)
+void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value)
{
nvram_write(nvram, addr, value);
}
-uint8_t NVRAM_get_byte (a_nvram *nvram, uint32_t addr)
+uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr)
{
return nvram_read(nvram, addr);
}
-void NVRAM_set_word (a_nvram *nvram, uint32_t addr, uint16_t value)
+void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value)
{
nvram_write(nvram, addr, value >> 8);
nvram_write(nvram, addr + 1, value & 0xFF);
}
-uint16_t NVRAM_get_word (a_nvram *nvram, uint32_t addr)
+uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr)
{
uint16_t tmp;
@@ -1153,7 +1153,7 @@ uint16_t NVRAM_get_word (a_nvram *nvram, uint32_t addr)
return tmp;
}
-void NVRAM_set_lword (a_nvram *nvram, uint32_t addr, uint32_t value)
+void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value)
{
nvram_write(nvram, addr, value >> 24);
nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
@@ -1161,7 +1161,7 @@ void NVRAM_set_lword (a_nvram *nvram, uint32_t addr, uint32_t value)
nvram_write(nvram, addr + 3, value & 0xFF);
}
-uint32_t NVRAM_get_lword (a_nvram *nvram, uint32_t addr)
+uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr)
{
uint32_t tmp;
@@ -1173,7 +1173,7 @@ uint32_t NVRAM_get_lword (a_nvram *nvram, uint32_t addr)
return tmp;
}
-void NVRAM_set_string (a_nvram *nvram, uint32_t addr,
+void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
const char *str, uint32_t max)
{
int i;
@@ -1185,7 +1185,7 @@ void NVRAM_set_string (a_nvram *nvram, uint32_t addr,
nvram_write(nvram, addr + max - 1, '\0');
}
-int NVRAM_get_string (a_nvram *nvram, uint8_t *dst, uint16_t addr, int max)
+int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max)
{
int i;
@@ -1214,7 +1214,7 @@ static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
return tmp;
}
-static uint16_t NVRAM_compute_crc (a_nvram *nvram, uint32_t start, uint32_t count)
+static uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count)
{
uint32_t i;
uint16_t crc = 0xFFFF;
@@ -1234,7 +1234,7 @@ static uint16_t NVRAM_compute_crc (a_nvram *nvram, uint32_t start, uint32_t coun
#define CMDLINE_ADDR 0x017ff000
-int PPC_NVRAM_set_params (a_nvram *nvram, uint16_t NVRAM_size,
+int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
const char *arch,
uint32_t RAM_size, int boot_device,
uint32_t kernel_image, uint32_t kernel_size,
diff --git a/hw/ppc.h b/hw/ppc.h
index c2a56c3e1..4b481afbc 100644
--- a/hw/ppc.h
+++ b/hw/ppc.h
@@ -1,11 +1,11 @@
/* PowerPC hardware exceptions management helpers */
typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
-typedef struct clk_setup a_clk_setup;
-struct clk_setup {
+typedef struct clk_setup_t clk_setup_t;
+struct clk_setup_t {
clk_setup_cb cb;
void *opaque;
};
-static inline void clk_setup (a_clk_setup *clk, uint32_t freq)
+static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
{
if (clk->cb != NULL)
(*clk->cb)(clk->opaque, freq);
diff --git a/hw/ppc405.h b/hw/ppc405.h
index ac1673a88..e042a05b3 100644
--- a/hw/ppc405.h
+++ b/hw/ppc405.h
@@ -28,8 +28,8 @@
#include "ppc4xx.h"
/* Bootinfo as set-up by u-boot */
-typedef struct ppc4xx_bd_info a_ppc4xx_bd_info;
-struct ppc4xx_bd_info {
+typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
+struct ppc4xx_bd_info_t {
uint32_t bi_memstart;
uint32_t bi_memsize;
uint32_t bi_flashstart;
@@ -56,21 +56,21 @@ struct ppc4xx_bd_info {
};
/* PowerPC 405 core */
-a_ram_addr ppc405_set_bootinfo (CPUState *env, a_ppc4xx_bd_info *bd,
+ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
uint32_t flags);
-CPUState *ppc405cr_init (a_target_phys_addr ram_bases[4],
- a_target_phys_addr ram_sizes[4],
+CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
+ target_phys_addr_t ram_sizes[4],
uint32_t sysclk, qemu_irq **picp,
int do_init);
-CPUState *ppc405ep_init (a_target_phys_addr ram_bases[2],
- a_target_phys_addr ram_sizes[2],
+CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
+ target_phys_addr_t ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
int do_init);
/* IBM STBxxx microcontrollers */
-CPUState *ppc_stb025_init (a_target_phys_addr ram_bases[2],
- a_target_phys_addr ram_sizes[2],
+CPUState *ppc_stb025_init (target_phys_addr_t ram_bases[2],
+ target_phys_addr_t ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
- a_ram_addr *offsetp);
+ ram_addr_t *offsetp);
#endif /* !defined(PPC_405_H) */
diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c
index 6a355ced5..9aa99c178 100644
--- a/hw/ppc405_boards.c
+++ b/hw/ppc405_boards.c
@@ -52,15 +52,15 @@
* - NVRAM (0xF0000000)
* - FPGA (0xF0300000)
*/
-typedef struct ref405ep_fpga a_ref405ep_fpga;
-struct ref405ep_fpga {
+typedef struct ref405ep_fpga_t ref405ep_fpga_t;
+struct ref405ep_fpga_t {
uint8_t reg0;
uint8_t reg1;
};
-static uint32_t ref405ep_fpga_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
{
- a_ref405ep_fpga *fpga;
+ ref405ep_fpga_t *fpga;
uint32_t ret;
fpga = opaque;
@@ -80,9 +80,9 @@ static uint32_t ref405ep_fpga_readb (void *opaque, a_target_phys_addr addr)
}
static void ref405ep_fpga_writeb (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
- a_ref405ep_fpga *fpga;
+ ref405ep_fpga_t *fpga;
fpga = opaque;
switch (addr) {
@@ -97,7 +97,7 @@ static void ref405ep_fpga_writeb (void *opaque,
}
}
-static uint32_t ref405ep_fpga_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
{
uint32_t ret;
@@ -108,13 +108,13 @@ static uint32_t ref405ep_fpga_readw (void *opaque, a_target_phys_addr addr)
}
static void ref405ep_fpga_writew (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
}
-static uint32_t ref405ep_fpga_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t ret;
@@ -127,7 +127,7 @@ static uint32_t ref405ep_fpga_readl (void *opaque, a_target_phys_addr addr)
}
static void ref405ep_fpga_writel (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
@@ -149,7 +149,7 @@ static CPUWriteMemoryFunc * const ref405ep_fpga_write[] = {
static void ref405ep_fpga_reset (void *opaque)
{
- a_ref405ep_fpga *fpga;
+ ref405ep_fpga_t *fpga;
fpga = opaque;
fpga->reg0 = 0x00;
@@ -158,10 +158,10 @@ static void ref405ep_fpga_reset (void *opaque)
static void ref405ep_fpga_init (uint32_t base)
{
- a_ref405ep_fpga *fpga;
+ ref405ep_fpga_t *fpga;
int fpga_memory;
- fpga = qemu_mallocz(sizeof(a_ref405ep_fpga));
+ fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,
ref405ep_fpga_write, fpga);
cpu_register_physical_memory(base, 0x00000100, fpga_memory);
@@ -169,7 +169,7 @@ static void ref405ep_fpga_init (uint32_t base)
qemu_register_reset(&ref405ep_fpga_reset, fpga);
}
-static void ref405ep_init (a_ram_addr ram_size,
+static void ref405ep_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
@@ -177,11 +177,11 @@ static void ref405ep_init (a_ram_addr ram_size,
const char *cpu_model)
{
char *filename;
- a_ppc4xx_bd_info bd;
+ ppc4xx_bd_info_t bd;
CPUPPCState *env;
qemu_irq *pic;
- a_ram_addr sram_offset, bios_offset, bdloc;
- a_target_phys_addr ram_bases[2], ram_sizes[2];
+ ram_addr_t sram_offset, bios_offset, bdloc;
+ target_phys_addr_t ram_bases[2], ram_sizes[2];
target_ulong sram_size, bios_size;
//int phy_addr = 0;
//static int phy_addr = 1;
@@ -382,7 +382,7 @@ struct taihu_cpld_t {
uint8_t reg1;
};
-static uint32_t taihu_cpld_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
{
taihu_cpld_t *cpld;
uint32_t ret;
@@ -404,7 +404,7 @@ static uint32_t taihu_cpld_readb (void *opaque, a_target_phys_addr addr)
}
static void taihu_cpld_writeb (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
taihu_cpld_t *cpld;
@@ -421,7 +421,7 @@ static void taihu_cpld_writeb (void *opaque,
}
}
-static uint32_t taihu_cpld_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
{
uint32_t ret;
@@ -432,13 +432,13 @@ static uint32_t taihu_cpld_readw (void *opaque, a_target_phys_addr addr)
}
static void taihu_cpld_writew (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
}
-static uint32_t taihu_cpld_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t ret;
@@ -451,7 +451,7 @@ static uint32_t taihu_cpld_readl (void *opaque, a_target_phys_addr addr)
}
static void taihu_cpld_writel (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
@@ -493,7 +493,7 @@ static void taihu_cpld_init (uint32_t base)
qemu_register_reset(&taihu_cpld_reset, cpld);
}
-static void taihu_405ep_init(a_ram_addr ram_size,
+static void taihu_405ep_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
@@ -503,8 +503,8 @@ static void taihu_405ep_init(a_ram_addr ram_size,
char *filename;
CPUPPCState *env;
qemu_irq *pic;
- a_ram_addr bios_offset;
- a_target_phys_addr ram_bases[2], ram_sizes[2];
+ ram_addr_t bios_offset;
+ target_phys_addr_t ram_bases[2], ram_sizes[2];
target_ulong bios_size;
target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
int linux_boot;
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index 2bac4ee31..59def4ceb 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -40,17 +40,17 @@
#define DEBUG_CLOCKS
//#define DEBUG_CLOCKS_LL
-a_ram_addr ppc405_set_bootinfo (CPUState *env, a_ppc4xx_bd_info *bd,
+ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
uint32_t flags)
{
- a_ram_addr bdloc;
+ ram_addr_t bdloc;
int i, n;
/* We put the bd structure at the top of memory */
if (bd->bi_memsize >= 0x01000000UL)
- bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info);
+ bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
else
- bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info);
+ bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
stl_phys(bdloc + 0x00, bd->bi_memstart);
stl_phys(bdloc + 0x04, bd->bi_memsize);
stl_phys(bdloc + 0x08, bd->bi_flashstart);
@@ -100,8 +100,8 @@ enum {
PLB0_ACR = 0x087,
};
-typedef struct ppc4xx_plb a_ppc4xx_plb;
-struct ppc4xx_plb {
+typedef struct ppc4xx_plb_t ppc4xx_plb_t;
+struct ppc4xx_plb_t {
uint32_t acr;
uint32_t bear;
uint32_t besr;
@@ -109,7 +109,7 @@ struct ppc4xx_plb {
static target_ulong dcr_read_plb (void *opaque, int dcrn)
{
- a_ppc4xx_plb *plb;
+ ppc4xx_plb_t *plb;
target_ulong ret;
plb = opaque;
@@ -134,7 +134,7 @@ static target_ulong dcr_read_plb (void *opaque, int dcrn)
static void dcr_write_plb (void *opaque, int dcrn, target_ulong val)
{
- a_ppc4xx_plb *plb;
+ ppc4xx_plb_t *plb;
plb = opaque;
switch (dcrn) {
@@ -156,7 +156,7 @@ static void dcr_write_plb (void *opaque, int dcrn, target_ulong val)
static void ppc4xx_plb_reset (void *opaque)
{
- a_ppc4xx_plb *plb;
+ ppc4xx_plb_t *plb;
plb = opaque;
plb->acr = 0x00000000;
@@ -166,9 +166,9 @@ static void ppc4xx_plb_reset (void *opaque)
static void ppc4xx_plb_init(CPUState *env)
{
- a_ppc4xx_plb *plb;
+ ppc4xx_plb_t *plb;
- plb = qemu_mallocz(sizeof(a_ppc4xx_plb));
+ plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
@@ -184,15 +184,15 @@ enum {
POB0_BEAR = 0x0A4,
};
-typedef struct ppc4xx_pob a_ppc4xx_pob;
-struct ppc4xx_pob {
+typedef struct ppc4xx_pob_t ppc4xx_pob_t;
+struct ppc4xx_pob_t {
uint32_t bear;
uint32_t besr[2];
};
static target_ulong dcr_read_pob (void *opaque, int dcrn)
{
- a_ppc4xx_pob *pob;
+ ppc4xx_pob_t *pob;
target_ulong ret;
pob = opaque;
@@ -215,7 +215,7 @@ static target_ulong dcr_read_pob (void *opaque, int dcrn)
static void dcr_write_pob (void *opaque, int dcrn, target_ulong val)
{
- a_ppc4xx_pob *pob;
+ ppc4xx_pob_t *pob;
pob = opaque;
switch (dcrn) {
@@ -232,7 +232,7 @@ static void dcr_write_pob (void *opaque, int dcrn, target_ulong val)
static void ppc4xx_pob_reset (void *opaque)
{
- a_ppc4xx_pob *pob;
+ ppc4xx_pob_t *pob;
pob = opaque;
/* No error */
@@ -243,9 +243,9 @@ static void ppc4xx_pob_reset (void *opaque)
static void ppc4xx_pob_init(CPUState *env)
{
- a_ppc4xx_pob *pob;
+ ppc4xx_pob_t *pob;
- pob = qemu_mallocz(sizeof(a_ppc4xx_pob));
+ pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
@@ -255,15 +255,15 @@ static void ppc4xx_pob_init(CPUState *env)
/*****************************************************************************/
/* OPB arbitrer */
-typedef struct ppc4xx_opba a_ppc4xx_opba;
-struct ppc4xx_opba {
+typedef struct ppc4xx_opba_t ppc4xx_opba_t;
+struct ppc4xx_opba_t {
uint8_t cr;
uint8_t pr;
};
-static uint32_t opba_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
{
- a_ppc4xx_opba *opba;
+ ppc4xx_opba_t *opba;
uint32_t ret;
#ifdef DEBUG_OPBA
@@ -286,9 +286,9 @@ static uint32_t opba_readb (void *opaque, a_target_phys_addr addr)
}
static void opba_writeb (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
- a_ppc4xx_opba *opba;
+ ppc4xx_opba_t *opba;
#ifdef DEBUG_OPBA
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -307,7 +307,7 @@ static void opba_writeb (void *opaque,
}
}
-static uint32_t opba_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
{
uint32_t ret;
@@ -321,7 +321,7 @@ static uint32_t opba_readw (void *opaque, a_target_phys_addr addr)
}
static void opba_writew (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_OPBA
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -331,7 +331,7 @@ static void opba_writew (void *opaque,
opba_writeb(opaque, addr + 1, value);
}
-static uint32_t opba_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t ret;
@@ -345,7 +345,7 @@ static uint32_t opba_readl (void *opaque, a_target_phys_addr addr)
}
static void opba_writel (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_OPBA
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -369,19 +369,19 @@ static CPUWriteMemoryFunc * const opba_write[] = {
static void ppc4xx_opba_reset (void *opaque)
{
- a_ppc4xx_opba *opba;
+ ppc4xx_opba_t *opba;
opba = opaque;
opba->cr = 0x00; /* No dynamic priorities - park disabled */
opba->pr = 0x11;
}
-static void ppc4xx_opba_init(a_target_phys_addr base)
+static void ppc4xx_opba_init(target_phys_addr_t base)
{
- a_ppc4xx_opba *opba;
+ ppc4xx_opba_t *opba;
int io;
- opba = qemu_mallocz(sizeof(a_ppc4xx_opba));
+ opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
#ifdef DEBUG_OPBA
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
@@ -397,8 +397,8 @@ static void ppc4xx_opba_init(a_target_phys_addr base)
/*****************************************************************************/
/* Peripheral controller */
-typedef struct ppc4xx_ebc a_ppc4xx_ebc;
-struct ppc4xx_ebc {
+typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
+struct ppc4xx_ebc_t {
uint32_t addr;
uint32_t bcr[8];
uint32_t bap[8];
@@ -415,7 +415,7 @@ enum {
static target_ulong dcr_read_ebc (void *opaque, int dcrn)
{
- a_ppc4xx_ebc *ebc;
+ ppc4xx_ebc_t *ebc;
target_ulong ret;
ebc = opaque;
@@ -499,7 +499,7 @@ static target_ulong dcr_read_ebc (void *opaque, int dcrn)
static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val)
{
- a_ppc4xx_ebc *ebc;
+ ppc4xx_ebc_t *ebc;
ebc = opaque;
switch (dcrn) {
@@ -559,7 +559,7 @@ static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val)
static void ebc_reset (void *opaque)
{
- a_ppc4xx_ebc *ebc;
+ ppc4xx_ebc_t *ebc;
int i;
ebc = opaque;
@@ -577,9 +577,9 @@ static void ebc_reset (void *opaque)
static void ppc405_ebc_init(CPUState *env)
{
- a_ppc4xx_ebc *ebc;
+ ppc4xx_ebc_t *ebc;
- ebc = qemu_mallocz(sizeof(a_ppc4xx_ebc));
+ ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
ebc_reset(ebc);
qemu_register_reset(&ebc_reset, ebc);
ppc_dcr_register(env, EBC0_CFGADDR,
@@ -617,8 +617,8 @@ enum {
DMA0_POL = 0x126,
};
-typedef struct ppc405_dma a_ppc405_dma;
-struct ppc405_dma {
+typedef struct ppc405_dma_t ppc405_dma_t;
+struct ppc405_dma_t {
qemu_irq irqs[4];
uint32_t cr[4];
uint32_t ct[4];
@@ -633,7 +633,7 @@ struct ppc405_dma {
static target_ulong dcr_read_dma (void *opaque, int dcrn)
{
- a_ppc405_dma *dma;
+ ppc405_dma_t *dma;
dma = opaque;
@@ -642,14 +642,14 @@ static target_ulong dcr_read_dma (void *opaque, int dcrn)
static void dcr_write_dma (void *opaque, int dcrn, target_ulong val)
{
- a_ppc405_dma *dma;
+ ppc405_dma_t *dma;
dma = opaque;
}
static void ppc405_dma_reset (void *opaque)
{
- a_ppc405_dma *dma;
+ ppc405_dma_t *dma;
int i;
dma = opaque;
@@ -668,9 +668,9 @@ static void ppc405_dma_reset (void *opaque)
static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
{
- a_ppc405_dma *dma;
+ ppc405_dma_t *dma;
- dma = qemu_mallocz(sizeof(a_ppc405_dma));
+ dma = qemu_mallocz(sizeof(ppc405_dma_t));
memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
ppc405_dma_reset(dma);
qemu_register_reset(&ppc405_dma_reset, dma);
@@ -726,8 +726,8 @@ static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
/*****************************************************************************/
/* GPIO */
-typedef struct ppc405_gpio a_ppc405_gpio;
-struct ppc405_gpio {
+typedef struct ppc405_gpio_t ppc405_gpio_t;
+struct ppc405_gpio_t {
uint32_t or;
uint32_t tcr;
uint32_t osrh;
@@ -741,9 +741,9 @@ struct ppc405_gpio {
uint32_t isr1l;
};
-static uint32_t ppc405_gpio_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
{
- a_ppc405_gpio *gpio;
+ ppc405_gpio_t *gpio;
gpio = opaque;
#ifdef DEBUG_GPIO
@@ -754,9 +754,9 @@ static uint32_t ppc405_gpio_readb (void *opaque, a_target_phys_addr addr)
}
static void ppc405_gpio_writeb (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
- a_ppc405_gpio *gpio;
+ ppc405_gpio_t *gpio;
gpio = opaque;
#ifdef DEBUG_GPIO
@@ -765,9 +765,9 @@ static void ppc405_gpio_writeb (void *opaque,
#endif
}
-static uint32_t ppc405_gpio_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
{
- a_ppc405_gpio *gpio;
+ ppc405_gpio_t *gpio;
gpio = opaque;
#ifdef DEBUG_GPIO
@@ -778,9 +778,9 @@ static uint32_t ppc405_gpio_readw (void *opaque, a_target_phys_addr addr)
}
static void ppc405_gpio_writew (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
- a_ppc405_gpio *gpio;
+ ppc405_gpio_t *gpio;
gpio = opaque;
#ifdef DEBUG_GPIO
@@ -789,9 +789,9 @@ static void ppc405_gpio_writew (void *opaque,
#endif
}
-static uint32_t ppc405_gpio_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
{
- a_ppc405_gpio *gpio;
+ ppc405_gpio_t *gpio;
gpio = opaque;
#ifdef DEBUG_GPIO
@@ -802,9 +802,9 @@ static uint32_t ppc405_gpio_readl (void *opaque, a_target_phys_addr addr)
}
static void ppc405_gpio_writel (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
- a_ppc405_gpio *gpio;
+ ppc405_gpio_t *gpio;
gpio = opaque;
#ifdef DEBUG_GPIO
@@ -827,17 +827,17 @@ static CPUWriteMemoryFunc * const ppc405_gpio_write[] = {
static void ppc405_gpio_reset (void *opaque)
{
- a_ppc405_gpio *gpio;
+ ppc405_gpio_t *gpio;
gpio = opaque;
}
-static void ppc405_gpio_init(a_target_phys_addr base)
+static void ppc405_gpio_init(target_phys_addr_t base)
{
- a_ppc405_gpio *gpio;
+ ppc405_gpio_t *gpio;
int io;
- gpio = qemu_mallocz(sizeof(a_ppc405_gpio));
+ gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
#ifdef DEBUG_GPIO
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
@@ -856,8 +856,8 @@ enum {
OCM0_DSACNTL = 0x01B,
};
-typedef struct ppc405_ocm a_ppc405_ocm;
-struct ppc405_ocm {
+typedef struct ppc405_ocm_t ppc405_ocm_t;
+struct ppc405_ocm_t {
target_ulong offset;
uint32_t isarc;
uint32_t isacntl;
@@ -865,7 +865,7 @@ struct ppc405_ocm {
uint32_t dsacntl;
};
-static void ocm_update_mappings (a_ppc405_ocm *ocm,
+static void ocm_update_mappings (ppc405_ocm_t *ocm,
uint32_t isarc, uint32_t isacntl,
uint32_t dsarc, uint32_t dsacntl)
{
@@ -922,7 +922,7 @@ static void ocm_update_mappings (a_ppc405_ocm *ocm,
static target_ulong dcr_read_ocm (void *opaque, int dcrn)
{
- a_ppc405_ocm *ocm;
+ ppc405_ocm_t *ocm;
target_ulong ret;
ocm = opaque;
@@ -949,7 +949,7 @@ static target_ulong dcr_read_ocm (void *opaque, int dcrn)
static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val)
{
- a_ppc405_ocm *ocm;
+ ppc405_ocm_t *ocm;
uint32_t isarc, dsarc, isacntl, dsacntl;
ocm = opaque;
@@ -980,7 +980,7 @@ static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val)
static void ocm_reset (void *opaque)
{
- a_ppc405_ocm *ocm;
+ ppc405_ocm_t *ocm;
uint32_t isarc, dsarc, isacntl, dsacntl;
ocm = opaque;
@@ -997,9 +997,9 @@ static void ocm_reset (void *opaque)
static void ppc405_ocm_init(CPUState *env)
{
- a_ppc405_ocm *ocm;
+ ppc405_ocm_t *ocm;
- ocm = qemu_mallocz(sizeof(a_ppc405_ocm));
+ ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
ocm->offset = qemu_ram_alloc(4096);
ocm_reset(ocm);
qemu_register_reset(&ocm_reset, ocm);
@@ -1015,8 +1015,8 @@ static void ppc405_ocm_init(CPUState *env)
/*****************************************************************************/
/* I2C controller */
-typedef struct ppc4xx_i2c a_ppc4xx_i2c;
-struct ppc4xx_i2c {
+typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
+struct ppc4xx_i2c_t {
qemu_irq irq;
uint8_t mdata;
uint8_t lmadr;
@@ -1035,9 +1035,9 @@ struct ppc4xx_i2c {
uint8_t directcntl;
};
-static uint32_t ppc4xx_i2c_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
{
- a_ppc4xx_i2c *i2c;
+ ppc4xx_i2c_t *i2c;
uint32_t ret;
#ifdef DEBUG_I2C
@@ -1103,9 +1103,9 @@ static uint32_t ppc4xx_i2c_readb (void *opaque, a_target_phys_addr addr)
}
static void ppc4xx_i2c_writeb (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
- a_ppc4xx_i2c *i2c;
+ ppc4xx_i2c_t *i2c;
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -1162,7 +1162,7 @@ static void ppc4xx_i2c_writeb (void *opaque,
}
}
-static uint32_t ppc4xx_i2c_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
{
uint32_t ret;
@@ -1176,7 +1176,7 @@ static uint32_t ppc4xx_i2c_readw (void *opaque, a_target_phys_addr addr)
}
static void ppc4xx_i2c_writew (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -1186,7 +1186,7 @@ static void ppc4xx_i2c_writew (void *opaque,
ppc4xx_i2c_writeb(opaque, addr + 1, value);
}
-static uint32_t ppc4xx_i2c_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t ret;
@@ -1202,7 +1202,7 @@ static uint32_t ppc4xx_i2c_readl (void *opaque, a_target_phys_addr addr)
}
static void ppc4xx_i2c_writel (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -1228,7 +1228,7 @@ static CPUWriteMemoryFunc * const i2c_write[] = {
static void ppc4xx_i2c_reset (void *opaque)
{
- a_ppc4xx_i2c *i2c;
+ ppc4xx_i2c_t *i2c;
i2c = opaque;
i2c->mdata = 0x00;
@@ -1242,12 +1242,12 @@ static void ppc4xx_i2c_reset (void *opaque)
i2c->directcntl = 0x0F;
}
-static void ppc405_i2c_init(a_target_phys_addr base, qemu_irq irq)
+static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
{
- a_ppc4xx_i2c *i2c;
+ ppc4xx_i2c_t *i2c;
int io;
- i2c = qemu_mallocz(sizeof(a_ppc4xx_i2c));
+ i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
i2c->irq = irq;
#ifdef DEBUG_I2C
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
@@ -1260,8 +1260,8 @@ static void ppc405_i2c_init(a_target_phys_addr base, qemu_irq irq)
/*****************************************************************************/
/* General purpose timers */
-typedef struct ppc4xx_gpt a_ppc4xx_gpt;
-struct ppc4xx_gpt {
+typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
+struct ppc4xx_gpt_t {
int64_t tb_offset;
uint32_t tb_freq;
struct QEMUTimer *timer;
@@ -1275,7 +1275,7 @@ struct ppc4xx_gpt {
uint32_t mask[5];
};
-static uint32_t ppc4xx_gpt_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_GPT
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -1285,7 +1285,7 @@ static uint32_t ppc4xx_gpt_readb (void *opaque, a_target_phys_addr addr)
}
static void ppc4xx_gpt_writeb (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -1294,7 +1294,7 @@ static void ppc4xx_gpt_writeb (void *opaque,
/* XXX: generate a bus fault */
}
-static uint32_t ppc4xx_gpt_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_GPT
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -1304,7 +1304,7 @@ static uint32_t ppc4xx_gpt_readw (void *opaque, a_target_phys_addr addr)
}
static void ppc4xx_gpt_writew (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -1313,18 +1313,18 @@ static void ppc4xx_gpt_writew (void *opaque,
/* XXX: generate a bus fault */
}
-static int ppc4xx_gpt_compare (a_ppc4xx_gpt *gpt, int n)
+static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
{
/* XXX: TODO */
return 0;
}
-static void ppc4xx_gpt_set_output (a_ppc4xx_gpt *gpt, int n, int level)
+static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
{
/* XXX: TODO */
}
-static void ppc4xx_gpt_set_outputs (a_ppc4xx_gpt *gpt)
+static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
{
uint32_t mask;
int i;
@@ -1345,7 +1345,7 @@ static void ppc4xx_gpt_set_outputs (a_ppc4xx_gpt *gpt)
}
}
-static void ppc4xx_gpt_set_irqs (a_ppc4xx_gpt *gpt)
+static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
{
uint32_t mask;
int i;
@@ -1360,14 +1360,14 @@ static void ppc4xx_gpt_set_irqs (a_ppc4xx_gpt *gpt)
}
}
-static void ppc4xx_gpt_compute_timer (a_ppc4xx_gpt *gpt)
+static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
{
/* XXX: TODO */
}
-static uint32_t ppc4xx_gpt_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
{
- a_ppc4xx_gpt *gpt;
+ ppc4xx_gpt_t *gpt;
uint32_t ret;
int idx;
@@ -1421,9 +1421,9 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, a_target_phys_addr addr)
}
static void ppc4xx_gpt_writel (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
- a_ppc4xx_gpt *gpt;
+ ppc4xx_gpt_t *gpt;
int idx;
#ifdef DEBUG_I2C
@@ -1496,7 +1496,7 @@ static CPUWriteMemoryFunc * const gpt_write[] = {
static void ppc4xx_gpt_cb (void *opaque)
{
- a_ppc4xx_gpt *gpt;
+ ppc4xx_gpt_t *gpt;
gpt = opaque;
ppc4xx_gpt_set_irqs(gpt);
@@ -1506,7 +1506,7 @@ static void ppc4xx_gpt_cb (void *opaque)
static void ppc4xx_gpt_reset (void *opaque)
{
- a_ppc4xx_gpt *gpt;
+ ppc4xx_gpt_t *gpt;
int i;
gpt = opaque;
@@ -1522,13 +1522,13 @@ static void ppc4xx_gpt_reset (void *opaque)
}
}
-static void ppc4xx_gpt_init(a_target_phys_addr base, qemu_irq irqs[5])
+static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
{
- a_ppc4xx_gpt *gpt;
+ ppc4xx_gpt_t *gpt;
int i;
int io;
- gpt = qemu_mallocz(sizeof(a_ppc4xx_gpt));
+ gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
for (i = 0; i < 5; i++) {
gpt->irqs[i] = irqs[i];
}
@@ -1566,8 +1566,8 @@ enum {
MAL0_RCBS1 = 0x1E1,
};
-typedef struct ppc40x_mal a_ppc40x_mal;
-struct ppc40x_mal {
+typedef struct ppc40x_mal_t ppc40x_mal_t;
+struct ppc40x_mal_t {
qemu_irq irqs[4];
uint32_t cfg;
uint32_t esr;
@@ -1589,7 +1589,7 @@ static void ppc40x_mal_reset (void *opaque);
static target_ulong dcr_read_mal (void *opaque, int dcrn)
{
- a_ppc40x_mal *mal;
+ ppc40x_mal_t *mal;
target_ulong ret;
mal = opaque;
@@ -1661,7 +1661,7 @@ static target_ulong dcr_read_mal (void *opaque, int dcrn)
static void dcr_write_mal (void *opaque, int dcrn, target_ulong val)
{
- a_ppc40x_mal *mal;
+ ppc40x_mal_t *mal;
int idx;
mal = opaque;
@@ -1741,7 +1741,7 @@ static void dcr_write_mal (void *opaque, int dcrn, target_ulong val)
static void ppc40x_mal_reset (void *opaque)
{
- a_ppc40x_mal *mal;
+ ppc40x_mal_t *mal;
mal = opaque;
mal->cfg = 0x0007C000;
@@ -1757,10 +1757,10 @@ static void ppc40x_mal_reset (void *opaque)
static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4])
{
- a_ppc40x_mal *mal;
+ ppc40x_mal_t *mal;
int i;
- mal = qemu_mallocz(sizeof(a_ppc40x_mal));
+ mal = qemu_mallocz(sizeof(ppc40x_mal_t));
for (i = 0; i < 4; i++)
mal->irqs[i] = irqs[i];
ppc40x_mal_reset(mal);
@@ -1895,9 +1895,9 @@ enum {
PPC405CR_CLK_NB = 7,
};
-typedef struct ppc405cr_cpc a_ppc405cr_cpc;
-struct ppc405cr_cpc {
- a_clk_setup clk_setup[PPC405CR_CLK_NB];
+typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
+struct ppc405cr_cpc_t {
+ clk_setup_t clk_setup[PPC405CR_CLK_NB];
uint32_t sysclk;
uint32_t psr;
uint32_t cr0;
@@ -1908,7 +1908,7 @@ struct ppc405cr_cpc {
uint32_t fr;
};
-static void ppc405cr_clk_setup (a_ppc405cr_cpc *cpc)
+static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
{
uint64_t VCO_out, PLL_out;
uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
@@ -1963,7 +1963,7 @@ static void ppc405cr_clk_setup (a_ppc405cr_cpc *cpc)
static target_ulong dcr_read_crcpc (void *opaque, int dcrn)
{
- a_ppc405cr_cpc *cpc;
+ ppc405cr_cpc_t *cpc;
target_ulong ret;
cpc = opaque;
@@ -2003,7 +2003,7 @@ static target_ulong dcr_read_crcpc (void *opaque, int dcrn)
static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val)
{
- a_ppc405cr_cpc *cpc;
+ ppc405cr_cpc_t *cpc;
cpc = opaque;
switch (dcrn) {
@@ -2036,7 +2036,7 @@ static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val)
static void ppc405cr_cpc_reset (void *opaque)
{
- a_ppc405cr_cpc *cpc;
+ ppc405cr_cpc_t *cpc;
int D;
cpc = opaque;
@@ -2095,7 +2095,7 @@ static void ppc405cr_cpc_reset (void *opaque)
ppc405cr_clk_setup(cpc);
}
-static void ppc405cr_clk_init (a_ppc405cr_cpc *cpc)
+static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
{
int D;
@@ -2121,14 +2121,14 @@ static void ppc405cr_clk_init (a_ppc405cr_cpc *cpc)
cpc->psr |= D << 17;
}
-static void ppc405cr_cpc_init (CPUState *env, a_clk_setup clk_setup[7],
+static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
uint32_t sysclk)
{
- a_ppc405cr_cpc *cpc;
+ ppc405cr_cpc_t *cpc;
- cpc = qemu_mallocz(sizeof(a_ppc405cr_cpc));
+ cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
memcpy(cpc->clk_setup, clk_setup,
- PPC405CR_CLK_NB * sizeof(a_clk_setup));
+ PPC405CR_CLK_NB * sizeof(clk_setup_t));
cpc->sysclk = sysclk;
cpc->jtagid = 0x42051049;
ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
@@ -2152,12 +2152,12 @@ static void ppc405cr_cpc_init (CPUState *env, a_clk_setup clk_setup[7],
ppc405cr_cpc_reset(cpc);
}
-CPUState *ppc405cr_init (a_target_phys_addr ram_bases[4],
- a_target_phys_addr ram_sizes[4],
+CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
+ target_phys_addr_t ram_sizes[4],
uint32_t sysclk, qemu_irq **picp,
int do_init)
{
- a_clk_setup clk_setup[PPC405CR_CLK_NB];
+ clk_setup_t clk_setup[PPC405CR_CLK_NB];
qemu_irq dma_irqs[4];
CPUState *env;
qemu_irq *pic, *irqs;
@@ -2240,10 +2240,10 @@ enum {
PPC405EP_CLK_NB = 8,
};
-typedef struct ppc405ep_cpc a_ppc405ep_cpc;
-struct ppc405ep_cpc {
+typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
+struct ppc405ep_cpc_t {
uint32_t sysclk;
- a_clk_setup clk_setup[PPC405EP_CLK_NB];
+ clk_setup_t clk_setup[PPC405EP_CLK_NB];
uint32_t boot;
uint32_t epctl;
uint32_t pllmr[2];
@@ -2257,7 +2257,7 @@ struct ppc405ep_cpc {
uint32_t sr;
};
-static void ppc405ep_compute_clocks (a_ppc405ep_cpc *cpc)
+static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
{
uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
uint32_t UART0_clk, UART1_clk;
@@ -2366,7 +2366,7 @@ static void ppc405ep_compute_clocks (a_ppc405ep_cpc *cpc)
static target_ulong dcr_read_epcpc (void *opaque, int dcrn)
{
- a_ppc405ep_cpc *cpc;
+ ppc405ep_cpc_t *cpc;
target_ulong ret;
cpc = opaque;
@@ -2406,7 +2406,7 @@ static target_ulong dcr_read_epcpc (void *opaque, int dcrn)
static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val)
{
- a_ppc405ep_cpc *cpc;
+ ppc405ep_cpc_t *cpc;
cpc = opaque;
switch (dcrn) {
@@ -2443,7 +2443,7 @@ static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val)
static void ppc405ep_cpc_reset (void *opaque)
{
- a_ppc405ep_cpc *cpc = opaque;
+ ppc405ep_cpc_t *cpc = opaque;
cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
cpc->epctl = 0x00000000;
@@ -2459,14 +2459,14 @@ static void ppc405ep_cpc_reset (void *opaque)
}
/* XXX: sysclk should be between 25 and 100 MHz */
-static void ppc405ep_cpc_init (CPUState *env, a_clk_setup clk_setup[8],
+static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
uint32_t sysclk)
{
- a_ppc405ep_cpc *cpc;
+ ppc405ep_cpc_t *cpc;
- cpc = qemu_mallocz(sizeof(a_ppc405ep_cpc));
+ cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
memcpy(cpc->clk_setup, clk_setup,
- PPC405EP_CLK_NB * sizeof(a_clk_setup));
+ PPC405EP_CLK_NB * sizeof(clk_setup_t));
cpc->jtagid = 0x20267049;
cpc->sysclk = sysclk;
ppc405ep_cpc_reset(cpc);
@@ -2497,12 +2497,12 @@ static void ppc405ep_cpc_init (CPUState *env, a_clk_setup clk_setup[8],
#endif
}
-CPUState *ppc405ep_init (a_target_phys_addr ram_bases[2],
- a_target_phys_addr ram_sizes[2],
+CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
+ target_phys_addr_t ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
int do_init)
{
- a_clk_setup clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
+ clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
CPUState *env;
qemu_irq *pic, *irqs;
diff --git a/hw/ppc440.c b/hw/ppc440.c
index 4d728cf39..abe0a560d 100644
--- a/hw/ppc440.c
+++ b/hw/ppc440.c
@@ -34,12 +34,12 @@ static const unsigned int ppc440ep_sdram_bank_sizes[] = {
256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0
};
-CPUState *ppc440ep_init(a_ram_addr *ram_size, PCIBus **pcip,
+CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,
const unsigned int pci_irq_nrs[4], int do_init,
const char *cpu_model)
{
- a_target_phys_addr ram_bases[PPC440EP_SDRAM_NR_BANKS];
- a_target_phys_addr ram_sizes[PPC440EP_SDRAM_NR_BANKS];
+ target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];
+ target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];
CPUState *env;
qemu_irq *pic;
qemu_irq *irqs;
diff --git a/hw/ppc440.h b/hw/ppc440.h
index 0501ee308..a40f9176d 100644
--- a/hw/ppc440.h
+++ b/hw/ppc440.h
@@ -14,7 +14,7 @@
#include "hw.h"
-CPUState *ppc440ep_init(a_ram_addr *ram_size, PCIBus **pcip,
+CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,
const unsigned int pci_irq_nrs[4], int do_init,
const char *cpu_model);
diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c
index 6d5bdd492..8a6b7ced9 100644
--- a/hw/ppc440_bamboo.c
+++ b/hw/ppc440_bamboo.c
@@ -27,10 +27,10 @@
#define BINARY_DEVICE_TREE_FILE "bamboo.dtb"
-static void *bamboo_load_device_tree(a_target_phys_addr addr,
+static void *bamboo_load_device_tree(target_phys_addr_t addr,
uint32_t ramsize,
- a_target_phys_addr initrd_base,
- a_target_phys_addr initrd_size,
+ target_phys_addr_t initrd_base,
+ target_phys_addr_t initrd_size,
const char *kernel_cmdline)
{
void *fdt = NULL;
@@ -83,7 +83,7 @@ out:
return fdt;
}
-static void bamboo_init(a_ram_addr ram_size,
+static void bamboo_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
@@ -95,8 +95,8 @@ static void bamboo_init(a_ram_addr ram_size,
CPUState *env;
uint64_t elf_entry;
uint64_t elf_lowaddr;
- a_target_phys_addr entry = 0;
- a_target_phys_addr loadaddr = 0;
+ target_phys_addr_t entry = 0;
+ target_phys_addr_t loadaddr = 0;
target_long kernel_size = 0;
target_ulong initrd_base = 0;
target_long initrd_size = 0;
diff --git a/hw/ppc4xx.h b/hw/ppc4xx.h
index 34592cf7f..bc4ee019a 100644
--- a/hw/ppc4xx.h
+++ b/hw/ppc4xx.h
@@ -29,7 +29,7 @@
/* PowerPC 4xx core initialization */
CPUState *ppc4xx_init (const char *cpu_model,
- a_clk_setup *cpu_clk, a_clk_setup *tb_clk,
+ clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
uint32_t sysclk);
/* PowerPC 4xx universal interrupt controller */
@@ -41,20 +41,20 @@ enum {
qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
uint32_t dcr_base, int has_ssr, int has_vr);
-a_ram_addr ppc4xx_sdram_adjust(a_ram_addr ram_size, int nr_banks,
- a_target_phys_addr ram_bases[],
- a_target_phys_addr ram_sizes[],
+ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
+ target_phys_addr_t ram_bases[],
+ target_phys_addr_t ram_sizes[],
const unsigned int sdram_bank_sizes[]);
void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
- a_target_phys_addr *ram_bases,
- a_target_phys_addr *ram_sizes,
+ target_phys_addr_t *ram_bases,
+ target_phys_addr_t *ram_sizes,
int do_init);
PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
- a_target_phys_addr config_space,
- a_target_phys_addr int_ack,
- a_target_phys_addr special_cycle,
- a_target_phys_addr registers);
+ target_phys_addr_t config_space,
+ target_phys_addr_t int_ack,
+ target_phys_addr_t special_cycle,
+ target_phys_addr_t registers);
#endif /* !defined(PPC_4XX_H) */
diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c
index 2f84e3cdd..0b1c93b80 100644
--- a/hw/ppc4xx_devs.c
+++ b/hw/ppc4xx_devs.c
@@ -41,7 +41,7 @@
/*****************************************************************************/
/* Generic PowerPC 4xx processor instanciation */
CPUState *ppc4xx_init (const char *cpu_model,
- a_clk_setup *cpu_clk, a_clk_setup *tb_clk,
+ clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
uint32_t sysclk)
{
CPUState *env;
@@ -81,8 +81,8 @@ enum {
};
#define UIC_MAX_IRQ 32
-typedef struct ppcuic a_ppcuic;
-struct ppcuic {
+typedef struct ppcuic_t ppcuic_t;
+struct ppcuic_t {
uint32_t dcr_base;
int use_vectors;
uint32_t level; /* Remembers the state of level-triggered interrupts. */
@@ -96,7 +96,7 @@ struct ppcuic {
qemu_irq *irqs;
};
-static void ppcuic_trigger_irq (a_ppcuic *uic)
+static void ppcuic_trigger_irq (ppcuic_t *uic)
{
uint32_t ir, cr;
int start, end, inc, i;
@@ -149,7 +149,7 @@ static void ppcuic_trigger_irq (a_ppcuic *uic)
static void ppcuic_set_irq (void *opaque, int irq_num, int level)
{
- a_ppcuic *uic;
+ ppcuic_t *uic;
uint32_t mask, sr;
uic = opaque;
@@ -185,7 +185,7 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level)
static target_ulong dcr_read_uic (void *opaque, int dcrn)
{
- a_ppcuic *uic;
+ ppcuic_t *uic;
target_ulong ret;
uic = opaque;
@@ -231,7 +231,7 @@ static target_ulong dcr_read_uic (void *opaque, int dcrn)
static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
{
- a_ppcuic *uic;
+ ppcuic_t *uic;
uic = opaque;
dcrn -= uic->dcr_base;
@@ -274,7 +274,7 @@ static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
static void ppcuic_reset (void *opaque)
{
- a_ppcuic *uic;
+ ppcuic_t *uic;
uic = opaque;
uic->uiccr = 0x00000000;
@@ -291,10 +291,10 @@ static void ppcuic_reset (void *opaque)
qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
uint32_t dcr_base, int has_ssr, int has_vr)
{
- a_ppcuic *uic;
+ ppcuic_t *uic;
int i;
- uic = qemu_mallocz(sizeof(a_ppcuic));
+ uic = qemu_mallocz(sizeof(ppcuic_t));
uic->dcr_base = dcr_base;
uic->irqs = irqs;
if (has_vr)
@@ -311,12 +311,12 @@ qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
/*****************************************************************************/
/* SDRAM controller */
-typedef struct ppc4xx_sdram a_ppc4xx_sdram;
-struct ppc4xx_sdram {
+typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
+struct ppc4xx_sdram_t {
uint32_t addr;
int nbanks;
- a_target_phys_addr ram_bases[4];
- a_target_phys_addr ram_sizes[4];
+ target_phys_addr_t ram_bases[4];
+ target_phys_addr_t ram_sizes[4];
uint32_t besr0;
uint32_t besr1;
uint32_t bear;
@@ -337,11 +337,11 @@ enum {
};
/* XXX: TOFIX: some patches have made this code become inconsistent:
- * there are type inconsistencies, mixing a_target_phys_addr, target_ulong
+ * there are type inconsistencies, mixing target_phys_addr_t, target_ulong
* and uint32_t
*/
-static uint32_t sdram_bcr (a_target_phys_addr ram_base,
- a_target_phys_addr ram_size)
+static uint32_t sdram_bcr (target_phys_addr_t ram_base,
+ target_phys_addr_t ram_size)
{
uint32_t bcr;
@@ -378,7 +378,7 @@ static uint32_t sdram_bcr (a_target_phys_addr ram_base,
return bcr;
}
-static inline a_target_phys_addr sdram_base(uint32_t bcr)
+static inline target_phys_addr_t sdram_base(uint32_t bcr)
{
return bcr & 0xFF800000;
}
@@ -419,7 +419,7 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
}
}
-static void sdram_map_bcr (a_ppc4xx_sdram *sdram)
+static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
{
int i;
@@ -434,7 +434,7 @@ static void sdram_map_bcr (a_ppc4xx_sdram *sdram)
}
}
-static void sdram_unmap_bcr (a_ppc4xx_sdram *sdram)
+static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
{
int i;
@@ -451,7 +451,7 @@ static void sdram_unmap_bcr (a_ppc4xx_sdram *sdram)
static target_ulong dcr_read_sdram (void *opaque, int dcrn)
{
- a_ppc4xx_sdram *sdram;
+ ppc4xx_sdram_t *sdram;
target_ulong ret;
sdram = opaque;
@@ -519,7 +519,7 @@ static target_ulong dcr_read_sdram (void *opaque, int dcrn)
static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
{
- a_ppc4xx_sdram *sdram;
+ ppc4xx_sdram_t *sdram;
sdram = opaque;
switch (dcrn) {
@@ -604,7 +604,7 @@ static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
static void sdram_reset (void *opaque)
{
- a_ppc4xx_sdram *sdram;
+ ppc4xx_sdram_t *sdram;
sdram = opaque;
sdram->addr = 0x00000000;
@@ -624,21 +624,21 @@ static void sdram_reset (void *opaque)
}
void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
- a_target_phys_addr *ram_bases,
- a_target_phys_addr *ram_sizes,
+ target_phys_addr_t *ram_bases,
+ target_phys_addr_t *ram_sizes,
int do_init)
{
- a_ppc4xx_sdram *sdram;
+ ppc4xx_sdram_t *sdram;
- sdram = qemu_mallocz(sizeof(a_ppc4xx_sdram));
+ sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
sdram->irq = irq;
sdram->nbanks = nbanks;
- memset(sdram->ram_bases, 0, 4 * sizeof(a_target_phys_addr));
+ memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
memcpy(sdram->ram_bases, ram_bases,
- nbanks * sizeof(a_target_phys_addr));
- memset(sdram->ram_sizes, 0, 4 * sizeof(a_target_phys_addr));
+ nbanks * sizeof(target_phys_addr_t));
+ memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
memcpy(sdram->ram_sizes, ram_sizes,
- nbanks * sizeof(a_target_phys_addr));
+ nbanks * sizeof(target_phys_addr_t));
sdram_reset(sdram);
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
@@ -656,12 +656,12 @@ void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
* The 4xx SDRAM controller supports a small number of banks, and each bank
* must be one of a small set of sizes. The number of banks and the supported
* sizes varies by SoC. */
-a_ram_addr ppc4xx_sdram_adjust(a_ram_addr ram_size, int nr_banks,
- a_target_phys_addr ram_bases[],
- a_target_phys_addr ram_sizes[],
+ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
+ target_phys_addr_t ram_bases[],
+ target_phys_addr_t ram_sizes[],
const unsigned int sdram_bank_sizes[])
{
- a_ram_addr size_left = ram_size;
+ ram_addr_t size_left = ram_size;
int i;
int j;
diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
index f9386603f..655fe8657 100644
--- a/hw/ppc4xx_pci.c
+++ b/hw/ppc4xx_pci.c
@@ -23,7 +23,7 @@
#include "ppc.h"
#include "ppc4xx.h"
-typedef a_target_phys_addr a_pci_addr;
+typedef target_phys_addr_t pci_addr_t;
#include "pci.h"
#include "pci_host.h"
#include "bswap.h"
@@ -86,7 +86,7 @@ typedef struct PPC4xxPCIState PPC4xxPCIState;
#define PCI_REG_SIZE 0x40
-static uint32_t pci4xx_cfgaddr_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t pci4xx_cfgaddr_readl(void *opaque, target_phys_addr_t addr)
{
PPC4xxPCIState *ppc4xx_pci = opaque;
@@ -99,7 +99,7 @@ static CPUReadMemoryFunc * const pci4xx_cfgaddr_read[] = {
&pci4xx_cfgaddr_readl,
};
-static void pci4xx_cfgaddr_writel(void *opaque, a_target_phys_addr addr,
+static void pci4xx_cfgaddr_writel(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
PPC4xxPCIState *ppc4xx_pci = opaque;
@@ -129,7 +129,7 @@ static CPUWriteMemoryFunc * const pci4xx_cfgdata_write[] = {
&pci_host_data_writel,
};
-static void ppc4xx_pci_reg_write4(void *opaque, a_target_phys_addr offset,
+static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
struct PPC4xxPCIState *pci = opaque;
@@ -201,7 +201,7 @@ static void ppc4xx_pci_reg_write4(void *opaque, a_target_phys_addr offset,
}
}
-static uint32_t ppc4xx_pci_reg_read4(void *opaque, a_target_phys_addr offset)
+static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset)
{
struct PPC4xxPCIState *pci = opaque;
uint32_t value;
@@ -359,10 +359,10 @@ static int ppc4xx_pci_load(QEMUFile *f, void *opaque, int version_id)
/* XXX Interrupt acknowledge cycles not supported. */
PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
- a_target_phys_addr config_space,
- a_target_phys_addr int_ack,
- a_target_phys_addr special_cycle,
- a_target_phys_addr registers)
+ target_phys_addr_t config_space,
+ target_phys_addr_t int_ack,
+ target_phys_addr_t special_cycle,
+ target_phys_addr_t registers)
{
PPC4xxPCIState *controller;
int index;
diff --git a/hw/ppc_mac.h b/hw/ppc_mac.h
index 5b3b7fe4c..a04dffea8 100644
--- a/hw/ppc_mac.h
+++ b/hw/ppc_mac.h
@@ -62,9 +62,9 @@ PCIBus *pci_pmac_init(qemu_irq *pic);
/* Mac NVRAM */
typedef struct MacIONVRAMState MacIONVRAMState;
-MacIONVRAMState *macio_nvram_init (int *mem_index, a_target_phys_addr size,
+MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size,
unsigned int it_shift);
-void macio_nvram_map (void *opaque, a_target_phys_addr mem_base);
+void macio_nvram_map (void *opaque, target_phys_addr_t mem_base);
void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len);
uint32_t macio_nvram_read (void *opaque, uint32_t addr);
void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val);
diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
index 5e18dd28f..6bd5234d8 100644
--- a/hw/ppc_newworld.c
+++ b/hw/ppc_newworld.c
@@ -54,12 +54,12 @@
#endif
/* UniN device */
-static void unin_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
+static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
UNIN_DPRINTF("writel addr " TARGET_FMT_plx " val %x\n", addr, value);
}
-static uint32_t unin_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t unin_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t value;
@@ -88,7 +88,7 @@ static int fw_cfg_boot_set(void *opaque, const char *boot_device)
}
/* PowerPC Mac99 hardware initialisation */
-static void ppc_core99_init (a_ram_addr ram_size,
+static void ppc_core99_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
@@ -100,7 +100,7 @@ static void ppc_core99_init (a_ram_addr ram_size,
qemu_irq *pic, **openpic_irqs;
int unin_memory;
int linux_boot, i;
- a_ram_addr ram_offset, bios_offset, vga_bios_offset;
+ ram_addr_t ram_offset, bios_offset, vga_bios_offset;
uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
PCIBus *pci_bus;
MacIONVRAMState *nvr;
diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c
index df9c006ac..bb8c969ca 100644
--- a/hw/ppc_oldworld.c
+++ b/hw/ppc_oldworld.c
@@ -119,7 +119,7 @@ static int fw_cfg_boot_set(void *opaque, const char *boot_device)
return 0;
}
-static void ppc_heathrow_init (a_ram_addr ram_size,
+static void ppc_heathrow_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
@@ -130,7 +130,7 @@ static void ppc_heathrow_init (a_ram_addr ram_size,
char *filename;
qemu_irq *pic, **heathrow_irqs;
int linux_boot, i;
- a_ram_addr ram_offset, bios_offset, vga_bios_offset;
+ ram_addr_t ram_offset, bios_offset, vga_bios_offset;
uint32_t kernel_base, initrd_base;
int32_t kernel_size, initrd_size;
PCIBus *pci_bus;
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 62025bb1b..0525b1e03 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -112,7 +112,7 @@ static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
/* PCI intack register */
/* Read-only register (?) */
static void _PPC_intack_write (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
#if 0
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
@@ -120,7 +120,7 @@ static void _PPC_intack_write (void *opaque,
#endif
}
-static inline uint32_t _PPC_intack_read(a_target_phys_addr addr)
+static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
{
uint32_t retval = 0;
@@ -134,12 +134,12 @@ static inline uint32_t _PPC_intack_read(a_target_phys_addr addr)
return retval;
}
-static uint32_t PPC_intack_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
{
return _PPC_intack_read(addr);
}
-static uint32_t PPC_intack_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
{
#ifdef TARGET_WORDS_BIGENDIAN
return bswap16(_PPC_intack_read(addr));
@@ -148,7 +148,7 @@ static uint32_t PPC_intack_readw (void *opaque, a_target_phys_addr addr)
#endif
}
-static uint32_t PPC_intack_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
{
#ifdef TARGET_WORDS_BIGENDIAN
return bswap32(_PPC_intack_read(addr));
@@ -197,14 +197,14 @@ static struct {
} XCSR;
static void PPC_XCSR_writeb (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
value);
}
static void PPC_XCSR_writew (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap16(value);
@@ -214,7 +214,7 @@ static void PPC_XCSR_writew (void *opaque,
}
static void PPC_XCSR_writel (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ target_phys_addr_t addr, uint32_t value)
{
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap32(value);
@@ -223,7 +223,7 @@ static void PPC_XCSR_writel (void *opaque,
value);
}
-static uint32_t PPC_XCSR_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
{
uint32_t retval = 0;
@@ -233,7 +233,7 @@ static uint32_t PPC_XCSR_readb (void *opaque, a_target_phys_addr addr)
return retval;
}
-static uint32_t PPC_XCSR_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
{
uint32_t retval = 0;
@@ -246,7 +246,7 @@ static uint32_t PPC_XCSR_readw (void *opaque, a_target_phys_addr addr)
return retval;
}
-static uint32_t PPC_XCSR_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t retval = 0;
@@ -273,25 +273,25 @@ static CPUReadMemoryFunc * const PPC_XCSR_read[] = {
#endif
/* Fake super-io ports for PREP platform (Intel 82378ZB) */
-typedef struct sysctrl {
+typedef struct sysctrl_t {
qemu_irq reset_irq;
- a_m48t59 *nvram;
+ m48t59_t *nvram;
uint8_t state;
uint8_t syscontrol;
uint8_t fake_io[2];
int contiguous_map;
int endian;
-} a_sysctrl;
+} sysctrl_t;
enum {
STATE_HARDFILE = 0x01,
};
-static a_sysctrl *sysctrl;
+static sysctrl_t *sysctrl;
static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
{
- a_sysctrl *sysctrl = opaque;
+ sysctrl_t *sysctrl = opaque;
PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
val);
@@ -300,7 +300,7 @@ static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
static uint32_t PREP_io_read (void *opaque, uint32_t addr)
{
- a_sysctrl *sysctrl = opaque;
+ sysctrl_t *sysctrl = opaque;
PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
sysctrl->fake_io[addr - 0x0398]);
@@ -309,7 +309,7 @@ static uint32_t PREP_io_read (void *opaque, uint32_t addr)
static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
{
- a_sysctrl *sysctrl = opaque;
+ sysctrl_t *sysctrl = opaque;
PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
addr - PPC_IO_BASE, val);
@@ -376,7 +376,7 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
{
- a_sysctrl *sysctrl = opaque;
+ sysctrl_t *sysctrl = opaque;
uint32_t retval = 0xFF;
switch (addr) {
@@ -440,8 +440,8 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
return retval;
}
-static inline a_target_phys_addr prep_IO_address(a_sysctrl *sysctrl,
- a_target_phys_addr addr)
+static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
+ target_phys_addr_t addr)
{
if (sysctrl->contiguous_map == 0) {
/* 64 KB contiguous space for IOs */
@@ -454,18 +454,18 @@ static inline a_target_phys_addr prep_IO_address(a_sysctrl *sysctrl,
return addr;
}
-static void PPC_prep_io_writeb (void *opaque, a_target_phys_addr addr,
+static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- a_sysctrl *sysctrl = opaque;
+ sysctrl_t *sysctrl = opaque;
addr = prep_IO_address(sysctrl, addr);
cpu_outb(addr, value);
}
-static uint32_t PPC_prep_io_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
{
- a_sysctrl *sysctrl = opaque;
+ sysctrl_t *sysctrl = opaque;
uint32_t ret;
addr = prep_IO_address(sysctrl, addr);
@@ -474,10 +474,10 @@ static uint32_t PPC_prep_io_readb (void *opaque, a_target_phys_addr addr)
return ret;
}
-static void PPC_prep_io_writew (void *opaque, a_target_phys_addr addr,
+static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- a_sysctrl *sysctrl = opaque;
+ sysctrl_t *sysctrl = opaque;
addr = prep_IO_address(sysctrl, addr);
#ifdef TARGET_WORDS_BIGENDIAN
@@ -487,9 +487,9 @@ static void PPC_prep_io_writew (void *opaque, a_target_phys_addr addr,
cpu_outw(addr, value);
}
-static uint32_t PPC_prep_io_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
{
- a_sysctrl *sysctrl = opaque;
+ sysctrl_t *sysctrl = opaque;
uint32_t ret;
addr = prep_IO_address(sysctrl, addr);
@@ -502,10 +502,10 @@ static uint32_t PPC_prep_io_readw (void *opaque, a_target_phys_addr addr)
return ret;
}
-static void PPC_prep_io_writel (void *opaque, a_target_phys_addr addr,
+static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- a_sysctrl *sysctrl = opaque;
+ sysctrl_t *sysctrl = opaque;
addr = prep_IO_address(sysctrl, addr);
#ifdef TARGET_WORDS_BIGENDIAN
@@ -515,9 +515,9 @@ static void PPC_prep_io_writel (void *opaque, a_target_phys_addr addr,
cpu_outl(addr, value);
}
-static uint32_t PPC_prep_io_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
{
- a_sysctrl *sysctrl = opaque;
+ sysctrl_t *sysctrl = opaque;
uint32_t ret;
addr = prep_IO_address(sysctrl, addr);
@@ -545,7 +545,7 @@ static CPUReadMemoryFunc * const PPC_prep_io_read[] = {
#define NVRAM_SIZE 0x2000
/* PowerPC PREP hardware initialisation */
-static void ppc_prep_init (a_ram_addr ram_size,
+static void ppc_prep_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
@@ -554,11 +554,11 @@ static void ppc_prep_init (a_ram_addr ram_size,
{
CPUState *env = NULL, *envs[MAX_CPUS];
char *filename;
- a_nvram nvram;
- a_m48t59 *m48t59;
+ nvram_t nvram;
+ m48t59_t *m48t59;
int PPC_io_memory;
int linux_boot, i, nb_nics1, bios_size;
- a_ram_addr ram_offset, bios_offset;
+ ram_addr_t ram_offset, bios_offset;
uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
PCIBus *pci_bus;
qemu_irq *i8259;
@@ -567,7 +567,7 @@ static void ppc_prep_init (a_ram_addr ram_size,
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
BlockDriverState *fd[MAX_FD];
- sysctrl = qemu_mallocz(sizeof(a_sysctrl));
+ sysctrl = qemu_mallocz(sizeof(sysctrl_t));
linux_boot = (kernel_filename != NULL);
@@ -606,7 +606,7 @@ static void ppc_prep_init (a_ram_addr ram_size,
bios_size = -1;
}
if (bios_size > 0 && bios_size <= BIOS_SIZE) {
- a_target_phys_addr bios_addr;
+ target_phys_addr_t bios_addr;
bios_size = (bios_size + 0xfff) & ~0xfff;
bios_addr = (uint32_t)(-bios_size);
cpu_register_physical_memory(bios_addr, bios_size,
diff --git a/hw/ppce500.h b/hw/ppce500.h
index a9ed10c40..24d49bb87 100644
--- a/hw/ppce500.h
+++ b/hw/ppce500.h
@@ -17,6 +17,6 @@
#if !defined(PPC_E500_H)
#define PPC_E500_H
-PCIBus *ppce500_pci_init(qemu_irq *pic, a_target_phys_addr registers);
+PCIBus *ppce500_pci_init(qemu_irq *pic, target_phys_addr_t registers);
#endif /* !defined(PPC_E500_H) */
diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index 1429de6eb..504419458 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -72,10 +72,10 @@ out:
}
#endif
-static void *mpc8544_load_device_tree(a_target_phys_addr addr,
+static void *mpc8544_load_device_tree(target_phys_addr_t addr,
uint32_t ramsize,
- a_target_phys_addr initrd_base,
- a_target_phys_addr initrd_size,
+ target_phys_addr_t initrd_base,
+ target_phys_addr_t initrd_size,
const char *kernel_cmdline)
{
void *fdt = NULL;
@@ -151,7 +151,7 @@ out:
return fdt;
}
-static void mpc8544ds_init(a_ram_addr ram_size,
+static void mpc8544ds_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
@@ -162,8 +162,8 @@ static void mpc8544ds_init(a_ram_addr ram_size,
CPUState *env;
uint64_t elf_entry;
uint64_t elf_lowaddr;
- a_target_phys_addr entry=0;
- a_target_phys_addr loadaddr=UIMAGE_LOAD_BASE;
+ target_phys_addr_t entry=0;
+ target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE;
target_long kernel_size=0;
target_ulong dt_base=DTB_LOAD_BASE;
target_ulong initrd_base=INITRD_LOAD_BASE;
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index ae438d872..64fccfdbc 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -17,7 +17,7 @@
#include "hw.h"
#include "ppc.h"
#include "ppce500.h"
-typedef a_target_phys_addr a_pci_addr;
+typedef target_phys_addr_t pci_addr_t;
#include "pci.h"
#include "pci_host.h"
#include "bswap.h"
@@ -85,7 +85,7 @@ struct PPCE500PCIState {
typedef struct PPCE500PCIState PPCE500PCIState;
-static uint32_t pcie500_cfgaddr_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t pcie500_cfgaddr_readl(void *opaque, target_phys_addr_t addr)
{
PPCE500PCIState *pci = opaque;
@@ -100,7 +100,7 @@ static CPUReadMemoryFunc * const pcie500_cfgaddr_read[] = {
&pcie500_cfgaddr_readl,
};
-static void pcie500_cfgaddr_writel(void *opaque, a_target_phys_addr addr,
+static void pcie500_cfgaddr_writel(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
PPCE500PCIState *controller = opaque;
@@ -128,7 +128,7 @@ static CPUWriteMemoryFunc * const pcie500_cfgdata_write[] = {
&pci_host_data_writel,
};
-static uint32_t pci_reg_read4(void *opaque, a_target_phys_addr addr)
+static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr)
{
PPCE500PCIState *pci = opaque;
unsigned long win;
@@ -181,7 +181,7 @@ static CPUReadMemoryFunc * const e500_pci_reg_read[] = {
&pci_reg_read4,
};
-static void pci_reg_write4(void *opaque, a_target_phys_addr addr,
+static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
PPCE500PCIState *pci = opaque;
@@ -313,7 +313,7 @@ static int ppce500_pci_load(QEMUFile *f, void *opaque, int version_id)
return 0;
}
-PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], a_target_phys_addr registers)
+PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
{
PPCE500PCIState *controller;
PCIDevice *d;
diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index cf46a3c61..2d8a0fa95 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -25,7 +25,7 @@
#include "hw.h"
#include "pci.h"
-typedef uint32_t a_pci_addr;
+typedef uint32_t pci_addr_t;
#include "pci_host.h"
typedef PCIHostState PREPPCIState;
@@ -42,7 +42,7 @@ static uint32_t pci_prep_addr_readl(void* opaque, uint32_t addr)
return s->config_reg;
}
-static inline uint32_t PPC_PCIIO_config(a_target_phys_addr addr)
+static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
{
int i;
@@ -53,13 +53,13 @@ static inline uint32_t PPC_PCIIO_config(a_target_phys_addr addr)
return (addr & 0x7ff) | (i << 11);
}
-static void PPC_PCIIO_writeb (void *opaque, a_target_phys_addr addr, uint32_t val)
+static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
{
PREPPCIState *s = opaque;
pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1);
}
-static void PPC_PCIIO_writew (void *opaque, a_target_phys_addr addr, uint32_t val)
+static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
{
PREPPCIState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -68,7 +68,7 @@ static void PPC_PCIIO_writew (void *opaque, a_target_phys_addr addr, uint32_t va
pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
}
-static void PPC_PCIIO_writel (void *opaque, a_target_phys_addr addr, uint32_t val)
+static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
{
PREPPCIState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -77,7 +77,7 @@ static void PPC_PCIIO_writel (void *opaque, a_target_phys_addr addr, uint32_t va
pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
}
-static uint32_t PPC_PCIIO_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
{
PREPPCIState *s = opaque;
uint32_t val;
@@ -85,7 +85,7 @@ static uint32_t PPC_PCIIO_readb (void *opaque, a_target_phys_addr addr)
return val;
}
-static uint32_t PPC_PCIIO_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
{
PREPPCIState *s = opaque;
uint32_t val;
@@ -96,7 +96,7 @@ static uint32_t PPC_PCIIO_readw (void *opaque, a_target_phys_addr addr)
return val;
}
-static uint32_t PPC_PCIIO_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
{
PREPPCIState *s = opaque;
uint32_t val;
diff --git a/hw/pxa.h b/hw/pxa.h
index 013dd2849..2ca36c2f6 100644
--- a/hw/pxa.h
+++ b/hw/pxa.h
@@ -63,15 +63,15 @@
# define PXA2XX_INTERNAL_SIZE 0x40000
/* pxa2xx_pic.c */
-qemu_irq *pxa2xx_pic_init(a_target_phys_addr base, CPUState *env);
+qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
/* pxa2xx_timer.c */
-void pxa25x_timer_init(a_target_phys_addr base, qemu_irq *irqs);
-void pxa27x_timer_init(a_target_phys_addr base, qemu_irq *irqs, qemu_irq irq4);
+void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs);
+void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4);
/* pxa2xx_gpio.c */
typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
-PXA2xxGPIOInfo *pxa2xx_gpio_init(a_target_phys_addr base,
+PXA2xxGPIOInfo *pxa2xx_gpio_init(target_phys_addr_t base,
CPUState *env, qemu_irq *pic, int lines);
qemu_irq *pxa2xx_gpio_in_get(PXA2xxGPIOInfo *s);
void pxa2xx_gpio_out_set(PXA2xxGPIOInfo *s,
@@ -80,29 +80,29 @@ void pxa2xx_gpio_read_notifier(PXA2xxGPIOInfo *s, qemu_irq handler);
/* pxa2xx_dma.c */
typedef struct PXA2xxDMAState PXA2xxDMAState;
-PXA2xxDMAState *pxa255_dma_init(a_target_phys_addr base,
+PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base,
qemu_irq irq);
-PXA2xxDMAState *pxa27x_dma_init(a_target_phys_addr base,
+PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base,
qemu_irq irq);
void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on);
/* pxa2xx_lcd.c */
typedef struct PXA2xxLCDState PXA2xxLCDState;
-PXA2xxLCDState *pxa2xx_lcdc_init(a_target_phys_addr base,
+PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base,
qemu_irq irq);
void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
void pxa2xx_lcdc_oritentation(void *opaque, int angle);
/* pxa2xx_mmci.c */
typedef struct PXA2xxMMCIState PXA2xxMMCIState;
-PXA2xxMMCIState *pxa2xx_mmci_init(a_target_phys_addr base,
+PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
BlockDriverState *bd, qemu_irq irq, void *dma);
void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
qemu_irq coverswitch);
/* pxa2xx_pcmcia.c */
typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
-PXA2xxPCMCIAState *pxa2xx_pcmcia_init(a_target_phys_addr base);
+PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base);
int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
int pxa2xx_pcmcia_dettach(void *opaque);
void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
@@ -113,14 +113,14 @@ struct keymap {
int row;
};
typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
-PXA2xxKeyPadState *pxa27x_keypad_init(a_target_phys_addr base,
+PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
qemu_irq irq);
void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map,
int size);
/* pxa2xx.c */
typedef struct PXA2xxI2CState PXA2xxI2CState;
-PXA2xxI2CState *pxa2xx_i2c_init(a_target_phys_addr base,
+PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
qemu_irq irq, uint32_t page_size);
i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
@@ -143,23 +143,23 @@ typedef struct {
PXA2xxKeyPadState *kp;
/* Power management */
- a_target_phys_addr pm_base;
+ target_phys_addr_t pm_base;
uint32_t pm_regs[0x40];
/* Clock management */
- a_target_phys_addr cm_base;
+ target_phys_addr_t cm_base;
uint32_t cm_regs[4];
uint32_t clkcfg;
/* Memory management */
- a_target_phys_addr mm_base;
+ target_phys_addr_t mm_base;
uint32_t mm_regs[0x1a];
/* Performance monitoring */
uint32_t pmnc;
/* Real-Time clock */
- a_target_phys_addr rtc_base;
+ target_phys_addr_t rtc_base;
uint32_t rttr;
uint32_t rtsr;
uint32_t rtar;
@@ -214,7 +214,7 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision);
PXA2xxState *pxa255_init(unsigned int sdram_size);
/* usb-ohci.c */
-void usb_ohci_init_pxa(a_target_phys_addr base, int num_ports, int devfn,
+void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn,
qemu_irq irq);
#endif /* PXA_H */
diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c
index 3dcd2c88e..e38a12544 100644
--- a/hw/pxa2xx.c
+++ b/hw/pxa2xx.c
@@ -17,7 +17,7 @@
#include "qemu-char.h"
static struct {
- a_target_phys_addr io_base;
+ target_phys_addr_t io_base;
int irqn;
} pxa255_serial[] = {
{ 0x40100000, PXA2XX_PIC_FFUART },
@@ -33,7 +33,7 @@ static struct {
};
typedef struct PXASSPDef {
- a_target_phys_addr io_base;
+ target_phys_addr_t io_base;
int irqn;
} PXASSPDef;
@@ -88,7 +88,7 @@ static PXASSPDef pxa27x_ssp[] = {
#define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
#define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
-static uint32_t pxa2xx_pm_read(void *opaque, a_target_phys_addr addr)
+static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -106,7 +106,7 @@ static uint32_t pxa2xx_pm_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void pxa2xx_pm_write(void *opaque, a_target_phys_addr addr,
+static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -171,7 +171,7 @@ static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id)
#define OSCC 0x08 /* Oscillator Configuration register */
#define CCSR 0x0c /* Core Clock Status register */
-static uint32_t pxa2xx_cm_read(void *opaque, a_target_phys_addr addr)
+static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -191,7 +191,7 @@ static uint32_t pxa2xx_cm_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void pxa2xx_cm_write(void *opaque, a_target_phys_addr addr,
+static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -481,7 +481,7 @@ static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
#define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
#define SA1110 0x64 /* SA-1110 Memory Compatibility register */
-static uint32_t pxa2xx_mm_read(void *opaque, a_target_phys_addr addr)
+static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -497,7 +497,7 @@ static uint32_t pxa2xx_mm_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void pxa2xx_mm_write(void *opaque, a_target_phys_addr addr,
+static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -656,7 +656,7 @@ static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
pxa2xx_ssp_int_update(s);
}
-static uint32_t pxa2xx_ssp_read(void *opaque, a_target_phys_addr addr)
+static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
{
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
uint32_t retval;
@@ -701,7 +701,7 @@ static uint32_t pxa2xx_ssp_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void pxa2xx_ssp_write(void *opaque, a_target_phys_addr addr,
+static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
@@ -1008,7 +1008,7 @@ static inline void pxa2xx_rtc_pi_tick(void *opaque)
pxa2xx_rtc_int_update(s);
}
-static uint32_t pxa2xx_rtc_read(void *opaque, a_target_phys_addr addr)
+static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -1053,7 +1053,7 @@ static uint32_t pxa2xx_rtc_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void pxa2xx_rtc_write(void *opaque, a_target_phys_addr addr,
+static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -1263,7 +1263,7 @@ struct PXA2xxI2CState {
PXA2xxI2CSlaveState *slave;
i2c_bus *bus;
qemu_irq irq;
- a_target_phys_addr offset;
+ target_phys_addr_t offset;
uint16_t control;
uint16_t status;
@@ -1343,7 +1343,7 @@ static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
return 1;
}
-static uint32_t pxa2xx_i2c_read(void *opaque, a_target_phys_addr addr)
+static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
{
PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
@@ -1370,7 +1370,7 @@ static uint32_t pxa2xx_i2c_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void pxa2xx_i2c_write(void *opaque, a_target_phys_addr addr,
+static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
@@ -1495,7 +1495,7 @@ static I2CSlaveInfo pxa2xx_i2c_slave_info = {
.send = pxa2xx_i2c_tx
};
-PXA2xxI2CState *pxa2xx_i2c_init(a_target_phys_addr base,
+PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
qemu_irq irq, uint32_t region_size)
{
int iomemtype;
@@ -1582,7 +1582,7 @@ static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
#define SADIV 0x60 /* Serial Audio Clock Divider register */
#define SADR 0x80 /* Serial Audio Data register */
-static uint32_t pxa2xx_i2s_read(void *opaque, a_target_phys_addr addr)
+static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
{
PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
@@ -1613,7 +1613,7 @@ static uint32_t pxa2xx_i2s_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void pxa2xx_i2s_write(void *opaque, a_target_phys_addr addr,
+static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
@@ -1736,7 +1736,7 @@ static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
pxa2xx_i2s_update(s);
}
-static PXA2xxI2SState *pxa2xx_i2s_init(a_target_phys_addr base,
+static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base,
qemu_irq irq, PXA2xxDMAState *dma)
{
int iomemtype;
@@ -1830,7 +1830,7 @@ static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
#define ICSR1 0x18 /* FICP Status register 1 */
#define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
-static uint32_t pxa2xx_fir_read(void *opaque, a_target_phys_addr addr)
+static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
{
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
uint8_t ret;
@@ -1867,7 +1867,7 @@ static uint32_t pxa2xx_fir_read(void *opaque, a_target_phys_addr addr)
return 0;
}
-static void pxa2xx_fir_write(void *opaque, a_target_phys_addr addr,
+static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
@@ -1994,7 +1994,7 @@ static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
return 0;
}
-static PXA2xxFIrState *pxa2xx_fir_init(a_target_phys_addr base,
+static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
qemu_irq irq, PXA2xxDMAState *dma,
CharDriverState *chr)
{
diff --git a/hw/pxa2xx_dma.c b/hw/pxa2xx_dma.c
index 32b79d750..66c2c30a8 100644
--- a/hw/pxa2xx_dma.c
+++ b/hw/pxa2xx_dma.c
@@ -12,9 +12,9 @@
#include "pxa.h"
typedef struct {
- a_target_phys_addr descr;
- a_target_phys_addr src;
- a_target_phys_addr dest;
+ target_phys_addr_t descr;
+ target_phys_addr_t src;
+ target_phys_addr_t dest;
uint32_t cmd;
uint32_t state;
int request;
@@ -148,7 +148,7 @@ static inline void pxa2xx_dma_descriptor_fetch(
PXA2xxDMAState *s, int ch)
{
uint32_t desc[4];
- a_target_phys_addr daddr = s->chan[ch].descr & ~0xf;
+ target_phys_addr_t daddr = s->chan[ch].descr & ~0xf;
if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST))
daddr += 32;
@@ -252,7 +252,7 @@ static void pxa2xx_dma_run(PXA2xxDMAState *s)
}
}
-static uint32_t pxa2xx_dma_read(void *opaque, a_target_phys_addr offset)
+static uint32_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset)
{
PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
unsigned int channel;
@@ -306,7 +306,7 @@ static uint32_t pxa2xx_dma_read(void *opaque, a_target_phys_addr offset)
}
static void pxa2xx_dma_write(void *opaque,
- a_target_phys_addr offset, uint32_t value)
+ target_phys_addr_t offset, uint32_t value)
{
PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
unsigned int channel;
@@ -404,14 +404,14 @@ static void pxa2xx_dma_write(void *opaque,
}
}
-static uint32_t pxa2xx_dma_readbad(void *opaque, a_target_phys_addr offset)
+static uint32_t pxa2xx_dma_readbad(void *opaque, target_phys_addr_t offset)
{
hw_error("%s: Bad access width\n", __FUNCTION__);
return 5;
}
static void pxa2xx_dma_writebad(void *opaque,
- a_target_phys_addr offset, uint32_t value)
+ target_phys_addr_t offset, uint32_t value)
{
hw_error("%s: Bad access width\n", __FUNCTION__);
}
@@ -483,7 +483,7 @@ static int pxa2xx_dma_load(QEMUFile *f, void *opaque, int version_id)
return 0;
}
-static PXA2xxDMAState *pxa2xx_dma_init(a_target_phys_addr base,
+static PXA2xxDMAState *pxa2xx_dma_init(target_phys_addr_t base,
qemu_irq irq, int channels)
{
int i, iomemtype;
@@ -512,13 +512,13 @@ static PXA2xxDMAState *pxa2xx_dma_init(a_target_phys_addr base,
return s;
}
-PXA2xxDMAState *pxa27x_dma_init(a_target_phys_addr base,
+PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base,
qemu_irq irq)
{
return pxa2xx_dma_init(base, irq, PXA27X_DMA_NUM_CHANNELS);
}
-PXA2xxDMAState *pxa255_dma_init(a_target_phys_addr base,
+PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base,
qemu_irq irq)
{
return pxa2xx_dma_init(base, irq, PXA255_DMA_NUM_CHANNELS);
diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c
index 5718aa104..f354f4bd1 100644
--- a/hw/pxa2xx_gpio.c
+++ b/hw/pxa2xx_gpio.c
@@ -134,7 +134,7 @@ static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
}
}
-static uint32_t pxa2xx_gpio_read(void *opaque, a_target_phys_addr offset)
+static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset)
{
PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
uint32_t ret;
@@ -186,7 +186,7 @@ static uint32_t pxa2xx_gpio_read(void *opaque, a_target_phys_addr offset)
}
static void pxa2xx_gpio_write(void *opaque,
- a_target_phys_addr offset, uint32_t value)
+ target_phys_addr_t offset, uint32_t value)
{
PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
int bank;
@@ -294,7 +294,7 @@ static int pxa2xx_gpio_load(QEMUFile *f, void *opaque, int version_id)
return 0;
}
-PXA2xxGPIOInfo *pxa2xx_gpio_init(a_target_phys_addr base,
+PXA2xxGPIOInfo *pxa2xx_gpio_init(target_phys_addr_t base,
CPUState *env, qemu_irq *pic, int lines)
{
int iomemtype;
diff --git a/hw/pxa2xx_keypad.c b/hw/pxa2xx_keypad.c
index a3481f4c6..060df5844 100644
--- a/hw/pxa2xx_keypad.c
+++ b/hw/pxa2xx_keypad.c
@@ -154,7 +154,7 @@ out:
return;
}
-static uint32_t pxa2xx_keypad_read(void *opaque, a_target_phys_addr offset)
+static uint32_t pxa2xx_keypad_read(void *opaque, target_phys_addr_t offset)
{
PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque;
uint32_t tmp;
@@ -216,7 +216,7 @@ static uint32_t pxa2xx_keypad_read(void *opaque, a_target_phys_addr offset)
}
static void pxa2xx_keypad_write(void *opaque,
- a_target_phys_addr offset, uint32_t value)
+ target_phys_addr_t offset, uint32_t value)
{
PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque;
@@ -304,7 +304,7 @@ static int pxa2xx_keypad_load(QEMUFile *f, void *opaque, int version_id)
return 0;
}
-PXA2xxKeyPadState *pxa27x_keypad_init(a_target_phys_addr base,
+PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
qemu_irq irq)
{
int iomemtype;
diff --git a/hw/pxa2xx_lcd.c b/hw/pxa2xx_lcd.c
index 127d0d72f..930299abd 100644
--- a/hw/pxa2xx_lcd.c
+++ b/hw/pxa2xx_lcd.c
@@ -51,15 +51,15 @@ struct PXA2xxLCDState {
uint8_t bscntr;
struct {
- a_target_phys_addr branch;
+ target_phys_addr_t branch;
int up;
uint8_t palette[1024];
uint8_t pbuffer[1024];
- void (*redraw)(PXA2xxLCDState *s, a_target_phys_addr addr,
+ void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr,
int *miny, int *maxy);
- a_target_phys_addr descriptor;
- a_target_phys_addr source;
+ target_phys_addr_t descriptor;
+ target_phys_addr_t source;
uint32_t id;
uint32_t command;
} dma_ch[7];
@@ -284,7 +284,7 @@ static inline void pxa2xx_dma_rdst_set(PXA2xxLCDState *s)
static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
{
PXAFrameDescriptor desc;
- a_target_phys_addr descptr;
+ target_phys_addr_t descptr;
int i;
for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
@@ -313,7 +313,7 @@ static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
}
}
-static uint32_t pxa2xx_lcdc_read(void *opaque, a_target_phys_addr offset)
+static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset)
{
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
int ch;
@@ -407,7 +407,7 @@ static uint32_t pxa2xx_lcdc_read(void *opaque, a_target_phys_addr offset)
}
static void pxa2xx_lcdc_write(void *opaque,
- a_target_phys_addr offset, uint32_t value)
+ target_phys_addr_t offset, uint32_t value)
{
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
int ch;
@@ -664,7 +664,7 @@ static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
}
static void pxa2xx_lcdc_dma0_redraw_horiz(PXA2xxLCDState *s,
- a_target_phys_addr addr, int *miny, int *maxy)
+ target_phys_addr_t addr, int *miny, int *maxy)
{
int src_width, dest_width;
drawfn fn = NULL;
@@ -691,7 +691,7 @@ static void pxa2xx_lcdc_dma0_redraw_horiz(PXA2xxLCDState *s,
}
static void pxa2xx_lcdc_dma0_redraw_vert(PXA2xxLCDState *s,
- a_target_phys_addr addr, int *miny, int *maxy)
+ target_phys_addr_t addr, int *miny, int *maxy)
{
int src_width, dest_width;
drawfn fn = NULL;
@@ -741,7 +741,7 @@ static void pxa2xx_lcdc_resize(PXA2xxLCDState *s)
static void pxa2xx_update_display(void *opaque)
{
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
- a_target_phys_addr fbptr;
+ target_phys_addr_t fbptr;
int miny, maxy;
int ch;
if (!(s->control[0] & LCCR0_ENB))
@@ -917,7 +917,7 @@ static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id)
#define BITS 32
#include "pxa2xx_template.h"
-PXA2xxLCDState *pxa2xx_lcdc_init(a_target_phys_addr base, qemu_irq irq)
+PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq)
{
int iomemtype;
PXA2xxLCDState *s;
diff --git a/hw/pxa2xx_mmci.c b/hw/pxa2xx_mmci.c
index 33539de31..a415349a7 100644
--- a/hw/pxa2xx_mmci.c
+++ b/hw/pxa2xx_mmci.c
@@ -211,7 +211,7 @@ static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
pxa2xx_mmci_fifo_update(s);
}
-static uint32_t pxa2xx_mmci_read(void *opaque, a_target_phys_addr offset)
+static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
uint32_t ret;
@@ -273,7 +273,7 @@ static uint32_t pxa2xx_mmci_read(void *opaque, a_target_phys_addr offset)
}
static void pxa2xx_mmci_write(void *opaque,
- a_target_phys_addr offset, uint32_t value)
+ target_phys_addr_t offset, uint32_t value)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
@@ -382,21 +382,21 @@ static void pxa2xx_mmci_write(void *opaque,
}
}
-static uint32_t pxa2xx_mmci_readb(void *opaque, a_target_phys_addr offset)
+static uint32_t pxa2xx_mmci_readb(void *opaque, target_phys_addr_t offset)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 1;
return pxa2xx_mmci_read(opaque, offset);
}
-static uint32_t pxa2xx_mmci_readh(void *opaque, a_target_phys_addr offset)
+static uint32_t pxa2xx_mmci_readh(void *opaque, target_phys_addr_t offset)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 2;
return pxa2xx_mmci_read(opaque, offset);
}
-static uint32_t pxa2xx_mmci_readw(void *opaque, a_target_phys_addr offset)
+static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 4;
@@ -410,7 +410,7 @@ static CPUReadMemoryFunc * const pxa2xx_mmci_readfn[] = {
};
static void pxa2xx_mmci_writeb(void *opaque,
- a_target_phys_addr offset, uint32_t value)
+ target_phys_addr_t offset, uint32_t value)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 1;
@@ -418,7 +418,7 @@ static void pxa2xx_mmci_writeb(void *opaque,
}
static void pxa2xx_mmci_writeh(void *opaque,
- a_target_phys_addr offset, uint32_t value)
+ target_phys_addr_t offset, uint32_t value)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 2;
@@ -426,7 +426,7 @@ static void pxa2xx_mmci_writeh(void *opaque,
}
static void pxa2xx_mmci_writew(void *opaque,
- a_target_phys_addr offset, uint32_t value)
+ target_phys_addr_t offset, uint32_t value)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 4;
@@ -517,7 +517,7 @@ static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id)
return 0;
}
-PXA2xxMMCIState *pxa2xx_mmci_init(a_target_phys_addr base,
+PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
BlockDriverState *bd, qemu_irq irq, void *dma)
{
int iomemtype;
diff --git a/hw/pxa2xx_pcmcia.c b/hw/pxa2xx_pcmcia.c
index 5c8a7059b..be1309f62 100644
--- a/hw/pxa2xx_pcmcia.c
+++ b/hw/pxa2xx_pcmcia.c
@@ -20,7 +20,7 @@ struct PXA2xxPCMCIAState {
};
static uint32_t pxa2xx_pcmcia_common_read(void *opaque,
- a_target_phys_addr offset)
+ target_phys_addr_t offset)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -32,7 +32,7 @@ static uint32_t pxa2xx_pcmcia_common_read(void *opaque,
}
static void pxa2xx_pcmcia_common_write(void *opaque,
- a_target_phys_addr offset, uint32_t value)
+ target_phys_addr_t offset, uint32_t value)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -42,7 +42,7 @@ static void pxa2xx_pcmcia_common_write(void *opaque,
}
static uint32_t pxa2xx_pcmcia_attr_read(void *opaque,
- a_target_phys_addr offset)
+ target_phys_addr_t offset)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -54,7 +54,7 @@ static uint32_t pxa2xx_pcmcia_attr_read(void *opaque,
}
static void pxa2xx_pcmcia_attr_write(void *opaque,
- a_target_phys_addr offset, uint32_t value)
+ target_phys_addr_t offset, uint32_t value)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -64,7 +64,7 @@ static void pxa2xx_pcmcia_attr_write(void *opaque,
}
static uint32_t pxa2xx_pcmcia_io_read(void *opaque,
- a_target_phys_addr offset)
+ target_phys_addr_t offset)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -76,7 +76,7 @@ static uint32_t pxa2xx_pcmcia_io_read(void *opaque,
}
static void pxa2xx_pcmcia_io_write(void *opaque,
- a_target_phys_addr offset, uint32_t value)
+ target_phys_addr_t offset, uint32_t value)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -130,7 +130,7 @@ static void pxa2xx_pcmcia_set_irq(void *opaque, int line, int level)
qemu_set_irq(s->irq, level