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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-10-08 13:32:20 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-10-08 13:32:20 +0000 |
| commit | dd43edf4e136bff05cbbb6b42b96c024c591dbb9 (patch) | |
| tree | d1f03b9c92753846ba462c5a1583af5106333d58 /tests/cris/check_movdelsr1.s | |
| parent | 83fa1010ae342c5ad0392182fcdcce438c71b163 (diff) | |
CRIS testsuite, based on the SIM testsuite, by Edgar E. Iglesias.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3365 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'tests/cris/check_movdelsr1.s')
| -rw-r--r-- | tests/cris/check_movdelsr1.s | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/tests/cris/check_movdelsr1.s b/tests/cris/check_movdelsr1.s new file mode 100644 index 000000000..300cc8774 --- /dev/null +++ b/tests/cris/check_movdelsr1.s @@ -0,0 +1,33 @@ +# mach: crisv0 crisv3 crisv8 crisv10 crisv32 +# output: aa117acd\n +# output: eeaabb42\n + +; Bug with move to special register in delay slot, due to +; special flush-insn-cache simulator use. Ordinary move worked; +; special register caused branch to fail. + + .include "testutils.inc" + start + move -1,srp + + move.d 0xaa117acd,r1 + moveq 3,r9 + cmpq 1,r9 + bhi 0f + move.d r1,r3 + + fail +0: + checkr3 aa117acd + + move.d 0xeeaabb42,r1 + moveq 3,r9 + cmpq 1,r9 + bhi 0f + move r1,srp + + fail +0: + move srp,r3 + checkr3 eeaabb42 + quit |