diff options
| author | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-12 23:29:14 +0000 |
|---|---|---|
| committer | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-12 23:29:14 +0000 |
| commit | 65d6c0f33c1a496d2a782bb0ef2ef18d4ed6b763 (patch) | |
| tree | 963351c4967cadac20f88ba9654a2c5c116e0a74 /target-ppc/cpu.h | |
| parent | 4f6cf9e839313f2da5a6690363fbe1756c20c2ca (diff) | |
PowerPC SPE extension fix: must always preserve GPR high bits when
running in 32 bits mode.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3631 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index a463b457c..7589ba215 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -530,7 +530,7 @@ struct CPUPPCState { /* general purpose registers */ ppc_gpr_t gpr[32]; -#if TARGET_GPR_BITS < 64 +#if !defined(TARGET_PPC64) /* Storage for GPR MSB, used by the SPE extension */ ppc_gpr_t gprh[32]; #endif |