diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-01-23 22:45:22 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-01-23 22:45:22 +0000 |
| commit | 9c2149c8e06cf6fbf1bd5096a50486abc3b71f17 (patch) | |
| tree | f2a4e4ad3e436d708dc1038d4ab612ef2f06f9b5 /target-mips/op_helper.c | |
| parent | 17c275d9ceb1921c43a4255adf6bd768c90c9992 (diff) | |
Implementing dmfc/dmtc.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2348 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/op_helper.c')
| -rw-r--r-- | target-mips/op_helper.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 4326b6621..bea5a905e 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -411,10 +411,10 @@ void do_tlbwi (void) that might be a further win. */ mips_tlb_flush_extra (env, MIPS_TLB_NB); - /* Wildly undefined effects for CP0_index containing a too high value and + /* Wildly undefined effects for CP0_Index containing a too high value and MIPS_TLB_NB not being a power of two. But so does real silicon. */ - invalidate_tlb(env, env->CP0_index & (MIPS_TLB_NB - 1), 0); - fill_tlb(env->CP0_index & (MIPS_TLB_NB - 1)); + invalidate_tlb(env, env->CP0_Index & (MIPS_TLB_NB - 1), 0); + fill_tlb(env->CP0_Index & (MIPS_TLB_NB - 1)); } void do_tlbwr (void) @@ -439,7 +439,7 @@ void do_tlbp (void) /* Check ASID, virtual page number & size */ if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { /* TLB match */ - env->CP0_index = i; + env->CP0_Index = i; break; } } @@ -455,7 +455,7 @@ void do_tlbp (void) } } - env->CP0_index |= 0x80000000; + env->CP0_Index |= 0x80000000; } } @@ -465,7 +465,7 @@ void do_tlbr (void) uint8_t ASID; ASID = env->CP0_EntryHi & 0xFF; - tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)]; + tlb = &env->tlb[env->CP0_Index & (MIPS_TLB_NB - 1)]; /* If this will change the current ASID, flush qemu's TLB. */ if (ASID != tlb->ASID) |