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authorEdgar E. Iglesias <edgar.iglesias@gmail.com>2009-11-12 02:12:44 +0100
committerEdgar E. Iglesias <edgar.iglesias@gmail.com>2009-11-12 02:12:44 +0100
commit4898427ec88821ff94571340c397d15e0bddb3e2 (patch)
tree6c66a5db47e36a36ceafc6fbb5219f1bad81a309 /target-microblaze
parentbe0f204aa0d8743f0627cd3cffb0ffc5bbf962e9 (diff)
microblaze: Unbreak reset.
Initialize synthesis config registers at reset to cope with the new cpu_reset sequences. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Diffstat (limited to 'target-microblaze')
-rw-r--r--target-microblaze/translate.c53
1 files changed, 26 insertions, 27 deletions
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index e91ea39dd..44f4db0c6 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1471,33 +1471,6 @@ CPUState *cpu_mb_init (const char *cpu_model)
cpu_exec_init(env);
cpu_reset(env);
- env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
- | PVR0_USE_BARREL_MASK \
- | PVR0_USE_DIV_MASK \
- | PVR0_USE_HW_MUL_MASK \
- | PVR0_USE_EXC_MASK \
- | PVR0_USE_ICACHE_MASK \
- | PVR0_USE_DCACHE_MASK \
- | PVR0_USE_MMU \
- | (0xb << 8);
- env->pvr.regs[2] = PVR2_D_OPB_MASK \
- | PVR2_D_LMB_MASK \
- | PVR2_I_OPB_MASK \
- | PVR2_I_LMB_MASK \
- | PVR2_USE_MSR_INSTR \
- | PVR2_USE_PCMP_INSTR \
- | PVR2_USE_BARREL_MASK \
- | PVR2_USE_DIV_MASK \
- | PVR2_USE_HW_MUL_MASK \
- | PVR2_USE_MUL64_MASK \
- | 0;
- env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
- env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
-#if !defined(CONFIG_USER_ONLY)
- env->mmu.c_mmu = 3;
- env->mmu.c_mmu_tlb_access = 3;
- env->mmu.c_mmu_zones = 16;
-#endif
if (tcg_initialized)
return env;
@@ -1547,12 +1520,38 @@ void cpu_reset (CPUState *env)
memset(env, 0, offsetof(CPUMBState, breakpoints));
tlb_flush(env, 1);
+ env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
+ | PVR0_USE_BARREL_MASK \
+ | PVR0_USE_DIV_MASK \
+ | PVR0_USE_HW_MUL_MASK \
+ | PVR0_USE_EXC_MASK \
+ | PVR0_USE_ICACHE_MASK \
+ | PVR0_USE_DCACHE_MASK \
+ | PVR0_USE_MMU \
+ | (0xb << 8);
+ env->pvr.regs[2] = PVR2_D_OPB_MASK \
+ | PVR2_D_LMB_MASK \
+ | PVR2_I_OPB_MASK \
+ | PVR2_I_LMB_MASK \
+ | PVR2_USE_MSR_INSTR \
+ | PVR2_USE_PCMP_INSTR \
+ | PVR2_USE_BARREL_MASK \
+ | PVR2_USE_DIV_MASK \
+ | PVR2_USE_HW_MUL_MASK \
+ | PVR2_USE_MUL64_MASK \
+ | 0;
+ env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
+ env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
+
env->sregs[SR_MSR] = 0;
#if defined(CONFIG_USER_ONLY)
/* start in user mode with interrupts enabled. */
env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
#else
mmu_init(&env->mmu);
+ env->mmu.c_mmu = 3;
+ env->mmu.c_mmu_tlb_access = 3;
+ env->mmu.c_mmu_zones = 16;
#endif
}