diff options
| author | edgar_igl <edgar_igl@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-02-28 08:28:32 +0000 |
|---|---|---|
| committer | edgar_igl <edgar_igl@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-02-28 08:28:32 +0000 |
| commit | 9004627f9b913085e9a6926d76c065c7372815ab (patch) | |
| tree | 001391668bd20401c8188e0b88db9d72cbe67cf3 /target-cris/translate.c | |
| parent | 8289b279756928f6f029731e2eec119231b9e240 (diff) | |
More consistent naming for CRIS register-number macros.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3996 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-cris/translate.c')
| -rw-r--r-- | target-cris/translate.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/target-cris/translate.c b/target-cris/translate.c index d8cfda555..4150737f8 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -882,7 +882,7 @@ static unsigned int dec_addoq(DisasContext *dc) /* Fetch register operand, */ gen_movl_T0_reg[dc->op2](); gen_op_movl_T1_im(imm); - crisv32_alu_op(dc, CC_OP_ADD, REG_ACR, 4); + crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4); return 2; } static unsigned int dec_addq(DisasContext *dc) @@ -1293,7 +1293,7 @@ static unsigned int dec_addi_acr(DisasContext *dc) dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0); gen_op_lsll_T0_im(dc->zzsize); gen_op_addl_T0_T1(); - gen_movl_reg_T0[REG_ACR](); + gen_movl_reg_T0[R_ACR](); return 2; } @@ -1736,7 +1736,7 @@ static unsigned int dec_addo_m(DisasContext *dc) cris_cc_mask(dc, 0); insn_len = dec_prep_alu_m(dc, 1, memsize); - crisv32_alu_op(dc, CC_OP_ADD, REG_ACR, 4); + crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4); do_postinc(dc, memsize); return insn_len; } @@ -2352,9 +2352,9 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb, if (!dc->flagx_live || (dc->flagx_live && !(dc->cc_op == CC_OP_FLAGS && dc->flags_x))) { - gen_movl_T0_preg[SR_CCS](); + gen_movl_T0_preg[PR_CCS](); gen_op_andl_T0_im(~X_FLAG); - gen_movl_preg_T0[SR_CCS](); + gen_movl_preg_T0[PR_CCS](); dc->flagx_live = 1; dc->flags_x = 0; } @@ -2453,7 +2453,7 @@ void cpu_dump_state (CPUState *env, FILE *f, cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n" "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n" "debug=%x %x %x\n", - env->pc, env->pregs[SR_CCS], env->btaken, env->btarget, + env->pc, env->pregs[PR_CCS], env->btaken, env->btarget, env->cc_op, env->cc_src, env->cc_dest, env->cc_result, env->cc_mask, env->debug1, env->debug2, env->debug3); @@ -2469,7 +2469,7 @@ void cpu_dump_state (CPUState *env, FILE *f, if ((i + 1) % 4 == 0) cpu_fprintf(f, "\n"); } - srs = env->pregs[SR_SRS]; + srs = env->pregs[PR_SRS]; cpu_fprintf(f, "\nsupport function regs bank %d:\n", srs); if (srs < 256) { for (i = 0; i < 16; i++) { |