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authorRichard Henderson <rth@twiddle.net>2009-12-11 09:07:29 -0800
committerAurelien Jarno <aurelien@aurel32.net>2009-12-13 21:26:26 +0100
commit73651cce62738f7f8732028a7b84f3484511eede (patch)
treed17f3b50cfbcfe8dd57b15f77d335bfa23496820 /target-alpha
parent377a43b6fbf0727e812d39b74e468ff0f59cb550 (diff)
target-alpha: Fix fbcond branch offset.
The instructions use a disp21 like all other branch insns, not the disp16 that was being passed. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-alpha')
-rw-r--r--target-alpha/translate.c9
1 files changed, 4 insertions, 5 deletions
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 029bcd998..fbcedde3e 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -314,8 +314,7 @@ static inline void gen_bcond(DisasContext *ctx, TCGCond cond, int ra,
gen_set_label(l2);
}
-static inline void gen_fbcond(DisasContext *ctx, int opc, int ra,
- int32_t disp16)
+static inline void gen_fbcond(DisasContext *ctx, int opc, int ra, int32_t disp)
{
int l1, l2;
TCGv tmp;
@@ -356,7 +355,7 @@ static inline void gen_fbcond(DisasContext *ctx, int opc, int ra,
tcg_gen_movi_i64(cpu_pc, ctx->pc);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2));
+ tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp << 2));
gen_set_label(l2);
}
@@ -2335,7 +2334,7 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn)
case 0x31: /* FBEQ */
case 0x32: /* FBLT */
case 0x33: /* FBLE */
- gen_fbcond(ctx, opc, ra, disp16);
+ gen_fbcond(ctx, opc, ra, disp21);
ret = 1;
break;
case 0x34:
@@ -2348,7 +2347,7 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn)
case 0x35: /* FBNE */
case 0x36: /* FBGE */
case 0x37: /* FBGT */
- gen_fbcond(ctx, opc, ra, disp16);
+ gen_fbcond(ctx, opc, ra, disp21);
ret = 1;
break;
case 0x38: