aboutsummaryrefslogtreecommitdiffstats
path: root/hw
diff options
context:
space:
mode:
authorIsaku Yamahata <yamahata@valinux.co.jp>2010-12-22 15:14:35 +0900
committerMichael S. Tsirkin <mst@redhat.com>2010-12-22 09:01:53 +0200
commit0ead87c8debaf12bf4e8cf5130e4e7fb83dbf126 (patch)
tree851fbd24dd47cfa05405ac732ccb31fcc3384fe7 /hw
parent362dd48c16728a656c1ef75f8160838127fd76d5 (diff)
pcie: add flr support
Support flr: trigger device reset on flr config write. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw')
-rw-r--r--hw/pci.c6
-rw-r--r--hw/pci.h1
-rw-r--r--hw/pcie.c11
-rw-r--r--hw/pcie.h2
-rw-r--r--hw/xio3130_downstream.c2
-rw-r--r--hw/xio3130_upstream.c3
6 files changed, 12 insertions, 13 deletions
diff --git a/hw/pci.c b/hw/pci.c
index 0cb411720..eb21848b0 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -137,7 +137,11 @@ static void pci_update_irq_status(PCIDevice *dev)
}
}
-static void pci_device_reset(PCIDevice *dev)
+/*
+ * This function is called on #RST and FLR.
+ * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
+ */
+void pci_device_reset(PCIDevice *dev)
{
int r;
/* TODO: call the below unconditionally once all pci devices
diff --git a/hw/pci.h b/hw/pci.h
index 17744dc85..6e80b08e0 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -237,6 +237,7 @@ void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
PCIBus *pci_register_bus(DeviceState *parent, const char *name,
pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
void *irq_opaque, int devfn_min, int nirq);
+void pci_device_reset(PCIDevice *dev);
void pci_bus_reset(PCIBus *bus);
void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
diff --git a/hw/pcie.c b/hw/pcie.c
index d1f008655..6a113a932 100644
--- a/hw/pcie.c
+++ b/hw/pcie.c
@@ -380,10 +380,6 @@ void pcie_cap_root_reset(PCIDevice *dev)
pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0);
}
-/*
- * TODO: implement FLR:
- * Right now sets the bit which indicates FLR is supported.
- */
/* function level reset(FLR) */
void pcie_cap_flr_init(PCIDevice *dev)
{
@@ -403,8 +399,11 @@ void pcie_cap_flr_write_config(PCIDevice *dev,
uint32_t addr, uint32_t val, int len)
{
uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
- if (pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR)) {
- /* TODO: implement FLR */
+ if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) {
+ /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler
+ so the handler can detect FLR by looking at this bit. */
+ pci_device_reset(dev);
+ pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR);
}
}
diff --git a/hw/pcie.h b/hw/pcie.h
index 7baa81350..bc909e279 100644
--- a/hw/pcie.h
+++ b/hw/pcie.h
@@ -63,8 +63,6 @@ struct PCIExpressDevice {
/* Offset of express capability in config space */
uint8_t exp_cap;
- /* TODO FLR */
-
/* SLOT */
unsigned int hpev_intx; /* INTx for hot plug event (0-3:INT[A-D]#)
* default is 0 = INTA#
diff --git a/hw/xio3130_downstream.c b/hw/xio3130_downstream.c
index 1a2d258bd..5aa6a6b14 100644
--- a/hw/xio3130_downstream.c
+++ b/hw/xio3130_downstream.c
@@ -89,7 +89,7 @@ static int xio3130_downstream_initfn(PCIDevice *d)
if (rc < 0) {
goto err_msi;
}
- pcie_cap_flr_init(d); /* TODO: implement FLR */
+ pcie_cap_flr_init(d);
pcie_cap_deverr_init(d);
pcie_cap_slot_init(d, s->slot);
pcie_chassis_create(s->chassis);
diff --git a/hw/xio3130_upstream.c b/hw/xio3130_upstream.c
index 387bf6c77..a7640f518 100644
--- a/hw/xio3130_upstream.c
+++ b/hw/xio3130_upstream.c
@@ -85,10 +85,7 @@ static int xio3130_upstream_initfn(PCIDevice *d)
if (rc < 0) {
goto err_msi;
}
-
- /* TODO: implement FLR */
pcie_cap_flr_init(d);
-
pcie_cap_deverr_init(d);
rc = pcie_aer_init(d, XIO3130_AER_OFFSET);
if (rc < 0) {