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authorPeter Maydell <peter.maydell@linaro.org>2012-01-17 10:54:07 +0000
committerPeter Maydell <peter.maydell@linaro.org>2012-01-17 10:54:07 +0000
commit5a15758874cfad886e637e015baa7888a0c60262 (patch)
tree10d55e64394ecb01e19471ef155fefdbe87d6b02 /hw/vexpress.c
parent8c4ec5c0269bda18bb777a64b2008088d1c632dc (diff)
vexpress, realview: Add (dummy) L2 cache controller
Instantiate the L2 cache controller on the ARM devboards which have one, since we have a dummy model of it now. Note that the only non-MP board with an L2x0 is the PB1176, which we don't model. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/vexpress.c')
-rw-r--r--hw/vexpress.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/vexpress.c b/hw/vexpress.c
index 71115564e..64fab4574 100644
--- a/hw/vexpress.c
+++ b/hw/vexpress.c
@@ -182,6 +182,7 @@ static void vexpress_a9_init(ram_addr_t ram_size,
/* 0x100ec000 TrustZone Address Space Controller */
/* 0x10200000 CoreSight debug APB */
/* 0x1e00a000 PL310 L2 Cache Controller */
+ sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
/* CS0: NOR0 flash : 0x40000000 .. 0x44000000 */
/* CS4: NOR1 flash : 0x44000000 .. 0x48000000 */