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authorAvi Kivity <avi@redhat.com>2011-08-15 17:17:25 +0300
committerAnthony Liguori <aliguori@us.ibm.com>2011-08-22 10:22:03 -0500
commitc76f990e8dd90b61dbc83ee0def95c41375b8921 (patch)
tree1588aa01578bcca65cc66529f20d2609634c2731 /hw/pcie_host.c
parent689a1921aef42ef2a3da1ca4a406c473a0531aed (diff)
pcie_host: convert to memory API
Assuming that mmcfg size cannot change at runtime. Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw/pcie_host.c')
-rw-r--r--hw/pcie_host.c98
1 files changed, 25 insertions, 73 deletions
diff --git a/hw/pcie_host.c b/hw/pcie_host.c
index f9fea3d91..28bbe72b3 100644
--- a/hw/pcie_host.c
+++ b/hw/pcie_host.c
@@ -22,6 +22,7 @@
#include "hw.h"
#include "pci.h"
#include "pcie_host.h"
+#include "exec-memory.h"
/*
* PCI express mmcfig address
@@ -52,9 +53,11 @@ static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s,
PCIE_MMCFG_DEVFN(mmcfg_addr));
}
-static void pcie_mmcfg_data_write(PCIBus *s,
- uint32_t mmcfg_addr, uint32_t val, int len)
+static void pcie_mmcfg_data_write(void *opaque, target_phys_addr_t mmcfg_addr,
+ uint64_t val, unsigned len)
{
+ PCIExpressHost *e = opaque;
+ PCIBus *s = e->pci.bus;
PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
uint32_t addr;
uint32_t limit;
@@ -72,8 +75,12 @@ static void pcie_mmcfg_data_write(PCIBus *s,
pci_host_config_write_common(pci_dev, addr, limit, val, len);
}
-static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t mmcfg_addr, int len)
+static uint64_t pcie_mmcfg_data_read(void *opaque,
+ target_phys_addr_t mmcfg_addr,
+ unsigned len)
{
+ PCIExpressHost *e = opaque;
+ PCIBus *s = e->pci.bus;
PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
uint32_t addr;
uint32_t limit;
@@ -91,72 +98,23 @@ static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t mmcfg_addr, int len)
return pci_host_config_read_common(pci_dev, addr, limit, len);
}
-static void pcie_mmcfg_data_writeb(void *opaque,
- target_phys_addr_t addr, uint32_t value)
-{
- PCIExpressHost *e = opaque;
- pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 1);
-}
-
-static void pcie_mmcfg_data_writew(void *opaque,
- target_phys_addr_t addr, uint32_t value)
-{
- PCIExpressHost *e = opaque;
- pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 2);
-}
-
-static void pcie_mmcfg_data_writel(void *opaque,
- target_phys_addr_t addr, uint32_t value)
-{
- PCIExpressHost *e = opaque;
- pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 4);
-}
-
-static uint32_t pcie_mmcfg_data_readb(void *opaque, target_phys_addr_t addr)
-{
- PCIExpressHost *e = opaque;
- return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 1);
-}
-
-static uint32_t pcie_mmcfg_data_readw(void *opaque, target_phys_addr_t addr)
-{
- PCIExpressHost *e = opaque;
- return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 2);
-}
-
-static uint32_t pcie_mmcfg_data_readl(void *opaque, target_phys_addr_t addr)
-{
- PCIExpressHost *e = opaque;
- return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 4);
-}
-
-
-static CPUWriteMemoryFunc * const pcie_mmcfg_write[] =
-{
- pcie_mmcfg_data_writeb,
- pcie_mmcfg_data_writew,
- pcie_mmcfg_data_writel,
-};
-
-static CPUReadMemoryFunc * const pcie_mmcfg_read[] =
-{
- pcie_mmcfg_data_readb,
- pcie_mmcfg_data_readw,
- pcie_mmcfg_data_readl,
+static const MemoryRegionOps pcie_mmcfg_ops = {
+ .read = pcie_mmcfg_data_read,
+ .write = pcie_mmcfg_data_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
#define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL)
-int pcie_host_init(PCIExpressHost *e)
+int pcie_host_init(PCIExpressHost *e, uint32_t size)
{
+ assert(!(size & (size - 1))); /* power of 2 */
+ assert(size >= PCIE_MMCFG_SIZE_MIN);
+ assert(size <= PCIE_MMCFG_SIZE_MAX);
e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
- e->mmio_index =
- cpu_register_io_memory(pcie_mmcfg_read, pcie_mmcfg_write, e,
- DEVICE_NATIVE_ENDIAN);
- if (e->mmio_index < 0) {
- return -1;
- }
+ e->size = size;
+ memory_region_init_io(&e->mmio, &pcie_mmcfg_ops, e, "pcie-mmcfg", e->size);
return 0;
}
@@ -164,29 +122,23 @@ int pcie_host_init(PCIExpressHost *e)
void pcie_host_mmcfg_unmap(PCIExpressHost *e)
{
if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) {
- cpu_register_physical_memory(e->base_addr, e->size, IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(), &e->mmio);
e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
}
}
-void pcie_host_mmcfg_map(PCIExpressHost *e,
- target_phys_addr_t addr, uint32_t size)
+void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr)
{
- assert(!(size & (size - 1))); /* power of 2 */
- assert(size >= PCIE_MMCFG_SIZE_MIN);
- assert(size <= PCIE_MMCFG_SIZE_MAX);
-
e->base_addr = addr;
- e->size = size;
- cpu_register_physical_memory(e->base_addr, e->size, e->mmio_index);
+ memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio);
}
void pcie_host_mmcfg_update(PCIExpressHost *e,
int enable,
- target_phys_addr_t addr, uint32_t size)
+ target_phys_addr_t addr)
{
pcie_host_mmcfg_unmap(e);
if (enable) {
- pcie_host_mmcfg_map(e, addr, size);
+ pcie_host_mmcfg_map(e, addr);
}
}