diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2011-09-17 19:51:48 +0100 |
|---|---|---|
| committer | Andrzej Zaborowski <andrew.zaborowski@intel.com> | 2011-09-23 08:36:36 +0200 |
| commit | 7196345549474719eb85c675174ce3717adf771b (patch) | |
| tree | be51621cca94f50c6a04276ea54724c7fa49a2a2 /hw/omap_gpmc.c | |
| parent | d85a1302a91912c52cdc3fe459b313848a8a0792 (diff) | |
hw/omap_gpmc: Add comment about FIFOTHRESHOLDSTATUS bit
Promote the remark about why we handle FIFOTHRESHOLDSTATUS the
way we do from the commit message of de8af7fe0 to a comment in
the code.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
Diffstat (limited to 'hw/omap_gpmc.c')
| -rw-r--r-- | hw/omap_gpmc.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/hw/omap_gpmc.c b/hw/omap_gpmc.c index 02f0c5210..e27b93c9b 100644 --- a/hw/omap_gpmc.c +++ b/hw/omap_gpmc.c @@ -569,6 +569,13 @@ static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr, case 0x1ec: /* GPMC_PREFETCH_CONTROL */ return s->prefetch.startengine; case 0x1f0: /* GPMC_PREFETCH_STATUS */ + /* NB: The OMAP3 TRM is inconsistent about whether the GPMC + * FIFOTHRESHOLDSTATUS bit should be set when + * FIFOPOINTER > FIFOTHRESHOLD or when it is >= FIFOTHRESHOLD. + * Apparently the underlying functional spec from which the TRM was + * created states that the behaviour is ">=", and this also + * makes more conceptual sense. + */ return (s->prefetch.fifopointer << 24) | ((s->prefetch.fifopointer >= ((s->prefetch.config1 >> 8) & 0x7f) ? 1 : 0) << 16) | |