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authorBlue Swirl <blauwirbel@gmail.com>2009-07-31 07:26:44 +0000
committerBlue Swirl <blauwirbel@gmail.com>2009-07-31 07:26:44 +0000
commit2814df28efc184dd327e15a2bb75119c1ef19564 (patch)
tree380ec38ca28e01bedb5235fbc68d707000cbf218 /hw/esp.c
parent14ed7adc1b14597741ac6f9bb64ca23ac26b3f2a (diff)
esp: fix interrupt register read
Read of interrupt register should clear it and also sequence step and status. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'hw/esp.c')
-rw-r--r--hw/esp.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/hw/esp.c b/hw/esp.c
index 9eacccbf8..cb6c993c8 100644
--- a/hw/esp.c
+++ b/hw/esp.c
@@ -422,7 +422,7 @@ static void parent_esp_reset(void *opaque, int irq, int level)
static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
{
ESPState *s = opaque;
- uint32_t saddr;
+ uint32_t saddr, old_val;
saddr = addr >> s->it_shift;
DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
@@ -445,10 +445,15 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
}
break;
case ESP_RINTR:
- // Clear interrupt/error status bits
- s->rregs[ESP_RSTAT] &= ~(STAT_GE | STAT_PE);
+ /* Clear sequence step, interrupt register and all status bits
+ except TC */
+ old_val = s->rregs[ESP_RINTR];
+ s->rregs[ESP_RINTR] = 0;
+ s->rregs[ESP_RSTAT] &= ~STAT_TC;
+ s->rregs[ESP_RSEQ] = SEQ_CD;
esp_lower_irq(s);
- break;
+
+ return old_val;
default:
break;
}