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authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2009-04-08 22:56:26 +0000
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2009-04-08 22:56:26 +0000
commit2c7c13d4b81d59dfe50ce4ae9afe1a34f2d573cf (patch)
tree24561f5158f97215c1576e6b3aa2fddaadeb9033 /hw/apic.c
parentb7df4bcc00725d293cc73dba0ded23106b448720 (diff)
apic: Fix access to non-existent APIC
When running with -M isapc, there is no env->apic_state. Fix cpu_get/set_apic_* helpers to handle this corner case gracefully. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7048 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/apic.c')
-rw-r--r--hw/apic.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/hw/apic.c b/hw/apic.c
index 5a7649872..d63d74b82 100644
--- a/hw/apic.c
+++ b/hw/apic.c
@@ -280,6 +280,8 @@ void cpu_set_apic_base(CPUState *env, uint64_t val)
#ifdef DEBUG_APIC
printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
#endif
+ if (!s)
+ return;
s->apicbase = (val & 0xfffff000) |
(s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
/* if disabled, cannot be enabled again */
@@ -294,14 +296,17 @@ uint64_t cpu_get_apic_base(CPUState *env)
{
APICState *s = env->apic_state;
#ifdef DEBUG_APIC
- printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase);
+ printf("cpu_get_apic_base: %016" PRIx64 "\n",
+ s ? (uint64_t)s->apicbase: 0);
#endif
- return s->apicbase;
+ return s ? s->apicbase : 0;
}
void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
{
APICState *s = env->apic_state;
+ if (!s)
+ return;
s->tpr = (val & 0x0f) << 4;
apic_update_irq(s);
}
@@ -309,7 +314,7 @@ void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
uint8_t cpu_get_apic_tpr(CPUX86State *env)
{
APICState *s = env->apic_state;
- return s->tpr >> 4;
+ return s ? s->tpr >> 4 : 0;
}
/* return -1 if no bit is set */