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authorMichael Walle <michael@walle.cc>2011-03-07 23:32:33 +0100
committerEdgar E. Iglesias <edgar.iglesias@gmail.com>2011-04-04 10:26:53 +0200
commite4dc6d2cdca3e64fe09d3c76a56294b7b7aa7d7f (patch)
tree9e68c3ed19318b60bd0574d47a5d51e2ea2c28f9
parent25a8bb96f4a9dcb27dc55027b81d9646273a937b (diff)
lm32: add Milkymist HPDMC support
This patch adds support for the Milkymist's High Performance Dynamic Memory Controller. This is just a dumb model without any functionality. While the real hardware acts for example as a bridge between software and hardware for sending SDRAM commans, this model will only eat up these commands and always returns the expected hardware states, eg. PLL locked etc. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
-rw-r--r--Makefile.target1
-rw-r--r--hw/milkymist-hpdmc.c161
-rw-r--r--trace-events4
3 files changed, 166 insertions, 0 deletions
diff --git a/Makefile.target b/Makefile.target
index 0610bb8c8..0e4f69379 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -268,6 +268,7 @@ obj-lm32-y += lm32_timer.o
obj-lm32-y += lm32_uart.o
obj-lm32-y += lm32_sys.o
obj-lm32-y += milkymist-ac97.o
+obj-lm32-y += milkymist-hpdmc.o
obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o
obj-mips-y += mips_addr.o mips_timer.o mips_int.o
diff --git a/hw/milkymist-hpdmc.c b/hw/milkymist-hpdmc.c
new file mode 100644
index 000000000..c0962fb52
--- /dev/null
+++ b/hw/milkymist-hpdmc.c
@@ -0,0 +1,161 @@
+/*
+ * QEMU model of the Milkymist High Performance Dynamic Memory Controller.
+ *
+ * Copyright (c) 2010 Michael Walle <michael@walle.cc>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ *
+ *
+ * Specification available at:
+ * http://www.milkymist.org/socdoc/hpdmc.pdf
+ */
+
+#include "hw.h"
+#include "sysbus.h"
+#include "trace.h"
+#include "qemu-error.h"
+
+enum {
+ R_SYSTEM = 0,
+ R_BYPASS,
+ R_TIMING,
+ R_IODELAY,
+ R_MAX
+};
+
+enum {
+ IODELAY_DQSDELAY_RDY = (1<<5),
+ IODELAY_PLL1_LOCKED = (1<<6),
+ IODELAY_PLL2_LOCKED = (1<<7),
+};
+
+struct MilkymistHpdmcState {
+ SysBusDevice busdev;
+
+ uint32_t regs[R_MAX];
+};
+typedef struct MilkymistHpdmcState MilkymistHpdmcState;
+
+static uint32_t hpdmc_read(void *opaque, target_phys_addr_t addr)
+{
+ MilkymistHpdmcState *s = opaque;
+ uint32_t r = 0;
+
+ addr >>= 2;
+ switch (addr) {
+ case R_SYSTEM:
+ case R_BYPASS:
+ case R_TIMING:
+ case R_IODELAY:
+ r = s->regs[addr];
+ break;
+
+ default:
+ error_report("milkymist_hpdmc: read access to unknown register 0x"
+ TARGET_FMT_plx, addr << 2);
+ break;
+ }
+
+ trace_milkymist_hpdmc_memory_read(addr << 2, r);
+
+ return r;
+}
+
+static void hpdmc_write(void *opaque, target_phys_addr_t addr, uint32_t value)
+{
+ MilkymistHpdmcState *s = opaque;
+
+ trace_milkymist_hpdmc_memory_write(addr, value);
+
+ addr >>= 2;
+ switch (addr) {
+ case R_SYSTEM:
+ case R_BYPASS:
+ case R_TIMING:
+ s->regs[addr] = value;
+ break;
+ case R_IODELAY:
+ /* ignore writes */
+ break;
+
+ default:
+ error_report("milkymist_hpdmc: write access to unknown register 0x"
+ TARGET_FMT_plx, addr << 2);
+ break;
+ }
+}
+
+static CPUReadMemoryFunc * const hpdmc_read_fn[] = {
+ NULL,
+ NULL,
+ &hpdmc_read,
+};
+
+static CPUWriteMemoryFunc * const hpdmc_write_fn[] = {
+ NULL,
+ NULL,
+ &hpdmc_write,
+};
+
+static void milkymist_hpdmc_reset(DeviceState *d)
+{
+ MilkymistHpdmcState *s = container_of(d, MilkymistHpdmcState, busdev.qdev);
+ int i;
+
+ for (i = 0; i < R_MAX; i++) {
+ s->regs[i] = 0;
+ }
+
+ /* defaults */
+ s->regs[R_IODELAY] = IODELAY_DQSDELAY_RDY | IODELAY_PLL1_LOCKED
+ | IODELAY_PLL2_LOCKED;
+}
+
+static int milkymist_hpdmc_init(SysBusDevice *dev)
+{
+ MilkymistHpdmcState *s = FROM_SYSBUS(typeof(*s), dev);
+ int hpdmc_regs;
+
+ hpdmc_regs = cpu_register_io_memory(hpdmc_read_fn, hpdmc_write_fn, s,
+ DEVICE_NATIVE_ENDIAN);
+ sysbus_init_mmio(dev, R_MAX * 4, hpdmc_regs);
+
+ return 0;
+}
+
+static const VMStateDescription vmstate_milkymist_hpdmc = {
+ .name = "milkymist-hpdmc",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, MilkymistHpdmcState, R_MAX),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static SysBusDeviceInfo milkymist_hpdmc_info = {
+ .init = milkymist_hpdmc_init,
+ .qdev.name = "milkymist-hpdmc",
+ .qdev.size = sizeof(MilkymistHpdmcState),
+ .qdev.vmsd = &vmstate_milkymist_hpdmc,
+ .qdev.reset = milkymist_hpdmc_reset,
+};
+
+static void milkymist_hpdmc_register(void)
+{
+ sysbus_register_withprop(&milkymist_hpdmc_info);
+}
+
+device_init(milkymist_hpdmc_register)
diff --git a/trace-events b/trace-events
index fc8caa8e5..9ccf82c9d 100644
--- a/trace-events
+++ b/trace-events
@@ -298,3 +298,7 @@ disable milkymist_ac97_in_cb(int avail, uint32_t remaining) "avail %d remaining
disable milkymist_ac97_in_cb_transferred(int transferred) "transferred %d"
disable milkymist_ac97_out_cb(int free, uint32_t remaining) "free %d remaining %u"
disable milkymist_ac97_out_cb_transferred(int transferred) "transferred %d"
+
+# hw/milkymist-hpdmc.c
+disable milkymist_hpdmc_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
+disable milkymist_hpdmc_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"