diff options
| author | Alexander Graf <agraf@suse.de> | 2010-12-08 12:05:37 +0100 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2010-12-11 15:24:25 +0000 |
| commit | 2507c12ab026b2286b0a47035c629f3d568c96f4 (patch) | |
| tree | 949765d6112d70536a3806eb822798a0e04577da | |
| parent | dd310534e3bf8045096654df41471fd7132887b2 (diff) | |
Add endianness as io mem parameter
As stated before, devices can be little, big or native endian. The
target endianness is not of their concern, so we need to push things
down a level.
This patch adds a parameter to cpu_register_io_memory that allows a
device to choose its endianness. For now, all devices simply choose
native endian, because that's the same behavior as before.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
154 files changed, 446 insertions, 262 deletions
@@ -3331,7 +3331,8 @@ static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys, mmio = qemu_mallocz(sizeof(subpage_t)); mmio->base = base; - subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio); + subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio, + DEVICE_NATIVE_ENDIAN); #if defined(DEBUG_SUBPAGE) printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__, mmio, base, TARGET_PAGE_SIZE, subpage_memory); @@ -3468,7 +3469,6 @@ static int cpu_register_io_memory_fixed(int io_index, void *opaque, enum device_endian endian) { int i; - int endian = DEVICE_NATIVE_ENDIAN; if (io_index <= 0) { io_index = get_free_io_mem_idx(); @@ -3513,7 +3513,7 @@ int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read, CPUWriteMemoryFunc * const *mem_write, void *opaque, enum device_endian endian) { - return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque); + return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque, endian); } void cpu_unregister_io_memory(int io_table_address) @@ -3535,14 +3535,21 @@ static void io_mem_init(void) { int i; - cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, unassigned_mem_write, NULL); - cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, unassigned_mem_write, NULL); - cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, notdirty_mem_write, NULL); + cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, + unassigned_mem_write, NULL, + DEVICE_NATIVE_ENDIAN); + cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, + unassigned_mem_write, NULL, + DEVICE_NATIVE_ENDIAN); + cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, + notdirty_mem_write, NULL, + DEVICE_NATIVE_ENDIAN); for (i=0; i<5; i++) io_mem_used[i] = 1; io_mem_watch = cpu_register_io_memory(watch_mem_read, - watch_mem_write, NULL); + watch_mem_write, NULL, + DEVICE_NATIVE_ENDIAN); } #endif /* !defined(CONFIG_USER_ONLY) */ diff --git a/hw/apb_pci.c b/hw/apb_pci.c index c619112b1..bf00c71d6 100644 --- a/hw/apb_pci.c +++ b/hw/apb_pci.c @@ -410,7 +410,8 @@ static int pci_pbm_init_device(SysBusDevice *dev) /* apb_config */ apb_config = cpu_register_io_memory(apb_config_read, - apb_config_write, s); + apb_config_write, s, + DEVICE_NATIVE_ENDIAN); /* at region 0 */ sysbus_init_mmio(dev, 0x10000ULL, apb_config); @@ -424,7 +425,8 @@ static int pci_pbm_init_device(SysBusDevice *dev) /* pci_ioport */ pci_ioport = cpu_register_io_memory(pci_apb_ioread, - pci_apb_iowrite, s); + pci_apb_iowrite, s, + DEVICE_NATIVE_ENDIAN); /* at region 2 */ sysbus_init_mmio(dev, 0x10000ULL, pci_ioport); @@ -980,7 +980,8 @@ static int apic_init1(SysBusDevice *dev) return -1; } apic_io_memory = cpu_register_io_memory(apic_mem_read, - apic_mem_write, NULL); + apic_mem_write, NULL, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory); s->timer = qemu_new_timer(vm_clock, apic_timer, s); diff --git a/hw/arm_gic.c b/hw/arm_gic.c index 8286a282e..e6b195324 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -742,7 +742,8 @@ static void gic_init(gic_state *s) sysbus_init_irq(&s->busdev, &s->parent_irq[i]); } s->iomemtype = cpu_register_io_memory(gic_dist_readfn, - gic_dist_writefn, s); + gic_dist_writefn, s, + DEVICE_NATIVE_ENDIAN); gic_reset(s); register_savevm(NULL, "arm_gic", -1, 1, gic_save, gic_load, s); } diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c index 0cb2ffc50..bd0664fe7 100644 --- a/hw/arm_sysctl.c +++ b/hw/arm_sysctl.c @@ -208,7 +208,8 @@ static int arm_sysctl_init1(SysBusDevice *dev) int iomemtype; iomemtype = cpu_register_io_memory(arm_sysctl_readfn, - arm_sysctl_writefn, s); + arm_sysctl_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); /* ??? Save/restore. */ return 0; diff --git a/hw/arm_timer.c b/hw/arm_timer.c index f009e9e51..82f05dec8 100644 --- a/hw/arm_timer.c +++ b/hw/arm_timer.c @@ -269,7 +269,7 @@ static int sp804_init(SysBusDevice *dev) s->timer[0]->irq = qi[0]; s->timer[1]->irq = qi[1]; iomemtype = cpu_register_io_memory(sp804_readfn, - sp804_writefn, s); + sp804_writefn, s, DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); register_savevm(&dev->qdev, "sp804", -1, 1, sp804_save, sp804_load, s); return 0; @@ -340,7 +340,8 @@ static int icp_pit_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->timer[2]->irq); iomemtype = cpu_register_io_memory(icp_pit_readfn, - icp_pit_writefn, s); + icp_pit_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); /* This device has no state to save/restore. The component timers will save themselves. */ diff --git a/hw/armv7m.c b/hw/armv7m.c index 588ec9805..304cd34bc 100644 --- a/hw/armv7m.c +++ b/hw/armv7m.c @@ -130,7 +130,7 @@ static int bitband_init(SysBusDevice *dev) int iomemtype; iomemtype = cpu_register_io_memory(bitband_readfn, bitband_writefn, - &s->base); + &s->base, DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x02000000, iomemtype); return 0; } diff --git a/hw/axis_dev88.c b/hw/axis_dev88.c index f16c76aee..57b5e2f04 100644 --- a/hw/axis_dev88.c +++ b/hw/axis_dev88.c @@ -280,11 +280,13 @@ void axisdev88_init (ram_addr_t ram_size, /* Attach a NAND flash to CS1. */ nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39); - nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state); + nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs); gpio_state.nand = &nand_state; - gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state); + gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs); diff --git a/hw/bonito.c b/hw/bonito.c index dcf031134..fd905273e 100644 --- a/hw/bonito.c +++ b/hw/bonito.c @@ -698,7 +698,8 @@ static int bonito_initfn(PCIDevice *dev) pci_config_set_revision(dev->config, 0x01); /* set the north bridge register mapping */ - s->bonito_reg_handle = cpu_register_io_memory(bonito_read, bonito_write, s); + s->bonito_reg_handle = cpu_register_io_memory(bonito_read, bonito_write, s, + DEVICE_NATIVE_ENDIAN); s->bonito_reg_start = BONITO_INTERNAL_REG_BASE; s->bonito_reg_length = BONITO_INTERNAL_REG_SIZE; cpu_register_physical_memory(s->bonito_reg_start, s->bonito_reg_length, @@ -706,7 +707,8 @@ static int bonito_initfn(PCIDevice *dev) /* set the north bridge pci configure mapping */ s->bonito_pciconf_handle = cpu_register_io_memory(bonito_pciconf_read, - bonito_pciconf_write, s); + bonito_pciconf_write, s, + DEVICE_NATIVE_ENDIAN); s->bonito_pciconf_start = BONITO_PCICONFIG_BASE; s->bonito_pciconf_length = BONITO_PCICONFIG_SIZE; cpu_register_physical_memory(s->bonito_pciconf_start, s->bonito_pciconf_length, @@ -714,21 +716,24 @@ static int bonito_initfn(PCIDevice *dev) /* set the south bridge pci configure mapping */ s->bonito_spciconf_handle = cpu_register_io_memory(bonito_spciconf_read, - bonito_spciconf_write, s); + bonito_spciconf_write, s, + DEVICE_NATIVE_ENDIAN); s->bonito_spciconf_start = BONITO_SPCICONFIG_BASE; s->bonito_spciconf_length = BONITO_SPCICONFIG_SIZE; cpu_register_physical_memory(s->bonito_spciconf_start, s->bonito_spciconf_length, s->bonito_spciconf_handle); s->bonito_ldma_handle = cpu_register_io_memory(bonito_ldma_read, - bonito_ldma_write, s); + bonito_ldma_write, s, + DEVICE_NATIVE_ENDIAN); s->bonito_ldma_start = 0xbfe00200; s->bonito_ldma_length = 0x100; cpu_register_physical_memory(s->bonito_ldma_start, s->bonito_ldma_length, s->bonito_ldma_handle); s->bonito_cop_handle = cpu_register_io_memory(bonito_cop_read, - bonito_cop_write, s); + bonito_cop_write, s, + DEVICE_NATIVE_ENDIAN); s->bonito_cop_start = 0xbfe00300; s->bonito_cop_length = 0x100; cpu_register_physical_memory(s->bonito_cop_start, s->bonito_cop_length, diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c index 40be55d1b..4f5040cf4 100644 --- a/hw/cirrus_vga.c +++ b/hw/cirrus_vga.c @@ -3076,23 +3076,27 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci) register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s); s->vga.vga_io_memory = cpu_register_io_memory(cirrus_vga_mem_read, - cirrus_vga_mem_write, s); + cirrus_vga_mem_write, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000, s->vga.vga_io_memory); qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000); /* I/O handler for LFB */ s->cirrus_linear_io_addr = - cpu_register_io_memory(cirrus_linear_read, cirrus_linear_write, s); + cpu_register_io_memory(cirrus_linear_read, cirrus_linear_write, s, + DEVICE_NATIVE_ENDIAN); /* I/O handler for LFB */ s->cirrus_linear_bitblt_io_addr = cpu_register_io_memory(cirrus_linear_bitblt_read, - cirrus_linear_bitblt_write, s); + cirrus_linear_bitblt_write, s, + DEVICE_NATIVE_ENDIAN); /* I/O handler for memory-mapped I/O */ s->cirrus_mmio_io_addr = - cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s); + cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s, + DEVICE_NATIVE_ENDIAN); s->real_vram_size = (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024; diff --git a/hw/cs4231.c b/hw/cs4231.c index 2977101e3..a65b697a1 100644 --- a/hw/cs4231.c +++ b/hw/cs4231.c @@ -148,7 +148,8 @@ static int cs4231_init1(SysBusDevice *dev) int io; CSState *s = FROM_SYSBUS(CSState, dev); - io = cpu_register_io_memory(cs_mem_read, cs_mem_write, s); + io = cpu_register_io_memory(cs_mem_read, cs_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, CS_SIZE, io); sysbus_init_irq(dev, &s->irq); @@ -762,7 +762,8 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq) s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s); - *cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s); + *cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s, + DEVICE_NATIVE_ENDIAN); register_savevm(NULL, "cuda", -1, 1, cuda_save, cuda_load, s); qemu_register_reset(cuda_reset, s); } diff --git a/hw/dp8393x.c b/hw/dp8393x.c index e65e4d153..0ef8abe83 100644 --- a/hw/dp8393x.c +++ b/hw/dp8393x.c @@ -908,6 +908,7 @@ void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift, qemu_register_reset(nic_reset, s); nic_reset(s); - s->mmio_index = cpu_register_io_memory(dp8393x_read, dp8393x_write, s); + s->mmio_index = cpu_register_io_memory(dp8393x_read, dp8393x_write, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x40 << it_shift, s->mmio_index); } diff --git a/hw/ds1225y.c b/hw/ds1225y.c index 009d12745..b1c52321f 100644 --- a/hw/ds1225y.c +++ b/hw/ds1225y.c @@ -171,10 +171,12 @@ void *ds1225y_init(target_phys_addr_t mem_base, const char *filename) } /* Read/write memory */ - mem_indexRW = cpu_register_io_memory(nvram_read, nvram_write, s); + mem_indexRW = cpu_register_io_memory(nvram_read, nvram_write, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(mem_base, s->chip_size, mem_indexRW); /* Read/write protected memory */ - mem_indexRP = cpu_register_io_memory(nvram_read, nvram_write_protected, s); + mem_indexRP = cpu_register_io_memory(nvram_read, nvram_write_protected, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(mem_base + s->chip_size, s->chip_size, mem_indexRP); return s; } diff --git a/hw/e1000.c b/hw/e1000.c index 57d08cfa3..bf3f2d341 100644 --- a/hw/e1000.c +++ b/hw/e1000.c @@ -1131,7 +1131,7 @@ static int pci_e1000_init(PCIDevice *pci_dev) pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0 d->mmio_index = cpu_register_io_memory(e1000_mmio_read, - e1000_mmio_write, d); + e1000_mmio_write, d, DEVICE_NATIVE_ENDIAN); pci_register_bar(&d->dev, 0, PNPMMIO_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY, e1000_mmio_map); diff --git a/hw/eccmemctl.c b/hw/eccmemctl.c index a8042e94b..2bda87b6c 100644 --- a/hw/eccmemctl.c +++ b/hw/eccmemctl.c @@ -297,12 +297,14 @@ static int ecc_init1(SysBusDevice *dev) sysbus_init_irq(dev, &s->irq); s->regs[0] = s->version; - ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s); + ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, ECC_SIZE, ecc_io_memory); if (s->version == ECC_MCC) { // SS-600MP only ecc_io_memory = cpu_register_io_memory(ecc_diag_mem_read, - ecc_diag_mem_write, s); + ecc_diag_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, ECC_DIAG_SIZE, ecc_io_memory); } diff --git a/hw/eepro100.c b/hw/eepro100.c index f8a700a2b..b31ad3e70 100644 --- a/hw/eepro100.c +++ b/hw/eepro100.c @@ -1878,7 +1878,8 @@ static int e100_nic_init(PCIDevice *pci_dev) /* Handler for memory-mapped I/O */ s->mmio_index = - cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s); + cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s, + DEVICE_NATIVE_ENDIAN); pci_register_bar(&s->dev, 0, PCI_MEM_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY | diff --git a/hw/empty_slot.c b/hw/empty_slot.c index ac1f6ebbf..664b8d9c4 100644 --- a/hw/empty_slot.c +++ b/hw/empty_slot.c @@ -73,7 +73,8 @@ static int empty_slot_init1(SysBusDevice *dev) ram_addr_t empty_slot_offset; empty_slot_offset = cpu_register_io_memory(empty_slot_read, - empty_slot_write, s); + empty_slot_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, s->size, empty_slot_offset | IO_MEM_RAM); return 0; } @@ -914,7 +914,8 @@ static int escc_init1(SysBusDevice *dev) s->chn[0].otherchn = &s->chn[1]; s->chn[1].otherchn = &s->chn[0]; - io = cpu_register_io_memory(escc_mem_read, escc_mem_write, s); + io = cpu_register_io_memory(escc_mem_read, escc_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, ESCC_SIZE << s->it_shift, io); s->mmio_index = io; @@ -722,7 +722,8 @@ static int esp_init1(SysBusDevice *dev) sysbus_init_irq(dev, &s->irq); assert(s->it_shift != -1); - esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s); + esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory); qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2); diff --git a/hw/etraxfs_dma.c b/hw/etraxfs_dma.c index 15c8ad3dc..c205ec1b8 100644 --- a/hw/etraxfs_dma.c +++ b/hw/etraxfs_dma.c @@ -750,7 +750,7 @@ void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels) ctrl->nr_channels = nr_channels; ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels); - ctrl->map = cpu_register_io_memory(dma_read, dma_write, ctrl); + ctrl->map = cpu_register_io_memory(dma_read, dma_write, ctrl, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, nr_channels * 0x2000, ctrl->map); return ctrl; } diff --git a/hw/etraxfs_eth.c b/hw/etraxfs_eth.c index ade96f14a..6aa400720 100644 --- a/hw/etraxfs_eth.c +++ b/hw/etraxfs_eth.c @@ -598,7 +598,8 @@ void *etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr) tdk_init(ð->phy); mdio_attach(ð->mdio_bus, ð->phy, eth->phyaddr); - eth->ethregs = cpu_register_io_memory(eth_read, eth_write, eth); + eth->ethregs = cpu_register_io_memory(eth_read, eth_write, eth, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory (base, 0x5c, eth->ethregs); memcpy(eth->conf.macaddr.a, nd->macaddr, sizeof(nd->macaddr)); diff --git a/hw/etraxfs_pic.c b/hw/etraxfs_pic.c index b2c485994..4feffda60 100644 --- a/hw/etraxfs_pic.c +++ b/hw/etraxfs_pic.c @@ -145,7 +145,8 @@ static int etraxfs_pic_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->parent_irq); sysbus_init_irq(dev, &s->parent_nmi); - intr_vect_regs = cpu_register_io_memory(pic_read, pic_write, s); + intr_vect_regs = cpu_register_io_memory(pic_read, pic_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, R_MAX * 4, intr_vect_regs); return 0; } diff --git a/hw/etraxfs_ser.c b/hw/etraxfs_ser.c index 336cc5476..2787ebd5c 100644 --- a/hw/etraxfs_ser.c +++ b/hw/etraxfs_ser.c @@ -200,7 +200,8 @@ static int etraxfs_ser_init(SysBusDevice *dev) s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE); sysbus_init_irq(dev, &s->irq); - ser_regs = cpu_register_io_memory(ser_read, ser_write, s); + ser_regs = cpu_register_io_memory(ser_read, ser_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, R_MAX * 4, ser_regs); s->chr = qdev_init_chardev(&dev->qdev); if (s->chr) diff --git a/hw/etraxfs_timer.c b/hw/etraxfs_timer.c index 87700d4cd..ba1adbe3c 100644 --- a/hw/etraxfs_timer.c +++ b/hw/etraxfs_timer.c @@ -323,7 +323,8 @@ static int etraxfs_timer_init(SysBusDevice *dev) sysbus_init_irq(dev, &t->irq); sysbus_init_irq(dev, &t->nmi); - timer_regs = cpu_register_io_memory(timer_read, timer_write, t); + timer_regs = cpu_register_io_memory(timer_read, timer_write, t, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x5c, timer_regs); qemu_register_reset(etraxfs_timer_reset, t); @@ -1999,7 +1999,8 @@ static int sysbus_fdc_init1(SysBusDevice *dev) int io; int ret; - io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl); + io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x08, io); sysbus_init_irq(dev, &fdctrl->irq); qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1); @@ -2017,7 +2018,8 @@ static int sun4m_fdc_init1(SysBusDevice *dev) int io; io = cpu_register_io_memory(fdctrl_mem_read_strict, - fdctrl_mem_write_strict, fdctrl); + fdctrl_mem_write_strict, fdctrl, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x08, io); sysbus_init_irq(dev, &fdctrl->irq); qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1); diff --git a/hw/fw_cfg.c b/hw/fw_cfg.c index 72866aea9..48b92d69e 100644 --- a/hw/fw_cfg.c +++ b/hw/fw_cfg.c @@ -360,11 +360,13 @@ static int fw_cfg_init1(SysBusDevice *dev) int io_ctl_memory, io_data_memory; io_ctl_memory = cpu_register_io_memory(fw_cfg_ctl_mem_read, - fw_cfg_ctl_mem_write, s); + fw_cfg_ctl_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, FW_CFG_SIZE, io_ctl_memory); io_data_memory = cpu_register_io_memory(fw_cfg_data_mem_read, - fw_cfg_data_mem_write, s); + fw_cfg_data_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, FW_CFG_SIZE, io_data_memory); if (s->ctl_iobase) { diff --git a/hw/g364fb.c b/hw/g364fb.c index 3c8fb982d..a41e98879 100644 --- a/hw/g364fb.c +++ b/hw/g364fb.c @@ -607,7 +607,8 @@ int g364fb_mm_init(target_phys_addr_t vram_base, cpu_register_physical_memory(vram_base, s->vram_size, s->vram_offset); - io_ctrl = cpu_register_io_memory(g364fb_ctrl_read, g364fb_ctrl_write, s); + io_ctrl = cpu_register_io_memory(g364fb_ctrl_read, g364fb_ctrl_write, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(ctrl_base, 0x200000, io_ctrl); return 0; diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c index cabf7ea0b..51e4db09b 100644 --- a/hw/gt64xxx.c +++ b/hw/gt64xxx.c @@ -1116,7 +1116,8 @@ PCIBus *pci_gt64120_init(qemu_irq *pic) s->pci->bus = pci_register_bus(NULL, "pci", pci_gt64120_set_irq, pci_gt64120_map_irq, pic, PCI_DEVFN(18, 0), 4); - s->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, s); + s->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, s, + DEVICE_NATIVE_ENDIAN); d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice), 0, NULL, NULL); diff --git a/hw/heathrow_pic.c b/hw/heathrow_pic.c index cd8612109..390b63ce4 100644 --- a/hw/heathrow_pic.c +++ b/hw/heathrow_pic.c @@ -222,7 +222,8 @@ qemu_irq *heathrow_pic_init(int *pmem_index, s = qemu_mallocz(sizeof(HeathrowPICS)); /* only 1 CPU */ s->irqs = irqs[0]; - *pmem_index = cpu_register_io_memory(pic_read, pic_write, s); + *pmem_index = cpu_register_io_memory(pic_read, pic_write, s, + DEVICE_NATIVE_ENDIAN); register_savevm(NULL, "heathrow_pic", -1, 1, heathrow_pic_save, heathrow_pic_load, s); @@ -720,7 +720,8 @@ static int hpet_init(SysBusDevice *dev) /* HPET Area */ iomemtype = cpu_register_io_memory(hpet_ram_read, - hpet_ram_write, s); + hpet_ram_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x400, iomemtype); return 0; } diff --git a/hw/ide/macio.c b/hw/ide/macio.c index bd1c73e62..c1b4caab5 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -320,7 +320,8 @@ int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq, DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d); pmac_ide_memory = cpu_register_io_memory(pmac_ide_read, - pmac_ide_write, d); + pmac_ide_write, d, + DEVICE_NATIVE_ENDIAN); vmstate_register(NULL, 0, &vmstate_pmac, d); qemu_register_reset(pmac_ide_reset, d); diff --git a/hw/ide/mmio.c b/hw/ide/mmio.c index 9f20e8bab..82b24b673 100644 --- a/hw/ide/mmio.c +++ b/hw/ide/mmio.c @@ -129,8 +129,10 @@ void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2, s->shift = shift; - mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s); - mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s); + mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s, + DEVICE_NATIVE_ENDIAN); + mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(membase, 16 << shift, mem1); cpu_register_physical_memory(membase2, 2 << shift, mem2); vmstate_register(NULL, 0, &vmstate_ide_mmio, s); diff --git a/hw/integratorcp.c b/hw/integratorcp.c index 3bf216bf8..b04994082 100644 --- a/hw/integratorcp.c +++ b/hw/integratorcp.c @@ -256,7 +256,8 @@ static int integratorcm_init(SysBusDevice *dev) s->flash_offset = qemu_ram_alloc(NULL, "integrator.flash", 0x100000); iomemtype = cpu_register_io_memory(integratorcm_readfn, - integratorcm_writefn, s); + integratorcm_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x00800000, iomemtype); integratorcm_do_remap(s, 1); /* ??? Save/restore. */ @@ -382,7 +383,8 @@ static int icp_pic_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->parent_irq); sysbus_init_irq(dev, &s->parent_fiq); iomemtype = cpu_register_io_memory(icp_pic_readfn, - icp_pic_writefn, s); + icp_pic_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x00800000, iomemtype); return 0; } @@ -435,7 +437,8 @@ static void icp_control_init(uint32_t base) int iomemtype; iomemtype = cpu_register_io_memory(icp_control_readfn, - icp_control_writefn, NULL); + icp_control_writefn, NULL, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x00800000, iomemtype); /* ??? Save/restore. */ } diff --git a/hw/intel-hda.c b/hw/intel-hda.c index fe316245a..b2b67082e 100644 --- a/hw/intel-hda.c +++ b/hw/intel-hda.c @@ -1156,7 +1156,8 @@ static int intel_hda_init(PCIDevice *pci) conf[0x40] = 0x01; d->mmio_addr = cpu_register_io_memory(intel_hda_mmio_read, - intel_hda_mmio_write, d); + intel_hda_mmio_write, d, + DEVICE_NATIVE_ENDIAN); pci_register_bar(&d->pci, 0, 0x4000, PCI_BASE_ADDRESS_SPACE_MEMORY, intel_hda_map); if (d->msi) { diff --git a/hw/ioapic.c b/hw/ioapic.c index 5ae21e910..210956860 100644 --- a/hw/ioapic.c +++ b/hw/ioapic.c @@ -242,7 +242,8 @@ static int ioapic_init1(SysBusDevice *dev) int io_memory; io_memory = cpu_register_io_memory(ioapic_mem_read, - ioapic_mem_write, s); + ioapic_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, io_memory); qdev_init_gpio_in(&dev->qdev, ioapic_set_irq, IOAPIC_NUM_PINS); diff --git a/hw/isa_mmio.c b/hw/isa_mmio.c index 66bdd2cef..46458f4a5 100644 --- a/hw/isa_mmio.c +++ b/hw/isa_mmio.c @@ -131,11 +131,13 @@ void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be) if (be) { isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_be, isa_mmio_write_be, - NULL); + NULL, + DEVICE_NATIVE_ENDIAN); } else { isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_le, isa_mmio_write_le, - NULL); + NULL, + DEVICE_NATIVE_ENDIAN); } } cpu_register_physical_memory(base, size, isa_mmio_iomemtype); diff --git a/hw/ivshmem.c b/hw/ivshmem.c index 06dce70e7..7b19a81a4 100644 --- a/hw/ivshmem.c +++ b/hw/ivshmem.c @@ -720,7 +720,7 @@ static int pci_ivshmem_init(PCIDevice *dev) s->shm_fd = 0; s->ivshmem_mmio_io_addr = cpu_register_io_memory(ivshmem_mmio_read, - ivshmem_mmio_write, s); + ivshmem_mmio_write, s, DEVICE_NATIVE_ENDIAN); /* region for registers*/ pci_register_bar(&s->dev, 0, IVSHMEM_REG_BAR_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY, ivshmem_mmio_map); diff --git a/hw/jazz_led.c b/hw/jazz_led.c index 4cb680c3e..1dc22cf2e 100644 --- a/hw/jazz_led.c +++ b/hw/jazz_led.c @@ -316,7 +316,8 @@ void jazz_led_init(target_phys_addr_t base) s->state = REDRAW_SEGMENTS | REDRAW_BACKGROUND; - io = cpu_register_io_memory(led_read, led_write, s); + io = cpu_register_io_memory(led_read, led_write, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 1, io); s->ds = graphic_console_init(jazz_led_update_display, diff --git a/hw/lan9118.c b/hw/lan9118.c index b996dc4f0..a98866479 100644 --- a/hw/lan9118.c +++ b/hw/lan9118.c @@ -1124,7 +1124,8 @@ static int lan9118_init1(SysBusDevice *dev) int i; s->mmio_index = cpu_register_io_memory(lan9118_readfn, - lan9118_writefn, s); + lan9118_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x100, s->mmio_index); sysbus_init_irq(dev, &s->irq); qemu_macaddr_default_if_unset(&s->conf.macaddr); diff --git a/hw/lance.c b/hw/lance.c index dc12144de..8c5185817 100644 --- a/hw/lance.c +++ b/hw/lance.c @@ -118,7 +118,8 @@ static int lance_init(SysBusDevice *dev) PCNetState *s = &d->state; s->mmio_index = - cpu_register_io_memory(lance_mem_read, lance_mem_write, d); + cpu_register_io_memory(lance_mem_read, lance_mem_write, d, + DEVICE_NATIVE_ENDIAN); qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1); diff --git a/hw/lsi53c895a.c b/hw/lsi53c895a.c index 1aef62f9a..0129ae3cc 100644 --- a/hw/lsi53c895a.c +++ b/hw/lsi53c895a.c @@ -2173,9 +2173,11 @@ static int lsi_scsi_init(PCIDevice *dev) pci_conf[PCI_INTERRUPT_PIN] = 0x01; s->mmio_io_addr = cpu_register_io_memory(lsi_mmio_readfn, - lsi_mmio_writefn, s); + lsi_mmio_writefn, s, + DEVICE_NATIVE_ENDIAN); s->ram_io_addr = cpu_register_io_memory(lsi_ram_readfn, - lsi_ram_writefn, s); + lsi_ram_writefn, s, + DEVICE_NATIVE_ENDIAN); pci_register_bar(&s->dev, 0, 256, PCI_BASE_ADDRESS_SPACE_IO, lsi_io_mapfunc); diff --git a/hw/m48t59.c b/hw/m48t59.c index c7492a65f..3c26b544f 100644 --- a/hw/m48t59.c +++ b/hw/m48t59.c @@ -716,7 +716,8 @@ static int m48t59_init1(SysBusDevice *dev) sysbus_init_irq(dev, &s->IRQ); - mem_index = cpu_register_io_memory(nvram_read, nvram_write, s); + mem_index = cpu_register_io_memory(nvram_read, nvram_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, s->size, mem_index); m48t59_init_common(s); diff --git a/hw/mac_dbdma.c b/hw/mac_dbdma.c index 03d2d16d2..f449a5991 100644 --- a/hw/mac_dbdma.c +++ b/hw/mac_dbdma.c @@ -844,7 +844,8 @@ void* DBDMA_init (int *dbdma_mem_index) s = qemu_mallocz(sizeof(DBDMA_channel) * DBDMA_CHANNELS); - *dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s); + *dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s, + DEVICE_NATIVE_ENDIAN); register_savevm(NULL, "dbdma", -1, 1, dbdma_save, dbdma_load, s); qemu_register_reset(dbdma_reset, s); diff --git a/hw/mac_nvram.c b/hw/mac_nvram.c index ce287c31d..c2a2fc21e 100644 --- a/hw/mac_nvram.c +++ b/hw/mac_nvram.c @@ -138,7 +138,8 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size, s->size = size; s->it_shift = it_shift; - s->mem_index = cpu_register_io_memory(nvram_read, nvram_write, s); + s->mem_index = cpu_register_io_memory(nvram_read, nvram_write, s, + DEVICE_NATIVE_ENDIAN); *mem_index = s->mem_index; register_savevm(NULL, "macio_nvram", -1, 1, macio_nvram_save, macio_nvram_load, s); diff --git a/hw/marvell_88w8618_audio.c b/hw/marvell_88w8618_audio.c index 307b58471..3eff925b0 100644 --- a/hw/marvell_88w8618_audio.c +++ b/hw/marvell_88w8618_audio.c @@ -249,7 +249,8 @@ static int mv88w8618_audio_init(SysBusDevice *dev) wm8750_data_req_set(s->wm, mv88w8618_audio_callback, s); iomemtype = cpu_register_io_memory(mv88w8618_audio_readfn, - mv88w8618_audio_writefn, s); + mv88w8618_audio_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, MP_AUDIO_SIZE, iomemtype); return 0; diff --git a/hw/mcf5206.c b/hw/mcf5206.c index c107de8c6..2a618d444 100644 --- a/hw/mcf5206.c +++ b/hw/mcf5206.c @@ -525,7 +525,8 @@ qemu_irq *mcf5206_init(uint32_t base, CPUState *env) s = (m5206_mbar_state *)qemu_mallocz(sizeof(m5206_mbar_state)); iomemtype = cpu_register_io_memory(m5206_mbar_readfn, - m5206_mbar_writefn, s); + m5206_mbar_writefn, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x00001000, iomemtype); pic = qemu_allocate_irqs(m5206_mbar_set_irq, s, 14); diff --git a/hw/mcf5208.c b/hw/mcf5208.c index 38645f728..17a692d4a 100644 --- a/hw/mcf5208.c +++ b/hw/mcf5208.c @@ -179,7 +179,8 @@ static void mcf5208_sys_init(qemu_irq *pic) int i; iomemtype = cpu_register_io_memory(m5208_sys_readfn, - m5208_sys_writefn, NULL); + m5208_sys_writefn, NULL, + DEVICE_NATIVE_ENDIAN); /* SDRAMC. */ cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype); /* Timers. */ @@ -188,7 +189,8 @@ static void mcf5208_sys_init(qemu_irq *pic) bh = qemu_bh_new(m5208_timer_trigger, s); s->timer = ptimer_init(bh); iomemtype = cpu_register_io_memory(m5208_timer_readfn, - m5208_timer_writefn, s); + m5208_timer_writefn, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000, iomemtype); s->irq = pic[4 + i]; diff --git a/hw/mcf_fec.c b/hw/mcf_fec.c index 4e7fbed16..21035da34 100644 --- a/hw/mcf_fec.c +++ b/hw/mcf_fec.c @@ -467,7 +467,8 @@ void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq) s = (mcf_fec_state *)qemu_mallocz(sizeof(mcf_fec_state)); s->irq = irq; s->mmio_index = cpu_register_io_memory(mcf_fec_readfn, - mcf_fec_writefn, s); + mcf_fec_writefn, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x400, s->mmio_index); memcpy(s->conf.macaddr.a, nd->macaddr, sizeof(nd->macaddr)); diff --git a/hw/mcf_intc.c b/hw/mcf_intc.c index f01bd320a..ac0429519 100644 --- a/hw/mcf_intc.c +++ b/hw/mcf_intc.c @@ -149,7 +149,8 @@ qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env) mcf_intc_reset(s); iomemtype = cpu_register_io_memory(mcf_intc_readfn, - mcf_intc_writefn, s); + mcf_intc_writefn, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x100, iomemtype); return qemu_allocate_irqs(mcf_intc_set_irq, s, 64); diff --git a/hw/mcf_uart.c b/hw/mcf_uart.c index d16bac733..db57096af 100644 --- a/hw/mcf_uart.c +++ b/hw/mcf_uart.c @@ -304,6 +304,7 @@ void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq, s = mcf_uart_init(irq, chr); iomemtype = cpu_register_io_memory(mcf_uart_readfn, - mcf_uart_writefn, s); + mcf_uart_writefn, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x40, iomemtype); } diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c index 66397c0c9..126474310 100644 --- a/hw/mips_jazz.c +++ b/hw/mips_jazz.c @@ -191,7 +191,8 @@ void mips_jazz_init (ram_addr_t ram_size, /* Chipset */ rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas); - s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL); + s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy); /* ISA devices */ @@ -259,7 +260,8 @@ void mips_jazz_init (ram_addr_t ram_size, /* Real time clock */ rtc_init(1980, NULL); - s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL); + s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc); /* Keyboard (i8042) */ diff --git a/hw/mips_malta.c b/hw/mips_malta.c index 6be8aa70f..5ef3fcbea 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -436,7 +436,8 @@ static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_ir s = (MaltaFPGAState *)qemu_mallocz(sizeof(MaltaFPGAState)); malta = cpu_register_io_memory(malta_fpga_read, - malta_fpga_write, s); + malta_fpga_write, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x900, malta); /* 0xa00 is less than a page, so will still get the right offsets. */ diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c index aa348904a..afe52f313 100644 --- a/hw/mips_r4k.c +++ b/hw/mips_r4k.c @@ -204,7 +204,8 @@ void mips_r4k_init (ram_addr_t ram_size, if (!mips_qemu_iomemtype) { mips_qemu_iomemtype = cpu_register_io_memory(mips_qemu_read, - mips_qemu_write, NULL); + mips_qemu_write, NULL, + DEVICE_NATIVE_ENDIAN); } cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype); diff --git a/hw/mpcore.c b/hw/mpcore.c index b4db1914b..fc0521549 100644 --- a/hw/mpcore.c +++ b/hw/mpcore.c @@ -276,7 +276,8 @@ static int mpcore_priv_init(SysBusDevice *dev) gic_init(&s->gic, s->num_cpu); s->iomemtype = cpu_register_io_memory(mpcore_priv_readfn, - mpcore_priv_writefn, s); + mpcore_priv_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio_cb(dev, 0x2000, mpcore_priv_map); for (i = 0; i < s->num_cpu * 2; i++) { mpcore_timer_init(s, &s->timer[i], i); @@ -254,7 +254,8 @@ int msix_init(struct PCIDevice *dev, unsigned short nentries, msix_mask_all(dev, nentries); dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read, - msix_mmio_write, dev); + msix_mmio_write, dev, + DEVICE_NATIVE_ENDIAN); if (dev->msix_mmio_index == -1) { ret = -EBUSY; goto err_index; diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c index 8fc348f75..5252fc5e1 100644 --- a/hw/mst_fpga.c +++ b/hw/mst_fpga.c @@ -232,7 +232,7 @@ qemu_irq *mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq) s->pins = qi; iomemtype = cpu_register_io_memory(mst_fpga_readfn, - mst_fpga_writefn, s); + mst_fpga_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x00100000, iomemtype); register_savevm(NULL, "mainstone_fpga", 0, 0, mst_fpga_save, mst_fpga_load, s); diff --git a/hw/musicpal.c b/hw/musicpal.c index 56f27669d..d98aa8d03 100644 --- a/hw/musicpal.c +++ b/hw/musicpal.c @@ -388,7 +388,8 @@ static int mv88w8618_eth_init(SysBusDevice *dev) s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf, dev->qdev.info->name, dev->qdev.id, s); s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn, - mv88w8618_eth_writefn, s); + mv88w8618_eth_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index); return 0; } @@ -600,7 +601,8 @@ static int musicpal_lcd_init(SysBusDevice *dev) s->brightness = 7; iomemtype = cpu_register_io_memory(musicpal_lcd_readfn, - musicpal_lcd_writefn, s); + musicpal_lcd_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype); s->ds = graphic_console_init(lcd_refresh, lcd_invalidate, @@ -725,7 +727,8 @@ static int mv88w8618_pic_init(SysBusDevice *dev) qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32); sysbus_init_irq(dev, &s->parent_irq); iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn, - mv88w8618_pic_writefn, s); + mv88w8618_pic_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype); return 0; } @@ -886,7 +889,8 @@ static int mv88w8618_pit_init(SysBusDevice *dev) } iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn, - mv88w8618_pit_writefn, s); + mv88w8618_pit_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype); return 0; } @@ -976,7 +980,8 @@ static int mv88w8618_flashcfg_init(SysBusDevice *dev) s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */ iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn, - mv88w8618_flashcfg_writefn, s); + mv88w8618_flashcfg_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype); return 0; } @@ -1037,7 +1042,8 @@ static void musicpal_misc_init(void) int iomemtype; iomemtype = cpu_register_io_memory(musicpal_misc_readfn, - musicpal_misc_writefn, NULL); + musicpal_misc_writefn, NULL, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype); } @@ -1082,7 +1088,8 @@ static int mv88w8618_wlan_init(SysBusDevice *dev) int iomemtype; iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn, - mv88w8618_wlan_writefn, NULL); + mv88w8618_wlan_writefn, NULL, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype); return 0; } @@ -1293,7 +1300,8 @@ static int musicpal_gpio_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->irq); iomemtype = cpu_register_io_memory(musicpal_gpio_readfn, - musicpal_gpio_writefn, s); + musicpal_gpio_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype); qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out)); @@ -1129,7 +1129,8 @@ inline static int debug_register_io_memory(CPUReadMemoryFunc * const *mem_read, s->mem_write = mem_write; s->opaque = opaque; s->in = 0; - return cpu_register_io_memory(io_readfn, io_writefn, s); + return cpu_register_io_memory(io_readfn, io_writefn, s, + DEVICE_NATIVE_ENDIAN); } # define cpu_register_io_memory debug_register_io_memory # endif diff --git a/hw/omap1.c b/hw/omap1.c index f4966f74b..d5e4dabc8 100644 --- a/hw/omap1.c +++ b/hw/omap1.c @@ -264,7 +264,7 @@ static struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base, omap_timer_clk_setup(s); iomemtype = cpu_register_io_memory(omap_mpu_timer_readfn, - omap_mpu_timer_writefn, s); + omap_mpu_timer_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x100, iomemtype); return s; @@ -387,7 +387,7 @@ static struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base, omap_timer_clk_setup(&s->timer); iomemtype = cpu_register_io_memory(omap_wd_timer_readfn, - omap_wd_timer_writefn, s); + omap_wd_timer_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x100, iomemtype); return s; @@ -489,7 +489,7 @@ static struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base, omap_timer_clk_setup(&s->timer); iomemtype = cpu_register_io_memory(omap_os_timer_readfn, - omap_os_timer_writefn, s); + omap_os_timer_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x800, iomemtype); return s; @@ -716,7 +716,7 @@ static void omap_ulpd_pm_init(target_phys_addr_t base, struct omap_mpu_state_s *mpu) { int iomemtype = cpu_register_io_memory(omap_ulpd_pm_readfn, - omap_ulpd_pm_writefn, mpu); + omap_ulpd_pm_writefn, mpu, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x800, iomemtype); omap_ulpd_pm_reset(mpu); @@ -931,7 +931,7 @@ static void omap_pin_cfg_init(target_phys_addr_t base, struct omap_mpu_state_s *mpu) { int iomemtype = cpu_register_io_memory(omap_pin_cfg_readfn, - omap_pin_cfg_writefn, mpu); + omap_pin_cfg_writefn, mpu, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x800, iomemtype); omap_pin_cfg_reset(mpu); @@ -1001,7 +1001,7 @@ static CPUWriteMemoryFunc * const omap_id_writefn[] = { static void omap_id_init(struct omap_mpu_state_s *mpu) { int iomemtype = cpu_register_io_memory(omap_id_readfn, - omap_id_writefn, mpu); + omap_id_writefn, mpu, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory_offset(0xfffe1800, 0x800, iomemtype, 0xfffe1800); cpu_register_physical_memory_offset(0xfffed400, 0x100, iomemtype, 0xfffed400); if (!cpu_is_omap15xx(mpu)) @@ -1084,7 +1084,7 @@ static void omap_mpui_init(target_phys_addr_t base, struct omap_mpu_state_s *mpu) { int iomemtype = cpu_register_io_memory(omap_mpui_readfn, - omap_mpui_writefn, mpu); + omap_mpui_writefn, mpu, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x100, iomemtype); @@ -1193,7 +1193,7 @@ static struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base, omap_tipb_bridge_reset(s); iomemtype = cpu_register_io_memory(omap_tipb_bridge_readfn, - omap_tipb_bridge_writefn, s); + omap_tipb_bridge_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x100, iomemtype); return s; @@ -1299,7 +1299,7 @@ static void omap_tcmi_init(target_phys_addr_t base, struct omap_mpu_state_s *mpu) { int iomemtype = cpu_register_io_memory(omap_tcmi_readfn, - omap_tcmi_writefn, mpu); + omap_tcmi_writefn, mpu, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x100, iomemtype); omap_tcmi_reset(mpu); @@ -1372,7 +1372,7 @@ static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base, omap_clk clk) { int iomemtype = cpu_register_io_memory(omap_dpll_readfn, - omap_dpll_writefn, s); + omap_dpll_writefn, s, DEVICE_NATIVE_ENDIAN); s->dpll = clk; omap_dpll_reset(s); @@ -1776,8 +1776,10 @@ static void omap_clkm_init(target_phys_addr_t mpu_base, target_phys_addr_t dsp_base, struct omap_mpu_state_s *s) { int iomemtype[2] = { - cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s), - cpu_register_io_memory(omap_clkdsp_readfn, omap_clkdsp_writefn, s), + cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s, + DEVICE_NATIVE_ENDIAN), + cpu_register_io_memory(omap_clkdsp_readfn, omap_clkdsp_writefn, s, + DEVICE_NATIVE_ENDIAN), }; s->clkm.arm_idlect1 = 0x03ff; @@ -2031,7 +2033,7 @@ struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base, omap_mpuio_reset(s); iomemtype = cpu_register_io_memory(omap_mpuio_readfn, - omap_mpuio_writefn, s); + omap_mpuio_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x800, iomemtype); omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]); @@ -2216,7 +2218,7 @@ struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base, omap_uwire_reset(s); iomemtype = cpu_register_io_memory(omap_uwire_readfn, - omap_uwire_writefn, s); + omap_uwire_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x800, iomemtype); return s; @@ -2317,7 +2319,7 @@ static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s, omap_pwl_reset(s); iomemtype = cpu_register_io_memory(omap_pwl_readfn, - omap_pwl_writefn, s); + omap_pwl_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x800, iomemtype); omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]); @@ -2412,7 +2414,7 @@ static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s, omap_pwt_reset(s); iomemtype = cpu_register_io_memory(omap_pwt_readfn, - omap_pwt_writefn, s); + omap_pwt_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x800, iomemtype); } @@ -2825,7 +2827,7 @@ static struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base, omap_rtc_reset(s); iomemtype = cpu_register_io_memory(omap_rtc_readfn, - omap_rtc_writefn, s); + omap_rtc_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x800, iomemtype); return s; @@ -3347,7 +3349,7 @@ struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base, omap_mcbsp_reset(s); iomemtype = cpu_register_io_memory(omap_mcbsp_readfn, - omap_mcbsp_writefn, s); + omap_mcbsp_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x800, iomemtype); return s; @@ -3519,7 +3521,7 @@ static struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk) omap_lpg_reset(s); iomemtype = cpu_register_io_memory(omap_lpg_readfn, - omap_lpg_writefn, s); + omap_lpg_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x800, iomemtype); omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]); @@ -3552,7 +3554,7 @@ static CPUWriteMemoryFunc * const omap_mpui_io_writefn[] = { static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu) { int iomemtype = cpu_register_io_memory(omap_mpui_io_readfn, - omap_mpui_io_writefn, mpu); + omap_mpui_io_writefn, mpu, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype); } diff --git a/hw/omap2.c b/hw/omap2.c index e35a56e04..0f13272c7 100644 --- a/hw/omap2.c +++ b/hw/omap2.c @@ -600,7 +600,7 @@ static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta, AUD_register_card("OMAP EAC", &s->codec.card); iomemtype = cpu_register_io_memory(omap_eac_readfn, - omap_eac_writefn, s); + omap_eac_writefn, s, DEVICE_NATIVE_ENDIAN); omap_l4_attach(ta, 0, iomemtype); return s; @@ -788,7 +788,7 @@ static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta, omap_l4_attach(ta, 0, iomemtype); iomemtype = cpu_register_io_memory(omap_sti_fifo_readfn, - omap_sti_fifo_writefn, s); + omap_sti_fifo_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(channel_base, 0x10000, iomemtype); return s; diff --git a/hw/omap_dma.c b/hw/omap_dma.c index 3e718ba7f..8e2dcc90c 100644 --- a/hw/omap_dma.c +++ b/hw/omap_dma.c @@ -1659,7 +1659,7 @@ struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs, omap_dma_clk_update(s, 0, 1); iomemtype = cpu_register_io_memory(omap_dma_readfn, - omap_dma_writefn, s); + omap_dma_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, memsize, iomemtype); mpu->drq = s->dma->drq; @@ -2066,7 +2066,7 @@ struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs, omap_dma_clk_update(s, 0, !!s->dma->freq); iomemtype = cpu_register_io_memory(omap_dma4_readfn, - omap_dma4_writefn, s); + omap_dma4_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x1000, iomemtype); mpu->drq = s->dma->drq; diff --git a/hw/omap_dss.c b/hw/omap_dss.c index 044f2d242..afe287a43 100644 --- a/hw/omap_dss.c +++ b/hw/omap_dss.c @@ -1045,7 +1045,7 @@ struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, iomemtype[3] = l4_register_io_memory(omap_venc1_readfn, omap_venc1_writefn, s); iomemtype[4] = cpu_register_io_memory(omap_im3_readfn, - omap_im3_writefn, s); + omap_im3_writefn, s, DEVICE_NATIVE_ENDIAN); omap_l4_attach(ta, 0, iomemtype[0]); omap_l4_attach(ta, 1, iomemtype[1]); omap_l4_attach(ta, 2, iomemtype[2]); diff --git a/hw/omap_gpio.c b/hw/omap_gpio.c index d978c7abf..478f7d982 100644 --- a/hw/omap_gpio.c +++ b/hw/omap_gpio.c @@ -183,7 +183,7 @@ struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base, omap_gpio_reset(s); iomemtype = cpu_register_io_memory(omap_gpio_readfn, - omap_gpio_writefn, s); + omap_gpio_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x1000, iomemtype); return s; diff --git a/hw/omap_gpmc.c b/hw/omap_gpmc.c index 72cfeccf6..8bf3343a6 100644 --- a/hw/omap_gpmc.c +++ b/hw/omap_gpmc.c @@ -390,7 +390,7 @@ struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq) omap_gpmc_reset(s); iomemtype = cpu_register_io_memory(omap_gpmc_readfn, - omap_gpmc_writefn, s); + omap_gpmc_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x1000, iomemtype); return s; diff --git a/hw/omap_i2c.c b/hw/omap_i2c.c index d133977e7..5cabb5a7b 100644 --- a/hw/omap_i2c.c +++ b/hw/omap_i2c.c @@ -437,7 +437,7 @@ struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base, omap_i2c_reset(s); iomemtype = cpu_register_io_memory(omap_i2c_readfn, - omap_i2c_writefn, s); + omap_i2c_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x800, iomemtype); return s; diff --git a/hw/omap_intc.c b/hw/omap_intc.c index 59893b7ad..001e20b9d 100644 --- a/hw/omap_intc.c +++ b/hw/omap_intc.c @@ -371,7 +371,7 @@ struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base, omap_inth_reset(s); iomemtype = cpu_register_io_memory(omap_inth_readfn, - omap_inth_writefn, s); + omap_inth_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, size, iomemtype); return s; @@ -591,7 +591,7 @@ struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base, omap_inth_reset(s); iomemtype = cpu_register_io_memory(omap2_inth_readfn, - omap2_inth_writefn, s); + omap2_inth_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, size, iomemtype); return s; diff --git a/hw/omap_l4.c b/hw/omap_l4.c index bf8ba36e9..4af0ca8ea 100644 --- a/hw/omap_l4.c +++ b/hw/omap_l4.c @@ -107,7 +107,8 @@ int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read, CPUWriteMemoryFunc * const *mem_write, void *opaque) { - return cpu_register_io_memory(mem_read, mem_write, opaque); + return cpu_register_io_memory(mem_read, mem_write, opaque, + DEVICE_NATIVE_ENDIAN); } #endif @@ -131,7 +132,7 @@ struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num) omap_cpu_io_entry = cpu_register_io_memory(omap_l4_io_readfn, - omap_l4_io_writefn, bus); + omap_l4_io_writefn, bus, DEVICE_NATIVE_ENDIAN); # define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE) omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); omap_l4_io_readh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); diff --git a/hw/omap_lcdc.c b/hw/omap_lcdc.c index 6affef67b..0c2c55012 100644 --- a/hw/omap_lcdc.c +++ b/hw/omap_lcdc.c @@ -450,7 +450,7 @@ struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq, omap_lcdc_reset(s); iomemtype = cpu_register_io_memory(omap_lcdc_readfn, - omap_lcdc_writefn, s); + omap_lcdc_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x100, iomemtype); s->state = graphic_console_init(omap_update_display, diff --git a/hw/omap_mmc.c b/hw/omap_mmc.c index 9d167ff53..e9ec2f398 100644 --- a/hw/omap_mmc.c +++ b/hw/omap_mmc.c @@ -587,7 +587,7 @@ struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base, omap_mmc_reset(s); iomemtype = cpu_register_io_memory(omap_mmc_readfn, - omap_mmc_writefn, s); + omap_mmc_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x800, iomemtype); /* Instantiate the storage */ diff --git a/hw/omap_sdrc.c b/hw/omap_sdrc.c index aefaebe04..e18376260 100644 --- a/hw/omap_sdrc.c +++ b/hw/omap_sdrc.c @@ -158,7 +158,7 @@ struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base) omap_sdrc_reset(s); iomemtype = cpu_register_io_memory(omap_sdrc_readfn, - omap_sdrc_writefn, s); + omap_sdrc_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x1000, iomemtype); return s; diff --git a/hw/omap_sx1.c b/hw/omap_sx1.c index 44dc514f3..06bccbdc4 100644 --- a/hw/omap_sx1.c +++ b/hw/omap_sx1.c @@ -143,12 +143,15 @@ static void sx1_init(ram_addr_t ram_size, qemu_ram_alloc(NULL, "omap_sx1.flash0-0", flash_size) | IO_MEM_ROM); - io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val); + io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(OMAP_CS0_BASE + flash_size, OMAP_CS0_SIZE - flash_size, io); - io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val); + io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io); - io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val); + io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io); fl_idx = 0; @@ -175,7 +178,8 @@ static void sx1_init(ram_addr_t ram_size, cpu_register_physical_memory(OMAP_CS1_BASE, flash1_size, qemu_ram_alloc(NULL, "omap_sx1.flash1-0", flash1_size) | IO_MEM_ROM); - io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val); + io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size, OMAP_CS1_SIZE - flash1_size, io); @@ -189,7 +193,8 @@ static void sx1_init(ram_addr_t ram_size, } fl_idx++; } else { - io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val); + io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io); } diff --git a/hw/omap_uart.c b/hw/omap_uart.c index cc66cd9d9..9cee81d7c 100644 --- a/hw/omap_uart.c +++ b/hw/omap_uart.c @@ -170,7 +170,7 @@ struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta, struct omap_uart_s *s = omap_uart_init(base, irq, fclk, iclk, txdma, rxdma, label, chr); int iomemtype = cpu_register_io_memory(omap_uart_readfn, - omap_uart_writefn, s); + omap_uart_writefn, s, DEVICE_NATIVE_ENDIAN); s->ta = ta; diff --git a/hw/onenand.c b/hw/onenand.c index f7afecaaa..d9cdcf294 100644 --- a/hw/onenand.c +++ b/hw/onenand.c @@ -630,7 +630,7 @@ void *onenand_init(uint32_t id, int regshift, qemu_irq irq) s->blockwp = qemu_malloc(s->blocks); s->density_mask = (id & (1 << 11)) ? (1 << (6 + ((id >> 12) & 7))) : 0; s->iomemtype = cpu_register_io_memory(onenand_readfn, - onenand_writefn, s); + onenand_writefn, s, DEVICE_NATIVE_ENDIAN); if (!dinfo) s->image = memset(qemu_malloc(size + (size >> 5)), 0xff, size + (size >> 5)); diff --git a/hw/openpic.c b/hw/openpic.c index f6b8f2127..9e2500ae3 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -1035,7 +1035,8 @@ static void openpic_map(PCIDevice *pci_dev, int region_num, cpu_register_physical_memory(addr, 0x40000, opp->mem_index); #if 0 // Don't implement ISU for now opp_io_memory = cpu_register_io_memory(openpic_src_read, - openpic_src_write); + openpic_src_write, NULL + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(isu_base, 0x20 * (EXT_IRQ + 2), opp_io_memory); #endif @@ -1202,8 +1203,8 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, } else { opp = qemu_mallocz(sizeof(openpic_t)); } - opp->mem_index = cpu_register_io_memory(openpic_read, - openpic_write, opp); + opp->mem_index = cpu_register_io_memory(openpic_read, openpic_write, opp, + DEVICE_NATIVE_ENDIAN); // isu_base &= 0xFFFC0000; opp->nb_cpus = nb_cpus; @@ -1671,7 +1672,8 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus, for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) { int mem_index; - mem_index = cpu_register_io_memory(list[i].read, list[i].write, mpp); + mem_index = cpu_register_io_memory(list[i].read, list[i].write, mpp, + DEVICE_NATIVE_ENDIAN); if (mem_index < 0) { goto free; } @@ -216,14 +216,18 @@ static void palmte_init(ram_addr_t ram_size, qemu_ram_alloc(NULL, "palmte.flash", flash_size) | IO_MEM_ROM); - io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val); + io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(OMAP_CS0_BASE + flash_size, OMAP_CS0_SIZE - flash_size, io); - io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val); + io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io); - io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val); + io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io); - io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val); + io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io); palmte_microwire_setup(cpu); diff --git a/hw/parallel.c b/hw/parallel.c index 6b11672e1..00005c431 100644 --- a/hw/parallel.c +++ b/hw/parallel.c @@ -577,7 +577,8 @@ ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq s->it_shift = it_shift; qemu_register_reset(parallel_reset, s); - io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw, s); + io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw, + s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 8 << it_shift, io_sw); return s; } diff --git a/hw/pcie_host.c b/hw/pcie_host.c index c4feecad7..21069eed8 100644 --- a/hw/pcie_host.c +++ b/hw/pcie_host.c @@ -137,7 +137,8 @@ int pcie_host_init(PCIExpressHost *e) { e->base_addr = PCIE_BASE_ADDR_UNMAPPED; e->mmio_index = - cpu_register_io_memory(pcie_mmcfg_read, pcie_mmcfg_write, e); + cpu_register_io_memory(pcie_mmcfg_read, pcie_mmcfg_write, e, + DEVICE_NATIVE_ENDIAN); if (e->mmio_index < 0) { return -1; } diff --git a/hw/pckbd.c b/hw/pckbd.c index 6e4e4062a..7f0e6bbb3 100644 --- a/hw/pckbd.c +++ b/hw/pckbd.c @@ -436,7 +436,8 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, s->mask = mask; vmstate_register(NULL, 0, &vmstate_kbd, s); - s_io_memory = cpu_register_io_memory(kbd_mm_read, kbd_mm_write, s); + s_io_memory = cpu_register_io_memory(kbd_mm_read, kbd_mm_write, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, size, s_io_memory); s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s); diff --git a/hw/pcnet-pci.c b/hw/pcnet-pci.c index 3dfbe4647..5c5bd213e 100644 --- a/hw/pcnet-pci.c +++ b/hw/pcnet-pci.c @@ -294,7 +294,8 @@ static int pci_pcnet_init(PCIDevice *pci_dev) /* Handler for memory-mapped I/O */ s->mmio_index = - cpu_register_io_memory(pcnet_mmio_read, pcnet_mmio_write, &d->state); + cpu_register_io_memory(pcnet_mmio_read, pcnet_mmio_write, &d->state, + DEVICE_NATIVE_ENDIAN); pci_register_bar(pci_dev, 0, PCNET_IOPORT_SIZE, PCI_BASE_ADDRESS_SPACE_IO, pcnet_ioport_map); diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c index 19e13d632..fb20dfb6f 100644 --- a/hw/pflash_cfi01.c +++ b/hw/pflash_cfi01.c @@ -600,10 +600,12 @@ pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off, pfl->storage = qemu_get_ram_ptr(off); if (be) { pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be, - pflash_write_ops_be, pfl); + pflash_write_ops_be, pfl, + DEVICE_NATIVE_ENDIAN); } else { pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le, - pflash_write_ops_le, pfl); + pflash_write_ops_le, pfl, + DEVICE_NATIVE_ENDIAN); } pfl->off = off; cpu_register_physical_memory(base, total_len, diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c index f3d3f41a9..3594a36f8 100644 --- a/hw/pflash_cfi02.c +++ b/hw/pflash_cfi02.c @@ -619,11 +619,11 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, if (be) { pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be, pflash_write_ops_be, - pfl); + pfl, DEVICE_NATIVE_ENDIAN); } else { pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le, pflash_write_ops_le, - pfl); + pfl, DEVICE_NATIVE_ENDIAN); } pfl->off = off; pfl->base = base; diff --git a/hw/pl011.c b/hw/pl011.c index 02cf84aee..77f0dbf13 100644 --- a/hw/pl011.c +++ b/hw/pl011.c @@ -292,7 +292,8 @@ static int pl011_init(SysBusDevice *dev, const unsigned char *id) pl011_state *s = FROM_SYSBUS(pl011_state, dev); iomemtype = cpu_register_io_memory(pl011_readfn, - pl011_writefn, s); + pl011_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000,iomemtype); sysbus_init_irq(dev, &s->irq); s->id = id; diff --git a/hw/pl022.c b/hw/pl022.c index d7862bc69..ffe05ab74 100644 --- a/hw/pl022.c +++ b/hw/pl022.c @@ -294,7 +294,8 @@ static int pl022_init(SysBusDevice *dev) int iomemtype; iomemtype = cpu_register_io_memory(pl022_readfn, - pl022_writefn, s); + pl022_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); sysbus_init_irq(dev, &s->irq); s->ssi = ssi_create_bus(&dev->qdev, "ssi"); diff --git a/hw/pl031.c b/hw/pl031.c index 45b7032c5..e3700c169 100644 --- a/hw/pl031.c +++ b/hw/pl031.c @@ -189,7 +189,8 @@ static int pl031_init(SysBusDevice *dev) pl031_state *s = FROM_SYSBUS(pl031_state, dev); struct tm tm; - iomemtype = cpu_register_io_memory(pl031_readfn, pl031_writefn, s); + iomemtype = cpu_register_io_memory(pl031_readfn, pl031_writefn, s, + DEVICE_NATIVE_ENDIAN); if (iomemtype == -1) { hw_error("pl031_init: Can't register I/O memory\n"); } diff --git a/hw/pl050.c b/hw/pl050.c index a47786cb0..057383985 100644 --- a/hw/pl050.c +++ b/hw/pl050.c @@ -128,7 +128,8 @@ static int pl050_init(SysBusDevice *dev, int is_mouse) int iomemtype; iomemtype = cpu_register_io_memory(pl050_readfn, - pl050_writefn, s); + pl050_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); sysbus_init_irq(dev, &s->irq); s->is_mouse = is_mouse; diff --git a/hw/pl061.c b/hw/pl061.c index e4505f5cb..1997b7cd2 100644 --- a/hw/pl061.c +++ b/hw/pl061.c @@ -297,7 +297,8 @@ static int pl061_init(SysBusDevice *dev) pl061_state *s = FROM_SYSBUS(pl061_state, dev); iomemtype = cpu_register_io_memory(pl061_readfn, - pl061_writefn, s); + pl061_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); sysbus_init_irq(dev, &s->irq); qdev_init_gpio_in(&dev->qdev, pl061_set_irq, 8); diff --git a/hw/pl080.c b/hw/pl080.c index 2df65fab9..1a3e06c92 100644 --- a/hw/pl080.c +++ b/hw/pl080.c @@ -325,7 +325,8 @@ static int pl08x_init(SysBusDevice *dev, int nchannels) pl080_state *s = FROM_SYSBUS(pl080_state, dev); iomemtype = cpu_register_io_memory(pl080_readfn, - pl080_writefn, s); + pl080_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); sysbus_init_irq(dev, &s->irq); s->nchannels = nchannels; diff --git a/hw/pl110.c b/hw/pl110.c index 173458a7c..a4adb630b 100644 --- a/hw/pl110.c +++ b/hw/pl110.c @@ -358,7 +358,8 @@ static int pl110_init(SysBusDevice *dev) int iomemtype; iomemtype = cpu_register_io_memory(pl110_readfn, - pl110_writefn, s); + pl110_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); sysbus_init_irq(dev, &s->irq); s->ds = graphic_console_init(pl110_update_display, diff --git a/hw/pl181.c b/hw/pl181.c index 85cadc4fe..3e5f92f0e 100644 --- a/hw/pl181.c +++ b/hw/pl181.c @@ -451,8 +451,8 @@ static int pl181_init(SysBusDevice *dev) pl181_state *s = FROM_SYSBUS(pl181_state, dev); BlockDriverState *bd; - iomemtype = cpu_register_io_memory(pl181_readfn, - pl181_writefn, s); + iomemtype = cpu_register_io_memory(pl181_readfn, pl181_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); sysbus_init_irq(dev, &s->irq[0]); sysbus_init_irq(dev, &s->irq[1]); diff --git a/hw/pl190.c b/hw/pl190.c index a4bc9c15e..e04e6c17f 100644 --- a/hw/pl190.c +++ b/hw/pl190.c @@ -233,7 +233,8 @@ static int pl190_init(SysBusDevice *dev) int iomemtype; iomemtype = cpu_register_io_memory(pl190_readfn, - pl190_writefn, s); + pl190_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); qdev_init_gpio_in(&dev->qdev, pl190_set_irq, 32); sysbus_init_irq(dev, &s->irq); diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c index c5897a9d4..9abede7e0 100644 --- a/hw/ppc405_boards.c +++ b/hw/ppc405_boards.c @@ -164,7 +164,8 @@ static void ref405ep_fpga_init (uint32_t base) fpga = qemu_mallocz(sizeof(ref405ep_fpga_t)); fpga_memory = cpu_register_io_memory(ref405ep_fpga_read, - ref405ep_fpga_write, fpga); + ref405ep_fpga_write, fpga, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x00000100, fpga_memory); qemu_register_reset(&ref405ep_fpga_reset, fpga); } @@ -488,7 +489,8 @@ static void taihu_cpld_init (uint32_t base) cpld = qemu_mallocz(sizeof(taihu_cpld_t)); cpld_memory = cpu_register_io_memory(taihu_cpld_read, - taihu_cpld_write, cpld); + taihu_cpld_write, cpld, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x00000100, cpld_memory); qemu_register_reset(&taihu_cpld_reset, cpld); } diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c index 360073741..8136cb962 100644 --- a/hw/ppc405_uc.c +++ b/hw/ppc405_uc.c @@ -383,7 +383,8 @@ static void ppc4xx_opba_init(target_phys_addr_t base) #ifdef DEBUG_OPBA printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); #endif - io = cpu_register_io_memory(opba_read, opba_write, opba); + io = cpu_register_io_memory(opba_read, opba_write, opba, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x002, io); qemu_register_reset(ppc4xx_opba_reset, opba); } @@ -809,7 +810,8 @@ static void ppc405_gpio_init(target_phys_addr_t base) #ifdef DEBUG_GPIO printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); #endif - io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio); + io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x038, io); qemu_register_reset(&ppc405_gpio_reset, gpio); } @@ -1218,7 +1220,8 @@ static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq) #ifdef DEBUG_I2C printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); #endif - io = cpu_register_io_memory(i2c_read, i2c_write, i2c); + io = cpu_register_io_memory(i2c_read, i2c_write, i2c, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x011, io); qemu_register_reset(ppc4xx_i2c_reset, i2c); } @@ -1501,7 +1504,7 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5]) #ifdef DEBUG_GPT printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); #endif - io = cpu_register_io_memory(gpt_read, gpt_write, gpt); + io = cpu_register_io_memory(gpt_read, gpt_write, gpt, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x0d4, io); qemu_register_reset(ppc4xx_gpt_reset, gpt); } diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c index 6e437e754..f2ececec5 100644 --- a/hw/ppc4xx_pci.c +++ b/hw/ppc4xx_pci.c @@ -372,7 +372,8 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], /* CFGADDR */ index = cpu_register_io_memory(pci4xx_cfgaddr_read, - pci4xx_cfgaddr_write, controller); + pci4xx_cfgaddr_write, controller, + DEVICE_NATIVE_ENDIAN); if (index < 0) goto free; cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index); @@ -384,7 +385,8 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index); /* Internal registers */ - index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller); + index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller, + DEVICE_NATIVE_ENDIAN); if (index < 0) goto free; cpu_register_physical_memory(registers, PCI_REG_SIZE, index); diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c index 305b2d45e..49b046b26 100644 --- a/hw/ppc_newworld.c +++ b/hw/ppc_newworld.c @@ -260,7 +260,8 @@ static void ppc_core99_init (ram_addr_t ram_size, isa_mmio_init(0xf2000000, 0x00800000, 1); /* UniN init */ - unin_memory = cpu_register_io_memory(unin_read, unin_write, NULL); + unin_memory = cpu_register_io_memory(unin_read, unin_write, NULL, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory); openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *)); diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index b1f9cc74f..80f5db6ac 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -690,7 +690,8 @@ static void ppc_prep_init (ram_addr_t ram_size, // pci_bus = i440fx_init(); /* Register 8 MB of ISA IO space (needed for non-contiguous map) */ PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read, - PPC_prep_io_write, sysctrl); + PPC_prep_io_write, sysctrl, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory); /* init basic PC hardware */ @@ -755,12 +756,13 @@ static void ppc_prep_init (ram_addr_t ram_size, register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); /* PCI intack location */ PPC_io_memory = cpu_register_io_memory(PPC_intack_read, - PPC_intack_write, NULL); + PPC_intack_write, NULL, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); /* PowerPC control and status register group */ #if 0 PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write, - NULL); + NULL, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory); #endif diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c index 8ac99f281..71302ba70 100644 --- a/hw/ppce500_pci.c +++ b/hw/ppce500_pci.c @@ -304,7 +304,8 @@ PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers) cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index); index = cpu_register_io_memory(e500_pci_reg_read, - e500_pci_reg_write, controller); + e500_pci_reg_write, controller, + DEVICE_NATIVE_ENDIAN); if (index < 0) goto free; cpu_register_physical_memory(registers + PCIE500_REG_BASE, diff --git a/hw/prep_pci.c b/hw/prep_pci.c index 0c2afe9c8..f88b8254c 100644 --- a/hw/prep_pci.c +++ b/hw/prep_pci.c @@ -125,7 +125,8 @@ PCIBus *pci_prep_init(qemu_irq *pic) pci_host_data_register_ioport(0xcfc, s); PPC_io_memory = cpu_register_io_memory(PPC_PCIIO_read, - PPC_PCIIO_write, s); + PPC_PCIIO_write, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory); /* PCI host bridge */ diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c index 6e046450d..ab524a779 100644 --- a/hw/pxa2xx.c +++ b/hw/pxa2xx.c @@ -859,7 +859,8 @@ static int pxa2xx_ssp_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->irq); iomemtype = cpu_register_io_memory(pxa2xx_ssp_readfn, - pxa2xx_ssp_writefn, s); + pxa2xx_ssp_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0, pxa2xx_ssp_save, pxa2xx_ssp_load, s); @@ -1512,7 +1513,7 @@ PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base, s->offset = base - (base & (~region_size) & TARGET_PAGE_MASK); iomemtype = cpu_register_io_memory(pxa2xx_i2c_readfn, - pxa2xx_i2c_writefn, s); + pxa2xx_i2c_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base & ~region_size, region_size + 1, iomemtype); @@ -1749,7 +1750,7 @@ static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base, pxa2xx_i2s_reset(s); iomemtype = cpu_register_io_memory(pxa2xx_i2s_readfn, - pxa2xx_i2s_writefn, s); + pxa2xx_i2s_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x100000, iomemtype); register_savevm(NULL, "pxa2xx_i2s", base, 0, @@ -2009,7 +2010,7 @@ static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base, pxa2xx_fir_reset(s); iomemtype = cpu_register_io_memory(pxa2xx_fir_readfn, - pxa2xx_fir_writefn, s); + pxa2xx_fir_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x1000, iomemtype); if (chr) @@ -2102,7 +2103,7 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision) s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ s->clkcfg = 0x00000009; /* Turbo mode active */ iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn, - pxa2xx_cm_writefn, s); + pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype); register_savevm(NULL, "pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s); @@ -2113,13 +2114,13 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision) s->mm_regs[MDREFR >> 2] = 0x03ca4000; s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn, - pxa2xx_mm_writefn, s); + pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype); register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s); s->pm_base = 0x40f00000; iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn, - pxa2xx_pm_writefn, s); + pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(s->pm_base, 0x100, iomemtype); register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s); @@ -2142,7 +2143,7 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision) s->rtc_base = 0x40900000; iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn, - pxa2xx_rtc_writefn, s); + pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype); pxa2xx_rtc_init(s); register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, @@ -2225,7 +2226,7 @@ PXA2xxState *pxa255_init(unsigned int sdram_size) s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ s->clkcfg = 0x00000009; /* Turbo mode active */ iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn, - pxa2xx_cm_writefn, s); + pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype); register_savevm(NULL, "pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s); @@ -2236,13 +2237,13 @@ PXA2xxState *pxa255_init(unsigned int sdram_size) s->mm_regs[MDREFR >> 2] = 0x03ca4000; s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn, - pxa2xx_mm_writefn, s); + pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype); register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s); s->pm_base = 0x40f00000; iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn, - pxa2xx_pm_writefn, s); + pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(s->pm_base, 0x100, iomemtype); register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s); @@ -2265,7 +2266,7 @@ PXA2xxState *pxa255_init(unsigned int sdram_size) s->rtc_base = 0x40900000; iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn, - pxa2xx_rtc_writefn, s); + pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype); pxa2xx_rtc_init(s); register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, diff --git a/hw/pxa2xx_dma.c b/hw/pxa2xx_dma.c index 9c479df04..b512d3450 100644 --- a/hw/pxa2xx_dma.c +++ b/hw/pxa2xx_dma.c @@ -504,7 +504,7 @@ static PXA2xxDMAState *pxa2xx_dma_init(target_phys_addr_t base, memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS); iomemtype = cpu_register_io_memory(pxa2xx_dma_readfn, - pxa2xx_dma_writefn, s); + pxa2xx_dma_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x00010000, iomemtype); register_savevm(NULL, "pxa2xx_dma", 0, 0, pxa2xx_dma_save, pxa2xx_dma_load, s); diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c index 2abcb6543..0d034462d 100644 --- a/hw/pxa2xx_gpio.c +++ b/hw/pxa2xx_gpio.c @@ -309,7 +309,7 @@ PXA2xxGPIOInfo *pxa2xx_gpio_init(target_phys_addr_t base, s->in = qemu_allocate_irqs(pxa2xx_gpio_set, s, lines); iomemtype = cpu_register_io_memory(pxa2xx_gpio_readfn, - pxa2xx_gpio_writefn, s); + pxa2xx_gpio_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x00001000, iomemtype); register_savevm(NULL, "pxa2xx_gpio", 0, 0, diff --git a/hw/pxa2xx_keypad.c b/hw/pxa2xx_keypad.c index dfa8945b2..4c999171b 100644 --- a/hw/pxa2xx_keypad.c +++ b/hw/pxa2xx_keypad.c @@ -314,7 +314,7 @@ PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base, s->irq = irq; iomemtype = cpu_register_io_memory(pxa2xx_keypad_readfn, - pxa2xx_keypad_writefn, s); + pxa2xx_keypad_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x00100000, iomemtype); register_savevm(NULL, "pxa2xx_keypad", 0, 0, diff --git a/hw/pxa2xx_lcd.c b/hw/pxa2xx_lcd.c index 111a0dc03..1f2211a2f 100644 --- a/hw/pxa2xx_lcd.c +++ b/hw/pxa2xx_lcd.c @@ -929,7 +929,7 @@ PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq) pxa2xx_lcdc_orientation(s, graphic_rotate); iomemtype = cpu_register_io_memory(pxa2xx_lcdc_readfn, - pxa2xx_lcdc_writefn, s); + pxa2xx_lcdc_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x00100000, iomemtype); s->ds = graphic_console_init(pxa2xx_update_display, diff --git a/hw/pxa2xx_mmci.c b/hw/pxa2xx_mmci.c index ca9866022..24d409d1a 100644 --- a/hw/pxa2xx_mmci.c +++ b/hw/pxa2xx_mmci.c @@ -528,7 +528,7 @@ PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base, s->dma = dma; iomemtype = cpu_register_io_memory(pxa2xx_mmci_readfn, - pxa2xx_mmci_writefn, s); + pxa2xx_mmci_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x00100000, iomemtype); /* Instantiate the actual storage */ diff --git a/hw/pxa2xx_pcmcia.c b/hw/pxa2xx_pcmcia.c index be1309f62..50d4649f6 100644 --- a/hw/pxa2xx_pcmcia.c +++ b/hw/pxa2xx_pcmcia.c @@ -140,19 +140,19 @@ PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base) /* Socket I/O Memory Space */ iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_io_readfn, - pxa2xx_pcmcia_io_writefn, s); + pxa2xx_pcmcia_io_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base | 0x00000000, 0x04000000, iomemtype); /* Then next 64 MB is reserved */ /* Socket Attribute Memory Space */ iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_attr_readfn, - pxa2xx_pcmcia_attr_writefn, s); + pxa2xx_pcmcia_attr_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base | 0x08000000, 0x04000000, iomemtype); /* Socket Common Memory Space */ iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_common_readfn, - pxa2xx_pcmcia_common_writefn, s); + pxa2xx_pcmcia_common_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base | 0x0c000000, 0x04000000, iomemtype); if (base == 0x30000000) diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c index 4d8944bfc..a36da233d 100644 --- a/hw/pxa2xx_pic.c +++ b/hw/pxa2xx_pic.c @@ -300,7 +300,7 @@ qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env) /* Enable IC memory-mapped registers access. */ iomemtype = cpu_register_io_memory(pxa2xx_pic_readfn, - pxa2xx_pic_writefn, s); + pxa2xx_pic_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x00100000, iomemtype); /* Enable IC coprocessor access. */ diff --git a/hw/pxa2xx_timer.c b/hw/pxa2xx_timer.c index 0f0ffd3f3..b556d1187 100644 --- a/hw/pxa2xx_timer.c +++ b/hw/pxa2xx_timer.c @@ -452,7 +452,7 @@ static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base, } iomemtype = cpu_register_io_memory(pxa2xx_timer_readfn, - pxa2xx_timer_writefn, s); + pxa2xx_timer_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x00001000, iomemtype); register_savevm(NULL, "pxa2xx_timer", 0, 0, @@ -189,7 +189,8 @@ static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl) s->irl = irl; iomemtype = cpu_register_io_memory(r2d_fpga_readfn, - r2d_fpga_writefn, s); + r2d_fpga_writefn, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x40, iomemtype); return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS); } diff --git a/hw/rc4030.c b/hw/rc4030.c index abbc3eb4e..0a9d98d1d 100644 --- a/hw/rc4030.c +++ b/hw/rc4030.c @@ -819,9 +819,11 @@ void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus, register_savevm(NULL, "rc4030", 0, 2, rc4030_save, rc4030_load, s); rc4030_reset(s); - s_chipset = cpu_register_io_memory(rc4030_read, rc4030_write, s); + s_chipset = cpu_register_io_memory(rc4030_read, rc4030_write, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(0x80000000, 0x300, s_chipset); - s_jazzio = cpu_register_io_memory(jazzio_read, jazzio_write, s); + s_jazzio = cpu_register_io_memory(jazzio_read, jazzio_write, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(0xf0000000, 0x00001000, s_jazzio); return s; diff --git a/hw/realview.c b/hw/realview.c index e9fcbc9a6..6eb6c6a1f 100644 --- a/hw/realview.c +++ b/hw/realview.c @@ -81,7 +81,8 @@ static int realview_i2c_init(SysBusDevice *dev) bus = i2c_init_bus(&dev->qdev, "i2c"); s->bitbang = bitbang_i2c_init(bus); iomemtype = cpu_register_io_memory(realview_i2c_readfn, - realview_i2c_writefn, s); + realview_i2c_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); return 0; } diff --git a/hw/realview_gic.c b/hw/realview_gic.c index bd02b095e..db908b643 100644 --- a/hw/realview_gic.c +++ b/hw/realview_gic.c @@ -64,7 +64,8 @@ static int realview_gic_init(SysBusDevice *dev) gic_init(&s->gic); s->iomemtype = cpu_register_io_memory(realview_gic_cpu_readfn, - realview_gic_cpu_writefn, s); + realview_gic_cpu_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio_cb(dev, 0x2000, realview_gic_map); return 0; } diff --git a/hw/rtl8139.c b/hw/rtl8139.c index d92981dc0..30a396013 100644 --- a/hw/rtl8139.c +++ b/hw/rtl8139.c @@ -3366,7 +3366,8 @@ static int pci_rtl8139_init(PCIDevice *dev) /* I/O handler for memory-mapped I/O */ s->rtl8139_mmio_io_addr = - cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s); + cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s, + DEVICE_NATIVE_ENDIAN); pci_register_bar(&s->dev, 0, 0x100, PCI_BASE_ADDRESS_SPACE_IO, rtl8139_ioport_map); @@ -125,7 +125,8 @@ static int sbi_init1(SysBusDevice *dev) sysbus_init_irq(dev, &s->cpu_irqs[i]); } - sbi_io_memory = cpu_register_io_memory(sbi_mem_read, sbi_mem_write, s); + sbi_io_memory = cpu_register_io_memory(sbi_mem_read, sbi_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, SBI_SIZE, sbi_io_memory); return 0; diff --git a/hw/serial.c b/hw/serial.c index 9ebc452ae..d21cbe9aa 100644 --- a/hw/serial.c +++ b/hw/serial.c @@ -955,10 +955,12 @@ SerialState *serial_mm_init (target_phys_addr_t base, int it_shift, if (ioregister) { if (be) { s_io_memory = cpu_register_io_memory(serial_mm_read_be, - serial_mm_write_be, s); + serial_mm_write_be, s, + DEVICE_NATIVE_ENDIAN); } else { s_io_memory = cpu_register_io_memory(serial_mm_read_le, - serial_mm_write_le, s); + serial_mm_write_le, s, + DEVICE_NATIVE_ENDIAN); } cpu_register_physical_memory(base, 8 << it_shift, s_io_memory); } diff --git a/hw/sh7750.c b/hw/sh7750.c index 0291d5fd4..9e54ad190 100644 --- a/hw/sh7750.c +++ b/hw/sh7750.c @@ -713,7 +713,8 @@ SH7750State *sh7750_init(CPUSH4State * cpu) s->cpu = cpu; s->periph_freq = 60000000; /* 60MHz */ sh7750_io_memory = cpu_register_io_memory(sh7750_mem_read, - sh7750_mem_write, s); + sh7750_mem_write, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory_offset(0x1f000000, 0x1000, sh7750_io_memory, 0x1f000000); cpu_register_physical_memory_offset(0xff000000, 0x1000, @@ -728,7 +729,8 @@ SH7750State *sh7750_init(CPUSH4State * cpu) sh7750_io_memory, 0x1fc00000); sh7750_mm_cache_and_tlb = cpu_register_io_memory(sh7750_mmct_read, - sh7750_mmct_write, s); + sh7750_mmct_write, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(0xf0000000, 0x08000000, sh7750_mm_cache_and_tlb); diff --git a/hw/sh_intc.c b/hw/sh_intc.c index d3f5ea57d..0734da90f 100644 --- a/hw/sh_intc.c +++ b/hw/sh_intc.c @@ -442,7 +442,8 @@ int sh_intc_init(struct intc_desc *desc, desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources); desc->iomemtype = cpu_register_io_memory(sh_intc_readfn, - sh_intc_writefn, desc); + sh_intc_writefn, desc, + DEVICE_NATIVE_ENDIAN); if (desc->mask_regs) { for (i = 0; i < desc->nr_mask_regs; i++) { struct intc_mask_reg *mr = desc->mask_regs + i; diff --git a/hw/sh_pci.c b/hw/sh_pci.c index cc2f19052..6042d9c15 100644 --- a/hw/sh_pci.c +++ b/hw/sh_pci.c @@ -103,7 +103,8 @@ PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice), -1, NULL, NULL); - reg = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, p); + reg = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, p, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(0x1e200000, 0x224, reg); cpu_register_physical_memory(0xfe200000, 0x224, reg); diff --git a/hw/sh_serial.c b/hw/sh_serial.c index 93dc144a3..1bdc0a5ab 100644 --- a/hw/sh_serial.c +++ b/hw/sh_serial.c @@ -395,7 +395,8 @@ void sh_serial_init (target_phys_addr_t base, int feat, sh_serial_clear_fifo(s); s_io_memory = cpu_register_io_memory(sh_serial_readfn, - sh_serial_writefn, s); + sh_serial_writefn, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(P4ADDR(base), 0x28, s_io_memory); cpu_register_physical_memory(A7ADDR(base), 0x28, s_io_memory); diff --git a/hw/sh_timer.c b/hw/sh_timer.c index fd2146a0c..5eec6b7c1 100644 --- a/hw/sh_timer.c +++ b/hw/sh_timer.c @@ -319,7 +319,8 @@ void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq, s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT, ch2_irq0); /* ch2_irq1 not supported */ iomemtype = cpu_register_io_memory(tmu012_readfn, - tmu012_writefn, s); + tmu012_writefn, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(P4ADDR(base), 0x00001000, iomemtype); cpu_register_physical_memory(A7ADDR(base), 0x00001000, iomemtype); /* ??? Save/restore. */ diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c index 9d5ad86d9..fd69354bb 100644 --- a/hw/slavio_intctl.c +++ b/hw/slavio_intctl.c @@ -422,7 +422,8 @@ static int slavio_intctl_init1(SysBusDevice *dev) qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS); io_memory = cpu_register_io_memory(slavio_intctlm_mem_read, - slavio_intctlm_mem_write, s); + slavio_intctlm_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, INTCTLM_SIZE, io_memory); for (i = 0; i < MAX_CPUS; i++) { @@ -431,7 +432,8 @@ static int slavio_intctl_init1(SysBusDevice *dev) } io_memory = cpu_register_io_memory(slavio_intctl_mem_read, slavio_intctl_mem_write, - &s->slaves[i]); + &s->slaves[i], + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, INTCTL_SIZE, io_memory); s->slaves[i].cpu = i; s->slaves[i].master = s; diff --git a/hw/slavio_misc.c b/hw/slavio_misc.c index 1d81a633c..198360d57 100644 --- a/hw/slavio_misc.c +++ b/hw/slavio_misc.c @@ -412,7 +412,8 @@ static int apc_init1(SysBusDevice *dev) sysbus_init_irq(dev, &s->cpu_halt); /* Power management (APC) XXX: not a Slavio device */ - io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s); + io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, MISC_SIZE, io); return 0; } @@ -428,39 +429,46 @@ static int slavio_misc_init1(SysBusDevice *dev) /* 8 bit registers */ /* Slavio control */ io = cpu_register_io_memory(slavio_cfg_mem_read, - slavio_cfg_mem_write, s); + slavio_cfg_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, MISC_SIZE, io); /* Diagnostics */ io = cpu_register_io_memory(slavio_diag_mem_read, - slavio_diag_mem_write, s); + slavio_diag_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, MISC_SIZE, io); /* Modem control */ io = cpu_register_io_memory(slavio_mdm_mem_read, - slavio_mdm_mem_write, s); + slavio_mdm_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, MISC_SIZE, io); /* 16 bit registers */ /* ss600mp diag LEDs */ io = cpu_register_io_memory(slavio_led_mem_read, - slavio_led_mem_write, s); + slavio_led_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, MISC_SIZE, io); /* 32 bit registers */ /* System control */ io = cpu_register_io_memory(slavio_sysctrl_mem_read, - slavio_sysctrl_mem_write, s); + slavio_sysctrl_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, SYSCTRL_SIZE, io); /* AUX 1 (Misc System Functions) */ io = cpu_register_io_memory(slavio_aux1_mem_read, - slavio_aux1_mem_write, s); + slavio_aux1_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, MISC_SIZE, io); /* AUX 2 (Software Powerdown Control) */ io = cpu_register_io_memory(slavio_aux2_mem_read, - slavio_aux2_mem_write, s); + slavio_aux2_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, MISC_SIZE, io); qdev_init_gpio_in(&dev->qdev, slavio_set_power_fail, 1); diff --git a/hw/slavio_timer.c b/hw/slavio_timer.c index 13f1e62ad..551131368 100644 --- a/hw/slavio_timer.c +++ b/hw/slavio_timer.c @@ -390,7 +390,8 @@ static int slavio_timer_init1(SysBusDevice *dev) ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD); io = cpu_register_io_memory(slavio_timer_mem_read, - slavio_timer_mem_write, tc); + slavio_timer_mem_write, tc, + DEVICE_NATIVE_ENDIAN); if (i == 0) { sysbus_init_mmio(dev, SYS_TIMER_SIZE, io); } else { diff --git a/hw/sm501.c b/hw/sm501.c index 705e0a5c7..f16e6e4e6 100644 --- a/hw/sm501.c +++ b/hw/sm501.c @@ -1379,15 +1379,18 @@ void sm501_init(uint32_t base, uint32_t local_mem_bytes, qemu_irq irq, /* map mmio */ sm501_system_config_index = cpu_register_io_memory(sm501_system_config_readfn, - sm501_system_config_writefn, s); + sm501_system_config_writefn, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base + MMIO_BASE_OFFSET, 0x6c, sm501_system_config_index); sm501_disp_ctrl_index = cpu_register_io_memory(sm501_disp_ctrl_readfn, - sm501_disp_ctrl_writefn, s); + sm501_disp_ctrl_writefn, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base + MMIO_BASE_OFFSET + SM501_DC, 0x1000, sm501_disp_ctrl_index); sm501_2d_engine_index = cpu_register_io_memory(sm501_2d_engine_readfn, - sm501_2d_engine_writefn, s); + sm501_2d_engine_writefn, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base + MMIO_BASE_OFFSET + SM501_2D_ENGINE, 0x54, sm501_2d_engine_index); diff --git a/hw/smc91c111.c b/hw/smc91c111.c index f7d58e126..fc714d7f2 100644 --- a/hw/smc91c111.c +++ b/hw/smc91c111.c @@ -719,7 +719,8 @@ static int smc91c111_init1(SysBusDevice *dev) smc91c111_state *s = FROM_SYSBUS(smc91c111_state, dev); s->mmio_index = cpu_register_io_memory(smc91c111_readfn, - smc91c111_writefn, s); + smc91c111_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 16, s->mmio_index); sysbus_init_irq(dev, &s->irq); qemu_macaddr_default_if_unset(&s->conf.macaddr); diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c index 0904188c9..e78f02547 100644 --- a/hw/sparc32_dma.c +++ b/hw/sparc32_dma.c @@ -257,7 +257,8 @@ static int sparc32_dma_init1(SysBusDevice *dev) sysbus_init_irq(dev, &s->irq); - dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s); + dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, DMA_SIZE, dma_io_memory); qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1); diff --git a/hw/spitz.c b/hw/spitz.c index a06446093..092bb64ea 100644 --- a/hw/spitz.c +++ b/hw/spitz.c @@ -176,7 +176,7 @@ static void sl_flash_register(PXA2xxState *cpu, int size) s->nand = nand_init(NAND_MFR_SAMSUNG, 0xf1); iomemtype = cpu_register_io_memory(sl_readfn, - sl_writefn, s); + sl_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(FLASH_BASE, 0x40, iomemtype); register_savevm(NULL, "sl_flash", 0, 0, sl_save, sl_load, s); diff --git a/hw/stellaris.c b/hw/stellaris.c index ccad1348a..b90327305 100644 --- a/hw/stellaris.c +++ b/hw/stellaris.c @@ -348,7 +348,8 @@ static int stellaris_gptm_init(SysBusDevice *dev) qdev_init_gpio_out(&dev->qdev, &s->trigger, 1); iomemtype = cpu_register_io_memory(gptm_readfn, - gptm_writefn, s); + gptm_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); s->opaque[0] = s->opaque[1] = s; @@ -671,7 +672,8 @@ static int stellaris_sys_init(uint32_t base, qemu_irq irq, s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); iomemtype = cpu_register_io_memory(ssys_readfn, - ssys_writefn, s); + ssys_writefn, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x00001000, iomemtype); ssys_reset(s); register_savevm(NULL, "stellaris_sys", -1, 1, ssys_save, ssys_load, s); @@ -884,7 +886,8 @@ static int stellaris_i2c_init(SysBusDevice * dev) s->bus = bus; iomemtype = cpu_register_io_memory(stellaris_i2c_readfn, - stellaris_i2c_writefn, s); + stellaris_i2c_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); /* ??? For now we only implement the master interface. */ stellaris_i2c_reset(s); @@ -1193,7 +1196,8 @@ static int stellaris_adc_init(SysBusDevice *dev) } iomemtype = cpu_register_io_memory(stellaris_adc_readfn, - stellaris_adc_writefn, s); + stellaris_adc_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); stellaris_adc_reset(s); qdev_init_gpio_in(&dev->qdev, stellaris_adc_trigger, 1); diff --git a/hw/stellaris_enet.c b/hw/stellaris_enet.c index 330a9d613..6a0583a25 100644 --- a/hw/stellaris_enet.c +++ b/hw/stellaris_enet.c @@ -409,7 +409,8 @@ static int stellaris_enet_init(SysBusDevice *dev) stellaris_enet_state *s = FROM_SYSBUS(stellaris_enet_state, dev); s->mmio_index = cpu_register_io_memory(stellaris_enet_readfn, - stellaris_enet_writefn, s); + stellaris_enet_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, s->mmio_index); sysbus_init_irq(dev, &s->irq); qemu_macaddr_default_if_unset(&s->conf.macaddr); diff --git a/hw/sun4c_intctl.c b/hw/sun4c_intctl.c index 7d7542dc9..5c7fdeffb 100644 --- a/hw/sun4c_intctl.c +++ b/hw/sun4c_intctl.c @@ -196,7 +196,8 @@ static int sun4c_intctl_init1(SysBusDevice *dev) unsigned int i; io_memory = cpu_register_io_memory(sun4c_intctl_mem_read, - sun4c_intctl_mem_write, s); + sun4c_intctl_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, INTCTL_SIZE, io_memory); qdev_init_gpio_in(&dev->qdev, sun4c_set_irq, 8); diff --git a/hw/sun4m_iommu.c b/hw/sun4m_iommu.c index 720ee3f0b..bba69eef9 100644 --- a/hw/sun4m_iommu.c +++ b/hw/sun4m_iommu.c @@ -351,7 +351,8 @@ static int iommu_init1(SysBusDevice *dev) sysbus_init_irq(dev, &s->irq); - io = cpu_register_io_memory(iommu_mem_read, iommu_mem_write, s); + io = cpu_register_io_memory(iommu_mem_read, iommu_mem_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, IOMMU_NREGS * sizeof(uint32_t), io); return 0; diff --git a/hw/syborg_fb.c b/hw/syborg_fb.c index ed57203f9..7e3736454 100644 --- a/hw/syborg_fb.c +++ b/hw/syborg_fb.c @@ -510,7 +510,8 @@ static int syborg_fb_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->irq); iomemtype = cpu_register_io_memory(syborg_fb_readfn, - syborg_fb_writefn, s); + syborg_fb_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); s->ds = graphic_console_init(syborg_fb_update_display, diff --git a/hw/syborg_interrupt.c b/hw/syborg_interrupt.c index 30140fba4..5217983f6 100644 --- a/hw/syborg_interrupt.c +++ b/hw/syborg_interrupt.c @@ -210,7 +210,8 @@ static int syborg_int_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->parent_irq); qdev_init_gpio_in(&dev->qdev, syborg_int_set_irq, s->num_irqs); iomemtype = cpu_register_io_memory(syborg_int_readfn, - syborg_int_writefn, s); + syborg_int_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); s->flags = qemu_mallocz(s->num_irqs * sizeof(syborg_int_flags)); diff --git a/hw/syborg_keyboard.c b/hw/syborg_keyboard.c index 7709100c1..d295e99eb 100644 --- a/hw/syborg_keyboard.c +++ b/hw/syborg_keyboard.c @@ -210,7 +210,8 @@ static int syborg_keyboard_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->irq); iomemtype = cpu_register_io_memory(syborg_keyboard_readfn, - syborg_keyboard_writefn, s); + syborg_keyboard_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); if (s->fifo_size <= 0) { fprintf(stderr, "syborg_keyboard: fifo too small\n"); diff --git a/hw/syborg_pointer.c b/hw/syborg_pointer.c index 69b8d96bb..a88688846 100644 --- a/hw/syborg_pointer.c +++ b/hw/syborg_pointer.c @@ -206,7 +206,8 @@ static int syborg_pointer_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->irq); iomemtype = cpu_register_io_memory(syborg_pointer_readfn, - syborg_pointer_writefn, s); + syborg_pointer_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); if (s->fifo_size <= 0) { diff --git a/hw/syborg_rtc.c b/hw/syborg_rtc.c index 78d5edb0f..329aa4266 100644 --- a/hw/syborg_rtc.c +++ b/hw/syborg_rtc.c @@ -130,7 +130,8 @@ static int syborg_rtc_init(SysBusDevice *dev) int iomemtype; iomemtype = cpu_register_io_memory(syborg_rtc_readfn, - syborg_rtc_writefn, s); + syborg_rtc_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); qemu_get_timedate(&tm, 0); diff --git a/hw/syborg_serial.c b/hw/syborg_serial.c index 8c429563a..34ce076d4 100644 --- a/hw/syborg_serial.c +++ b/hw/syborg_serial.c @@ -322,7 +322,8 @@ static int syborg_serial_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->irq); iomemtype = cpu_register_io_memory(syborg_serial_readfn, - syborg_serial_writefn, s); + syborg_serial_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); s->chr = qdev_init_chardev(&dev->qdev); if (s->chr) { diff --git a/hw/syborg_timer.c b/hw/syborg_timer.c index 95e07d7bb..cedcd8ed4 100644 --- a/hw/syborg_timer.c +++ b/hw/syborg_timer.c @@ -215,7 +215,8 @@ static int syborg_timer_init(SysBusDevice *dev) } sysbus_init_irq(dev, &s->irq); iomemtype = cpu_register_io_memory(syborg_timer_readfn, - syborg_timer_writefn, s); + syborg_timer_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); bh = qemu_bh_new(syborg_timer_tick, s); diff --git a/hw/syborg_virtio.c b/hw/syborg_virtio.c index 4dfd1a87b..ee08c4910 100644 --- a/hw/syborg_virtio.c +++ b/hw/syborg_virtio.c @@ -265,7 +265,8 @@ static int syborg_virtio_init(SyborgVirtIOProxy *proxy, VirtIODevice *vdev) proxy->vdev->nvectors = 0; sysbus_init_irq(&proxy->busdev, &proxy->irq); iomemtype = cpu_register_io_memory(syborg_virtio_readfn, - syborg_virtio_writefn, proxy); + syborg_virtio_writefn, proxy, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(&proxy->busdev, 0x1000, iomemtype); proxy->id = ((uint32_t)0x1af4 << 16) | vdev->device_id; diff --git a/hw/tc6393xb.c b/hw/tc6393xb.c index 16db51dc2..c3fbe4e20 100644 --- a/hw/tc6393xb.c +++ b/hw/tc6393xb.c @@ -590,7 +590,7 @@ TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq) s->flash = nand_init(NAND_MFR_TOSHIBA, 0x76); iomemtype = cpu_register_io_memory(tc6393xb_readfn, - tc6393xb_writefn, s); + tc6393xb_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x10000, iomemtype); s->vram_addr = qemu_ram_alloc(NULL, "tc6393xb.vram", 0x100000); @@ -522,12 +522,13 @@ static int tcx_init1(SysBusDevice *dev) vram_base += size; /* DAC */ - io_memory = cpu_register_io_memory(tcx_dac_read, tcx_dac_write, s); + io_memory = cpu_register_io_memory(tcx_dac_read, tcx_dac_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, TCX_DAC_NREGS, io_memory); /* TEC (dummy) */ dummy_memory = cpu_register_io_memory(tcx_dummy_read, tcx_dummy_write, - s); + s, DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, TCX_TEC_NREGS, dummy_memory); /* THC: NetBSD writes here even with 8-bit display: dummy */ sysbus_init_mmio(dev, TCX_THC_NREGS_24, dummy_memory); diff --git a/hw/tusb6010.c b/hw/tusb6010.c index 4864be5e8..0005e1cff 100644 --- a/hw/tusb6010.c +++ b/hw/tusb6010.c @@ -740,7 +740,7 @@ TUSBState *tusb6010_init(qemu_irq intr) s->intr = 0x00000000; s->otg_timer_val = 0; s->iomemtype[1] = cpu_register_io_memory(tusb_async_readfn, - tusb_async_writefn, s); + tusb_async_writefn, s, DEVICE_NATIVE_ENDIAN); s->irq = intr; s->otg_timer = qemu_new_timer(vm_clock, tusb_otg_tick, s); s->pwr_timer = qemu_new_timer(vm_clock, tusb_power_tick, s); diff --git a/hw/usb-ohci.c b/hw/usb-ohci.c index 8fb2f83f0..ba1ebbcae 100644 --- a/hw/usb-ohci.c +++ b/hw/usb-ohci.c @@ -1697,7 +1697,8 @@ static void usb_ohci_init(OHCIState *ohci, DeviceState *dev, usb_frame_time, usb_bit_time); } - ohci->mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci); + ohci->mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci, + DEVICE_NATIVE_ENDIAN); ohci->localmem_base = localmem_base; ohci->name = dev->info->name; diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c index a76bdfad6..3baad968d 100644 --- a/hw/versatile_pci.c +++ b/hw/versatile_pci.c @@ -132,7 +132,8 @@ static int pci_vpb_init(SysBusDevice *dev) /* ??? Register memory space. */ s->mem_config = cpu_register_io_memory(pci_vpb_config_read, - pci_vpb_config_write, bus); + pci_vpb_config_write, bus, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio_cb(dev, 0x04000000, pci_vpb_map); pci_create_simple(bus, -1, "versatile_pci_host"); diff --git a/hw/versatilepb.c b/hw/versatilepb.c index c51ee02c4..be758e447 100644 --- a/hw/versatilepb.c +++ b/hw/versatilepb.c @@ -143,7 +143,8 @@ static int vpb_sic_init(SysBusDevice *dev) } s->irq = 31; iomemtype = cpu_register_io_memory(vpb_sic_readfn, - vpb_sic_writefn, s); + vpb_sic_writefn, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); /* ??? Save/restore. */ return 0; diff --git a/hw/vga-isa-mm.c b/hw/vga-isa-mm.c index 680b557a0..4954bb18b 100644 --- a/hw/vga-isa-mm.c +++ b/hw/vga-isa-mm.c @@ -97,8 +97,10 @@ static void vga_mm_init(ISAVGAMMState *s, target_phys_addr_t vram_base, int s_ioport_ctrl, vga_io_memory; s->it_shift = it_shift; - s_ioport_ctrl = cpu_register_io_memory(vga_mm_read_ctrl, vga_mm_write_ctrl, s); - vga_io_memory = cpu_register_io_memory(vga_mem_read, vga_mem_write, s); + s_ioport_ctrl = cpu_register_io_memory(vga_mm_read_ctrl, vga_mm_write_ctrl, s, + DEVICE_NATIVE_ENDIAN); + vga_io_memory = cpu_register_io_memory(vga_mem_read, vga_mem_write, s, + DEVICE_NATIVE_ENDIAN); vmstate_register(NULL, 0, &vmstate_vga_common, s); @@ -2320,7 +2320,8 @@ void vga_init(VGACommonState *s) #endif #endif /* CONFIG_BOCHS_VBE */ - vga_io_memory = cpu_register_io_memory(vga_mem_read, vga_mem_write, s); + vga_io_memory = cpu_register_io_memory(vga_mem_read, vga_mem_write, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000, vga_io_memory); qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000); diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c index d0f4e1b5b..d9dd52fc6 100644 --- a/hw/vmware_vga.c +++ b/hw/vmware_vga.c @@ -1250,7 +1250,7 @@ static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num, s->vram_base = addr; #ifdef DIRECT_VRAM iomemtype = cpu_register_io_memory(vmsvga_vram_read, - vmsvga_vram_write, s); + vmsvga_vram_write, s, DEVICE_NATIVE_ENDIAN); #else iomemtype = s->vga.vram_offset | IO_MEM_RAM; #endif diff --git a/hw/wdt_i6300esb.c b/hw/wdt_i6300esb.c index 46e1df8b6..09f2f58ad 100644 --- a/hw/wdt_i6300esb.c +++ b/hw/wdt_i6300esb.c @@ -361,7 +361,8 @@ static void i6300esb_map(PCIDevice *dev, int region_num, i6300esb_debug("addr = %"FMT_PCIBUS", size = %"FMT_PCIBUS", type = %d\n", addr, size, type); - io_mem = cpu_register_io_memory(mem_read, mem_write, d); + io_mem = cpu_register_io_memory(mem_read, mem_write, d, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory (addr, 0x10, io_mem); /* qemu_register_coalesced_mmio (addr, 0x10); ? */ } diff --git a/hw/xilinx_ethlite.c b/hw/xilinx_ethlite.c index 37e33ec01..54b57d774 100644 --- a/hw/xilinx_ethlite.c +++ b/hw/xilinx_ethlite.c @@ -224,7 +224,7 @@ static int xilinx_ethlite_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->irq); s->rxbuf = 0; - regs = cpu_register_io_memory(eth_read, eth_write, s); + regs = cpu_register_io_memory(eth_read, eth_write, s, DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, R_MAX * 4, regs); qemu_macaddr_default_if_unset(&s->conf.macaddr); diff --git a/hw/xilinx_intc.c b/hw/xilinx_intc.c index 8ef6474fb..cb72d5a14 100644 --- a/hw/xilinx_intc.c +++ b/hw/xilinx_intc.c @@ -153,7 +153,7 @@ static int xilinx_intc_init(SysBusDevice *dev) qdev_init_gpio_in(&dev->qdev, irq_handler, 32); sysbus_init_irq(dev, &p->parent_irq); - pic_regs = cpu_register_io_memory(pic_read, pic_write, p); + pic_regs = cpu_register_io_memory(pic_read, pic_write, p, DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, R_MAX * 4, pic_regs); return 0; } diff --git a/hw/xilinx_timer.c b/hw/xilinx_timer.c index e2d9541cd..30827b03c 100644 --- a/hw/xilinx_timer.c +++ b/hw/xilinx_timer.c @@ -210,7 +210,8 @@ static int xilinx_timer_init(SysBusDevice *dev) ptimer_set_freq(xt->ptimer, t->freq_hz); } - timer_regs = cpu_register_io_memory(timer_read, timer_write, t); + timer_regs = cpu_register_io_memory(timer_read, timer_write, t, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, R_MAX * 4 * t->nr_timers, timer_regs); return 0; } diff --git a/hw/xilinx_uartlite.c b/hw/xilinx_uartlite.c index adab759fd..9b94e98fe 100644 --- a/hw/xilinx_uartlite.c +++ b/hw/xilinx_uartlite.c @@ -201,7 +201,8 @@ static int xilinx_uartlite_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->irq); uart_update_status(s); - uart_regs = cpu_register_io_memory(uart_read, uart_write, s); + uart_regs = cpu_register_io_memory(uart_read, uart_write, s, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, R_MAX * 4, uart_regs); s->chr = qdev_init_chardev(&dev->qdev); diff --git a/hw/zaurus.c b/hw/zaurus.c index dd999d7d4..54ec3f00d 100644 --- a/hw/zaurus.c +++ b/hw/zaurus.c @@ -228,7 +228,7 @@ ScoopInfo *scoop_init(PXA2xxState *cpu, s->status = 0x02; s->in = qemu_allocate_irqs(scoop_gpio_set, s, 16); iomemtype = cpu_register_io_memory(scoop_readfn, - scoop_writefn, s); + scoop_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(target_base, 0x1000, iomemtype); register_savevm(NULL, "scoop", instance, 1, scoop_save, scoop_load, s); diff --git a/rwhandler.c b/rwhandler.c index 1f9b6db4b..88dfcc5c1 100644 --- a/rwhandler.c +++ b/rwhandler.c @@ -42,7 +42,7 @@ int cpu_register_io_memory_simple(struct ReadWriteHandler *handler) } return cpu_register_io_memory(cpu_io_memory_simple_read, cpu_io_memory_simple_write, - handler); + handler, DEVICE_NATIVE_ENDIAN); } RWHANDLER_WRITE(ioport_simple_writeb, 1, uint32_t); |