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author | Martin Hauke <mardnh@gmx.de> | 2018-02-18 17:04:50 +0100 |
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committer | Martin Hauke <mardnh@gmx.de> | 2018-02-18 17:04:50 +0100 |
commit | 6cbecaaf5cbbf0cf1fe9d3d657c91dfdabd6de5c (patch) | |
tree | 13cc6c6a26a8eee141f8f22678a709db3b6eb1ce | |
parent | d9d2b941eb2f8f1566767ed4957295fb391a999d (diff) |
transport/serial: Fix serial transport
Fix a typo that broke the serial transport.
Change-Id: I7fcc97d505a5369f9f14d4a2abda92b7114a58cd
-rw-r--r-- | pySim/transport/serial.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/pySim/transport/serial.py b/pySim/transport/serial.py index 5b15b2f..7a2bfd3 100644 --- a/pySim/transport/serial.py +++ b/pySim/transport/serial.py @@ -143,19 +143,19 @@ class SerialSimLink(LinkBase): for i in range(4): if t0 & (0x10 << i): b = self._rx_byte() - self._atr.apend(ord(b)) + self._atr.append(ord(b)) self._dbg_print("T%si = %x" % (chr(ord('A')+i), ord(b))) for i in range(0, t0 & 0xf): b = self._rx_byte() - self._atr.apend(ord(b)) + self._atr.append(ord(b)) self._dbg_print("Historical = %x" % ord(b)) while True: x = self._rx_byte() if not x: break - self._atr.apend(ord(x)) + self._atr.append(ord(x)) self._dbg_print("Extra: %x" % ord(x)) return 1 |