diff options
author | Steve Markgraf <steve@steve-m.de> | 2022-01-25 00:57:06 +0100 |
---|---|---|
committer | Steve Markgraf <steve@steve-m.de> | 2022-01-25 01:14:44 +0100 |
commit | 9c93cec32ab812a8de8377a93d4c7b8f83b49301 (patch) | |
tree | 0c03fda1696aea160492cb2862ffabe9e6667c59 | |
parent | 0c840f0aab3f4554003ce4467c721c3895022205 (diff) |
transport/serial: fix for Python 3
Change-Id: I21e5a7ad4f623ed30681dce1ff819679b8714c5b
-rw-r--r-- | pySim/transport/serial.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/pySim/transport/serial.py b/pySim/transport/serial.py index 4f2b28f..c080926 100644 --- a/pySim/transport/serial.py +++ b/pySim/transport/serial.py @@ -184,7 +184,7 @@ class SerialSimLink(LinkBase): def _send_apdu_raw(self, pdu): pdu = h2b(pdu) - data_len = ord(pdu[4]) # P3 + data_len = pdu[4] # P3 # Send first CLASS,INS,P1,P2,P3 self._tx_string(pdu[0:5]) @@ -195,7 +195,7 @@ class SerialSimLink(LinkBase): # - SW1: The card can apparently proceed ... while True: b = self._rx_byte() - if b == pdu[1]: + if ord(b) == pdu[1]: break elif b != '\x60': # Ok, it 'could' be SW1 @@ -215,7 +215,7 @@ class SerialSimLink(LinkBase): # length = [P3 - tx_data (=len(pdu)-len(hdr)) + 2 (SW1//2) ] to_recv = data_len - len(pdu) + 5 + 2 - data = '' + data = bytes(0) while (len(data) < to_recv): b = self._rx_byte() if (to_recv == 2) and (b == '\x60'): # Ignore NIL if we have no RX data (hack ?) |