summaryrefslogtreecommitdiffstats
path: root/src/host/trxcon/sched_lchan_rach.c
AgeCommit message (Collapse)AuthorFilesLines
2019-05-09trxcon/l1ctl.c: pass band_arfcn to l1ctl_tx_rach_conf()Vadim Yanitskiy1-1/+1
This would allow to abstract both L1CTL and TRX interfaces from each other in the upcoming refactoring. Change-Id: I74a23c73b03bad822272b9cfe76c2501666912b7
2019-04-22trxcon: introduce extended (11-bit) RACH supportVadim Yanitskiy1-42/+104
According to 3GPP TS 05.03, section 5.3, two coding schemes are specified for access bursts: one for regular 8-bit bursts, another - for extended 11-bit packet access bursts. According to 3GPP TS 05.02, section 5.2.7, there are two additional training (synchronization) sequences for RACH bursts: TS1 & TS2. By default, TS0 synch. sequence is used, unless explicitly stated otherwise (see 3GPP TS 04.60). According to 3GPP TS 04.60, section 11.2.5a, the EGPRS capability can be indicated by the MS using an alternative training sequence (i.e. TS1 or TS2) and the 11-bit RACH coding scheme. Change-Id: I36fd20cd5502ce33c52f644ee4c22abb83350df8
2019-01-17trxcon: do not include trxcon.h everywhereVadim Yanitskiy1-1/+0
Change-Id: Ia78bd6dac7ab12970838e0b1a2929a106b898d9d
2018-07-24trxcon/scheduler: fix: check primitive len before encodingVadim Yanitskiy1-0/+9
We used to trust (and still doing this) the messages coming from L1CTL interface too much, and not to check the primitive length before passing the payload to the libosmocoding API. As was discovered and described in OS#3415, sending a L1CTL message (either DATA_REQ, or TRAFFIC_REQ) with an incorrect length (lower than expected) may cause heap overflow. Let's explicitly check a primitive before encoding, and drop it if its length doesn't match the expected value(s). Change-Id: I258ee9f6d0124b183b1db23a73f1e523fcea89a8 Fixes: OS#3415
2018-07-16trxcon: fix tail bits at the front of Access burstPiotr Krysik1-1/+10
Currently Access Burst generated by trxcon has 8 zero bits at the beginning. According to the 3GPP 05.02 specification (Chapter 5.2.7 Access burst) custom 8-bit extended tail bits sequence should be used: (BN0, BN1, BN2 ... BN7) = (0,0,1,1,1,0,1,0) After this fix trxcon sets correct 8-bit sequence at the front of Access burst. Change-Id: I1f624e783de6c585d2e292965c9e5810b0a4f27d
2017-12-18trxcon/scheduler: preprocess UL bursts before sendingVadim Yanitskiy1-4/+2
Having a possibility to preprocess UL burst before sending to transceiver is required for the further ciphering support integration and probably some other tasks. Change-Id: Ia6eead5d4f51d7c0bf277b9d5ebb0a74676df567
2017-12-18trxcon/scheduler: move prim management outside lchan handlersVadim Yanitskiy1-9/+12
Previously, each lchan handler used to obtain and delete primitives from a timeslot's tranmit queue itself. This approach entails many potential problems and bugs: - The lchan handlers shall not do that by definition, they should encode and decode frames according to GSM 05.03. - In some cases (e.g. TCH), a single transmit queue may contain primitives of different types (e.g. TCH, FACCH and SACCH). At the same time, the lchan handlers don't care and don't even know about each other. So, this could cause an unexpected behaviour in some cases. This change separates all primitive management routines, providing a new API for obtaining and dropping them. "Write programs that do one thing and do it well." Change-Id: I29503ece51903784bc53541015285234471c8d15
2017-12-16host/trxcon/scheduler: use new libosmocoding API for RACHVadim Yanitskiy1-2/+3
Since the 32e5641d, the gsm0503_rach_encode() is deprecated, and the library provides new API with extended (11-bit) RACH support. Change-Id: I1955fe46eebd173d6eddd1d47ee9f7318b9b4e2d
2017-11-19host/trxcon/scheduler: separate logging of data messagesVadim Yanitskiy1-3/+3
Change-Id: I3a33687a688db2a183b546425f71c7a0a7030594
2017-11-19host/trxcon/scheduler: send stored tx_power to transceiverVadim Yanitskiy1-1/+1
Previously a fixed fake value (10) was used. Change-Id: I8ba70bbda6c8c9249f8eb4294aeb41ab8769a19a
2017-11-19host/trxcon/scheduler: clean up some includesVadim Yanitskiy1-4/+0
Change-Id: I47e3b953b80f4f822d563579d15498181009ca80
2017-11-19host/trxcon/scheduler: get rid of useless nbits argumentVadim Yanitskiy1-2/+1
Change-Id: I8508676e2cb347396c6ca6b394f13113f3e63084
2017-11-19host/trxcon/scheduler: pass trx_lchan_state to lchan handlersVadim Yanitskiy1-1/+1
It's better to pass a trx_lchan_state instance directly from caller to lchan handler instead of passing trx_lchan_type. This way a handler wouldn't need to find lchan itself. Change-Id: I47a40542b03ab31da12b0abb1c263c83662ff018
2017-11-19host/trxcon: split sched_lchan_handlers.cVadim Yanitskiy1-0/+108
It would be better to have xCCH, SCH and RACH burst handlers in separate files, because as much code we add to a single file, as harder it becomes to read and understand one. Change-Id: I456a60e68b32b792e63dd03ae97159dc101fd4bf