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-rw-r--r--src/target/firmware/include/layer1/tpu_window.h5
-rw-r--r--src/target/firmware/layer1/prim_rach.c2
-rw-r--r--src/target/firmware/layer1/prim_rx_nb.c6
-rw-r--r--src/target/firmware/layer1/prim_tx_nb.c4
-rw-r--r--src/target/firmware/layer1/sync.c3
-rw-r--r--src/target/firmware/layer1/tpu_window.c48
6 files changed, 48 insertions, 20 deletions
diff --git a/src/target/firmware/include/layer1/tpu_window.h b/src/target/firmware/include/layer1/tpu_window.h
index 09856c7e..7b146f12 100644
--- a/src/target/firmware/include/layer1/tpu_window.h
+++ b/src/target/firmware/include/layer1/tpu_window.h
@@ -15,8 +15,9 @@ enum l1_txwin_type {
_NUM_L1_TXWIN
};
-void l1s_rx_win_ctrl(uint16_t arfcn, enum l1_rxwin_type wtype, uint8_t tn);
-void l1s_tx_win_ctrl(uint16_t arfcn, enum l1_txwin_type wtype, uint8_t pwr, uint8_t tn);
+void l1s_win_init(void);
+void l1s_rx_win_ctrl(uint16_t arfcn, enum l1_rxwin_type wtype, uint8_t tn_ofs);
+void l1s_tx_win_ctrl(uint16_t arfcn, enum l1_txwin_type wtype, uint8_t pwr, uint8_t tn_ofs);
void tpu_end_scenario(void);
diff --git a/src/target/firmware/layer1/prim_rach.c b/src/target/firmware/layer1/prim_rach.c
index 58672935..d1880e30 100644
--- a/src/target/firmware/layer1/prim_rach.c
+++ b/src/target/firmware/layer1/prim_rach.c
@@ -73,7 +73,7 @@ static int l1s_tx_rach_cmd(__unused uint8_t p1, __unused uint8_t p2, __unused ui
dsp_api.db_w->d_task_ra = RACH_DSP_TASK;
- l1s_tx_win_ctrl(l1s.serving_cell.arfcn, L1_TXWIN_AB, 0, 0);
+ l1s_tx_win_ctrl(l1s.serving_cell.arfcn, L1_TXWIN_AB, 0, 3);
return 0;
}
diff --git a/src/target/firmware/layer1/prim_rx_nb.c b/src/target/firmware/layer1/prim_rx_nb.c
index 6c765457..868800e5 100644
--- a/src/target/firmware/layer1/prim_rx_nb.c
+++ b/src/target/firmware/layer1/prim_rx_nb.c
@@ -165,7 +165,7 @@ static int l1s_nb_cmd(__unused uint8_t p1, uint8_t burst_id,
__unused uint16_t p3)
{
uint16_t arfcn;
- uint8_t tsc, tn;
+ uint8_t tsc;
putchart('N');
@@ -183,11 +183,11 @@ static int l1s_nb_cmd(__unused uint8_t p1, uint8_t burst_id,
rxnb.di = (struct l1ctl_data_ind *) msgb_put(rxnb.msg, sizeof(*rxnb.di));
}
- rfch_get_params(&l1s.next_time, &arfcn, &tsc, &tn);
+ rfch_get_params(&l1s.next_time, &arfcn, &tsc, NULL);
dsp_load_rx_task(ALLC_DSP_TASK, burst_id, tsc);
- l1s_rx_win_ctrl(arfcn, L1_RXWIN_NB, tn);
+ l1s_rx_win_ctrl(arfcn, L1_RXWIN_NB, 0);
return 0;
}
diff --git a/src/target/firmware/layer1/prim_tx_nb.c b/src/target/firmware/layer1/prim_tx_nb.c
index a1459ce9..0e52ef9d 100644
--- a/src/target/firmware/layer1/prim_tx_nb.c
+++ b/src/target/firmware/layer1/prim_tx_nb.c
@@ -153,11 +153,11 @@ static int l1s_tx_cmd(uint8_t p1, uint8_t burst_id, uint16_t p3)
msgb_free(msg);
}
- rfch_get_params(&l1s.next_time, &arfcn, &tsc, &tn);
+ rfch_get_params(&l1s.next_time, &arfcn, &tsc, NULL);
dsp_load_tx_task(DUL_DSP_TASK, burst_id, tsc);
- l1s_tx_win_ctrl(arfcn, L1_TXWIN_NB, 0, tn);
+ l1s_tx_win_ctrl(arfcn, L1_TXWIN_NB, 0, 3);
return 0;
}
diff --git a/src/target/firmware/layer1/sync.c b/src/target/firmware/layer1/sync.c
index cd76c2eb..c8840ded 100644
--- a/src/target/firmware/layer1/sync.c
+++ b/src/target/firmware/layer1/sync.c
@@ -257,6 +257,9 @@ static void l1_sync(void)
* TDMA frame (including setup/cleanup steps) */
sched_flags = tdma_sched_flag_scan();
+ if (sched_flags & TDMA_IFLG_TPU)
+ l1s_win_init();
+
tdma_sched_execute();
if (dsp_api.r_page_used) {
diff --git a/src/target/firmware/layer1/tpu_window.c b/src/target/firmware/layer1/tpu_window.c
index 32cbdb83..00eaa8f4 100644
--- a/src/target/firmware/layer1/tpu_window.c
+++ b/src/target/firmware/layer1/tpu_window.c
@@ -22,6 +22,7 @@
#include <stdint.h>
#include <debug.h>
+#include <defines.h>
#include <stdio.h>
#include <rffe.h>
@@ -65,18 +66,41 @@ static const uint16_t tx_burst_duration[_NUM_L1_TXWIN] = {
[L1_TXWIN_AB] = L1_TX_AB_DURATION_Q,
};
-void l1s_rx_win_ctrl(uint16_t arfcn, enum l1_rxwin_type wtype, uint8_t tn)
+
+static int _win_setup(__unused uint8_t p1, __unused uint8_t p2, __unused uint8_t p3)
{
- int16_t start = DSP_SETUP_TIME;
- int16_t stop = start + rx_burst_duration[wtype] - 1;
+ uint8_t tn;
- /* FIXME: AGC */
- /* FIXME: RF PLL */
+ rfch_get_params(&l1s.next_time, NULL, NULL, &tn);
- /* Alignement */
tpu_enq_offset( (5000 + l1s.tpu_offset + (L1_BURST_LENGTH_Q * tn)) % 5000 );
tpu_enq_at(5000 - 1000 - (L1_BURST_LENGTH_Q * tn));
+ return 0;
+}
+
+static int _win_cleanup(__unused uint8_t p1, __unused uint8_t p2, __unused uint8_t p3)
+{
+ return 0;
+}
+
+void l1s_win_init(void)
+{
+ tdma_schedule(0, _win_setup, 0, 0, 0, -2);
+ tdma_schedule(0, _win_cleanup, 0, 0, 0, 9);
+}
+
+void l1s_rx_win_ctrl(uint16_t arfcn, enum l1_rxwin_type wtype, uint8_t tn_ofs)
+{
+ int16_t start, stop;
+
+ /* TN offset & TA adjust */
+ start = DSP_SETUP_TIME;
+ start += L1_BURST_LENGTH_Q * tn_ofs;
+ start -= l1s.ta << 2;
+
+ stop = start + rx_burst_duration[wtype] - 1;
+
/* window open for TRF6151 */
/* FIXME: why do we need the magic value 100 ? */
rffe_mode(gsm_arfcn2band(arfcn), 0);
@@ -101,14 +125,14 @@ void l1s_rx_win_ctrl(uint16_t arfcn, enum l1_rxwin_type wtype, uint8_t tn)
trf6151_set_mode(TRF6151_IDLE);
}
-void l1s_tx_win_ctrl(uint16_t arfcn, enum l1_txwin_type wtype, uint8_t pwr, uint8_t tn)
+void l1s_tx_win_ctrl(uint16_t arfcn, enum l1_txwin_type wtype, uint8_t pwr, uint8_t tn_ofs)
{
- /* uplink is three TS after downlink ( "+ 32" gives a TA of 1) */
- uint16_t offset = (L1_BURST_LENGTH_Q * 3) + 28;
+ uint16_t offset;
- /* Alignement */
- tpu_enq_offset( (5000 + l1s.tpu_offset - (l1s.ta << 2) + (L1_BURST_LENGTH_Q * tn)) % 5000 );
- tpu_enq_at(5000 - 10 - (L1_BURST_LENGTH_Q * tn));
+ /* TN offset & TA adjust */
+ offset = 28; /* ("+ 32" gives a TA of 1) */
+ offset += L1_BURST_LENGTH_Q * tn_ofs;
+ offset -= l1s.ta << 2;
#ifdef CONFIG_TX_ENABLE
/* window open for TRF6151 and RFFE */