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authorVadim Yanitskiy <axilirator@gmail.com>2017-12-09 01:25:52 +0700
committerVadim Yanitskiy <axilirator@gmail.com>2017-12-09 01:25:52 +0700
commitaf217395ccd058a8aeab6992c0bd0743a8e6895e (patch)
tree77e20f16216df3084ba06d08dfbc659db4205bf3 /src/target
parent26ecb9460e1871b26a5e3a3c72c2f7163ece2652 (diff)
fake_trx: don't sent clock indications until POWERON
Diffstat (limited to 'src/target')
-rw-r--r--src/target/fake_trx/ctrl_if_bts.py9
-rwxr-xr-xsrc/target/fake_trx/fake_trx.py2
2 files changed, 10 insertions, 1 deletions
diff --git a/src/target/fake_trx/ctrl_if_bts.py b/src/target/fake_trx/ctrl_if_bts.py
index 96027fe9..d0a7db3c 100644
--- a/src/target/fake_trx/ctrl_if_bts.py
+++ b/src/target/fake_trx/ctrl_if_bts.py
@@ -28,6 +28,7 @@ class CTRLInterfaceBTS(CTRLInterface):
# Internal state variables
trx_started = False
burst_fwd = None
+ clck_gen = None
rx_freq = None
tx_freq = None
pm = None
@@ -62,6 +63,10 @@ class CTRLInterfaceBTS(CTRLInterface):
if self.pm is not None:
self.pm.add_bts_list([self.tx_freq])
+ # Start clock indications
+ if self.clck_gen is not None:
+ self.clck_gen.start()
+
return 0
elif self.verify_cmd(request, "POWEROFF", 0):
@@ -74,6 +79,10 @@ class CTRLInterfaceBTS(CTRLInterface):
if self.pm is not None:
self.pm.del_bts_list([self.tx_freq])
+ # Stop clock indications
+ if self.clck_gen is not None:
+ self.clck_gen.stop()
+
return 0
# Tuning Control
diff --git a/src/target/fake_trx/fake_trx.py b/src/target/fake_trx/fake_trx.py
index 47727019..962101c3 100755
--- a/src/target/fake_trx/fake_trx.py
+++ b/src/target/fake_trx/fake_trx.py
@@ -89,7 +89,7 @@ class Application:
self.bts_clck = UDPLink(self.bts_addr,
self.bts_base_port + 100, self.bts_base_port)
self.clck_gen = CLCKGen([self.bts_clck])
- self.clck_gen.start()
+ self.bts_ctrl.clck_gen = self.clck_gen
print("[i] Init complete")