diff options
| author | Vadim Yanitskiy <vyanitskiy@sysmocom.de> | 2020-07-10 04:59:36 +0700 |
|---|---|---|
| committer | Vadim Yanitskiy <vyanitskiy@sysmocom.de> | 2020-07-14 17:20:14 +0700 |
| commit | 8d19fbef57f2fa74a63477f7f324f3dc8d5d36d4 (patch) | |
| tree | 44027d670984f004a04539899e4f5b24caf32593 /src/target/trx_toolkit/clck_gen.py | |
| parent | 93beb3f5c580c5c08297e0000a2840029731aeba (diff) | |
trx_toolkit/clck_gen.py: fix TDMA clock counter wrapping
Change-Id: I157447c7610402f6d62d2b74c9f04fcaa0bc1724
Diffstat (limited to 'src/target/trx_toolkit/clck_gen.py')
| -rwxr-xr-x | src/target/trx_toolkit/clck_gen.py | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/src/target/trx_toolkit/clck_gen.py b/src/target/trx_toolkit/clck_gen.py index 92be8b03..9f396438 100755 --- a/src/target/trx_toolkit/clck_gen.py +++ b/src/target/trx_toolkit/clck_gen.py @@ -91,10 +91,6 @@ class CLCKGen: self.send_clck_ind() def send_clck_ind(self): - # Keep clock cycle - if self.clck_src % GSM_HYPERFRAME >= 0: - self.clck_src %= GSM_HYPERFRAME - # We don't need to send so often if self.clck_src % self.ind_period == 0: # Create UDP payload @@ -107,8 +103,8 @@ class CLCKGen: # Debug print log.debug(payload.rstrip("\0")) - # Increase frame count - self.clck_src += 1 + # Increase frame count (modular arithmetic) + self.clck_src = (self.clck_src + 1) % GSM_HYPERFRAME # Just a wrapper for independent usage class Application(ApplicationBase): |