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authorSylvain Munaut <tnt@246tNt.com>2010-09-19 15:51:26 +0200
committerSylvain Munaut <tnt@246tNt.com>2010-10-25 20:58:32 +0200
commitf1d942b8f4a28e7c57674e5b9d16d6635b24e88c (patch)
treed3456a8e38184685f0277ebe43b794e532bf99c8 /src/target/firmware/layer1
parent76bfbc819397d15764c4fcb7b578f53f5bef7c37 (diff)
target/fw/layer1: Add support for the various TCH multi frame tasks
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Diffstat (limited to 'src/target/firmware/layer1')
-rw-r--r--src/target/firmware/layer1/l23_api.c5
-rw-r--r--src/target/firmware/layer1/mframe_sched.c76
2 files changed, 79 insertions, 2 deletions
diff --git a/src/target/firmware/layer1/l23_api.c b/src/target/firmware/layer1/l23_api.c
index 0aa5b1a2..f6a2a9c9 100644
--- a/src/target/firmware/layer1/l23_api.c
+++ b/src/target/firmware/layer1/l23_api.c
@@ -56,14 +56,15 @@ void l1_queue_for_l2(struct msgb *msg)
static enum mframe_task chan_nr2mf_task(uint8_t chan_nr)
{
uint8_t cbits = chan_nr >> 3;
+ uint8_t tn = chan_nr & 0x7;
uint8_t lch_idx;
if (cbits == 0x01) {
lch_idx = 0;
- /* FIXME: TCH/F */
+ return (tn & 1) ? MF_TASK_TCH_F_ODD : MF_TASK_TCH_F_EVEN;
} else if ((cbits & 0x1e) == 0x02) {
lch_idx = cbits & 0x1;
- /* FIXME: TCH/H */
+ return MF_TASK_TCH_H_0 + lch_idx;
} else if ((cbits & 0x1c) == 0x04) {
lch_idx = cbits & 0x3;
return MF_TASK_SDCCH4_0 + lch_idx;
diff --git a/src/target/firmware/layer1/mframe_sched.c b/src/target/firmware/layer1/mframe_sched.c
index 8e92b93c..30cd03f7 100644
--- a/src/target/firmware/layer1/mframe_sched.c
+++ b/src/target/firmware/layer1/mframe_sched.c
@@ -197,6 +197,67 @@ static const struct mframe_sched_item mf_sdcch8_7[] = {
{ .sched_set = NULL }
};
+/* TCH */
+#define TCH tch_sched_set
+#define TCH_A tch_a_sched_set
+
+static const struct mframe_sched_item mf_tch_f_even[] = {
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 0 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 1 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 2 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 3 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 4 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 5 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 6 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 7 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 8 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 9 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 10 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 11 },
+ { .sched_set = TCH_A, .modulo = 26, .frame_nr = 12 },
+ { .sched_set = NULL }
+};
+
+static const struct mframe_sched_item mf_tch_f_odd[] = {
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 0 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 1 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 2 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 3 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 4 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 5 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 6 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 7 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 8 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 9 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 10 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 11 },
+ { .sched_set = TCH_A, .modulo = 26, .frame_nr = 25 },
+ { .sched_set = NULL }
+};
+
+static const struct mframe_sched_item mf_tch_h_0[] = {
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 0 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 2 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 4 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 6 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 8 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 10 },
+ { .sched_set = TCH_A, .modulo = 26, .frame_nr = 12 },
+ { .sched_set = NULL }
+};
+
+static const struct mframe_sched_item mf_tch_h_1[] = {
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 1 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 3 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 5 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 7 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 9 },
+ { .sched_set = TCH, .modulo = 13, .frame_nr = 11 },
+ { .sched_set = TCH_A, .modulo = 26, .frame_nr = 25 },
+ { .sched_set = NULL }
+};
+
+/* Test TX */
static const struct mframe_sched_item mf_tx_all_nb[] = {
{ .sched_set = NB_QUAD_FH_UL, .modulo = 4, .frame_nr = 0 },
{ .sched_set = NULL }
@@ -222,6 +283,11 @@ static const struct mframe_sched_item *sched_set_for_task[32] = {
[MF_TASK_SDCCH8_6] = mf_sdcch8_6,
[MF_TASK_SDCCH8_7] = mf_sdcch8_7,
+ [MF_TASK_TCH_F_EVEN] = mf_tch_f_even,
+ [MF_TASK_TCH_F_ODD] = mf_tch_f_odd,
+ [MF_TASK_TCH_H_0] = mf_tch_h_0,
+ [MF_TASK_TCH_H_1] = mf_tch_h_1,
+
[MF_TASK_UL_ALL_NB] = mf_tx_all_nb,
};
@@ -275,6 +341,16 @@ uint8_t mframe_task2chan_nr(enum mframe_task mft, uint8_t ts)
case MF_TASK_SDCCH8_7:
cbits = 0x08 + 7;
break;
+ case MF_TASK_TCH_F_EVEN:
+ case MF_TASK_TCH_F_ODD:
+ cbits = 0x01;
+ break;
+ case MF_TASK_TCH_H_0:
+ cbits = 0x02 + 0;
+ break;
+ case MF_TASK_TCH_H_1:
+ cbits = 0x02 + 1;
+ break;
case MF_TASK_UL_ALL_NB:
/* ERROR: cannot express as channel number */
cbits = 0;