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authorVadim Yanitskiy <vyanitskiy@sysmocom.de>2024-04-15 02:55:56 +0700
committerfixeria <vyanitskiy@sysmocom.de>2024-04-15 15:18:28 +0000
commitf4ba2252dee1e9eb2fba415f71569fe5e470a6be (patch)
treea8e82e5638014b8ba1c8cfa83234271761f4905b
parent06dec6b324f6f25595b0125f66d1a09eacc5fb51 (diff)
msc: expect TC_attached_imsi_lu_unknown_tmsi to pass
The "VLR evil twin" problem has been fixed in osmo-msc.git: https://gerrit.osmocom.org/c/osmo-msc/+/36452 https://cgit.osmocom.org/osmo-msc/commit/?id=2fd69e15d36d5a8e87029741ad66632c57d24cd4 And the testcase is finally passing now. Change-Id: I57a277fa7e6e0d10ff38e23f416ace87472e6602 Related: OS#4721
-rw-r--r--msc/expected-results.xml7
1 files changed, 1 insertions, 6 deletions
diff --git a/msc/expected-results.xml b/msc/expected-results.xml
index b6e0bb29..aad96a7c 100644
--- a/msc/expected-results.xml
+++ b/msc/expected-results.xml
@@ -27,12 +27,7 @@
<testcase classname='MSC_Tests' name='TC_lu_disconnect' time='MASKED'/>
<testcase classname='MSC_Tests' name='TC_lu_by_imei' time='MASKED'/>
<testcase classname='MSC_Tests' name='TC_lu_by_tmsi_noauth_unknown' time='MASKED'/>
- <testcase classname='MSC_Tests' name='TC_attached_imsi_lu_unknown_tmsi' time='MASKED'>
- <failure type='fail-verdict'>Expected LU ACK, but received REJ
- MSC_Tests.ttcn:MASKED MSC_Tests control part
- MSC_Tests.ttcn:MASKED TC_attached_imsi_lu_unknown_tmsi testcase
- </failure>
- </testcase>
+ <testcase classname='MSC_Tests' name='TC_attached_imsi_lu_unknown_tmsi' time='MASKED'/>
<testcase classname='MSC_Tests' name='TC_imsi_detach_by_imsi' time='MASKED'/>
<testcase classname='MSC_Tests' name='TC_imsi_detach_by_tmsi' time='MASKED'/>
<testcase classname='MSC_Tests' name='TC_imsi_detach_by_imei' time='MASKED'/>