osmo-trx - OpenBTS transceiver retro-fit

Age	Commit message (Collapse)	Author	Files	Lines
2017-06-09	build: Require and check for gcc C++11 support	Tom Tsou	2	-0/+1021
	It is now 2017. We can and should be able to use C++11 features now. Change-Id: I96477e4125390b17b43a3705bb1daf98fa01c9bb Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
2017-06-08	buildenv: cosmetic changes	Vadim Yanitskiy	1	-6/+8
	Change-Id: I9c52f2981513fa6322bdf992215e3e099ac3ddee
2017-06-08	buildenv: fix build on systems without SIMD support	Vadim Yanitskiy	1	-2/+3
	HAVE_SSE3 and HAVE_SSE4_1 were never defined if CPU architecture doesn't match the (86\|x86_64\|amd64*) condition. Change-Id: I3350b14dbc91e9b388d0b04a0ed22ba27d436313
2017-06-08	buildenv: actually strip unused cpuid functionality	Vadim Yanitskiy	3	-164/+0
	Despite the macro message says, that cpuid functionality was stripped it was still partially preset and wasn't used anyhow. Change-Id: I380bc9c13d29319685781ef27973afe6744fcf3d
2017-06-08	buildenv: correct the ax_sse macro description	Vadim Yanitskiy	1	-6/+5
	Change-Id: I4ce65443c8a33ae9add8f6da9d911c3178472ab2
2017-05-19	buildenv: Split up SSE3 and SSE4.1 code	Philipp Maier	1	-1/+5
	Currently we find SSE3 and SSE4.1 code mixed togehter along with generic code in one file. This introduces the risk that the compiler exidantly mixes SSE4.1 instructions into an SSE3, or even worse into a generic code path. This commit splits the SSE3 and SSE4.1 code into separate files and compiles them with the matching target options. Change-Id: I846e190e92f1258cd412d1b2d79b539e204e04b3
2017-05-19	buildenv: Make build CPU invariant	Philipp Maier	1	-166/+16
	Currently the build environment checks which extension the current CPU supports and picks the compiler flags accordingly. If the build is happening on a machine that does not support the extensions we need (SSE3, SSE4.1), the binary will lack those extensions, even if its intended to be used on a more powerful machine that would support the extensions. This commit removes the CPU tests from the build process. Change-Id: Ic913aa13c23c348ae62e78c9dfd6ed8b0a62798c
2013-10-18	Transceiver52M: Replace convolve and related calls with SSE implementation	Thomas Tsou	4	-0/+451
	This large patch replaced the convolve() call with an SSE vector enabled version. The lower C and SSE intrinsic based code operates on fixed and aligned vectors for the filter taps. The storage format of interleaved I/Q for both complex and real vectors is maintained. SSE filter tap values must: 1. Start 16-byte aligned 2. Number with a multiple of 4 between 4 and 20 for real taps 3. Number with a multiple of 4 for complex taps Non-compliant values will fall back to non-SSE usage. Fixed length iterators mean that head and tail cases may require reallocation of the input vector, which is automatically handled by the upper C++ interface. Other calls are affected by these changes and adjusted or rewritten accordingly. The underlying algorithms, however, are unchanged. generateGSMPulse() analyzeTrafficBurst() detectRACHBurst() Intel SSE configuration is automatically detected and configured at build time with Autoconf macros. Signed-off-by: Thomas Tsou <tom@tsou.cc>