path: root/config/ax_gcc_x86_cpuid.m4
AgeCommit message (Collapse)AuthorFilesLines
2017-06-08buildenv: actually strip unused cpuid functionalityVadim Yanitskiy1-79/+0
Despite the macro message says, that cpuid functionality was stripped it was still partially preset and wasn't used anyhow. Change-Id: I380bc9c13d29319685781ef27973afe6744fcf3d
2013-10-18Transceiver52M: Replace convolve and related calls with SSE implementationThomas Tsou1-0/+79
This large patch replaced the convolve() call with an SSE vector enabled version. The lower C and SSE intrinsic based code operates on fixed and aligned vectors for the filter taps. The storage format of interleaved I/Q for both complex and real vectors is maintained. SSE filter tap values must: 1. Start 16-byte aligned 2. Number with a multiple of 4 between 4 and 20 for real taps 3. Number with a multiple of 4 for complex taps Non-compliant values will fall back to non-SSE usage. Fixed length iterators mean that head and tail cases may require reallocation of the input vector, which is automatically handled by the upper C++ interface. Other calls are affected by these changes and adjusted or rewritten accordingly. The underlying algorithms, however, are unchanged. generateGSMPulse() analyzeTrafficBurst() detectRACHBurst() Intel SSE configuration is automatically detected and configured at build time with Autoconf macros. Signed-off-by: Thomas Tsou <tom@tsou.cc>