diff options
| author | Tom Tsou <tom.tsou@ettus.com> | 2016-08-11 15:15:04 -0700 |
|---|---|---|
| committer | Tom Tsou <tom.tsou@ettus.com> | 2016-08-11 15:17:55 -0700 |
| commit | 1cc9505011eeacda0b74e73159820a6c2242cc48 (patch) | |
| tree | aacb3dc502286977fc63ec266c145844dbbd670b /Transceiver52M | |
| parent | aa15d62a8cac2bfa30a336b76cd18f3b9647dd0d (diff) | |
uhd: Set default Rx sampling to 4 sps
Matching Tx and Rx sample rates reduces run-to-run timing
variability due to DDC/DUC timing ambiguity within the UHD
FPGA. Make this the default setting.
Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
Diffstat (limited to 'Transceiver52M')
| -rw-r--r-- | Transceiver52M/osmo-trx.cpp | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/Transceiver52M/osmo-trx.cpp b/Transceiver52M/osmo-trx.cpp index 5e81586..7c41780 100644 --- a/Transceiver52M/osmo-trx.cpp +++ b/Transceiver52M/osmo-trx.cpp @@ -43,11 +43,10 @@ /* * Samples-per-symbol for uplink (receiver) path - * Do not modify this value. EDGE configures 4 sps automatically on - * B200/B210 devices only. Use of 4 sps on the receive path for other - * configurations is not supported. + * 4 - Provides better timing precision (avoids FPGA DDC timing ambiguity) + * 1 - Reduces processor load, but increases timing ambiguity */ -#define DEFAULT_RX_SPS 1 +#define DEFAULT_RX_SPS 4 /* Default configuration parameters * Note that these values are only used if the particular key does not |