Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2020-10-14 | clock-generator: Add 'export' version of frontpanel (mirrored) | Harald Welte | 1 | -0/+4322 | |
2020-10-09 | clock-generator-frontpanel: Fix spacing of panel mount cut-outs | Harald Welte | 1 | -72/+72 | |
they must not be symmetric, but in multiple of 5.08mm | |||||
2020-10-09 | clock-generator: Add actual "TFP 7" outline | Harald Welte | 1 | -69/+589 | |
2020-10-09 | clock-converter/clock-generator frontpanels | Joachim Steiger | 1 | -0/+4166 | |
layout generated from eagle to dxf and transferring the measurements. no outline yet (needs offset pcb border to frontpanel corner) | |||||
2020-07-24 | clk-gen: commit GPIO pinsheet for SAMD21E in clk-gen v2 (solves OS#4656) | Martin Schramm | 1 | -0/+878 | |
... in Gnumeric format | |||||
2020-07-07 | clock-generator: create updated sch + brd views, purge old data | Martin Schramm | 5 | -0/+0 | |
2020-07-07 | clock-generator: purge old v1 eBOM | Martin Schramm | 1 | -727/+0 | |
2020-07-07 | clock-generator: upd ext'd BOM attributes and update v2 eBOM | Martin Schramm | 3 | -137/+1228 | |
2020-06-08 | clock-generator: update schematics pdf | Martin Schramm | 1 | -0/+0 | |
2020-03-01 | clock-generator: Fix VDD connection of TC2050 SWD connector | Harald Welte | 2 | -10/+11 | |
Closes: OS#4431 | |||||
2020-02-07 | clock-gen: increase I2C PU's to 4k7 | Martin Schramm | 2 | -24/+24 | |
Although the SI5153 datasheet mentions the I2C PUs as ">=1k", this appears to be unusually strong for no obvious reason, and we don't have high data rates there... changed them to more reasonable 4k7. | |||||
2020-01-31 | clock-gen: update ATSAMD21's BOM attributes (solves OS#4387) | Martin Schramm | 2 | -23/+23 | |
2020-01-30 | clock-generator: exchange mini-USB foorprint (solves OS#4386) | Martin Schramm | 2 | -191/+63 | |
... and purge unneeded layers | |||||
2020-01-28 | clock-generator: exchange silk screen position of R14 vs. C19 | Martin Schramm | 1 | -2/+2 | |
fortunately, they have a different size (0603 vs 0402), so while placing this be#came obvious. | |||||
2019-11-05 | clock-generator: Replace SAM D11 data sheet with D21 data sheet | Harald Welte | 1 | -0/+0 | |
2019-06-19 | clock-generator: Move GND via to avoid overlap with N$15 | Harald Welte | 1 | -6/+6 | |
2019-06-19 | <osmo-clock-gen: add more TVS for exposed signals, clean up and finish | Martin Schramm | 2 | -536/+1391 | |
2019-06-19 | osmo-clock-gen: capacitive coupling for XA input needed - added 100n | Martin Schramm | 2 | -58/+101 | |
This was a remark by tnt, thanks. | |||||
2019-06-19 | clock-generator: compacting + place MTA100 header (solves OSM#4050) | Martin Schramm | 2 | -1208/+509 | |
2019-06-19 | clock-generator: changes adressing OSM#4050 | Martin Schramm | 2 | -1831/+2677 | |
A shouded UEXT would need much space; no room for an MTA100 yet... tbd | |||||
2019-06-19 | clock-generator: insert changes discussed so far for v2 | Martin Schramm | 2 | -4207/+7211 | |
* selectable VDDIO{1..4} for PLL: either 3V3 or ADJ (VOUT/DAC) * use SAMD21 instead of SAMD11 * bring some GPIO on pin header * use GCLK_IO4 (PA10) to feed XA of PLL | |||||
2019-06-19 | clock-generator: add tracking LDO, make PCB four layer | Martin Schramm | 2 | -634/+1045 | |
2019-06-19 | WIP: click-generator: Replace U3 (so far SAMD11) with SAMD21 | Harald Welte | 2 | -775/+696 | |
Closes: OS#3856 | |||||
2019-01-28 | clock-gen: Add BOM information + PDF exports of schematics | Harald Welte | 5 | -298/+3653 | |
2019-01-27 | clock-gen: Update gpio spreadsheet with all assignments | Harald Welte | 1 | -30/+73 | |
The assignments have been chosen to be nearly identical to the SAMD11-XPRO board. | |||||
2019-01-27 | clock-gen: Minor changes; final version as ordered | Harald Welte | 2 | -40/+52 | |
* move DC jack to extend beyond PCB edge into front panel * harmonize component variants (10n only 0402, 4.7u only 0805) * add "sysmocom" as manufacturer name (WEEE requirement) | |||||
2019-01-27 | clock-gen: Cosmetic changes | Harald Welte | 2 | -1118/+1177 | |
2019-01-27 | clock-gen: finish routing of PCB layout | Harald Welte | 4 | -442/+1596 | |
2019-01-26 | clock-gen: Connect EEPROM WP to GND to disable write-protect | Harald Welte | 2 | -0/+6 | |
2019-01-26 | clock-gen: Add SPI; UEXT header; mounting holes; do layout/routing | Harald Welte | 3 | -177/+1042 | |
2019-01-23 | clock-generator: Most of the layout | Harald Welte | 2 | -2093/+2770 | |
Traces are intended for dual-layer 1mm FR4 PCB with 35um copper. | |||||
2019-01-23 | clock-generator: More schematics work; initial placement/grouping | Harald Welte | 2 | -0/+2366 | |
* add I2C EEPROM * start board design file * group parts to their respective "main part" * define TC-2030 pinout | |||||
2019-01-21 | clock-generator: More work on schematics (USB, UART, ESD) | Harald Welte | 1 | -57/+868 | |
2019-01-16 | initial check-in of upcoming clock-generator board | Harald Welte | 9 | -0/+114422 | |