Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2019-01-27 | clock-gen: finish routing of PCB layout | Harald Welte | 4 | -442/+1596 |
2019-01-26 | clock-gen: Connect EEPROM WP to GND to disable write-protect | Harald Welte | 2 | -0/+6 |
2019-01-26 | clock-gen: Add SPI; UEXT header; mounting holes; do layout/routing | Harald Welte | 3 | -177/+1042 |
2019-01-23 | clock-generator: Most of the layout | Harald Welte | 2 | -2093/+2770 |
2019-01-23 | clock-generator: More schematics work; initial placement/grouping | Harald Welte | 2 | -0/+2366 |
2019-01-21 | clock-generator: More work on schematics (USB, UART, ESD) | Harald Welte | 1 | -57/+868 |
2019-01-16 | initial check-in of upcoming clock-generator board | Harald Welte | 9 | -0/+114422 |