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2019-08-27ngff: finishing worklaforge/ngff-breakoutMartin Schramm2-1026/+1632
2019-08-27Merge branch 'laforge/ngff-breakout' of ↵Martin Schramm0-0/+0
ssh://git.osmocom.org/osmo-small-hardware into laforge/ngff-breakout
2019-08-16ngff-breakout: almost readyMartin Schramm2-3413/+7664
missing: more vias, more ext. attributes (for BOM)
2019-08-16ngff-breakout: intermediate stateMartin Schramm2-2974/+2471
2019-08-16ngff-breakout: make 4layer PCBMartin Schramm1-265/+55
2019-08-16ngff-breakout: Update con-ngff.lbr to get PCIe lanesHarald Welte1-0/+26
2019-08-16ngff-breakout: Partial migration over to NGFFHarald Welte2-1221/+741
The mPCIe slot has been removed and the NGFF slot added. Basic connections have been made in the schematics, but it's far from being complete. No effort on the PCB routing has been made so far.
2019-08-16ngff-breakout: Rename "mPCIe" -> "NGFF WWAN" and re-start version at v1Harald Welte2-10/+10
2019-08-16Add ngff-breakout as copy of mpcie-breakoutHarald Welte3-0/+18191
... ngff specific modifications will follow
2019-08-15ngff-breakout: almost readyMartin Schramm2-3413/+7664
missing: more vias, more ext. attributes (for BOM)
2019-08-07add SC14CVMDECT module breakout boardHarald Welte2-0/+18026
2019-06-22v3 final with gerber outputohm4_ocxo_v3Harald Welte12-0/+7484
2019-06-22final v3 as it goes in pcb productionHarald Welte2-85/+178
* smash components and move labels to where they can be read * add indication of + / GND to X3/X4 * re-route some traces to ensure sufficient distance between them * make all traces 0.508 mm wide, even signal traces.
2019-06-22update OHM4 OCXO, preliminary v3Harald Welte2-538/+532
* use new LDO (single LDO with range up to 12V input) * add U.FL clock input (instead of OCXO as source) * no parallel, but series resistors to trimmer * allow output of PLL to be fed through resistive divider
2019-06-22remove .pro file, not neededHarald Welte1-25/+0
2019-06-22update to version with PLL ic onboardHarald Welte4-98/+351
2019-06-22initial import of OHM4 OCXO boardHarald Welte5-0/+10578
2019-06-22add gerber output of osm-nvs-gps v3Harald Welte10-0/+4334
2019-06-22avoid short-circuit of power LEDHarald Welte4-8/+7
2019-06-22update PDF schematics and placement to v2ohm4_ocxo_v2Harald Welte2-0/+0
2019-06-22add a power-indicator LED to the NVS board and tag it v2Harald Welte2-41/+451
2019-06-22initial import of osmo-nvs-gps projectHarald Welte5-0/+9316
This is a small eval board for the NVS GPS/GLONASS/GALILEO module, exporting UARTs on headers.
2019-06-22update gerbers...Harald Welte4-664/+681
2019-06-22don't put solder cream on SMA edge pads.Harald Welte2-194/+204
The sma edge connectors are hand soldered after the SMT soldering is already done. We don't want to have solder paste on them...
2019-06-22component placement PDFs bottom and topHarald Welte2-0/+0
2019-06-22re-generate geber (fiducials, labels on soldermask)Harald Welte6-1678/+1803
2019-06-22move fonts on bottom to soldermask layer (no silk screen rqd)Harald Welte1-3/+3
2019-06-22add fiducials for automatic mounting of componentsHarald Welte1-0/+24
2019-06-22Specify LED series resistor as 100 OhmsHarald Welte2-2/+2
2019-06-22mark R1 as 'DNP' (no stub to U.FL connector)Harald Welte2-2/+2
2019-06-22add placement files for top and bottomHarald Welte2-0/+53
2019-06-22import gerber outputHarald Welte10-0/+12173
2019-06-22add CAM file for generating gerber outputHarald Welte1-0/+135
2019-06-22remove D45014F marking (seeedstudio)Harald Welte1-1/+0
2019-06-22update the _brd.pdf to include the LED and R13 and correspond with schemsticsHarald Welte1-0/+0
2019-06-22add updated PDF schematicsHarald Welte1-0/+0
2019-06-22approve various ERC changesHarald Welte2-3/+21
2019-06-22re-merge my previous changes manually into the projectHarald Welte2-24/+25
2019-06-22sylvains branch (ignores some of harald's changes)Harald Welte2-59/+1678
2019-06-22don't have two SERIAL_RXD labels but one RXD and one TXDHarald Welte1-1/+1
2019-06-22add ublox LEA6T evaluation board design, first versionHarald Welte4-0/+13218
2019-06-19Merge branch 'laforge/clock-gen-v2'Harald Welte2-5152/+9533
2019-06-19clock-generator: Move GND via to avoid overlap with N$15Harald Welte1-6/+6
2019-06-19<osmo-clock-gen: add more TVS for exposed signals, clean up and finishMartin Schramm2-536/+1391
2019-06-19osmo-clock-gen: capacitive coupling for XA input needed - added 100nMartin Schramm2-58/+101
This was a remark by tnt, thanks.
2019-06-19clock-generator: compacting + place MTA100 header (solves OSM#4050)Martin Schramm2-1208/+509
2019-06-19clock-generator: changes adressing OSM#4050Martin Schramm2-1831/+2677
A shouded UEXT would need much space; no room for an MTA100 yet... tbd
2019-06-19clock-generator: insert changes discussed so far for v2Martin Schramm2-4207/+7211
* selectable VDDIO{1..4} for PLL: either 3V3 or ADJ (VOUT/DAC) * use SAMD21 instead of SAMD11 * bring some GPIO on pin header * use GCLK_IO4 (PA10) to feed XA of PLL
2019-06-19clock-generator: add tracking LDO, make PCB four layerMartin Schramm2-634/+1045
2019-06-19WIP: click-generator: Replace U3 (so far SAMD11) with SAMD21Harald Welte2-775/+696
Closes: OS#3856
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