AgeCommit message (Collapse)AuthorFilesLines
2019-06-06ngff-breakout: Update con-ngff.lbr to get PCIe lanesclock_gen-v2Harald Welte1-0/+26
2019-06-06ngff-breakout: Partial migration over to NGFFHarald Welte2-1221/+741
The mPCIe slot has been removed and the NGFF slot added. Basic connections have been made in the schematics, but it's far from being complete. No effort on the PCB routing has been made so far.
2019-06-06ngff-breakout: Rename "mPCIe" -> "NGFF WWAN" and re-start version at v1Harald Welte2-10/+10
2019-06-06Add ngff-breakout as copy of mpcie-breakoutHarald Welte3-0/+18191
... ngff specific modifications will follow
2019-05-09sfp-*: add OSHW logo, fill ext'd attribs for BOMMartin Schramm4-444/+912
2019-05-08sfp: update BOMs for both breakout and experimenter PCBsMartin Schramm2-0/+1059
2019-02-14clock-converter: Export BOMHarald Welte1-0/+591
2019-02-14clock-converter: Add attributes with digikey linksHarald Welte2-106/+1589
2019-02-02Clock converter for low phase noise sine -> square conversionHarald Welte5-0/+5194
2019-01-28clock-gen: Add BOM information + PDF exports of schematicsHarald Welte5-298/+3653
2019-01-27clock-gen: Update gpio spreadsheet with all assignmentsHarald Welte1-30/+73
The assignments have been chosen to be nearly identical to the SAMD11-XPRO board.
2019-01-27Merge branch 'laforge/clock-gen'Harald Welte12-0/+120372
2019-01-27clock-gen: Minor changes; final version as orderedHarald Welte2-40/+52
* move DC jack to extend beyond PCB edge into front panel * harmonize component variants (10n only 0402, 4.7u only 0805) * add "sysmocom" as manufacturer name (WEEE requirement)
2019-01-27clock-gen: Cosmetic changesHarald Welte2-1118/+1177
2019-01-27clock-gen: finish routing of PCB layoutHarald Welte4-442/+1596
2019-01-26clock-gen: Connect EEPROM WP to GND to disable write-protectHarald Welte2-0/+6
2019-01-26clock-gen: Add SPI; UEXT header; mounting holes; do layout/routingHarald Welte3-177/+1042
2019-01-23clock-generator: Most of the layoutHarald Welte2-2093/+2770
Traces are intended for dual-layer 1mm FR4 PCB with 35um copper.
2019-01-23clock-generator: More schematics work; initial placement/groupingHarald Welte2-0/+2366
* add I2C EEPROM * start board design file * group parts to their respective "main part" * define TC-2030 pinout
2019-01-21clock-generator: More work on schematics (USB, UART, ESD)Harald Welte1-57/+868
2019-01-16initial check-in of upcoming clock-generator boardHarald Welte9-0/+114422
2019-01-08SFP: publish experimenter and breakout schematicss as pdfMartin Schramm2-0/+0
2018-10-06add SFP multi-source agreement to give context to the boardsHarald Welte1-0/+0
2018-09-05sfp-breakout: X1 pin 5 missing connection to VCC_3V3Harald Welte2-0/+6
Due to an overisght, pin 5 of the X1 header was missing the intended connection to the 3V3 plane. Let's fix this. No routing changes on the PCB required, as this simply connects the VCC plane layer to the through-hole.
2018-08-30sfp: add part numbers for SFP conn and cageMartin Schramm4-10/+14
2018-08-23mvuart: align JP2 in 0.1' grid with JP3 (solves OSM#3037)Martin Schramm1-50/+60
2018-08-21sfp-{breakout,experimenter}: Commit GERBER exportssfp-v1Harald Welte28-0/+77913
2018-08-21sfp: Use minimum clearance of 0.25mm as 0.15mm is needlessly tight in this boardHarald Welte2-12/+12
2018-08-17sfp: remove unneeded layer in brd + schMartin Schramm3-165/+0
2018-08-17sfp: add LOS, TX_FAULT LEDs + add more supply pinheader on both PCBsMartin Schramm4-1152/+9484
2018-08-17spf: revise both SFP designs (OSM#3313/OSM#3314)Martin Schramm4-2394/+4653
2018-06-19sfp: commit simple SFP breakout (OSM#3313)Martin Schramm2-0/+13258
2018-06-19sfp: add license to schMartin Schramm1-0/+8
2018-06-19sfp: commit first proposal for PCB w/ LVDS xcvr (adresses OSM#3314)Martin Schramm2-0/+13713
2018-06-08sfp: add Eagle libs for SN65LVDS1 and SN65LVDT2 (single line LVDS rcv/drv)Martin Schramm2-0/+455
2018-06-07sfp: add Eagle lib for SN65LVDS180 LVDS diff line xcvrMartin Schramm1-0/+263
2018-06-06sfp.lbr: review tnt's SFP lib, refineMartin Schramm1-0/+483
2018-05-18mv-uart.brd: add signal names of JP2,JP3,JP5 in bottom silk screenMartin Schramm1-102/+76
solves OSM#2387
2017-07-22mv-uart: annotate individual pins in brd and generate mv-uart-pinout.pdfHarald Welte2-0/+19
2017-05-24mpcie-breakout: add v3 picturesHarald Welte5-0/+0
2017-05-07e1-tap: Add BOM attributesHarald Welte2-21/+258
2017-05-07import e1-tap design filesHarald Welte16-0/+9085
This is a project started in 2012 to have an easy-to-use E1/T1 tap.
2017-04-04mpcie-breakout: update schematics + placement PDF with v3Harald Welte2-0/+0
2017-04-04mpcie-breakout: update .mnt/.mnb files with v3 pcbHarald Welte2-10/+13
2017-03-25mpcie-breakout: move PCB specs to pcb subdirectory where they belongHarald Welte2-0/+0
2017-03-25import PCB and stencil specs for v3Harald Welte2-0/+0
2017-03-23mpcie-breakout: update BOMHarald Welte1-33/+67
2017-03-23mpcie-breakout: Restore link for M1 (mPCIe mounting clamp)Harald Welte1-5/+1
2017-03-23mpcie-breakout: Change to vertical SMA jacksHarald Welte2-26/+31
2017-03-23mpcie-breakout: rounding of padsHarald Welte1-3/+3