AgeCommit message (Collapse)AuthorFilesLines
2017-03-23mpcie-breakout: DRC changesHarald Welte1-3/+17
2017-03-23mpcie-breakout: disable tPlace layerHarald Welte1-1/+1
2017-03-23mpcie-breakout: USB_VBUS second parallel via to reduce impedanceHarald Welte1-0/+4
2017-03-23mpcie-breakout: Digikey part numbers for U.FL and SMAHarald Welte2-17/+198
2017-03-23mcie-breakout: Align bLabels, more vias, cosmeticsHarald Welte2-28/+129
2017-03-23mpcie-breakout: Add third U.FL-SMA groupHarald Welte2-24/+75
2017-03-23mpcie-breakout: Enlarge to 70x70mm, add SMA, U.FL and Mounting HolesHarald Welte2-232/+589
2016-12-05mv-uart: Fix 'board doesn't enumerate if JP4 is closed" issueHarald Welte3-82/+22
Make sure the LDO is always powered up, so the CP2105 internal and external !RESET pull-ups are towards an active VIO voltage, rather than one that is switched off by !SUSPEND and thus keeps the CP2105 in reset. Closes: #1870 (https://osmocom.org/issues/1870)
2016-11-25add PCBA photographsHarald Welte4-0/+0
2016-10-28mpcie-breakoud: Add pdf renderings of schematicsmv_uart-v1mpcie_breakout-v2Harald Welte2-0/+0
2016-10-28add mnb/mt files for mv-uart and mpcie-breakoutHarald Welte3-0/+66
2016-10-28mpcie-breakout: mark C4 as POPULATED=FALSEHarald Welte3-6/+10
2016-10-28mv-uart: Add schematics + placement as PDFHarald Welte2-0/+0
2016-10-28mv-uart: Add digikey attributes for various 2.54mm hedaersHarald Welte3-61/+79
2016-10-28add PCB panel images for mv-uart and mpcie-breakoutHarald Welte2-0/+0
2016-10-27mpcie-breakout: Change '1' marker of JP4 and avoid silk-screen overlapHarald Welte1-2/+5
2016-10-27mpcie-breakout: fix DRC violations (clearance)Harald Welte1-25/+28
2016-10-27mpcie-breakout: Add series LED for LED_WWANHarald Welte2-18/+63
2016-10-27mpcie-breakout: Fix R4 (0603, not 0201 part)Harald Welte3-16/+16
2016-10-27mpcie-breakout: change 100uF caps from 1210 to 1206, reducing heightHarald Welte3-165/+262
The current 100uF caps are too high at 2.9mm. They touch the shielding can of Quectel EC-20 modules, for exampel. Let's use 1206 packaged versions at 1.6mm instead. Also, add two more, for safety.
2016-10-27mv-uart: Use SP6T flash *without* OFF positionHarald Welte3-11/+11
2016-10-10mpci-breakout: Add BOM attributes + export BOMHarald Welte3-201/+598
2016-10-10add .gitignoreHarald Welte1-0/+5
2016-10-10Complete BOM attributes + export BOMHarald Welte4-384/+838
2016-10-09mpcie-breakout: Beautify schematicsHarald Welte1-707/+725
2016-10-09mv-uart: Add PDF renderingsHarald Welte2-0/+0
2016-10-09mv-uart: Beatify schematics + Add commentsHarald Welte1-678/+711
2016-10-09mpcie-breakout: Add Digikey LINK for all major partsHarald Welte2-50/+668
2016-10-09mv-uart: Add digikey link for all major partsHarald Welte2-81/+1213
2016-10-08mv-uart: Add generated gerber filesHarald Welte12-0/+13830
2016-10-08mv-uart: use Seeed Studio DRUHarald Welte1-30/+34
2016-10-08mv-uart: Add labels with name / copyright / licenseHarald Welte1-3/+14
2016-10-08mv-uart: align tNames labels in non-overlapping fashionHarald Welte1-45/+153
2016-10-08mpcie-breakout: add rendered gerber filesHarald Welte12-0/+27996
2016-10-08mpcie-breakoud: Fix layer of JP4 label on silk-screenHarald Welte1-1/+1
2016-10-08initial import of new mpcie breakout board projectHarald Welte3-0/+16694
2016-10-08move all mv-uart files to sub-directoryHarald Welte6-0/+0
2016-10-07first fully routed version of mv-uartHarald Welte2-84/+234
2016-10-07WIP: design for a multi-voltage USB UARTHarald Welte6-0/+5220
* an adjustible LDO with rotary switch is able to configure the UART voltage levels as needed. * alternatively, the UART logic level voltage (in the 1.8-3.3V range) can be provided by an external voltage reference. * TVS diodes protect the USB and UART sides from overvoltage and ESD * all voltages are available on a header to supply external circuitry * five GPIO pins are available on a header