diff options
author | Harald Welte <laforge@osmocom.org> | 2020-09-10 22:50:23 +0200 |
---|---|---|
committer | Harald Welte <laforge@osmocom.org> | 2020-09-10 22:50:23 +0200 |
commit | cdd8f3c4d4cb69caffc50e4e6a179a7d4118826f (patch) | |
tree | 070d7ea08b5f622e9788f7a50bb8fc8ef27727eb | |
parent | ba452d6f699b49db79cfc4800e1315a2e3f45d2e (diff) |
mpcie-breakout: Remove GND via underneath U.FL connectors
-rw-r--r-- | mpcie-breakout/mpcie-breakout.brd | 9 | ||||
-rw-r--r-- | mpcie-breakout/mpcie-breakout.sch | 38 |
2 files changed, 41 insertions, 6 deletions
diff --git a/mpcie-breakout/mpcie-breakout.brd b/mpcie-breakout/mpcie-breakout.brd index 0b91163..fb459c1 100644 --- a/mpcie-breakout/mpcie-breakout.brd +++ b/mpcie-breakout/mpcie-breakout.brd @@ -28,7 +28,7 @@ <layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/> <layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/> <layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/> -<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="yes"/> +<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/> <layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/> <layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/> <layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/> @@ -748,6 +748,8 @@ Source: http://www.osram.convergy.de/ ... Lb_q993.pdf</description> <wire x1="1.5" y1="-1.5" x2="1.5" y2="-1.3" width="0.127" layer="21"/> <text x="-3" y="0" size="1.27" layer="25" rot="R90" align="center">>NAME</text> <text x="3" y="0" size="1.27" layer="27" rot="R90" align="center">>VALUE</text> +<rectangle x1="-0.9" y1="-0.95" x2="0.9" y2="1.27" layer="41"/> +<rectangle x1="-0.9" y1="-0.95" x2="0.9" y2="1.27" layer="43"/> </package> </packages> </library> @@ -2109,7 +2111,7 @@ Source: www.farnell.com/datasheets/247.pdf</description> </library> </libraries> <attributes> -<attribute name="VERSION" value="v3"/> +<attribute name="VERSION" value="v3.1"/> </attributes> <variantdefs> </variantdefs> @@ -3030,9 +3032,6 @@ design rules under a new name.</description> <via x="-8.89" y="26.162" extent="1-16" drill="0.3"/> <via x="-7.366" y="26.162" extent="1-16" drill="0.3"/> <via x="-5.842" y="24.892" extent="1-16" drill="0.3"/> -<via x="-8.128" y="23.368" extent="1-16" drill="0.3"/> -<via x="-8.128" y="13.208" extent="1-16" drill="0.3"/> -<via x="-3.302" y="11.684" extent="1-16" drill="0.3"/> <via x="-5.842" y="23.622" extent="1-16" drill="0.3"/> <via x="-5.842" y="21.844" extent="1-16" drill="0.3"/> <via x="-8.128" y="20.32" extent="1-16" drill="0.3"/> diff --git a/mpcie-breakout/mpcie-breakout.sch b/mpcie-breakout/mpcie-breakout.sch index 903200c..d750848 100644 --- a/mpcie-breakout/mpcie-breakout.sch +++ b/mpcie-breakout/mpcie-breakout.sch @@ -4001,6 +4001,30 @@ High volt MLC; no solder stop between for higher isolation</description> <wire x1="1.5" y1="-1.5" x2="1.5" y2="-1.3" width="0.127" layer="21"/> <text x="-3" y="0" size="1.27" layer="25" rot="R90" align="center">>NAME</text> <text x="3" y="0" size="1.27" layer="27" rot="R90" align="center">>VALUE</text> +<rectangle x1="-0.9" y1="-0.95" x2="0.9" y2="1.27" layer="41"/> +<rectangle x1="-0.9" y1="-0.95" x2="0.9" y2="1.27" layer="43"/> +</package> +<package name="SMA-F-S-TH-73251-2201"> +<description>Molex 73251-2201</description> +<pad name="C" x="0" y="0" drill="1.5"/> +<pad name="G1" x="-2.54" y="2.54" drill="1.5"/> +<pad name="G2" x="2.54" y="2.54" drill="1.5"/> +<pad name="G4" x="2.54" y="-2.54" drill="1.5"/> +<pad name="G3" x="-2.54" y="-2.54" drill="1.5"/> +<text x="-3.81" y="4.1275" size="1.27" layer="25" font="vector" ratio="10">>NAME</text> +<text x="-3.81" y="-5.3975" size="1.27" layer="27" font="vector" ratio="10">>VALUE</text> +<wire x1="-5.08" y1="3.25" x2="-16.51" y2="3.25" width="0.127" layer="21"/> +<wire x1="-16.51" y1="3.25" x2="-16.51" y2="-3.25" width="0.127" layer="21"/> +<wire x1="-16.51" y1="-3.25" x2="-5.08" y2="-3.25" width="0.127" layer="21"/> +<wire x1="-5.08" y1="3.5" x2="-5.08" y2="3.25" width="0.127" layer="21"/> +<wire x1="-5.08" y1="3.25" x2="-5.08" y2="-3.25" width="0.127" layer="21"/> +<wire x1="-5.08" y1="-3.25" x2="-5.08" y2="-3.5" width="0.127" layer="21"/> +<wire x1="-3.5" y1="3.5" x2="3.05" y2="3.5" width="0.127" layer="21"/> +<wire x1="3.05" y1="3.5" x2="3.05" y2="-3.5" width="0.127" layer="21"/> +<wire x1="3.05" y1="-3.5" x2="-3.5" y2="-3.5" width="0.127" layer="21"/> +<wire x1="-3.5" y1="-3.5" x2="-3.5" y2="3.5" width="0.127" layer="21"/> +<wire x1="-3.5" y1="-3.5" x2="-5.08" y2="-3.5" width="0.127" layer="21"/> +<wire x1="-5.08" y1="3.5" x2="-3.5" y2="3.5" width="0.127" layer="21"/> </package> </packages> <symbols> @@ -4118,6 +4142,18 @@ High volt MLC; no solder stop between for higher isolation</description> <technology name=""/> </technologies> </device> +<device name="73251-2201" package="SMA-F-S-TH-73251-2201"> +<connects> +<connect gate="G" pin="1" pad="C"/> +<connect gate="G" pin="GND@1" pad="G1"/> +<connect gate="G" pin="GND@2" pad="G2"/> +<connect gate="G" pin="GND@3" pad="G3"/> +<connect gate="G" pin="GND@4" pad="G4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> </devices> </deviceset> <deviceset name="HRS_UFL" prefix="X" uservalue="yes"> @@ -12483,7 +12519,7 @@ DIN A4, landscape with extra doc field</description> </library> </libraries> <attributes> -<attribute name="VERSION" value="v3"/> +<attribute name="VERSION" value="v3.1"/> </attributes> <variantdefs> </variantdefs> |