diff options
author | Harald Welte <laforge@gnumonks.org> | 2012-03-05 23:20:18 +0100 |
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committer | Harald Welte <laforge@gnumonks.org> | 2012-03-05 23:20:18 +0100 |
commit | ef60309e63b99c5ccafb6b3b4a7835f4f19076c8 (patch) | |
tree | a719a9fcbe5353514746c73d2805b47509c048ee | |
parent | df93598cc82c5d5169f379970a5e4f99d0eb415c (diff) |
osdr_fpga: Add support for enabling test (counter) mode
-rw-r--r-- | firmware/src/osdr_fpga.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/firmware/src/osdr_fpga.c b/firmware/src/osdr_fpga.c index 4562c16..03e3cfb 100644 --- a/firmware/src/osdr_fpga.c +++ b/firmware/src/osdr_fpga.c @@ -188,6 +188,28 @@ static int cmd_fpga_field(struct cmd_state *cs, enum cmd_op op, return reg_field_cmd(cs, op, cmd, argc, argv, &fpga_fops); } +static int cmd_fpga_test(struct cmd_state *cs, enum cmd_op op, + const char *cmd, int argc, char **argv) +{ + uint32_t on; + + /* in the test mode, the FPGA will not send samples but an incrementing + * and decrementing counter to detect lost samples. */ + switch (op) { + case CMD_OP_SET: + if (atoi(argv[0]) == 0) + on = 0; + else + on = 1; + osdr_fpga_reg_write(4, on); + break; + case CMD_OP_GET: + printf("FPGA Test mode is %u\n\r", osdr_fpga_reg_read(4)); + break; + } + return 0; +} + static struct cmd cmds[] = { { "fpga.dump", CMD_OP_EXEC, cmd_fpga_dump, "Dump FPGA registers" }, @@ -203,6 +225,8 @@ static struct cmd cmds[] = { "FPGA Clock Divider for ADC (80 MHz/CLKDIV)" }, { "fpga.adc_acqlen", CMD_OP_SET|CMD_OP_GET, cmd_fpga_field, "Num of SCK cycles nCS to AD7357 is held high betewen conversions" }, + { "fpga.test_mode", CMD_OP_SET|CMD_OP_GET, cmd_fpga_test, + "Enable/disable test mode" }, }; |