diff options
Diffstat (limited to 'tests/msc_vlr/msc_vlr_test_call.err')
| -rw-r--r-- | tests/msc_vlr/msc_vlr_test_call.err | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/msc_vlr/msc_vlr_test_call.err b/tests/msc_vlr/msc_vlr_test_call.err index b65165952..a8c79847e 100644 --- a/tests/msc_vlr/msc_vlr_test_call.err +++ b/tests/msc_vlr/msc_vlr_test_call.err @@ -695,7 +695,7 @@ DMSC dummy_msc_i{0}: is child of msub_fsm DREF msc_a(unknown:UTRAN-Iu:NONE){MSC_A_ST_VALIDATE_L3}: + rx_from_ms: now used by 1 (rx_from_ms) DIUCS msc_a(unknown:UTRAN-Iu:NONE){MSC_A_ST_VALIDATE_L3}: RAN decode: COMPL_L3 DRLL msc_a(unknown:UTRAN-Iu:NONE){MSC_A_ST_VALIDATE_L3}: Dispatching 04.08 message: RR GSM48_MT_RR_PAG_RESP -DRR msc_a(IMSI-901700000010650:UTRAN-Iu:PAGING_RESP){MSC_A_ST_VALIDATE_L3}: Rx PAGING RESPONSE +DRR msc_a(IMSI-901700000010650:UTRAN-Iu:PAGING_RESP){MSC_A_ST_VALIDATE_L3}: Rx PAGING RESPONSE IMSI-901700000010650 DREF msc_a(IMSI-901700000010650:UTRAN-Iu:PAGING_RESP){MSC_A_ST_VALIDATE_L3}: + paging-response: now used by 2 (rx_from_ms,paging-response) DVLR Process_Access_Request_VLR(IMSI-901700000010650:UTRAN-Iu:PAGING_RESP){PR_ARQ_S_INIT}: Allocated DVLR Process_Access_Request_VLR(IMSI-901700000010650:UTRAN-Iu:PAGING_RESP){PR_ARQ_S_INIT}: is child of msc_a(IMSI-901700000010650:UTRAN-Iu:PAGING_RESP) @@ -1166,7 +1166,7 @@ DMSC dummy_msc_i{0}: is child of msub_fsm DREF msc_a(unknown:UTRAN-Iu:NONE){MSC_A_ST_VALIDATE_L3}: + rx_from_ms: now used by 1 (rx_from_ms) DIUCS msc_a(unknown:UTRAN-Iu:NONE){MSC_A_ST_VALIDATE_L3}: RAN decode: COMPL_L3 DRLL msc_a(unknown:UTRAN-Iu:NONE){MSC_A_ST_VALIDATE_L3}: Dispatching 04.08 message: RR GSM48_MT_RR_PAG_RESP -DRR msc_a(IMSI-901700000010650:UTRAN-Iu:PAGING_RESP){MSC_A_ST_VALIDATE_L3}: Rx PAGING RESPONSE +DRR msc_a(IMSI-901700000010650:UTRAN-Iu:PAGING_RESP){MSC_A_ST_VALIDATE_L3}: Rx PAGING RESPONSE IMSI-901700000010650 DREF msc_a(IMSI-901700000010650:UTRAN-Iu:PAGING_RESP){MSC_A_ST_VALIDATE_L3}: + paging-response: now used by 2 (rx_from_ms,paging-response) DVLR Process_Access_Request_VLR(IMSI-901700000010650:UTRAN-Iu:PAGING_RESP){PR_ARQ_S_INIT}: Allocated DVLR Process_Access_Request_VLR(IMSI-901700000010650:UTRAN-Iu:PAGING_RESP){PR_ARQ_S_INIT}: is child of msc_a(IMSI-901700000010650:UTRAN-Iu:PAGING_RESP) |