aboutsummaryrefslogtreecommitdiffstats
AgeCommit message (Expand)AuthorFilesLines
2020-07-31relax the timeoutsEric Wild1-2/+9
2020-07-31ccid: support warm resetEric Wild1-16/+27
2020-07-31ccid: handle timeoutsEric Wild1-2/+18
2020-07-31Enable timersEric Wild1-1/+1
2020-07-31handle card ejection during poweron/wait for ATREric Wild1-12/+26
2020-07-30contrib/jenkins.sh: Disable thread-local storage in libosmocoreHarald Welte1-1/+2
2020-07-30contrib/jenkins.sh: Disable libosmogb (we certainly don't need it)Harald Welte1-1/+1
2020-07-30Fix returned data in case of command TPDUHarald Welte2-1/+5
2020-03-17switch to using 'usbrelay' and more generic,inexpensive relay boardJoachim Steiger7-75/+40
2020-03-03generic improvements for the testsbedJoachim Steiger20-26/+214
2020-02-25Implement CI scripts for testing the resulting binary on hardware for jenkinsJoachim Steiger20-0/+506
2020-02-10dfu: proper product name for dfu runtime descriptorEric Wild2-2/+2
2020-02-10usb dfu header cleanupEric Wild6-317/+44
2020-02-10git version appended to the product usb string descriptorEric Wild2-6/+25
2020-02-10support DFU detach to switch from fw to bootloaderEric Wild8-3/+658
2020-02-10Add DFU runtime descriptorHarald Welte4-4/+133
2020-02-06Implement serial number string descriptor in CTRL EP callbackHarald Welte3-3/+77
2020-01-28PC_to_RDR_ResetParameters fixEric Wild1-0/+2
2020-01-28PC_to_RDR_SetDataRateAndClockFrequency supportEric Wild3-4/+9
2020-01-14reserve RAM for DFU magicKévin Redon2-2/+4
2019-12-17jenkins.sh: Add verify_value_string_arrays_are_terminated.pyHarald Welte1-0/+2
2019-12-17Add --disable-libusb for libosmocore cross-compileHarald Welte1-1/+1
2019-12-06change iManufacturer to full sysmocom company nameHarald Welte4-6/+6
2019-12-02reenable host buildsEric Wild1-2/+2
2019-12-02rename the global talloc contextEric Wild3-15/+15
2019-12-02fix the host/emulation buildEric Wild5-19/+32
2019-12-01Check for osmo_fsm_register() error return valueHarald Welte1-4/+4
2019-11-30jenkins.sh: Add --publish to publish binaries, similar to simtrace2.gitHarald Welte1-1/+25
2019-11-28reenable firmware build0.2Eric Wild1-3/+3
2019-11-28prettier slot bitmask codeEric Wild1-2/+2
2019-11-28enable the final slotEric Wild12-264/+353
2019-11-28first attempt at rx timeout handlingEric Wild3-28/+142
2019-11-28cuart cleanupEric Wild1-15/+15
2019-11-28cuart: fix etu calculationEric Wild1-2/+6
2019-11-28cuart: allow getting the icc baud rate and clock freqEric Wild2-0/+12
2019-11-28change uart ctl define namesEric Wild3-6/+6
2019-11-28the magic sauce that makes it workEric Wild1-0/+4
2019-11-28boost uart priorityEric Wild1-0/+6
2019-11-28pps warningEric Wild1-0/+7
2019-11-28add a note for D=64 pecularitiesEric Wild1-0/+8
2019-11-28fsm completion event handling from main loopEric Wild4-21/+68
2019-11-28fix power descriptor valueEric Wild1-1/+2
2019-11-28better ccid error handling, fix buffer leaksEric Wild3-8/+30
2019-11-28add some volatility to debug missing state changesEric Wild1-1/+1
2019-11-28switching rx/tx is too slow, and not necessaryEric Wild1-4/+1
2019-11-28add a "no rx or tx" stateEric Wild3-1/+4
2019-11-28debug code to measure uart timing using the CAN headerEric Wild3-1/+37
2019-11-28debug code to use the DWT unitEric Wild1-0/+23
2019-11-28increase the debug uart buffer sizeEric Wild1-1/+1
2019-11-28attempt at handling card insertion/removalEric Wild6-31/+89
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-26 05:09:39 +0000