diff options
| author | Harald Welte <laforge@gnumonks.org> | 2019-05-17 16:10:00 +0200 |
|---|---|---|
| committer | Harald Welte <laforge@gnumonks.org> | 2019-05-17 16:10:00 +0200 |
| commit | 9bb8bfedb3676228b7c3385844eb23b4f0582a46 (patch) | |
| tree | e8b049cd21640aa46d797295da63dcb6263aa9ad | |
| parent | fa9ea7703d496d50662793b7c6140a0bb7ef4371 (diff) | |
Update from Atmel START 1.0.87 to 1.1.134
Change-Id: I095f2f3f4de8ebba154b7d8f9f763a2fa6472ebd
26 files changed, 603 insertions, 1402 deletions
diff --git a/sysmoOCTSIM/AtmelStart.env_conf b/sysmoOCTSIM/AtmelStart.env_conf index cad5b65..236b063 100644 --- a/sysmoOCTSIM/AtmelStart.env_conf +++ b/sysmoOCTSIM/AtmelStart.env_conf @@ -1,6 +1,6 @@ <environment> <configurations/> <device-packs> - <device-pack device="ATSAME54N19A" name="SAME54_DFP" vendor="Atmel" version="1.0.87"/> + <device-pack device="ATSAME54N19A" name="SAME54_DFP" vendor="Atmel" version="1.1.134"/> </device-packs> </environment> diff --git a/sysmoOCTSIM/AtmelStart.gpdsc b/sysmoOCTSIM/AtmelStart.gpdsc index 75029a0..4a0d932 100644 --- a/sysmoOCTSIM/AtmelStart.gpdsc +++ b/sysmoOCTSIM/AtmelStart.gpdsc @@ -24,7 +24,7 @@ <condition id="CMSIS Device Startup"> <description>Dependency on CMSIS core and Device Startup components</description> <require Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"/> - <require Cclass="Device" Cgroup="Startup" Cversion="1.0.0"/> + <require Cclass="Device" Cgroup="Startup" Cversion="1.1.0"/> </condition> <condition id="ARMCC, GCC, IAR"> <require Dname="ATSAME54N19A"/> diff --git a/sysmoOCTSIM/atmel_start_config.atstart b/sysmoOCTSIM/atmel_start_config.atstart index 3854fb5..2847c1b 100644 --- a/sysmoOCTSIM/atmel_start_config.atstart +++ b/sysmoOCTSIM/atmel_start_config.atstart @@ -4,10 +4,10 @@ versions: api: '1.0' backend: 1.5.122 commit: 820baecf7dd115d94b0d42ee3b0b9d6ba2da7113 - content: 1.0.1465 + content: 1.0.1507 content_pack_name: acme-packs-all format: '2' - frontend: 1.5.1826 + frontend: 1.5.1877 board: identifier: CustomBoard device: SAME54N19A-AF diff --git a/sysmoOCTSIM/gcc/Makefile b/sysmoOCTSIM/gcc/Makefile index d1b8d89..b143057 100644 --- a/sysmoOCTSIM/gcc/Makefile +++ b/sysmoOCTSIM/gcc/Makefile @@ -105,9 +105,9 @@ INC_DIRS = \ # List the object files OBJS += \ + atmel_start.o \ ccid/ccid_proto.o \ ccid/ccid_device.o \ - atmel_start.o \ command.o \ dma_m2m/dma_memory.o \ driver_init.o \ diff --git a/sysmoOCTSIM/hpl/core/hpl_core_m4.c b/sysmoOCTSIM/hpl/core/hpl_core_m4.c index acb75bc..4680ec3 100644 --- a/sysmoOCTSIM/hpl/core/hpl_core_m4.c +++ b/sysmoOCTSIM/hpl/core/hpl_core_m4.c @@ -216,8 +216,14 @@ void _delay_cycles(void *const hw, uint32_t cycles) #ifndef _UNIT_TEST_ (void)hw; (void)cycles; -#if defined __GNUC__ +#if defined(__GNUC__) && (__ARMCOMPILER_VERSION > 6000000) /* Keil MDK with ARM Compiler 6 */ + __asm(".align 3 \n" + "__delay:\n" + "subs r1, r1, #1\n" + "bhi __delay\n"); +#elif defined __GNUC__ __asm(".syntax unified\n" + ".align 3 \n" "__delay:\n" "subs r1, r1, #1\n" "bhi __delay\n" diff --git a/sysmoOCTSIM/hri/hri_dsu_e54.h b/sysmoOCTSIM/hri/hri_dsu_e54.h index 82e24b6..b192276 100644 --- a/sysmoOCTSIM/hri/hri_dsu_e54.h +++ b/sysmoOCTSIM/hri/hri_dsu_e54.h @@ -3,7 +3,7 @@ * * \brief SAM DSU * - * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. * * \asf_license_start * @@ -58,7 +58,6 @@ typedef uint32_t hri_dsu_cid2_reg_t; typedef uint32_t hri_dsu_cid3_reg_t; typedef uint32_t hri_dsu_data_reg_t; typedef uint32_t hri_dsu_dcc_reg_t; -typedef uint32_t hri_dsu_dcfg_reg_t; typedef uint32_t hri_dsu_did_reg_t; typedef uint32_t hri_dsu_end_reg_t; typedef uint32_t hri_dsu_entry0_reg_t; @@ -107,16 +106,6 @@ static inline bool hri_dsu_get_STATUSB_CELCK_bit(const void *const hw) return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_CELCK) >> DSU_STATUSB_CELCK_Pos; } -static inline bool hri_dsu_get_STATUSB_TDCCD0_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_TDCCD0) >> DSU_STATUSB_TDCCD0_Pos; -} - -static inline bool hri_dsu_get_STATUSB_TDCCD1_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_TDCCD1) >> DSU_STATUSB_TDCCD1_Pos; -} - static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask) { uint8_t tmp; @@ -1172,95 +1161,6 @@ static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_reg(const void *const hw) return ((Dsu *)hw)->CFG.reg; } -static inline void hri_dsu_set_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg |= DSU_DCFG_DCFG(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCFG[index].reg; - tmp = (tmp & DSU_DCFG_DCFG(mask)) >> DSU_DCFG_DCFG_Pos; - return tmp; -} - -static inline void hri_dsu_write_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->DCFG[index].reg; - tmp &= ~DSU_DCFG_DCFG_Msk; - tmp |= DSU_DCFG_DCFG(data); - ((Dsu *)hw)->DCFG[index].reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg &= ~DSU_DCFG_DCFG(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg ^= DSU_DCFG_DCFG(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_DCFG_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCFG[index].reg; - tmp = (tmp & DSU_DCFG_DCFG_Msk) >> DSU_DCFG_DCFG_Pos; - return tmp; -} - -static inline void hri_dsu_set_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCFG[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_reg(const void *const hw, uint8_t index) -{ - return ((Dsu *)hw)->DCFG[index].reg; -} - static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw) { return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos; diff --git a/sysmoOCTSIM/hri/hri_supc_e54.h b/sysmoOCTSIM/hri/hri_supc_e54.h index 3f38d15..501c36f 100644 --- a/sysmoOCTSIM/hri/hri_supc_e54.h +++ b/sysmoOCTSIM/hri/hri_supc_e54.h @@ -3,7 +3,7 @@ * * \brief SAM SUPC * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. * * \asf_license_start * @@ -53,7 +53,6 @@ extern "C" { typedef uint32_t hri_supc_bbps_reg_t; typedef uint32_t hri_supc_bkin_reg_t; typedef uint32_t hri_supc_bkout_reg_t; -typedef uint32_t hri_supc_bod12_reg_t; typedef uint32_t hri_supc_bod33_reg_t; typedef uint32_t hri_supc_intenset_reg_t; typedef uint32_t hri_supc_intflag_reg_t; @@ -91,36 +90,6 @@ static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw) ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; } -static inline bool hri_supc_get_INTFLAG_BOD12RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_BOD12RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY; -} - -static inline bool hri_supc_get_INTFLAG_BOD12DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos; -} - -static inline void hri_supc_clear_INTFLAG_BOD12DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET; -} - -static inline bool hri_supc_get_INTFLAG_B12SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_B12SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY; -} - static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw) { return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; @@ -171,36 +140,6 @@ static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw) ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; } -static inline bool hri_supc_get_interrupt_BOD12RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos; -} - -static inline void hri_supc_clear_interrupt_BOD12RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY; -} - -static inline bool hri_supc_get_interrupt_BOD12DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos; -} - -static inline void hri_supc_clear_interrupt_BOD12DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET; -} - -static inline bool hri_supc_get_interrupt_B12SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos; -} - -static inline void hri_supc_clear_interrupt_B12SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY; -} - static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw) { return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; @@ -311,78 +250,6 @@ static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw) ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; } -static inline void hri_supc_set_INTEN_BOD12RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY; -} - -static inline bool hri_supc_get_INTEN_BOD12RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12RDY) >> SUPC_INTENSET_BOD12RDY_Pos; -} - -static inline void hri_supc_write_INTEN_BOD12RDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY; - } -} - -static inline void hri_supc_clear_INTEN_BOD12RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY; -} - -static inline void hri_supc_set_INTEN_BOD12DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET; -} - -static inline bool hri_supc_get_INTEN_BOD12DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12DET) >> SUPC_INTENSET_BOD12DET_Pos; -} - -static inline void hri_supc_write_INTEN_BOD12DET_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET; - } -} - -static inline void hri_supc_clear_INTEN_BOD12DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET; -} - -static inline void hri_supc_set_INTEN_B12SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY; -} - -static inline bool hri_supc_get_INTEN_B12SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B12SRDY) >> SUPC_INTENSET_B12SRDY_Pos; -} - -static inline void hri_supc_write_INTEN_B12SRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY; - } -} - -static inline void hri_supc_clear_INTEN_B12SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY; -} - static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw) { ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; @@ -475,21 +342,6 @@ static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw) return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos; } -static inline bool hri_supc_get_STATUS_BOD12RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12RDY) >> SUPC_STATUS_BOD12RDY_Pos; -} - -static inline bool hri_supc_get_STATUS_BOD12DET_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12DET) >> SUPC_STATUS_BOD12DET_Pos; -} - -static inline bool hri_supc_get_STATUS_B12SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B12SRDY) >> SUPC_STATUS_B12SRDY_Pos; -} - static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw) { return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos; @@ -1017,391 +869,6 @@ static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw) return ((Supc *)hw)->BOD33.reg; } -static inline void hri_supc_set_BOD12_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD12_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_ENABLE) >> SUPC_BOD12_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD12_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_ENABLE; - tmp |= value << SUPC_BOD12_ENABLE_Pos; - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD12_HYST_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_HYST; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD12_HYST_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_HYST) >> SUPC_BOD12_HYST_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD12_HYST_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_HYST; - tmp |= value << SUPC_BOD12_HYST_Pos; - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_HYST_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_HYST; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_HYST_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_HYST; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD12_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD12_STDBYCFG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_STDBYCFG) >> SUPC_BOD12_STDBYCFG_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD12_STDBYCFG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_STDBYCFG; - tmp |= value << SUPC_BOD12_STDBYCFG_Pos; - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD12_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD12_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_RUNSTDBY) >> SUPC_BOD12_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD12_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_RUNSTDBY; - tmp |= value << SUPC_BOD12_RUNSTDBY_Pos; - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD12_ACTCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD12_ACTCFG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_ACTCFG) >> SUPC_BOD12_ACTCFG_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD12_ACTCFG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_ACTCFG; - tmp |= value << SUPC_BOD12_ACTCFG_Pos; - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_ACTCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_ACTCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_ACTION(mask)) >> SUPC_BOD12_ACTION_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_ACTION_Msk; - tmp |= SUPC_BOD12_ACTION(data); - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_ACTION_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_ACTION_Msk) >> SUPC_BOD12_ACTION_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_PSEL(mask)) >> SUPC_BOD12_PSEL_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_PSEL_Msk; - tmp |= SUPC_BOD12_PSEL(data); - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_PSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_PSEL_Msk) >> SUPC_BOD12_PSEL_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_LEVEL(mask)) >> SUPC_BOD12_LEVEL_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_LEVEL_Msk; - tmp |= SUPC_BOD12_LEVEL(data); - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_LEVEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_LEVEL_Msk) >> SUPC_BOD12_LEVEL_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_reg(const void *const hw) -{ - return ((Supc *)hw)->BOD12.reg; -} - static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw) { SUPC_CRITICAL_SECTION_ENTER(); diff --git a/sysmoOCTSIM/include/component-version.h b/sysmoOCTSIM/include/component-version.h index 0e44af5..154ac4d 100644 --- a/sysmoOCTSIM/include/component-version.h +++ b/sysmoOCTSIM/include/component-version.h @@ -3,7 +3,7 @@ * * \brief Component version header file * - * Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * Copyright (c) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
* * \license_start * @@ -29,7 +29,7 @@ #define _COMPONENT_VERSION_H_INCLUDED #define COMPONENT_VERSION_MAJOR 1 -#define COMPONENT_VERSION_MINOR 0 +#define COMPONENT_VERSION_MINOR 1
// // The COMPONENT_VERSION define is composed of the major and the minor version number. @@ -37,18 +37,18 @@ // The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. // The rest of the COMPONENT_VERSION is the major version. // -#define COMPONENT_VERSION 10000 +#define COMPONENT_VERSION 10001
// // The build number does not refer to the component, but to the build number // of the device pack that provides the component. // -#define BUILD_NUMBER 87 +#define BUILD_NUMBER 134
// // The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. // -#define COMPONENT_VERSION_STRING "1.0" +#define COMPONENT_VERSION_STRING "1.1"
// // The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. @@ -58,7 +58,7 @@ // "%Y-%m-%d %H:%M:%S" // // -#define COMPONENT_DATE_STRING "2018-09-21 03:52:00" +#define COMPONENT_DATE_STRING "2019-04-09 08:16:19"
#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ diff --git a/sysmoOCTSIM/include/component/dsu.h b/sysmoOCTSIM/include/component/dsu.h index feedfa9..043f4d8 100644 --- a/sysmoOCTSIM/include/component/dsu.h +++ b/sysmoOCTSIM/include/component/dsu.h @@ -3,7 +3,7 @@ * * \brief Component description for DSU * - * Copyright (c) 2018 Microchip Technology Inc. + * Copyright (c) 2019 Microchip Technology Inc.
* * \asf_license_start * @@ -113,14 +113,12 @@ typedef union { uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */ uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */ uint8_t CELCK:1; /*!< bit: 5 Chip Erase Locked */ - uint8_t TDCCD0:1; /*!< bit: 6 Test Debug Communication Channel 0 Dirty */ - uint8_t TDCCD1:1; /*!< bit: 7 Test Debug Communication Channel 1 Dirty */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */ struct { uint8_t :2; /*!< bit: 0.. 1 Reserved */ uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */ - uint8_t :2; /*!< bit: 4.. 5 Reserved */ - uint8_t TDCCD:2; /*!< bit: 6.. 7 Test Debug Communication Channel x Dirty */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */
} vec; /*!< Structure used for vec access */ uint8_t reg; /*!< Type used for register access */ } DSU_STATUSB_Type; @@ -144,14 +142,7 @@ typedef union { #define DSU_STATUSB_HPE (_U_(0x1) << DSU_STATUSB_HPE_Pos) #define DSU_STATUSB_CELCK_Pos 5 /**< \brief (DSU_STATUSB) Chip Erase Locked */ #define DSU_STATUSB_CELCK (_U_(0x1) << DSU_STATUSB_CELCK_Pos) -#define DSU_STATUSB_TDCCD0_Pos 6 /**< \brief (DSU_STATUSB) Test Debug Communication Channel 0 Dirty */ -#define DSU_STATUSB_TDCCD0 (_U_(1) << DSU_STATUSB_TDCCD0_Pos) -#define DSU_STATUSB_TDCCD1_Pos 7 /**< \brief (DSU_STATUSB) Test Debug Communication Channel 1 Dirty */ -#define DSU_STATUSB_TDCCD1 (_U_(1) << DSU_STATUSB_TDCCD1_Pos) -#define DSU_STATUSB_TDCCD_Pos 6 /**< \brief (DSU_STATUSB) Test Debug Communication Channel x Dirty */ -#define DSU_STATUSB_TDCCD_Msk (_U_(0x3) << DSU_STATUSB_TDCCD_Pos) -#define DSU_STATUSB_TDCCD(value) (DSU_STATUSB_TDCCD_Msk & ((value) << DSU_STATUSB_TDCCD_Pos)) -#define DSU_STATUSB_MASK _U_(0xFF) /**< \brief (DSU_STATUSB) MASK Register */ +#define DSU_STATUSB_MASK _U_(0x3F) /**< \brief (DSU_STATUSB) MASK Register */
/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -318,24 +309,6 @@ typedef union { #define DSU_CFG_ETBRAMEN (_U_(0x1) << DSU_CFG_ETBRAMEN_Pos) #define DSU_CFG_MASK _U_(0x0000001F) /**< \brief (DSU_CFG) MASK Register */ -/* -------- DSU_DCFG : (DSU Offset: 0x00F0) (R/W 32) Device Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DCFG:32; /*!< bit: 0..31 Device Configuration */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DSU_DCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DSU_DCFG_OFFSET 0x00F0 /**< \brief (DSU_DCFG offset) Device Configuration */ -#define DSU_DCFG_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DCFG reset_value) Device Configuration */ - -#define DSU_DCFG_DCFG_Pos 0 /**< \brief (DSU_DCFG) Device Configuration */ -#define DSU_DCFG_DCFG_Msk (_U_(0xFFFFFFFF) << DSU_DCFG_DCFG_Pos) -#define DSU_DCFG_DCFG(value) (DSU_DCFG_DCFG_Msk & ((value) << DSU_DCFG_DCFG_Pos)) -#define DSU_DCFG_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DCFG) MASK Register */ - /* -------- DSU_ENTRY0 : (DSU Offset: 0x1000) (R/ 32) CoreSight ROM Table Entry 0 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { @@ -648,13 +621,11 @@ typedef struct { __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */ __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */ __IO DSU_CFG_Type CFG; /**< \brief Offset: 0x001C (R/W 32) Configuration */ - RoReg8 Reserved2[0xD0]; - __IO DSU_DCFG_Type DCFG[2]; /**< \brief Offset: 0x00F0 (R/W 32) Device Configuration */ - RoReg8 Reserved3[0xF08]; + RoReg8 Reserved2[0xFE0];
__I DSU_ENTRY0_Type ENTRY0; /**< \brief Offset: 0x1000 (R/ 32) CoreSight ROM Table Entry 0 */ __I DSU_ENTRY1_Type ENTRY1; /**< \brief Offset: 0x1004 (R/ 32) CoreSight ROM Table Entry 1 */ __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) CoreSight ROM Table End */ - RoReg8 Reserved4[0xFC0]; + RoReg8 Reserved3[0xFC0];
__I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) CoreSight ROM Table Memory Type */ __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */ __I DSU_PID5_Type PID5; /**< \brief Offset: 0x1FD4 (R/ 32) Peripheral Identification 5 */ diff --git a/sysmoOCTSIM/include/component/nvmctrl.h b/sysmoOCTSIM/include/component/nvmctrl.h index e16038b..771f050 100644 --- a/sysmoOCTSIM/include/component/nvmctrl.h +++ b/sysmoOCTSIM/include/component/nvmctrl.h @@ -3,7 +3,7 @@ * * \brief Component description for NVMCTRL * - * Copyright (c) 2018 Microchip Technology Inc. + * Copyright (c) 2019 Microchip Technology Inc.
* * \asf_license_start * @@ -647,24 +647,6 @@ typedef struct { #define ADC1_FUSES_BIASREFBUF_Msk (_U_(0x7) << ADC1_FUSES_BIASREFBUF_Pos) #define ADC1_FUSES_BIASREFBUF(value) (ADC1_FUSES_BIASREFBUF_Msk & ((value) << ADC1_FUSES_BIASREFBUF_Pos)) -#define FUSES_BOD12USERLEVEL_ADDR NVMCTRL_USER -#define FUSES_BOD12USERLEVEL_Pos 17 /**< \brief (NVMCTRL_USER) BOD12 User Level */ -#define FUSES_BOD12USERLEVEL_Msk (_U_(0x3F) << FUSES_BOD12USERLEVEL_Pos) -#define FUSES_BOD12USERLEVEL(value) (FUSES_BOD12USERLEVEL_Msk & ((value) << FUSES_BOD12USERLEVEL_Pos)) - -#define FUSES_BOD12_ACTION_ADDR NVMCTRL_USER -#define FUSES_BOD12_ACTION_Pos 23 /**< \brief (NVMCTRL_USER) BOD12 Action */ -#define FUSES_BOD12_ACTION_Msk (_U_(0x3) << FUSES_BOD12_ACTION_Pos) -#define FUSES_BOD12_ACTION(value) (FUSES_BOD12_ACTION_Msk & ((value) << FUSES_BOD12_ACTION_Pos)) - -#define FUSES_BOD12_DIS_ADDR NVMCTRL_USER -#define FUSES_BOD12_DIS_Pos 16 /**< \brief (NVMCTRL_USER) BOD12 Disable */ -#define FUSES_BOD12_DIS_Msk (_U_(0x1) << FUSES_BOD12_DIS_Pos) - -#define FUSES_BOD12_HYST_ADDR NVMCTRL_USER -#define FUSES_BOD12_HYST_Pos 25 /**< \brief (NVMCTRL_USER) BOD12 Hysteresis */ -#define FUSES_BOD12_HYST_Msk (_U_(0x1) << FUSES_BOD12_HYST_Pos) - #define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER #define FUSES_BOD33USERLEVEL_Pos 1 /**< \brief (NVMCTRL_USER) BOD33 User Level */ #define FUSES_BOD33USERLEVEL_Msk (_U_(0xFF) << FUSES_BOD33USERLEVEL_Pos) diff --git a/sysmoOCTSIM/include/component/supc.h b/sysmoOCTSIM/include/component/supc.h index be1f48b..8967092 100644 --- a/sysmoOCTSIM/include/component/supc.h +++ b/sysmoOCTSIM/include/component/supc.h @@ -3,7 +3,7 @@ * * \brief Component description for SUPC * - * Copyright (c) 2018 Microchip Technology Inc. + * Copyright (c) 2019 Microchip Technology Inc.
* * \asf_license_start * @@ -46,10 +46,7 @@ typedef union { uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ - uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ - uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ - uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t :5; /*!< bit: 3.. 7 Reserved */
uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ uint32_t :1; /*!< bit: 9 Reserved */ uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ @@ -68,17 +65,11 @@ typedef union { #define SUPC_INTENCLR_BOD33DET (_U_(0x1) << SUPC_INTENCLR_BOD33DET_Pos) #define SUPC_INTENCLR_B33SRDY_Pos 2 /**< \brief (SUPC_INTENCLR) BOD33 Synchronization Ready */ #define SUPC_INTENCLR_B33SRDY (_U_(0x1) << SUPC_INTENCLR_B33SRDY_Pos) -#define SUPC_INTENCLR_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENCLR) BOD12 Ready */ -#define SUPC_INTENCLR_BOD12RDY (_U_(0x1) << SUPC_INTENCLR_BOD12RDY_Pos) -#define SUPC_INTENCLR_BOD12DET_Pos 4 /**< \brief (SUPC_INTENCLR) BOD12 Detection */ -#define SUPC_INTENCLR_BOD12DET (_U_(0x1) << SUPC_INTENCLR_BOD12DET_Pos) -#define SUPC_INTENCLR_B12SRDY_Pos 5 /**< \brief (SUPC_INTENCLR) BOD12 Synchronization Ready */ -#define SUPC_INTENCLR_B12SRDY (_U_(0x1) << SUPC_INTENCLR_B12SRDY_Pos) #define SUPC_INTENCLR_VREGRDY_Pos 8 /**< \brief (SUPC_INTENCLR) Voltage Regulator Ready */ #define SUPC_INTENCLR_VREGRDY (_U_(0x1) << SUPC_INTENCLR_VREGRDY_Pos) #define SUPC_INTENCLR_VCORERDY_Pos 10 /**< \brief (SUPC_INTENCLR) VDDCORE Ready */ #define SUPC_INTENCLR_VCORERDY (_U_(0x1) << SUPC_INTENCLR_VCORERDY_Pos) -#define SUPC_INTENCLR_MASK _U_(0x0000053F) /**< \brief (SUPC_INTENCLR) MASK Register */ +#define SUPC_INTENCLR_MASK _U_(0x00000507) /**< \brief (SUPC_INTENCLR) MASK Register */
/* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -87,10 +78,7 @@ typedef union { uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ - uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ - uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ - uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t :5; /*!< bit: 3.. 7 Reserved */
uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ uint32_t :1; /*!< bit: 9 Reserved */ uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ @@ -109,17 +97,11 @@ typedef union { #define SUPC_INTENSET_BOD33DET (_U_(0x1) << SUPC_INTENSET_BOD33DET_Pos) #define SUPC_INTENSET_B33SRDY_Pos 2 /**< \brief (SUPC_INTENSET) BOD33 Synchronization Ready */ #define SUPC_INTENSET_B33SRDY (_U_(0x1) << SUPC_INTENSET_B33SRDY_Pos) -#define SUPC_INTENSET_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENSET) BOD12 Ready */ -#define SUPC_INTENSET_BOD12RDY (_U_(0x1) << SUPC_INTENSET_BOD12RDY_Pos) -#define SUPC_INTENSET_BOD12DET_Pos 4 /**< \brief (SUPC_INTENSET) BOD12 Detection */ -#define SUPC_INTENSET_BOD12DET (_U_(0x1) << SUPC_INTENSET_BOD12DET_Pos) -#define SUPC_INTENSET_B12SRDY_Pos 5 /**< \brief (SUPC_INTENSET) BOD12 Synchronization Ready */ -#define SUPC_INTENSET_B12SRDY (_U_(0x1) << SUPC_INTENSET_B12SRDY_Pos) #define SUPC_INTENSET_VREGRDY_Pos 8 /**< \brief (SUPC_INTENSET) Voltage Regulator Ready */ #define SUPC_INTENSET_VREGRDY (_U_(0x1) << SUPC_INTENSET_VREGRDY_Pos) #define SUPC_INTENSET_VCORERDY_Pos 10 /**< \brief (SUPC_INTENSET) VDDCORE Ready */ #define SUPC_INTENSET_VCORERDY (_U_(0x1) << SUPC_INTENSET_VCORERDY_Pos) -#define SUPC_INTENSET_MASK _U_(0x0000053F) /**< \brief (SUPC_INTENSET) MASK Register */ +#define SUPC_INTENSET_MASK _U_(0x00000507) /**< \brief (SUPC_INTENSET) MASK Register */
/* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -128,10 +110,7 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register __I uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ __I uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ __I uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ - __I uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ - __I uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ - __I uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ - __I uint32_t :2; /*!< bit: 6.. 7 Reserved */ + __I uint32_t :5; /*!< bit: 3.. 7 Reserved */
__I uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ __I uint32_t :1; /*!< bit: 9 Reserved */ __I uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ @@ -150,17 +129,11 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register #define SUPC_INTFLAG_BOD33DET (_U_(0x1) << SUPC_INTFLAG_BOD33DET_Pos) #define SUPC_INTFLAG_B33SRDY_Pos 2 /**< \brief (SUPC_INTFLAG) BOD33 Synchronization Ready */ #define SUPC_INTFLAG_B33SRDY (_U_(0x1) << SUPC_INTFLAG_B33SRDY_Pos) -#define SUPC_INTFLAG_BOD12RDY_Pos 3 /**< \brief (SUPC_INTFLAG) BOD12 Ready */ -#define SUPC_INTFLAG_BOD12RDY (_U_(0x1) << SUPC_INTFLAG_BOD12RDY_Pos) -#define SUPC_INTFLAG_BOD12DET_Pos 4 /**< \brief (SUPC_INTFLAG) BOD12 Detection */ -#define SUPC_INTFLAG_BOD12DET (_U_(0x1) << SUPC_INTFLAG_BOD12DET_Pos) -#define SUPC_INTFLAG_B12SRDY_Pos 5 /**< \brief (SUPC_INTFLAG) BOD12 Synchronization Ready */ -#define SUPC_INTFLAG_B12SRDY (_U_(0x1) << SUPC_INTFLAG_B12SRDY_Pos) #define SUPC_INTFLAG_VREGRDY_Pos 8 /**< \brief (SUPC_INTFLAG) Voltage Regulator Ready */ #define SUPC_INTFLAG_VREGRDY (_U_(0x1) << SUPC_INTFLAG_VREGRDY_Pos) #define SUPC_INTFLAG_VCORERDY_Pos 10 /**< \brief (SUPC_INTFLAG) VDDCORE Ready */ #define SUPC_INTFLAG_VCORERDY (_U_(0x1) << SUPC_INTFLAG_VCORERDY_Pos) -#define SUPC_INTFLAG_MASK _U_(0x0000053F) /**< \brief (SUPC_INTFLAG) MASK Register */ +#define SUPC_INTFLAG_MASK _U_(0x00000507) /**< \brief (SUPC_INTFLAG) MASK Register */
/* -------- SUPC_STATUS : (SUPC Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -169,10 +142,7 @@ typedef union { uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ - uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ - uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ - uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t :5; /*!< bit: 3.. 7 Reserved */
uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ uint32_t :1; /*!< bit: 9 Reserved */ uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ @@ -191,17 +161,11 @@ typedef union { #define SUPC_STATUS_BOD33DET (_U_(0x1) << SUPC_STATUS_BOD33DET_Pos) #define SUPC_STATUS_B33SRDY_Pos 2 /**< \brief (SUPC_STATUS) BOD33 Synchronization Ready */ #define SUPC_STATUS_B33SRDY (_U_(0x1) << SUPC_STATUS_B33SRDY_Pos) -#define SUPC_STATUS_BOD12RDY_Pos 3 /**< \brief (SUPC_STATUS) BOD12 Ready */ -#define SUPC_STATUS_BOD12RDY (_U_(0x1) << SUPC_STATUS_BOD12RDY_Pos) -#define SUPC_STATUS_BOD12DET_Pos 4 /**< \brief (SUPC_STATUS) BOD12 Detection */ -#define SUPC_STATUS_BOD12DET (_U_(0x1) << SUPC_STATUS_BOD12DET_Pos) -#define SUPC_STATUS_B12SRDY_Pos 5 /**< \brief (SUPC_STATUS) BOD12 Synchronization Ready */ -#define SUPC_STATUS_B12SRDY (_U_(0x1) << SUPC_STATUS_B12SRDY_Pos) #define SUPC_STATUS_VREGRDY_Pos 8 /**< \brief (SUPC_STATUS) Voltage Regulator Ready */ #define SUPC_STATUS_VREGRDY (_U_(0x1) << SUPC_STATUS_VREGRDY_Pos) #define SUPC_STATUS_VCORERDY_Pos 10 /**< \brief (SUPC_STATUS) VDDCORE Ready */ #define SUPC_STATUS_VCORERDY (_U_(0x1) << SUPC_STATUS_VCORERDY_Pos) -#define SUPC_STATUS_MASK _U_(0x0000053F) /**< \brief (SUPC_STATUS) MASK Register */ +#define SUPC_STATUS_MASK _U_(0x00000507) /**< \brief (SUPC_STATUS) MASK Register */
/* -------- SUPC_BOD33 : (SUPC Offset: 0x10) (R/W 32) BOD33 Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -278,89 +242,6 @@ typedef union { #define SUPC_BOD33_VBATLEVEL(value) (SUPC_BOD33_VBATLEVEL_Msk & ((value) << SUPC_BOD33_VBATLEVEL_Pos)) #define SUPC_BOD33_MASK _U_(0xFFFF7FFE) /**< \brief (SUPC_BOD33) MASK Register */ -/* -------- SUPC_BOD12 : (SUPC Offset: 0x14) (R/W 32) BOD12 Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */ - uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */ - uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */ - uint32_t :3; /*!< bit: 9..11 Reserved */ - uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ - uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} SUPC_BOD12_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SUPC_BOD12_OFFSET 0x14 /**< \brief (SUPC_BOD12 offset) BOD12 Control */ -#define SUPC_BOD12_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BOD12 reset_value) BOD12 Control */ - -#define SUPC_BOD12_ENABLE_Pos 1 /**< \brief (SUPC_BOD12) Enable */ -#define SUPC_BOD12_ENABLE (_U_(0x1) << SUPC_BOD12_ENABLE_Pos) -#define SUPC_BOD12_HYST_Pos 2 /**< \brief (SUPC_BOD12) Hysteresis Enable */ -#define SUPC_BOD12_HYST (_U_(0x1) << SUPC_BOD12_HYST_Pos) -#define SUPC_BOD12_ACTION_Pos 3 /**< \brief (SUPC_BOD12) Action when Threshold Crossed */ -#define SUPC_BOD12_ACTION_Msk (_U_(0x3) << SUPC_BOD12_ACTION_Pos) -#define SUPC_BOD12_ACTION(value) (SUPC_BOD12_ACTION_Msk & ((value) << SUPC_BOD12_ACTION_Pos)) -#define SUPC_BOD12_ACTION_NONE_Val _U_(0x0) /**< \brief (SUPC_BOD12) No action */ -#define SUPC_BOD12_ACTION_RESET_Val _U_(0x1) /**< \brief (SUPC_BOD12) The BOD12 generates a reset */ -#define SUPC_BOD12_ACTION_INT_Val _U_(0x2) /**< \brief (SUPC_BOD12) The BOD12 generates an interrupt */ -#define SUPC_BOD12_ACTION_NONE (SUPC_BOD12_ACTION_NONE_Val << SUPC_BOD12_ACTION_Pos) -#define SUPC_BOD12_ACTION_RESET (SUPC_BOD12_ACTION_RESET_Val << SUPC_BOD12_ACTION_Pos) -#define SUPC_BOD12_ACTION_INT (SUPC_BOD12_ACTION_INT_Val << SUPC_BOD12_ACTION_Pos) -#define SUPC_BOD12_STDBYCFG_Pos 5 /**< \brief (SUPC_BOD12) Configuration in Standby mode */ -#define SUPC_BOD12_STDBYCFG (_U_(0x1) << SUPC_BOD12_STDBYCFG_Pos) -#define SUPC_BOD12_RUNSTDBY_Pos 6 /**< \brief (SUPC_BOD12) Run during Standby */ -#define SUPC_BOD12_RUNSTDBY (_U_(0x1) << SUPC_BOD12_RUNSTDBY_Pos) -#define SUPC_BOD12_ACTCFG_Pos 8 /**< \brief (SUPC_BOD12) Configuration in Active mode */ -#define SUPC_BOD12_ACTCFG (_U_(0x1) << SUPC_BOD12_ACTCFG_Pos) -#define SUPC_BOD12_PSEL_Pos 12 /**< \brief (SUPC_BOD12) Prescaler Select */ -#define SUPC_BOD12_PSEL_Msk (_U_(0xF) << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL(value) (SUPC_BOD12_PSEL_Msk & ((value) << SUPC_BOD12_PSEL_Pos)) -#define SUPC_BOD12_PSEL_DIV2_Val _U_(0x0) /**< \brief (SUPC_BOD12) Divide clock by 2 */ -#define SUPC_BOD12_PSEL_DIV4_Val _U_(0x1) /**< \brief (SUPC_BOD12) Divide clock by 4 */ -#define SUPC_BOD12_PSEL_DIV8_Val _U_(0x2) /**< \brief (SUPC_BOD12) Divide clock by 8 */ -#define SUPC_BOD12_PSEL_DIV16_Val _U_(0x3) /**< \brief (SUPC_BOD12) Divide clock by 16 */ -#define SUPC_BOD12_PSEL_DIV32_Val _U_(0x4) /**< \brief (SUPC_BOD12) Divide clock by 32 */ -#define SUPC_BOD12_PSEL_DIV64_Val _U_(0x5) /**< \brief (SUPC_BOD12) Divide clock by 64 */ -#define SUPC_BOD12_PSEL_DIV128_Val _U_(0x6) /**< \brief (SUPC_BOD12) Divide clock by 128 */ -#define SUPC_BOD12_PSEL_DIV256_Val _U_(0x7) /**< \brief (SUPC_BOD12) Divide clock by 256 */ -#define SUPC_BOD12_PSEL_DIV512_Val _U_(0x8) /**< \brief (SUPC_BOD12) Divide clock by 512 */ -#define SUPC_BOD12_PSEL_DIV1024_Val _U_(0x9) /**< \brief (SUPC_BOD12) Divide clock by 1024 */ -#define SUPC_BOD12_PSEL_DIV2048_Val _U_(0xA) /**< \brief (SUPC_BOD12) Divide clock by 2048 */ -#define SUPC_BOD12_PSEL_DIV4096_Val _U_(0xB) /**< \brief (SUPC_BOD12) Divide clock by 4096 */ -#define SUPC_BOD12_PSEL_DIV8192_Val _U_(0xC) /**< \brief (SUPC_BOD12) Divide clock by 8192 */ -#define SUPC_BOD12_PSEL_DIV16384_Val _U_(0xD) /**< \brief (SUPC_BOD12) Divide clock by 16384 */ -#define SUPC_BOD12_PSEL_DIV32768_Val _U_(0xE) /**< \brief (SUPC_BOD12) Divide clock by 32768 */ -#define SUPC_BOD12_PSEL_DIV65536_Val _U_(0xF) /**< \brief (SUPC_BOD12) Divide clock by 65536 */ -#define SUPC_BOD12_PSEL_DIV2 (SUPC_BOD12_PSEL_DIV2_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV4 (SUPC_BOD12_PSEL_DIV4_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV8 (SUPC_BOD12_PSEL_DIV8_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV16 (SUPC_BOD12_PSEL_DIV16_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV32 (SUPC_BOD12_PSEL_DIV32_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV64 (SUPC_BOD12_PSEL_DIV64_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV128 (SUPC_BOD12_PSEL_DIV128_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV256 (SUPC_BOD12_PSEL_DIV256_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV512 (SUPC_BOD12_PSEL_DIV512_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV1024 (SUPC_BOD12_PSEL_DIV1024_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV2048 (SUPC_BOD12_PSEL_DIV2048_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV4096 (SUPC_BOD12_PSEL_DIV4096_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV8192 (SUPC_BOD12_PSEL_DIV8192_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV16384 (SUPC_BOD12_PSEL_DIV16384_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV32768 (SUPC_BOD12_PSEL_DIV32768_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_PSEL_DIV65536 (SUPC_BOD12_PSEL_DIV65536_Val << SUPC_BOD12_PSEL_Pos) -#define SUPC_BOD12_LEVEL_Pos 16 /**< \brief (SUPC_BOD12) Threshold Level */ -#define SUPC_BOD12_LEVEL_Msk (_U_(0x3F) << SUPC_BOD12_LEVEL_Pos) -#define SUPC_BOD12_LEVEL(value) (SUPC_BOD12_LEVEL_Msk & ((value) << SUPC_BOD12_LEVEL_Pos)) -#define SUPC_BOD12_MASK _U_(0x003FF17E) /**< \brief (SUPC_BOD12) MASK Register */ - /* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { @@ -540,7 +421,7 @@ typedef struct { __IO SUPC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ __I SUPC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ __IO SUPC_BOD33_Type BOD33; /**< \brief Offset: 0x10 (R/W 32) BOD33 Control */ - __IO SUPC_BOD12_Type BOD12; /**< \brief Offset: 0x14 (R/W 32) BOD12 Control */ + RoReg8 Reserved1[0x4];
__IO SUPC_VREG_Type VREG; /**< \brief Offset: 0x18 (R/W 32) VREG Control */ __IO SUPC_VREF_Type VREF; /**< \brief Offset: 0x1C (R/W 32) VREF Control */ __IO SUPC_BBPS_Type BBPS; /**< \brief Offset: 0x20 (R/W 32) Battery Backup Power Switch */ diff --git a/sysmoOCTSIM/include/instance/dsu.h b/sysmoOCTSIM/include/instance/dsu.h index 3c7ae23..80c09e6 100644 --- a/sysmoOCTSIM/include/instance/dsu.h +++ b/sysmoOCTSIM/include/instance/dsu.h @@ -3,7 +3,7 @@ * * \brief Instance description for DSU * - * Copyright (c) 2018 Microchip Technology Inc. + * Copyright (c) 2019 Microchip Technology Inc.
* * \asf_license_start * @@ -42,8 +42,6 @@ #define REG_DSU_DCC1 (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */ #define REG_DSU_DID (0x41002018) /**< \brief (DSU) Device Identification */ #define REG_DSU_CFG (0x4100201C) /**< \brief (DSU) Configuration */ -#define REG_DSU_DCFG0 (0x410020F0) /**< \brief (DSU) Device Configuration 0 */ -#define REG_DSU_DCFG1 (0x410020F4) /**< \brief (DSU) Device Configuration 1 */ #define REG_DSU_ENTRY0 (0x41003000) /**< \brief (DSU) CoreSight ROM Table Entry 0 */ #define REG_DSU_ENTRY1 (0x41003004) /**< \brief (DSU) CoreSight ROM Table Entry 1 */ #define REG_DSU_END (0x41003008) /**< \brief (DSU) CoreSight ROM Table End */ @@ -71,8 +69,6 @@ #define REG_DSU_DCC1 (*(RwReg *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */ #define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identification */ #define REG_DSU_CFG (*(RwReg *)0x4100201CUL) /**< \brief (DSU) Configuration */ -#define REG_DSU_DCFG0 (*(RwReg *)0x410020F0UL) /**< \brief (DSU) Device Configuration 0 */ -#define REG_DSU_DCFG1 (*(RwReg *)0x410020F4UL) /**< \brief (DSU) Device Configuration 1 */ #define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL) /**< \brief (DSU) CoreSight ROM Table Entry 0 */ #define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) CoreSight ROM Table Entry 1 */ #define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) CoreSight ROM Table End */ diff --git a/sysmoOCTSIM/include/instance/evsys.h b/sysmoOCTSIM/include/instance/evsys.h index 20d127f..0c25ff2 100644 --- a/sysmoOCTSIM/include/instance/evsys.h +++ b/sysmoOCTSIM/include/instance/evsys.h @@ -3,7 +3,7 @@ * * \brief Instance description for EVSYS * - * Copyright (c) 2018 Microchip Technology Inc. + * Copyright (c) 2019 Microchip Technology Inc.
* * \asf_license_start * @@ -572,65 +572,65 @@ #define EVSYS_ID_GEN_TCC0_OVF 41 #define EVSYS_ID_GEN_TCC0_TRG 42 #define EVSYS_ID_GEN_TCC0_CNT 43 -#define EVSYS_ID_GEN_TCC0_MCX_0 44 -#define EVSYS_ID_GEN_TCC0_MCX_1 45 -#define EVSYS_ID_GEN_TCC0_MCX_2 46 -#define EVSYS_ID_GEN_TCC0_MCX_3 47 -#define EVSYS_ID_GEN_TCC0_MCX_4 48 -#define EVSYS_ID_GEN_TCC0_MCX_5 49 +#define EVSYS_ID_GEN_TCC0_MC_0 44
+#define EVSYS_ID_GEN_TCC0_MC_1 45
+#define EVSYS_ID_GEN_TCC0_MC_2 46
+#define EVSYS_ID_GEN_TCC0_MC_3 47
+#define EVSYS_ID_GEN_TCC0_MC_4 48
+#define EVSYS_ID_GEN_TCC0_MC_5 49
#define EVSYS_ID_GEN_TCC1_OVF 50 #define EVSYS_ID_GEN_TCC1_TRG 51 #define EVSYS_ID_GEN_TCC1_CNT 52 -#define EVSYS_ID_GEN_TCC1_MCX_0 53 -#define EVSYS_ID_GEN_TCC1_MCX_1 54 -#define EVSYS_ID_GEN_TCC1_MCX_2 55 -#define EVSYS_ID_GEN_TCC1_MCX_3 56 +#define EVSYS_ID_GEN_TCC1_MC_0 53
+#define EVSYS_ID_GEN_TCC1_MC_1 54
+#define EVSYS_ID_GEN_TCC1_MC_2 55
+#define EVSYS_ID_GEN_TCC1_MC_3 56
#define EVSYS_ID_GEN_TCC2_OVF 57 #define EVSYS_ID_GEN_TCC2_TRG 58 #define EVSYS_ID_GEN_TCC2_CNT 59 -#define EVSYS_ID_GEN_TCC2_MCX_0 60 -#define EVSYS_ID_GEN_TCC2_MCX_1 61 -#define EVSYS_ID_GEN_TCC2_MCX_2 62 +#define EVSYS_ID_GEN_TCC2_MC_0 60
+#define EVSYS_ID_GEN_TCC2_MC_1 61
+#define EVSYS_ID_GEN_TCC2_MC_2 62
#define EVSYS_ID_GEN_TCC3_OVF 63 #define EVSYS_ID_GEN_TCC3_TRG 64 #define EVSYS_ID_GEN_TCC3_CNT 65 -#define EVSYS_ID_GEN_TCC3_MCX_0 66 -#define EVSYS_ID_GEN_TCC3_MCX_1 67 +#define EVSYS_ID_GEN_TCC3_MC_0 66
+#define EVSYS_ID_GEN_TCC3_MC_1 67
#define EVSYS_ID_GEN_TCC4_OVF 68 #define EVSYS_ID_GEN_TCC4_TRG 69 #define EVSYS_ID_GEN_TCC4_CNT 70 -#define EVSYS_ID_GEN_TCC4_MCX_0 71 -#define EVSYS_ID_GEN_TCC4_MCX_1 72 +#define EVSYS_ID_GEN_TCC4_MC_0 71
+#define EVSYS_ID_GEN_TCC4_MC_1 72
#define EVSYS_ID_GEN_TC0_OVF 73 -#define EVSYS_ID_GEN_TC0_MCX_0 74 -#define EVSYS_ID_GEN_TC0_MCX_1 75 +#define EVSYS_ID_GEN_TC0_MC_0 74
+#define EVSYS_ID_GEN_TC0_MC_1 75
#define EVSYS_ID_GEN_TC1_OVF 76 -#define EVSYS_ID_GEN_TC1_MCX_0 77 -#define EVSYS_ID_GEN_TC1_MCX_1 78 +#define EVSYS_ID_GEN_TC1_MC_0 77
+#define EVSYS_ID_GEN_TC1_MC_1 78
#define EVSYS_ID_GEN_TC2_OVF 79 -#define EVSYS_ID_GEN_TC2_MCX_0 80 -#define EVSYS_ID_GEN_TC2_MCX_1 81 +#define EVSYS_ID_GEN_TC2_MC_0 80
+#define EVSYS_ID_GEN_TC2_MC_1 81
#define EVSYS_ID_GEN_TC3_OVF 82 -#define EVSYS_ID_GEN_TC3_MCX_0 83 -#define EVSYS_ID_GEN_TC3_MCX_1 84 +#define EVSYS_ID_GEN_TC3_MC_0 83
+#define EVSYS_ID_GEN_TC3_MC_1 84
#define EVSYS_ID_GEN_TC4_OVF 85 -#define EVSYS_ID_GEN_TC4_MCX_0 86 -#define EVSYS_ID_GEN_TC4_MCX_1 87 +#define EVSYS_ID_GEN_TC4_MC_0 86
+#define EVSYS_ID_GEN_TC4_MC_1 87
#define EVSYS_ID_GEN_TC5_OVF 88 -#define EVSYS_ID_GEN_TC5_MCX_0 89 -#define EVSYS_ID_GEN_TC5_MCX_1 90 +#define EVSYS_ID_GEN_TC5_MC_0 89
+#define EVSYS_ID_GEN_TC5_MC_1 90
#define EVSYS_ID_GEN_TC6_OVF 91 -#define EVSYS_ID_GEN_TC6_MCX_0 92 -#define EVSYS_ID_GEN_TC6_MCX_1 93 +#define EVSYS_ID_GEN_TC6_MC_0 92
+#define EVSYS_ID_GEN_TC6_MC_1 93
#define EVSYS_ID_GEN_TC7_OVF 94 -#define EVSYS_ID_GEN_TC7_MCX_0 95 -#define EVSYS_ID_GEN_TC7_MCX_1 96 +#define EVSYS_ID_GEN_TC7_MC_0 95
+#define EVSYS_ID_GEN_TC7_MC_1 96
#define EVSYS_ID_GEN_PDEC_OVF 97 #define EVSYS_ID_GEN_PDEC_ERR 98 #define EVSYS_ID_GEN_PDEC_DIR 99 #define EVSYS_ID_GEN_PDEC_VLC 100 -#define EVSYS_ID_GEN_PDEC_MCX_0 101 -#define EVSYS_ID_GEN_PDEC_MCX_1 102 +#define EVSYS_ID_GEN_PDEC_MC_0 101
+#define EVSYS_ID_GEN_PDEC_MC_1 102
#define EVSYS_ID_GEN_ADC0_RESRDY 103 #define EVSYS_ID_GEN_ADC0_WINMON 104 #define EVSYS_ID_GEN_ADC1_RESRDY 105 diff --git a/sysmoOCTSIM/include/instance/sercom0.h b/sysmoOCTSIM/include/instance/sercom0.h index afe95e6..61dbab5 100644 --- a/sysmoOCTSIM/include/instance/sercom0.h +++ b/sysmoOCTSIM/include/instance/sercom0.h @@ -3,7 +3,7 @@ * * \brief Instance description for SERCOM0 * - * Copyright (c) 2018 Microchip Technology Inc. + * Copyright (c) 2019 Microchip Technology Inc.
* * \asf_license_start * @@ -145,6 +145,18 @@ #define SERCOM0_GCLK_ID_CORE 7 #define SERCOM0_GCLK_ID_SLOW 3 #define SERCOM0_INT_MSB 6 +#define SERCOM0_I2CM 1 // I2C Master mode implemented?
+#define SERCOM0_I2CS 1 // I2C Slave mode implemented?
+#define SERCOM0_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
+#define SERCOM0_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
+#define SERCOM0_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
+#define SERCOM0_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
+#define SERCOM0_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
+#define SERCOM0_I2C_FASTMP 1 // I2C fast mode plus implemented?
+#define SERCOM0_I2C_HSMODE 1 // USART mode implemented?
+#define SERCOM0_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
+#define SERCOM0_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
+#define SERCOM0_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
#define SERCOM0_PMSB 3 #define SERCOM0_RETENTION_SUPPORT 0 // Retention supported? #define SERCOM0_SE_CNT 1 // SE counter included? @@ -154,18 +166,6 @@ #define SERCOM0_SPI_OZMO 0 // OZMO features implemented? #define SERCOM0_SPI_WAKE_ON_SSL 1 // _SS low detect implemented? #define SERCOM0_TTBIT_EXTENSION 1 // 32-bit extension implemented? -#define SERCOM0_TWIM 1 // TWI Master mode implemented? -#define SERCOM0_TWIS 1 // TWI Slave mode implemented? -#define SERCOM0_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented? -#define SERCOM0_TWIS_GROUP_CMD 1 // TWI slave group command implemented? -#define SERCOM0_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size -#define SERCOM0_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size -#define SERCOM0_TWIS_SUDAT 1 // TWI slave SDA setup implemented? -#define SERCOM0_TWI_FASTMP 1 // TWI fast mode plus implemented? -#define SERCOM0_TWI_HSMODE 1 // USART mode implemented? -#define SERCOM0_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented? -#define SERCOM0_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented? -#define SERCOM0_TWI_TENBIT_ADR 1 // TWI ten bit enabled? #define SERCOM0_USART 1 // USART mode implemented? #define SERCOM0_USART_AUTOBAUD 1 // USART autobaud implemented? #define SERCOM0_USART_COLDET 1 // USART collision detection implemented? diff --git a/sysmoOCTSIM/include/instance/sercom1.h b/sysmoOCTSIM/include/instance/sercom1.h index 72c7bda..82a9084 100644 --- a/sysmoOCTSIM/include/instance/sercom1.h +++ b/sysmoOCTSIM/include/instance/sercom1.h @@ -3,7 +3,7 @@ * * \brief Instance description for SERCOM1 * - * Copyright (c) 2018 Microchip Technology Inc. + * Copyright (c) 2019 Microchip Technology Inc.
* * \asf_license_start * @@ -145,6 +145,18 @@ #define SERCOM1_GCLK_ID_CORE 8 #define SERCOM1_GCLK_ID_SLOW 3 #define SERCOM1_INT_MSB 6 +#define SERCOM1_I2CM 1 // I2C Master mode implemented?
+#define SERCOM1_I2CS 1 // I2C Slave mode implemented?
+#define SERCOM1_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
+#define SERCOM1_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
+#define SERCOM1_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
+#define SERCOM1_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
+#define SERCOM1_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
+#define SERCOM1_I2C_FASTMP 1 // I2C fast mode plus implemented?
+#define SERCOM1_I2C_HSMODE 1 // USART mode implemented?
+#define SERCOM1_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
+#define SERCOM1_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
+#define SERCOM1_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
#define SERCOM1_PMSB 3 #define SERCOM1_RETENTION_SUPPORT 0 // Retention supported? #define SERCOM1_SE_CNT 1 // SE counter included? @@ -154,18 +166,6 @@ #define SERCOM1_SPI_OZMO 0 // OZMO features implemented? #define SERCOM1_SPI_WAKE_ON_SSL 1 // _SS low detect implemented? #define SERCOM1_TTBIT_EXTENSION 1 // 32-bit extension implemented? -#define SERCOM1_TWIM 1 // TWI Master mode implemented? -#define SERCOM1_TWIS 1 // TWI Slave mode implemented? -#define SERCOM1_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented? -#define SERCOM1_TWIS_GROUP_CMD 1 // TWI slave group command implemented? -#define SERCOM1_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size -#define SERCOM1_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size -#define SERCOM1_TWIS_SUDAT 1 // TWI slave SDA setup implemented? -#define SERCOM1_TWI_FASTMP 1 // TWI fast mode plus implemented? -#define SERCOM1_TWI_HSMODE 1 // USART mode implemented? -#define SERCOM1_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented? -#define SERCOM1_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented? -#define SERCOM1_TWI_TENBIT_ADR 1 // TWI ten bit enabled? #define SERCOM1_USART 1 // USART mode implemented? #define SERCOM1_USART_AUTOBAUD 1 // USART autobaud implemented? #define SERCOM1_USART_COLDET 1 // USART collision detection implemented? diff --git a/sysmoOCTSIM/include/instance/sercom2.h b/sysmoOCTSIM/include/instance/sercom2.h index 852cd50..bd672b1 100644 --- a/sysmoOCTSIM/include/instance/sercom2.h +++ b/sysmoOCTSIM/include/instance/sercom2.h @@ -3,7 +3,7 @@ * * \brief Instance description for SERCOM2 * - * Copyright (c) 2018 Microchip Technology Inc. + * Copyright (c) 2019 Microchip Technology Inc.
* * \asf_license_start * @@ -145,6 +145,18 @@ #define SERCOM2_GCLK_ID_CORE 23 #define SERCOM2_GCLK_ID_SLOW 3 #define SERCOM2_INT_MSB 6 +#define SERCOM2_I2CM 1 // I2C Master mode implemented?
+#define SERCOM2_I2CS 1 // I2C Slave mode implemented?
+#define SERCOM2_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
+#define SERCOM2_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
+#define SERCOM2_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
+#define SERCOM2_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
+#define SERCOM2_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
+#define SERCOM2_I2C_FASTMP 1 // I2C fast mode plus implemented?
+#define SERCOM2_I2C_HSMODE 1 // USART mode implemented?
+#define SERCOM2_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
+#define SERCOM2_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
+#define SERCOM2_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
#define SERCOM2_PMSB 3 #define SERCOM2_RETENTION_SUPPORT 0 // Retention supported? #define SERCOM2_SE_CNT 1 // SE counter included? @@ -154,18 +166,6 @@ #define SERCOM2_SPI_OZMO 0 // OZMO features implemented? #define SERCOM2_SPI_WAKE_ON_SSL 1 // _SS low detect implemented? #define SERCOM2_TTBIT_EXTENSION 1 // 32-bit extension implemented? -#define SERCOM2_TWIM 1 // TWI Master mode implemented? -#define SERCOM2_TWIS 1 // TWI Slave mode implemented? -#define SERCOM2_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented? -#define SERCOM2_TWIS_GROUP_CMD 1 // TWI slave group command implemented? -#define SERCOM2_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size -#define SERCOM2_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size -#define SERCOM2_TWIS_SUDAT 1 // TWI slave SDA setup implemented? -#define SERCOM2_TWI_FASTMP 1 // TWI fast mode plus implemented? -#define SERCOM2_TWI_HSMODE 1 // USART mode implemented? -#define SERCOM2_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented? -#define SERCOM2_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented? -#define SERCOM2_TWI_TENBIT_ADR 1 // TWI ten bit enabled? #define SERCOM2_USART 1 // USART mode implemented? #define SERCOM2_USART_AUTOBAUD 1 // USART autobaud implemented? #define SERCOM2_USART_COLDET 1 // USART collision detection implemented? diff --git a/sysmoOCTSIM/include/instance/sercom3.h b/sysmoOCTSIM/include/instance/sercom3.h index 39ec12d..46cd992 100644 --- a/sysmoOCTSIM/include/instance/sercom3.h +++ b/sysmoOCTSIM/include/instance/sercom3.h @@ -3,7 +3,7 @@ * * \brief Instance description for SERCOM3 * - * Copyright (c) 2018 Microchip Technology Inc. + * Copyright (c) 2019 Microchip Technology Inc.
* * \asf_license_start * @@ -145,6 +145,18 @@ #define SERCOM3_GCLK_ID_CORE 24 #define SERCOM3_GCLK_ID_SLOW 3 #define SERCOM3_INT_MSB 6 +#define SERCOM3_I2CM 1 // I2C Master mode implemented?
+#define SERCOM3_I2CS 1 // I2C Slave mode implemented?
+#define SERCOM3_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
+#define SERCOM3_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
+#define SERCOM3_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
+#define SERCOM3_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
+#define SERCOM3_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
+#define SERCOM3_I2C_FASTMP 1 // I2C fast mode plus implemented?
+#define SERCOM3_I2C_HSMODE 1 // USART mode implemented?
+#define SERCOM3_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
+#define SERCOM3_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
+#define SERCOM3_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
#define SERCOM3_PMSB 3 #define SERCOM3_RETENTION_SUPPORT 0 // Retention supported? #define SERCOM3_SE_CNT 1 // SE counter included? @@ -154,18 +166,6 @@ #define SERCOM3_SPI_OZMO 0 // OZMO features implemented? #define SERCOM3_SPI_WAKE_ON_SSL 1 // _SS low detect implemented? #define SERCOM3_TTBIT_EXTENSION 1 // 32-bit extension implemented? -#define SERCOM3_TWIM 1 // TWI Master mode implemented? -#define SERCOM3_TWIS 1 // TWI Slave mode implemented? -#define SERCOM3_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented? -#define SERCOM3_TWIS_GROUP_CMD 1 // TWI slave group command implemented? -#define SERCOM3_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size -#define SERCOM3_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size -#define SERCOM3_TWIS_SUDAT 1 // TWI slave SDA setup implemented? -#define SERCOM3_TWI_FASTMP 1 // TWI fast mode plus implemented? -#define SERCOM3_TWI_HSMODE 1 // USART mode implemented? -#define SERCOM3_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented? -#define SERCOM3_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented? -#define SERCOM3_TWI_TENBIT_ADR 1 // TWI ten bit enabled? #define SERCOM3_USART 1 // USART mode implemented? #define SERCOM3_USART_AUTOBAUD 1 // USART autobaud implemented? #define SERCOM3_USART_COLDET 1 // USART collision detection implemented? diff --git a/sysmoOCTSIM/include/instance/sercom4.h b/sysmoOCTSIM/include/instance/sercom4.h index 8806404..b487a21 100644 --- a/sysmoOCTSIM/include/instance/sercom4.h +++ b/sysmoOCTSIM/include/instance/sercom4.h @@ -3,7 +3,7 @@ * * \brief Instance description for SERCOM4 * - * Copyright (c) 2018 Microchip Technology Inc. + * Copyright (c) 2019 Microchip Technology Inc.
* * \asf_license_start * @@ -145,6 +145,18 @@ #define SERCOM4_GCLK_ID_CORE 34 #define SERCOM4_GCLK_ID_SLOW 3 #define SERCOM4_INT_MSB 6 +#define SERCOM4_I2CM 1 // I2C Master mode implemented?
+#define SERCOM4_I2CS 1 // I2C Slave mode implemented?
+#define SERCOM4_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
+#define SERCOM4_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
+#define SERCOM4_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
+#define SERCOM4_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
+#define SERCOM4_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
+#define SERCOM4_I2C_FASTMP 1 // I2C fast mode plus implemented?
+#define SERCOM4_I2C_HSMODE 1 // USART mode implemented?
+#define SERCOM4_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
+#define SERCOM4_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
+#define SERCOM4_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
#define SERCOM4_PMSB 3 #define SERCOM4_RETENTION_SUPPORT 0 // Retention supported? #define SERCOM4_SE_CNT 1 // SE counter included? @@ -154,18 +166,6 @@ #define SERCOM4_SPI_OZMO 0 // OZMO features implemented? #define SERCOM4_SPI_WAKE_ON_SSL 1 // _SS low detect implemented? #define SERCOM4_TTBIT_EXTENSION 1 // 32-bit extension implemented? -#define SERCOM4_TWIM 1 // TWI Master mode implemented? -#define SERCOM4_TWIS 1 // TWI Slave mode implemented? -#define SERCOM4_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented? -#define SERCOM4_TWIS_GROUP_CMD 1 // TWI slave group command implemented? -#define SERCOM4_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size -#define SERCOM4_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size -#define SERCOM4_TWIS_SUDAT 1 // TWI slave SDA setup implemented? -#define SERCOM4_TWI_FASTMP 1 // TWI fast mode plus implemented? -#define SERCOM4_TWI_HSMODE 1 // USART mode implemented? -#define SERCOM4_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented? -#define SERCOM4_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented? -#define SERCOM4_TWI_TENBIT_ADR 1 // TWI ten bit enabled? #define SERCOM4_USART 1 // USART mode implemented? #define SERCOM4_USART_AUTOBAUD 1 // USART autobaud implemented? #define SERCOM4_USART_COLDET 1 // USART collision detection implemented? diff --git a/sysmoOCTSIM/include/instance/sercom5.h b/sysmoOCTSIM/include/instance/sercom5.h index a1fe75e..eaa937f 100644 --- a/sysmoOCTSIM/include/instance/sercom5.h +++ b/sysmoOCTSIM/include/instance/sercom5.h @@ -3,7 +3,7 @@ * * \brief Instance description for SERCOM5 * - * Copyright (c) 2018 Microchip Technology Inc. + * Copyright (c) 2019 Microchip Technology Inc.
* * \asf_license_start * @@ -145,6 +145,18 @@ #define SERCOM5_GCLK_ID_CORE 35 #define SERCOM5_GCLK_ID_SLOW 3 #define SERCOM5_INT_MSB 6 +#define SERCOM5_I2CM 1 // I2C Master mode implemented?
+#define SERCOM5_I2CS 1 // I2C Slave mode implemented?
+#define SERCOM5_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
+#define SERCOM5_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
+#define SERCOM5_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
+#define SERCOM5_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
+#define SERCOM5_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
+#define SERCOM5_I2C_FASTMP 1 // I2C fast mode plus implemented?
+#define SERCOM5_I2C_HSMODE 1 // USART mode implemented?
+#define SERCOM5_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
+#define SERCOM5_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
+#define SERCOM5_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
#define SERCOM5_PMSB 3 #define SERCOM5_RETENTION_SUPPORT 0 // Retention supported? #define SERCOM5_SE_CNT 1 // SE counter included? @@ -154,18 +166,6 @@ #define SERCOM5_SPI_OZMO 0 // OZMO features implemented? #define SERCOM5_SPI_WAKE_ON_SSL 1 // _SS low detect implemented? #define SERCOM5_TTBIT_EXTENSION 1 // 32-bit extension implemented? -#define SERCOM5_TWIM 1 // TWI Master mode implemented? -#define SERCOM5_TWIS 1 // TWI Slave mode implemented? -#define SERCOM5_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented? -#define SERCOM5_TWIS_GROUP_CMD 1 // TWI slave group command implemented? -#define SERCOM5_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size -#define SERCOM5_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size -#define SERCOM5_TWIS_SUDAT 1 // TWI slave SDA setup implemented? -#define SERCOM5_TWI_FASTMP 1 // TWI fast mode plus implemented? -#define SERCOM5_TWI_HSMODE 1 // USART mode implemented? -#define SERCOM5_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented? -#define SERCOM5_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented? -#define SERCOM5_TWI_TENBIT_ADR 1 // TWI ten bit enabled? #define SERCOM5_USART 1 // USART mode implemented? #define SERCOM5_USART_AUTOBAUD 1 // USART autobaud implemented? #define SERCOM5_USART_COLDET 1 // USART collision detection implemented? diff --git a/sysmoOCTSIM/include/instance/sercom6.h b/sysmoOCTSIM/include/instance/sercom6.h index b47957c..3f5a6c7 100644 --- a/sysmoOCTSIM/include/instance/sercom6.h +++ b/sysmoOCTSIM/include/instance/sercom6.h @@ -3,7 +3,7 @@ * * \brief Instance description for SERCOM6 * - * Copyright (c) 2018 Microchip Technology Inc. + * Copyright (c) 2019 Microchip Technology Inc.
* * \asf_license_start * @@ -145,6 +145,18 @@ #define SERCOM6_GCLK_ID_CORE 36 #define SERCOM6_GCLK_ID_SLOW 3 #define SERCOM6_INT_MSB 6 +#define SERCOM6_I2CM 1 // I2C Master mode implemented?
+#define SERCOM6_I2CS 1 // I2C Slave mode implemented?
+#define SERCOM6_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
+#define SERCOM6_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
+#define SERCOM6_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
+#define SERCOM6_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
+#define SERCOM6_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
+#define SERCOM6_I2C_FASTMP 1 // I2C fast mode plus implemented?
+#define SERCOM6_I2C_HSMODE 1 // USART mode implemented?
+#define SERCOM6_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
+#define SERCOM6_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
+#define SERCOM6_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
#define SERCOM6_PMSB 3 #define SERCOM6_RETENTION_SUPPORT 0 // Retention supported? #define SERCOM6_SE_CNT 1 // SE counter included? @@ -154,18 +166,6 @@ #define SERCOM6_SPI_OZMO 0 // OZMO features implemented? #define SERCOM6_SPI_WAKE_ON_SSL 1 // _SS low detect implemented? #define SERCOM6_TTBIT_EXTENSION 1 // 32-bit extension implemented? -#define SERCOM6_TWIM 1 // TWI Master mode implemented? -#define SERCOM6_TWIS 1 // TWI Slave mode implemented? -#define SERCOM6_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented? -#define SERCOM6_TWIS_GROUP_CMD 1 // TWI slave group command implemented? -#define SERCOM6_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size -#define SERCOM6_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size -#define SERCOM6_TWIS_SUDAT 1 // TWI slave SDA setup implemented? -#define SERCOM6_TWI_FASTMP 1 // TWI fast mode plus implemented? -#define SERCOM6_TWI_HSMODE 1 // USART mode implemented? -#define SERCOM6_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented? -#define SERCOM6_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented? -#define SERCOM6_TWI_TENBIT_ADR 1 // TWI ten bit enabled? #define SERCOM6_USART 1 // USART mode implemented? #define SERCOM6_USART_AUTOBAUD 1 // USART autobaud implemented? #define SERCOM6_USART_COLDET 1 // USART collision detection implemented? diff --git a/sysmoOCTSIM/include/instance/sercom7.h b/sysmoOCTSIM/include/instance/sercom7.h index 5bf5ae4..1118bca 100644 --- a/sysmoOCTSIM/include/instance/sercom7.h +++ b/sysmoOCTSIM/include/instance/sercom7.h @@ -3,7 +3,7 @@ * * \brief Instance description for SERCOM7 * - * Copyright (c) 2018 Microchip Technology Inc. + * Copyright (c) 2019 Microchip Technology Inc.
* * \asf_license_start * @@ -145,6 +145,18 @@ #define SERCOM7_GCLK_ID_CORE 37 #define SERCOM7_GCLK_ID_SLOW 3 #define SERCOM7_INT_MSB 6 +#define SERCOM7_I2CM 1 // I2C Master mode implemented?
+#define SERCOM7_I2CS 1 // I2C Slave mode implemented?
+#define SERCOM7_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
+#define SERCOM7_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
+#define SERCOM7_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
+#define SERCOM7_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
+#define SERCOM7_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
+#define SERCOM7_I2C_FASTMP 1 // I2C fast mode plus implemented?
+#define SERCOM7_I2C_HSMODE 1 // USART mode implemented?
+#define SERCOM7_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
+#define SERCOM7_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
+#define SERCOM7_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
#define SERCOM7_PMSB 3 #define SERCOM7_RETENTION_SUPPORT 0 // Retention supported? #define SERCOM7_SE_CNT 1 // SE counter included? @@ -154,18 +166,6 @@ #define SERCOM7_SPI_OZMO 0 // OZMO features implemented? #define SERCOM7_SPI_WAKE_ON_SSL 1 // _SS low detect implemented? #define SERCOM7_TTBIT_EXTENSION 1 // 32-bit extension implemented? -#define SERCOM7_TWIM 1 // TWI Master mode implemented? -#define SERCOM7_TWIS 1 // TWI Slave mode implemented? -#define SERCOM7_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented? -#define SERCOM7_TWIS_GROUP_CMD 1 // TWI slave group command implemented? -#define SERCOM7_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size -#define SERCOM7_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size -#define SERCOM7_TWIS_SUDAT 1 // TWI slave SDA setup implemented? -#define SERCOM7_TWI_FASTMP 1 // TWI fast mode plus implemented? -#define SERCOM7_TWI_HSMODE 1 // USART mode implemented? -#define SERCOM7_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented? -#define SERCOM7_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented? -#define SERCOM7_TWI_TENBIT_ADR 1 // TWI ten bit enabled? #define SERCOM7_USART 1 // USART mode implemented? #define SERCOM7_USART_AUTOBAUD 1 // USART autobaud implemented? #define SERCOM7_USART_COLDET 1 // USART collision detection implemented? diff --git a/sysmoOCTSIM/include/instance/supc.h b/sysmoOCTSIM/include/instance/supc.h index 734c682..4018344 100644 --- a/sysmoOCTSIM/include/instance/supc.h +++ b/sysmoOCTSIM/include/instance/supc.h @@ -3,7 +3,7 @@ * * \brief Instance description for SUPC * - * Copyright (c) 2018 Microchip Technology Inc. + * Copyright (c) 2019 Microchip Technology Inc.
* * \asf_license_start * @@ -37,7 +37,6 @@ #define REG_SUPC_INTFLAG (0x40001808) /**< \brief (SUPC) Interrupt Flag Status and Clear */ #define REG_SUPC_STATUS (0x4000180C) /**< \brief (SUPC) Power and Clocks Status */ #define REG_SUPC_BOD33 (0x40001810) /**< \brief (SUPC) BOD33 Control */ -#define REG_SUPC_BOD12 (0x40001814) /**< \brief (SUPC) BOD12 Control */ #define REG_SUPC_VREG (0x40001818) /**< \brief (SUPC) VREG Control */ #define REG_SUPC_VREF (0x4000181C) /**< \brief (SUPC) VREF Control */ #define REG_SUPC_BBPS (0x40001820) /**< \brief (SUPC) Battery Backup Power Switch */ @@ -49,7 +48,6 @@ #define REG_SUPC_INTFLAG (*(RwReg *)0x40001808UL) /**< \brief (SUPC) Interrupt Flag Status and Clear */ #define REG_SUPC_STATUS (*(RoReg *)0x4000180CUL) /**< \brief (SUPC) Power and Clocks Status */ #define REG_SUPC_BOD33 (*(RwReg *)0x40001810UL) /**< \brief (SUPC) BOD33 Control */ -#define REG_SUPC_BOD12 (*(RwReg *)0x40001814UL) /**< \brief (SUPC) BOD12 Control */ #define REG_SUPC_VREG (*(RwReg *)0x40001818UL) /**< \brief (SUPC) VREG Control */ #define REG_SUPC_VREF (*(RwReg *)0x4000181CUL) /**< \brief (SUPC) VREF Control */ #define REG_SUPC_BBPS (*(RwReg *)0x40001820UL) /**< \brief (SUPC) Battery Backup Power Switch */ diff --git a/sysmoOCTSIM/include/same54n19a.h b/sysmoOCTSIM/include/same54n19a.h index fb6724c..6812e73 100644 --- a/sysmoOCTSIM/include/same54n19a.h +++ b/sysmoOCTSIM/include/same54n19a.h @@ -3,7 +3,7 @@ * * \brief Header file for SAME54N19A * - * Copyright (c) 2018 Microchip Technology Inc. + * Copyright (c) 2019 Microchip Technology Inc.
* * \asf_license_start * @@ -103,108 +103,108 @@ typedef enum IRQn /****** SAME54N19A-specific Interrupt Numbers *********************/ PM_IRQn = 0, /**< 0 SAME54N19A Power Manager (PM) */ MCLK_IRQn = 1, /**< 1 SAME54N19A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAME54N19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAME54N19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAME54N19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAME54N19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAME54N19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSCCTRL_0_IRQn = 2, /**< 2 SAME54N19A Oscillators Control (OSCCTRL) IRQ 0 */
+ OSCCTRL_1_IRQn = 3, /**< 3 SAME54N19A Oscillators Control (OSCCTRL) IRQ 1 */
+ OSCCTRL_2_IRQn = 4, /**< 4 SAME54N19A Oscillators Control (OSCCTRL) IRQ 2 */
+ OSCCTRL_3_IRQn = 5, /**< 5 SAME54N19A Oscillators Control (OSCCTRL) IRQ 3 */
+ OSCCTRL_4_IRQn = 6, /**< 6 SAME54N19A Oscillators Control (OSCCTRL) IRQ 4 */
OSC32KCTRL_IRQn = 7, /**< 7 SAME54N19A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAME54N19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAME54N19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + SUPC_0_IRQn = 8, /**< 8 SAME54N19A Supply Controller (SUPC) IRQ 0 */
+ SUPC_1_IRQn = 9, /**< 9 SAME54N19A Supply Controller (SUPC) IRQ 1 */
WDT_IRQn = 10, /**< 10 SAME54N19A Watchdog Timer (WDT) */ RTC_IRQn = 11, /**< 11 SAME54N19A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAME54N19A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + EIC_0_IRQn = 12, /**< 12 SAME54N19A External Interrupt Controller (EIC) IRQ 0 */
+ EIC_1_IRQn = 13, /**< 13 SAME54N19A External Interrupt Controller (EIC) IRQ 1 */
+ EIC_2_IRQn = 14, /**< 14 SAME54N19A External Interrupt Controller (EIC) IRQ 2 */
+ EIC_3_IRQn = 15, /**< 15 SAME54N19A External Interrupt Controller (EIC) IRQ 3 */
+ EIC_4_IRQn = 16, /**< 16 SAME54N19A External Interrupt Controller (EIC) IRQ 4 */
+ EIC_5_IRQn = 17, /**< 17 SAME54N19A External Interrupt Controller (EIC) IRQ 5 */
+ EIC_6_IRQn = 18, /**< 18 SAME54N19A External Interrupt Controller (EIC) IRQ 6 */
+ EIC_7_IRQn = 19, /**< 19 SAME54N19A External Interrupt Controller (EIC) IRQ 7 */
+ EIC_8_IRQn = 20, /**< 20 SAME54N19A External Interrupt Controller (EIC) IRQ 8 */
+ EIC_9_IRQn = 21, /**< 21 SAME54N19A External Interrupt Controller (EIC) IRQ 9 */
+ EIC_10_IRQn = 22, /**< 22 SAME54N19A External Interrupt Controller (EIC) IRQ 10 */
+ EIC_11_IRQn = 23, /**< 23 SAME54N19A External Interrupt Controller (EIC) IRQ 11 */
+ EIC_12_IRQn = 24, /**< 24 SAME54N19A External Interrupt Controller (EIC) IRQ 12 */
+ EIC_13_IRQn = 25, /**< 25 SAME54N19A External Interrupt Controller (EIC) IRQ 13 */
+ EIC_14_IRQn = 26, /**< 26 SAME54N19A External Interrupt Controller (EIC) IRQ 14 */
+ EIC_15_IRQn = 27, /**< 27 SAME54N19A External Interrupt Controller (EIC) IRQ 15 */
FREQM_IRQn = 28, /**< 28 SAME54N19A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAME54N19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAME54N19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAME54N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAME54N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAME54N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAME54N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAME54N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAME54N19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAME54N19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAME54N19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAME54N19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAME54N19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + NVMCTRL_0_IRQn = 29, /**< 29 SAME54N19A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */
+ NVMCTRL_1_IRQn = 30, /**< 30 SAME54N19A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */
+ DMAC_0_IRQn = 31, /**< 31 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 0 */
+ DMAC_1_IRQn = 32, /**< 32 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 1 */
+ DMAC_2_IRQn = 33, /**< 33 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 2 */
+ DMAC_3_IRQn = 34, /**< 34 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 3 */
+ DMAC_4_IRQn = 35, /**< 35 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 4 */
+ EVSYS_0_IRQn = 36, /**< 36 SAME54N19A Event System Interface (EVSYS) IRQ 0 */
+ EVSYS_1_IRQn = 37, /**< 37 SAME54N19A Event System Interface (EVSYS) IRQ 1 */
+ EVSYS_2_IRQn = 38, /**< 38 SAME54N19A Event System Interface (EVSYS) IRQ 2 */
+ EVSYS_3_IRQn = 39, /**< 39 SAME54N19A Event System Interface (EVSYS) IRQ 3 */
+ EVSYS_4_IRQn = 40, /**< 40 SAME54N19A Event System Interface (EVSYS) IRQ 4 */
PAC_IRQn = 41, /**< 41 SAME54N19A Peripheral Access Controller (PAC) */ RAMECC_IRQn = 45, /**< 45 SAME54N19A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAME54N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAME54N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAME54N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAME54N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAME54N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAME54N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAME54N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAME54N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAME54N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAME54N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAME54N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAME54N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAME54N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAME54N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAME54N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAME54N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAME54N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAME54N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAME54N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAME54N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAME54N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAME54N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAME54N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAME54N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - SERCOM6_0_IRQn = 70, /**< 70 SAME54N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ - SERCOM6_1_IRQn = 71, /**< 71 SAME54N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ - SERCOM6_2_IRQn = 72, /**< 72 SAME54N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ - SERCOM6_3_IRQn = 73, /**< 73 SAME54N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ - SERCOM7_0_IRQn = 74, /**< 74 SAME54N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ - SERCOM7_1_IRQn = 75, /**< 75 SAME54N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ - SERCOM7_2_IRQn = 76, /**< 76 SAME54N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ - SERCOM7_3_IRQn = 77, /**< 77 SAME54N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ + SERCOM0_0_IRQn = 46, /**< 46 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 0 */
+ SERCOM0_1_IRQn = 47, /**< 47 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 1 */
+ SERCOM0_2_IRQn = 48, /**< 48 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 2 */
+ SERCOM0_3_IRQn = 49, /**< 49 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 3 */
+ SERCOM1_0_IRQn = 50, /**< 50 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 0 */
+ SERCOM1_1_IRQn = 51, /**< 51 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 1 */
+ SERCOM1_2_IRQn = 52, /**< 52 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 2 */
+ SERCOM1_3_IRQn = 53, /**< 53 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 3 */
+ SERCOM2_0_IRQn = 54, /**< 54 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 0 */
+ SERCOM2_1_IRQn = 55, /**< 55 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 1 */
+ SERCOM2_2_IRQn = 56, /**< 56 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 2 */
+ SERCOM2_3_IRQn = 57, /**< 57 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 3 */
+ SERCOM3_0_IRQn = 58, /**< 58 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 0 */
+ SERCOM3_1_IRQn = 59, /**< 59 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 1 */
+ SERCOM3_2_IRQn = 60, /**< 60 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 2 */
+ SERCOM3_3_IRQn = 61, /**< 61 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 3 */
+ SERCOM4_0_IRQn = 62, /**< 62 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 0 */
+ SERCOM4_1_IRQn = 63, /**< 63 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 1 */
+ SERCOM4_2_IRQn = 64, /**< 64 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 2 */
+ SERCOM4_3_IRQn = 65, /**< 65 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 3 */
+ SERCOM5_0_IRQn = 66, /**< 66 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 0 */
+ SERCOM5_1_IRQn = 67, /**< 67 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 1 */
+ SERCOM5_2_IRQn = 68, /**< 68 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 2 */
+ SERCOM5_3_IRQn = 69, /**< 69 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 3 */
+ SERCOM6_0_IRQn = 70, /**< 70 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 0 */
+ SERCOM6_1_IRQn = 71, /**< 71 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 1 */
+ SERCOM6_2_IRQn = 72, /**< 72 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 2 */
+ SERCOM6_3_IRQn = 73, /**< 73 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 3 */
+ SERCOM7_0_IRQn = 74, /**< 74 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 0 */
+ SERCOM7_1_IRQn = 75, /**< 75 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 1 */
+ SERCOM7_2_IRQn = 76, /**< 76 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 2 */
+ SERCOM7_3_IRQn = 77, /**< 77 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 3 */
CAN0_IRQn = 78, /**< 78 SAME54N19A Control Area Network 0 (CAN0) */ CAN1_IRQn = 79, /**< 79 SAME54N19A Control Area Network 1 (CAN1) */ - USB_0_IRQn = 80, /**< 80 SAME54N19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAME54N19A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAME54N19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAME54N19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + USB_0_IRQn = 80, /**< 80 SAME54N19A Universal Serial Bus (USB) IRQ 0 */
+ USB_1_IRQn = 81, /**< 81 SAME54N19A Universal Serial Bus (USB) IRQ 1 */
+ USB_2_IRQn = 82, /**< 82 SAME54N19A Universal Serial Bus (USB) IRQ 2 */
+ USB_3_IRQn = 83, /**< 83 SAME54N19A Universal Serial Bus (USB) IRQ 3 */
GMAC_IRQn = 84, /**< 84 SAME54N19A Ethernet MAC (GMAC) */ - TCC0_0_IRQn = 85, /**< 85 SAME54N19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAME54N19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAME54N19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAME54N19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAME54N19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAME54N19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAME54N19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAME54N19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAME54N19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAME54N19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAME54N19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAME54N19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAME54N19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAME54N19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAME54N19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAME54N19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TCC3_0_IRQn = 101, /**< 101 SAME54N19A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - TCC3_1_IRQn = 102, /**< 102 SAME54N19A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ - TCC3_2_IRQn = 103, /**< 103 SAME54N19A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ - TCC4_0_IRQn = 104, /**< 104 SAME54N19A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - TCC4_1_IRQn = 105, /**< 105 SAME54N19A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ - TCC4_2_IRQn = 106, /**< 106 SAME54N19A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ + TCC0_0_IRQn = 85, /**< 85 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 0 */
+ TCC0_1_IRQn = 86, /**< 86 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 1 */
+ TCC0_2_IRQn = 87, /**< 87 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 2 */
+ TCC0_3_IRQn = 88, /**< 88 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 3 */
+ TCC0_4_IRQn = 89, /**< 89 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 4 */
+ TCC0_5_IRQn = 90, /**< 90 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 5 */
+ TCC0_6_IRQn = 91, /**< 91 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 6 */
+ TCC1_0_IRQn = 92, /**< 92 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 0 */
+ TCC1_1_IRQn = 93, /**< 93 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 1 */
+ TCC1_2_IRQn = 94, /**< 94 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 2 */
+ TCC1_3_IRQn = 95, /**< 95 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 3 */
+ TCC1_4_IRQn = 96, /**< 96 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 4 */
+ TCC2_0_IRQn = 97, /**< 97 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 0 */
+ TCC2_1_IRQn = 98, /**< 98 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 1 */
+ TCC2_2_IRQn = 99, /**< 99 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 2 */
+ TCC2_3_IRQn = 100, /**< 100 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 3 */
+ TCC3_0_IRQn = 101, /**< 101 SAME54N19A Timer Counter Control 3 (TCC3) IRQ 0 */
+ TCC3_1_IRQn = 102, /**< 102 SAME54N19A Timer Counter Control 3 (TCC3) IRQ 1 */
+ TCC3_2_IRQn = 103, /**< 103 SAME54N19A Timer Counter Control 3 (TCC3) IRQ 2 */
+ TCC4_0_IRQn = 104, /**< 104 SAME54N19A Timer Counter Control 4 (TCC4) IRQ 0 */
+ TCC4_1_IRQn = 105, /**< 105 SAME54N19A Timer Counter Control 4 (TCC4) IRQ 1 */
+ TCC4_2_IRQn = 106, /**< 106 SAME54N19A Timer Counter Control 4 (TCC4) IRQ 2 */
TC0_IRQn = 107, /**< 107 SAME54N19A Basic Timer Counter 0 (TC0) */ TC1_IRQn = 108, /**< 108 SAME54N19A Basic Timer Counter 1 (TC1) */ TC2_IRQn = 109, /**< 109 SAME54N19A Basic Timer Counter 2 (TC2) */ @@ -213,19 +213,19 @@ typedef enum IRQn TC5_IRQn = 112, /**< 112 SAME54N19A Basic Timer Counter 5 (TC5) */ TC6_IRQn = 113, /**< 113 SAME54N19A Basic Timer Counter 6 (TC6) */ TC7_IRQn = 114, /**< 114 SAME54N19A Basic Timer Counter 7 (TC7) */ - PDEC_0_IRQn = 115, /**< 115 SAME54N19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAME54N19A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAME54N19A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAME54N19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAME54N19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAME54N19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAME54N19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + PDEC_0_IRQn = 115, /**< 115 SAME54N19A Quadrature Decodeur (PDEC) IRQ 0 */
+ PDEC_1_IRQn = 116, /**< 116 SAME54N19A Quadrature Decodeur (PDEC) IRQ 1 */
+ PDEC_2_IRQn = 117, /**< 117 SAME54N19A Quadrature Decodeur (PDEC) IRQ 2 */
+ ADC0_0_IRQn = 118, /**< 118 SAME54N19A Analog Digital Converter 0 (ADC0) IRQ 0 */
+ ADC0_1_IRQn = 119, /**< 119 SAME54N19A Analog Digital Converter 0 (ADC0) IRQ 1 */
+ ADC1_0_IRQn = 120, /**< 120 SAME54N19A Analog Digital Converter 1 (ADC1) IRQ 0 */
+ ADC1_1_IRQn = 121, /**< 121 SAME54N19A Analog Digital Converter 1 (ADC1) IRQ 1 */
AC_IRQn = 122, /**< 122 SAME54N19A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAME54N19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAME54N19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAME54N19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAME54N19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAME54N19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + DAC_0_IRQn = 123, /**< 123 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 0 */
+ DAC_1_IRQn = 124, /**< 124 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 1 */
+ DAC_2_IRQn = 125, /**< 125 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 2 */
+ DAC_3_IRQn = 126, /**< 126 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 3 */
+ DAC_4_IRQn = 127, /**< 127 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 4 */
I2S_IRQn = 128, /**< 128 SAME54N19A Inter-IC Sound Interface (I2S) */ PCC_IRQn = 129, /**< 129 SAME54N19A Parallel Capture Controller (PCC) */ AES_IRQn = 130, /**< 130 SAME54N19A Advanced Encryption Standard (AES) */ diff --git a/sysmoOCTSIM/include/same54n20a.h b/sysmoOCTSIM/include/same54n20a.h index 936c1d4..3366134 100644 --- a/sysmoOCTSIM/include/same54n20a.h +++ b/sysmoOCTSIM/include/same54n20a.h @@ -3,7 +3,7 @@ * * \brief Header file for SAME54N20A * - * Copyright (c) 2018 Microchip Technology Inc. + * Copyright (c) 2019 Microchip Technology Inc.
* * \asf_license_start * @@ -103,108 +103,108 @@ typedef enum IRQn /****** SAME54N20A-specific Interrupt Numbers *********************/ PM_IRQn = 0, /**< 0 SAME54N20A Power Manager (PM) */ MCLK_IRQn = 1, /**< 1 SAME54N20A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAME54N20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAME54N20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAME54N20A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAME54N20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAME54N20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSCCTRL_0_IRQn = 2, /**< 2 SAME54N20A Oscillators Control (OSCCTRL) IRQ 0 */
+ OSCCTRL_1_IRQn = 3, /**< 3 SAME54N20A Oscillators Control (OSCCTRL) IRQ 1 */
+ OSCCTRL_2_IRQn = 4, /**< 4 SAME54N20A Oscillators Control (OSCCTRL) IRQ 2 */
+ OSCCTRL_3_IRQn = 5, /**< 5 SAME54N20A Oscillators Control (OSCCTRL) IRQ 3 */
+ OSCCTRL_4_IRQn = 6, /**< 6 SAME54N20A Oscillators Control (OSCCTRL) IRQ 4 */
OSC32KCTRL_IRQn = 7, /**< 7 SAME54N20A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAME54N20A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAME54N20A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + SUPC_0_IRQn = 8, /**< 8 SAME54N20A Supply Controller (SUPC) IRQ 0 */
+ SUPC_1_IRQn = 9, /**< 9 SAME54N20A Supply Controller (SUPC) IRQ 1 */
WDT_IRQn = 10, /**< 10 SAME54N20A Watchdog Timer (WDT) */ RTC_IRQn = 11, /**< 11 SAME54N20A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAME54N20A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + EIC_0_IRQn = 12, /**< 12 SAME54N20A External Interrupt Controller (EIC) IRQ 0 */
+ EIC_1_IRQn = 13, /**< 13 SAME54N20A External Interrupt Controller (EIC) IRQ 1 */
+ EIC_2_IRQn = 14, /**< 14 SAME54N20A External Interrupt Controller (EIC) IRQ 2 */
+ EIC_3_IRQn = 15, /**< 15 SAME54N20A External Interrupt Controller (EIC) IRQ 3 */
+ EIC_4_IRQn = 16, /**< 16 SAME54N20A External Interrupt Controller (EIC) IRQ 4 */
+ EIC_5_IRQn = 17, /**< 17 SAME54N20A External Interrupt Controller (EIC) IRQ 5 */
+ EIC_6_IRQn = 18, /**< 18 SAME54N20A External Interrupt Controller (EIC) IRQ 6 */
+ EIC_7_IRQn = 19, /**< 19 SAME54N20A External Interrupt Controller (EIC) IRQ 7 */
+ EIC_8_IRQn = 20, /**< 20 SAME54N20A External Interrupt Controller (EIC) IRQ 8 */
+ EIC_9_IRQn = 21, /**< 21 SAME54N20A External Interrupt Controller (EIC) IRQ 9 */
+ EIC_10_IRQn = 22, /**< 22 SAME54N20A External Interrupt Controller (EIC) IRQ 10 */
+ EIC_11_IRQn = 23, /**< 23 SAME54N20A External Interrupt Controller (EIC) IRQ 11 */
+ EIC_12_IRQn = 24, /**< 24 SAME54N20A External Interrupt Controller (EIC) IRQ 12 */
+ EIC_13_IRQn = 25, /**< 25 SAME54N20A External Interrupt Controller (EIC) IRQ 13 */
+ EIC_14_IRQn = 26, /**< 26 SAME54N20A External Interrupt Controller (EIC) IRQ 14 */
+ EIC_15_IRQn = 27, /**< 27 SAME54N20A External Interrupt Controller (EIC) IRQ 15 */
FREQM_IRQn = 28, /**< 28 SAME54N20A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAME54N20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAME54N20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAME54N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAME54N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAME54N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAME54N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAME54N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAME54N20A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAME54N20A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAME54N20A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAME54N20A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAME54N20A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + NVMCTRL_0_IRQn = 29, /**< 29 SAME54N20A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */
+ NVMCTRL_1_IRQn = 30, /**< 30 SAME54N20A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */
+ DMAC_0_IRQn = 31, /**< 31 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 0 */
+ DMAC_1_IRQn = 32, /**< 32 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 1 */
+ DMAC_2_IRQn = 33, /**< 33 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 2 */
+ DMAC_3_IRQn = 34, /**< 34 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 3 */
+ DMAC_4_IRQn = 35, /**< 35 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 4 */
+ EVSYS_0_IRQn = 36, /**< 36 SAME54N20A Event System Interface (EVSYS) IRQ 0 */
+ EVSYS_1_IRQn = 37, /**< 37 SAME54N20A Event System Interface (EVSYS) IRQ 1 */
+ EVSYS_2_IRQn = 38, /**< 38 SAME54N20A Event System Interface (EVSYS) IRQ 2 */
+ EVSYS_3_IRQn = 39, /**< 39 SAME54N20A Event System Interface (EVSYS) IRQ 3 */
+ EVSYS_4_IRQn = 40, /**< 40 SAME54N20A Event System Interface (EVSYS) IRQ 4 */
PAC_IRQn = 41, /**< 41 SAME54N20A Peripheral Access Controller (PAC) */ RAMECC_IRQn = 45, /**< 45 SAME54N20A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAME54N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAME54N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAME54N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAME54N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAME54N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAME54N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAME54N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAME54N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAME54N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAME54N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAME54N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAME54N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAME54N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAME54N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAME54N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAME54N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAME54N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAME54N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAME54N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAME54N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAME54N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAME54N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAME54N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAME54N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - SERCOM6_0_IRQn = 70, /**< 70 SAME54N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ - SERCOM6_1_IRQn = 71, /**< 71 SAME54N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ - SERCOM6_2_IRQn = 72, /**< 72 SAME54N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ - SERCOM6_3_IRQn = 73, /**< 73 SAME54N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ - SERCOM7_0_IRQn = 74, /**< 74 SAME54N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ - SERCOM7_1_IRQn = 75, /**< 75 SAME54N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ - SERCOM7_2_IRQn = 76, /**< 76 SAME54N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ - SERCOM7_3_IRQn = 77, /**< 77 SAME54N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ + SERCOM0_0_IRQn = 46, /**< 46 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 0 */
+ SERCOM0_1_IRQn = 47, /**< 47 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 1 */
+ SERCOM0_2_IRQn = 48, /**< 48 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 2 */
+ SERCOM0_3_IRQn = 49, /**< 49 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 3 */
+ SERCOM1_0_IRQn = 50, /**< 50 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 0 */
+ SERCOM1_1_IRQn = 51, /**< 51 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 1 */
+ SERCOM1_2_IRQn = 52, /**< 52 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 2 */
+ SERCOM1_3_IRQn = 53, /**< 53 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 3 */
+ SERCOM2_0_IRQn = 54, /**< 54 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 0 */
+ SERCOM2_1_IRQn = 55, /**< 55 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 1 */
+ SERCOM2_2_IRQn = 56, /**< 56 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 2 */
+ SERCOM2_3_IRQn = 57, /**< 57 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 3 */
+ SERCOM3_0_IRQn = 58, /**< 58 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 0 */
+ SERCOM3_1_IRQn = 59, /**< 59 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 1 */
+ SERCOM3_2_IRQn = 60, /**< 60 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 2 */
+ SERCOM3_3_IRQn = 61, /**< 61 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 3 */
+ SERCOM4_0_IRQn = 62, /**< 62 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 0 */
+ SERCOM4_1_IRQn = 63, /**< 63 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 1 */
+ SERCOM4_2_IRQn = 64, /**< 64 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 2 */
+ SERCOM4_3_IRQn = 65, /**< 65 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 3 */
+ SERCOM5_0_IRQn = 66, /**< 66 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 0 */
+ SERCOM5_1_IRQn = 67, /**< 67 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 1 */
+ SERCOM5_2_IRQn = 68, /**< 68 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 2 */
+ SERCOM5_3_IRQn = 69, /**< 69 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 3 */
+ SERCOM6_0_IRQn = 70, /**< 70 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 0 */
+ SERCOM6_1_IRQn = 71, /**< 71 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 1 */
+ SERCOM6_2_IRQn = 72, /**< 72 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 2 */
+ SERCOM6_3_IRQn = 73, /**< 73 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 3 */
+ SERCOM7_0_IRQn = 74, /**< 74 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 0 */
+ SERCOM7_1_IRQn = 75, /**< 75 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 1 */
+ SERCOM7_2_IRQn = 76, /**< 76 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 2 */
+ SERCOM7_3_IRQn = 77, /**< 77 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 3 */
CAN0_IRQn = 78, /**< 78 SAME54N20A Control Area Network 0 (CAN0) */ CAN1_IRQn = 79, /**< 79 SAME54N20A Control Area Network 1 (CAN1) */ - USB_0_IRQn = 80, /**< 80 SAME54N20A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAME54N20A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAME54N20A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAME54N20A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + USB_0_IRQn = 80, /**< 80 SAME54N20A Universal Serial Bus (USB) IRQ 0 */
+ USB_1_IRQn = 81, /**< 81 SAME54N20A Universal Serial Bus (USB) IRQ 1 */
+ USB_2_IRQn = 82, /**< 82 SAME54N20A Universal Serial Bus (USB) IRQ 2 */
+ USB_3_IRQn = 83, /**< 83 SAME54N20A Universal Serial Bus (USB) IRQ 3 */
GMAC_IRQn = 84, /**< 84 SAME54N20A Ethernet MAC (GMAC) */ - TCC0_0_IRQn = 85, /**< 85 SAME54N20A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAME54N20A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAME54N20A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAME54N20A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAME54N20A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAME54N20A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAME54N20A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAME54N20A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAME54N20A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAME54N20A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAME54N20A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAME54N20A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAME54N20A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAME54N20A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAME54N20A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAME54N20A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TCC3_0_IRQn = 101, /**< 101 SAME54N20A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - TCC3_1_IRQn = 102, /**< 102 SAME54N20A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ - TCC3_2_IRQn = 103, /**< 103 SAME54N20A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ - TCC4_0_IRQn = 104, /**< 104 SAME54N20A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - TCC4_1_IRQn = 105, /**< 105 SAME54N20A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ - TCC4_2_IRQn = 106, /**< 106 SAME54N20A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ + TCC0_0_IRQn = 85, /**< 85 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 0 */
+ TCC0_1_IRQn = 86, /**< 86 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 1 */
+ TCC0_2_IRQn = 87, /**< 87 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 2 */
+ TCC0_3_IRQn = 88, /**< 88 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 3 */
+ TCC0_4_IRQn = 89, /**< 89 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 4 */
+ TCC0_5_IRQn = 90, /**< 90 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 5 */
+ TCC0_6_IRQn = 91, /**< 91 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 6 */
+ TCC1_0_IRQn = 92, /**< 92 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 0 */
+ TCC1_1_IRQn = 93, /**< 93 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 1 */
+ TCC1_2_IRQn = 94, /**< 94 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 2 */
+ TCC1_3_IRQn = 95, /**< 95 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 3 */
+ TCC1_4_IRQn = 96, /**< 96 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 4 */
+ TCC2_0_IRQn = 97, /**< 97 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 0 */
+ TCC2_1_IRQn = 98, /**< 98 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 1 */
+ TCC2_2_IRQn = 99, /**< 99 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 2 */
+ TCC2_3_IRQn = 100, /**< 100 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 3 */
+ TCC3_0_IRQn = 101, /**< 101 SAME54N20A Timer Counter Control 3 (TCC3) IRQ 0 */
+ TCC3_1_IRQn = 102, /**< 102 SAME54N20A Timer Counter Control 3 (TCC3) IRQ 1 */
+ TCC3_2_IRQn = 103, /**< 103 SAME54N20A Timer Counter Control 3 (TCC3) IRQ 2 */
+ TCC4_0_IRQn = 104, /**< 104 SAME54N20A Timer Counter Control 4 (TCC4) IRQ 0 */
+ TCC4_1_IRQn = 105, /**< 105 SAME54N20A Timer Counter Control 4 (TCC4) IRQ 1 */
+ TCC4_2_IRQn = 106, /**< 106 SAME54N20A Timer Counter Control 4 (TCC4) IRQ 2 */
TC0_IRQn = 107, /**< 107 SAME54N20A Basic Timer Counter 0 (TC0) */ TC1_IRQn = 108, /**< 108 SAME54N20A Basic Timer Counter 1 (TC1) */ TC2_IRQn = 109, /**< 109 SAME54N20A Basic Timer Counter 2 (TC2) */ @@ -213,19 +213,19 @@ typedef enum IRQn TC5_IRQn = 112, /**< 112 SAME54N20A Basic Timer Counter 5 (TC5) */ TC6_IRQn = 113, /**< 113 SAME54N20A Basic Timer Counter 6 (TC6) */ TC7_IRQn = 114, /**< 114 SAME54N20A Basic Timer Counter 7 (TC7) */ - PDEC_0_IRQn = 115, /**< 115 SAME54N20A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAME54N20A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAME54N20A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAME54N20A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAME54N20A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAME54N20A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAME54N20A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + PDEC_0_IRQn = 115, /**< 115 SAME54N20A Quadrature Decodeur (PDEC) IRQ 0 */
+ PDEC_1_IRQn = 116, /**< 116 SAME54N20A Quadrature Decodeur (PDEC) IRQ 1 */
+ PDEC_2_IRQn = 117, /**< 117 SAME54N20A Quadrature Decodeur (PDEC) IRQ 2 */
+ ADC0_0_IRQn = 118, /**< 118 SAME54N20A Analog Digital Converter 0 (ADC0) IRQ 0 */
+ ADC0_1_IRQn = 119, /**< 119 SAME54N20A Analog Digital Converter 0 (ADC0) IRQ 1 */
+ ADC1_0_IRQn = 120, /**< 120 SAME54N20A Analog Digital Converter 1 (ADC1) IRQ 0 */
+ ADC1_1_IRQn = 121, /**< 121 SAME54N20A Analog Digital Converter 1 (ADC1) IRQ 1 */
AC_IRQn = 122, /**< 122 SAME54N20A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAME54N20A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAME54N20A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAME54N20A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAME54N20A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAME54N20A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + DAC_0_IRQn = 123, /**< 123 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 0 */
+ DAC_1_IRQn = 124, /**< 124 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 1 */
+ DAC_2_IRQn = 125, /**< 125 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 2 */
+ DAC_3_IRQn = 126, /**< 126 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 3 */
+ DAC_4_IRQn = 127, /**< 127 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 4 */
I2S_IRQn = 128, /**< 128 SAME54N20A Inter-IC Sound Interface (I2S) */ PCC_IRQn = 129, /**< 129 SAME54N20A Parallel Capture Controller (PCC) */ AES_IRQn = 130, /**< 130 SAME54N20A Advanced Encryption Standard (AES) */ diff --git a/sysmoOCTSIM/include/same54p19a.h b/sysmoOCTSIM/include/same54p19a.h index 6e13002..931adcf 100644 --- a/sysmoOCTSIM/include/same54p19a.h +++ b/sysmoOCTSIM/include/same54p19a.h @@ -3,7 +3,7 @@ * * \brief Header file for SAME54P19A * - * Copyright (c) 2018 Microchip Technology Inc. + * Copyright (c) 2019 Microchip Technology Inc.
* * \asf_license_start * @@ -103,108 +103,108 @@ typedef enum IRQn /****** SAME54P19A-specific Interrupt Numbers *********************/ PM_IRQn = 0, /**< 0 SAME54P19A Power Manager (PM) */ MCLK_IRQn = 1, /**< 1 SAME54P19A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAME54P19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAME54P19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAME54P19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAME54P19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAME54P19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSCCTRL_0_IRQn = 2, /**< 2 SAME54P19A Oscillators Control (OSCCTRL) IRQ 0 */
+ OSCCTRL_1_IRQn = 3, /**< 3 SAME54P19A Oscillators Control (OSCCTRL) IRQ 1 */
+ OSCCTRL_2_IRQn = 4, /**< 4 SAME54P19A Oscillators Control (OSCCTRL) IRQ 2 */
+ OSCCTRL_3_IRQn = 5, /**< 5 SAME54P19A Oscillators Control (OSCCTRL) IRQ 3 */
+ OSCCTRL_4_IRQn = 6, /**< 6 SAME54P19A Oscillators Control (OSCCTRL) IRQ 4 */
OSC32KCTRL_IRQn = 7, /**< 7 SAME54P19A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAME54P19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAME54P19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + SUPC_0_IRQn = 8, /**< 8 SAME54P19A Supply Controller (SUPC) IRQ 0 */
+ SUPC_1_IRQn = 9, /**< 9 SAME54P19A Supply Controller (SUPC) IRQ 1 */
WDT_IRQn = 10, /**< 10 SAME54P19A Watchdog Timer (WDT) */ RTC_IRQn = 11, /**< 11 SAME54P19A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAME54P19A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + EIC_0_IRQn = 12, /**< 12 SAME54P19A External Interrupt Controller (EIC) IRQ 0 */
+ EIC_1_IRQn = 13, /**< 13 SAME54P19A External Interrupt Controller (EIC) IRQ 1 */
+ EIC_2_IRQn = 14, /**< 14 SAME54P19A External Interrupt Controller (EIC) IRQ 2 */
+ EIC_3_IRQn = 15, /**< 15 SAME54P19A External Interrupt Controller (EIC) IRQ 3 */
+ EIC_4_IRQn = 16, /**< 16 SAME54P19A External Interrupt Controller (EIC) IRQ 4 */
+ EIC_5_IRQn = 17, /**< 17 SAME54P19A External Interrupt Controller (EIC) IRQ 5 */
+ EIC_6_IRQn = 18, /**< 18 SAME54P19A External Interrupt Controller (EIC) IRQ 6 */
+ EIC_7_IRQn = 19, /**< 19 SAME54P19A External Interrupt Controller (EIC) IRQ 7 */
+ EIC_8_IRQn = 20, /**< 20 SAME54P19A External Interrupt Controller (EIC) IRQ 8 */
+ EIC_9_IRQn = 21, /**< 21 SAME54P19A External Interrupt Controller (EIC) IRQ 9 */
+ EIC_10_IRQn = 22, /**< 22 SAME54P19A External Interrupt Controller (EIC) IRQ 10 */
+ EIC_11_IRQn = 23, /**< 23 SAME54P19A External Interrupt Controller (EIC) IRQ 11 */
+ EIC_12_IRQn = 24, /**< 24 SAME54P19A External Interrupt Controller (EIC) IRQ 12 */
+ EIC_13_IRQn = 25, /**< 25 SAME54P19A External Interrupt Controller (EIC) IRQ 13 */
+ EIC_14_IRQn = 26, /**< 26 SAME54P19A External Interrupt Controller (EIC) IRQ 14 */
+ EIC_15_IRQn = 27, /**< 27 SAME54P19A External Interrupt Controller (EIC) IRQ 15 */
FREQM_IRQn = 28, /**< 28 SAME54P19A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAME54P19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAME54P19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAME54P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAME54P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAME54P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAME54P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAME54P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAME54P19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAME54P19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAME54P19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAME54P19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAME54P19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + NVMCTRL_0_IRQn = 29, /**< 29 SAME54P19A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */
+ NVMCTRL_1_IRQn = 30, /**< 30 SAME54P19A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */
+ DMAC_0_IRQn = 31, /**< 31 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 0 */
+ DMAC_1_IRQn = 32, /**< 32 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 1 */
+ DMAC_2_IRQn = 33, /**< 33 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 2 */
+ DMAC_3_IRQn = 34, /**< 34 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 3 */
+ DMAC_4_IRQn = 35, /**< 35 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 4 */
+ EVSYS_0_IRQn = 36, /**< 36 SAME54P19A Event System Interface (EVSYS) IRQ 0 */
+ EVSYS_1_IRQn = 37, /**< 37 SAME54P19A Event System Interface (EVSYS) IRQ 1 */
+ EVSYS_2_IRQn = 38, /**< 38 SAME54P19A Event System Interface (EVSYS) IRQ 2 */
+ EVSYS_3_IRQn = 39, /**< 39 SAME54P19A Event System Interface (EVSYS) IRQ 3 */
+ EVSYS_4_IRQn = 40, /**< 40 SAME54P19A Event System Interface (EVSYS) IRQ 4 */
PAC_IRQn = 41, /**< 41 SAME54P19A Peripheral Access Controller (PAC) */ RAMECC_IRQn = 45, /**< 45 SAME54P19A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAME54P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAME54P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAME54P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAME54P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAME54P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAME54P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAME54P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAME54P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAME54P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAME54P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAME54P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAME54P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAME54P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAME54P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAME54P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAME54P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAME54P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAME54P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAME54P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAME54P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAME54P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAME54P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAME54P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAME54P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - SERCOM6_0_IRQn = 70, /**< 70 SAME54P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ - SERCOM6_1_IRQn = 71, /**< 71 SAME54P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ - SERCOM6_2_IRQn = 72, /**< 72 SAME54P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ - SERCOM6_3_IRQn = 73, /**< 73 SAME54P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ - SERCOM7_0_IRQn = 74, /**< 74 SAME54P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ - SERCOM7_1_IRQn = 75, /**< 75 SAME54P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ - SERCOM7_2_IRQn = 76, /**< 76 SAME54P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ - SERCOM7_3_IRQn = 77, /**< 77 SAME54P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ + SERCOM0_0_IRQn = 46, /**< 46 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 0 */
+ SERCOM0_1_IRQn = 47, /**< 47 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 1 */
+ SERCOM0_2_IRQn = 48, /**< 48 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 2 */
+ SERCOM0_3_IRQn = 49, /**< 49 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 3 */
+ SERCOM1_0_IRQn = 50, /**< 50 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 0 */
+ SERCOM1_1_IRQn = 51, /**< 51 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 1 */
+ SERCOM1_2_IRQn = 52, /**< 52 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 2 */
+ SERCOM1_3_IRQn = 53, /**< 53 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 3 */
+ SERCOM2_0_IRQn = 54, /**< 54 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 0 */
+ SERCOM2_1_IRQn = 55, /**< 55 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 1 */
+ SERCOM2_2_IRQn = 56, /**< 56 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 2 */
+ SERCOM2_3_IRQn = 57, /**< 57 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 3 */
+ SERCOM3_0_IRQn = 58, /**< 58 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 0 */
+ SERCOM3_1_IRQn = 59, /**< 59 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 1 */
+ SERCOM3_2_IRQn = 60, /**< 60 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 2 */
+ SERCOM3_3_IRQn = 61, /**< 61 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 3 */
+ SERCOM4_0_IRQn = 62, /**< 62 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 0 */
+ SERCOM4_1_IRQn = 63, /**< 63 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 1 */
+ SERCOM4_2_IRQn = 64, /**< 64 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 2 */
+ SERCOM4_3_IRQn = 65, /**< 65 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 3 */
+ SERCOM5_0_IRQn = 66, /**< 66 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 0 */
+ SERCOM5_1_IRQn = 67, /**< 67 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 1 */
+ SERCOM5_2_IRQn = 68, /**< 68 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 2 */
+ SERCOM5_3_IRQn = 69, /**< 69 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 3 */
+ SERCOM6_0_IRQn = 70, /**< 70 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 0 */
+ SERCOM6_1_IRQn = 71, /**< 71 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 1 */
+ SERCOM6_2_IRQn = 72, /**< 72 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 2 */
+ SERCOM6_3_IRQn = 73, /**< 73 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 3 */
+ SERCOM7_0_IRQn = 74, /**< 74 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 0 */
+ SERCOM7_1_IRQn = 75, /**< 75 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 1 */
+ SERCOM7_2_IRQn = 76, /**< 76 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 2 */
+ SERCOM7_3_IRQn = 77, /**< 77 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 3 */
CAN0_IRQn = 78, /**< 78 SAME54P19A Control Area Network 0 (CAN0) */ CAN1_IRQn = 79, /**< 79 SAME54P19A Control Area Network 1 (CAN1) */ - USB_0_IRQn = 80, /**< 80 SAME54P19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAME54P19A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAME54P19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAME54P19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + USB_0_IRQn = 80, /**< 80 SAME54P19A Universal Serial Bus (USB) IRQ 0 */
+ USB_1_IRQn = 81, /**< 81 SAME54P19A Universal Serial Bus (USB) IRQ 1 */
+ USB_2_IRQn = 82, /**< 82 SAME54P19A Universal Serial Bus (USB) IRQ 2 */
+ USB_3_IRQn = 83, /**< 83 SAME54P19A Universal Serial Bus (USB) IRQ 3 */
GMAC_IRQn = 84, /**< 84 SAME54P19A Ethernet MAC (GMAC) */ - TCC0_0_IRQn = 85, /**< 85 SAME54P19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAME54P19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAME54P19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAME54P19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAME54P19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAME54P19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAME54P19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAME54P19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAME54P19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAME54P19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAME54P19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAME54P19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAME54P19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAME54P19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAME54P19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAME54P19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TCC3_0_IRQn = 101, /**< 101 SAME54P19A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - TCC3_1_IRQn = 102, /**< 102 SAME54P19A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ - TCC3_2_IRQn = 103, /**< 103 SAME54P19A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ - TCC4_0_IRQn = 104, /**< 104 SAME54P19A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - TCC4_1_IRQn = 105, /**< 105 SAME54P19A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ - TCC4_2_IRQn = 106, /**< 106 SAME54P19A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ + TCC0_0_IRQn = 85, /**< 85 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 0 */
+ TCC0_1_IRQn = 86, /**< 86 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 1 */
+ TCC0_2_IRQn = 87, /**< 87 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 2 */
+ TCC0_3_IRQn = 88, /**< 88 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 3 */
+ TCC0_4_IRQn = 89, /**< 89 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 4 */
+ TCC0_5_IRQn = 90, /**< 90 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 5 */
+ TCC0_6_IRQn = 91, /**< 91 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 6 */
+ TCC1_0_IRQn = 92, /**< 92 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 0 */
+ TCC1_1_IRQn = 93, /**< 93 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 1 */
+ TCC1_2_IRQn = 94, /**< 94 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 2 */
+ TCC1_3_IRQn = 95, /**< 95 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 3 */
+ TCC1_4_IRQn = 96, /**< 96 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 4 */
+ TCC2_0_IRQn = 97, /**< 97 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 0 */
+ TCC2_1_IRQn = 98, /**< 98 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 1 */
+ TCC2_2_IRQn = 99, /**< 99 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 2 */
+ TCC2_3_IRQn = 100, /**< 100 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 3 */
+ TCC3_0_IRQn = 101, /**< 101 SAME54P19A Timer Counter Control 3 (TCC3) IRQ 0 */
+ TCC3_1_IRQn = 102, /**< 102 SAME54P19A Timer Counter Control 3 (TCC3) IRQ 1 */
+ TCC3_2_IRQn = 103, /**< 103 SAME54P19A Timer Counter Control 3 (TCC3) IRQ 2 */
+ TCC4_0_IRQn = 104, /**< 104 SAME54P19A Timer Counter Control 4 (TCC4) IRQ 0 */
+ TCC4_1_IRQn = 105, /**< 105 SAME54P19A Timer Counter Control 4 (TCC4) IRQ 1 */
+ TCC4_2_IRQn = 106, /**< 106 SAME54P19A Timer Counter Control 4 (TCC4) IRQ 2 */
TC0_IRQn = 107, /**< 107 SAME54P19A Basic Timer Counter 0 (TC0) */ TC1_IRQn = 108, /**< 108 SAME54P19A Basic Timer Counter 1 (TC1) */ TC2_IRQn = 109, /**< 109 SAME54P19A Basic Timer Counter 2 (TC2) */ @@ -213,19 +213,19 @@ typedef enum IRQn TC5_IRQn = 112, /**< 112 SAME54P19A Basic Timer Counter 5 (TC5) */ TC6_IRQn = 113, /**< 113 SAME54P19A Basic Timer Counter 6 (TC6) */ TC7_IRQn = 114, /**< 114 SAME54P19A Basic Timer Counter 7 (TC7) */ - PDEC_0_IRQn = 115, /**< 115 SAME54P19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAME54P19A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAME54P19A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAME54P19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAME54P19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAME54P19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAME54P19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + PDEC_0_IRQn = 115, /**< 115 SAME54P19A Quadrature Decodeur (PDEC) IRQ 0 */
+ PDEC_1_IRQn = 116, /**< 116 SAME54P19A Quadrature Decodeur (PDEC) IRQ 1 */
+ PDEC_2_IRQn = 117, /**< 117 SAME54P19A Quadrature Decodeur (PDEC) IRQ 2 */
+ ADC0_0_IRQn = 118, /**< 118 SAME54P19A Analog Digital Converter 0 (ADC0) IRQ 0 */
+ ADC0_1_IRQn = 119, /**< 119 SAME54P19A Analog Digital Converter 0 (ADC0) IRQ 1 */
+ ADC1_0_IRQn = 120, /**< 120 SAME54P19A Analog Digital Converter 1 (ADC1) IRQ 0 */
+ ADC1_1_IRQn = 121, /**< 121 SAME54P19A Analog Digital Converter 1 (ADC1) IRQ 1 */
AC_IRQn = 122, /**< 122 SAME54P19A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAME54P19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAME54P19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAME54P19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAME54P19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAME54P19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + DAC_0_IRQn = 123, /**< 123 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 0 */
+ DAC_1_IRQn = 124, /**< 124 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 1 */
+ DAC_2_IRQn = 125, /**< 125 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 2 */
+ DAC_3_IRQn = 126, /**< 126 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 3 */
+ DAC_4_IRQn = 127, /**< 127 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 4 */
I2S_IRQn = 128, /**< 128 SAME54P19A Inter-IC Sound Interface (I2S) */ PCC_IRQn = 129, /**< 129 SAME54P19A Parallel Capture Controller (PCC) */ AES_IRQn = 130, /**< 130 SAME54P19A Advanced Encryption Standard (AES) */ diff --git a/sysmoOCTSIM/include/same54p20a.h b/sysmoOCTSIM/include/same54p20a.h index 99ce6f3..fcf1f9b 100644 --- a/sysmoOCTSIM/include/same54p20a.h +++ b/sysmoOCTSIM/include/same54p20a.h @@ -3,7 +3,7 @@ * * \brief Header file for SAME54P20A * - * Copyright (c) 2018 Microchip Technology Inc. + * Copyright (c) 2019 Microchip Technology Inc.
* * \asf_license_start * @@ -103,108 +103,108 @@ typedef enum IRQn /****** SAME54P20A-specific Interrupt Numbers *********************/ PM_IRQn = 0, /**< 0 SAME54P20A Power Manager (PM) */ MCLK_IRQn = 1, /**< 1 SAME54P20A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAME54P20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAME54P20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAME54P20A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAME54P20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAME54P20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSCCTRL_0_IRQn = 2, /**< 2 SAME54P20A Oscillators Control (OSCCTRL) IRQ 0 */
+ OSCCTRL_1_IRQn = 3, /**< 3 SAME54P20A Oscillators Control (OSCCTRL) IRQ 1 */
+ OSCCTRL_2_IRQn = 4, /**< 4 SAME54P20A Oscillators Control (OSCCTRL) IRQ 2 */
+ OSCCTRL_3_IRQn = 5, /**< 5 SAME54P20A Oscillators Control (OSCCTRL) IRQ 3 */
+ OSCCTRL_4_IRQn = 6, /**< 6 SAME54P20A Oscillators Control (OSCCTRL) IRQ 4 */
OSC32KCTRL_IRQn = 7, /**< 7 SAME54P20A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAME54P20A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAME54P20A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + SUPC_0_IRQn = 8, /**< 8 SAME54P20A Supply Controller (SUPC) IRQ 0 */
+ SUPC_1_IRQn = 9, /**< 9 SAME54P20A Supply Controller (SUPC) IRQ 1 */
WDT_IRQn = 10, /**< 10 SAME54P20A Watchdog Timer (WDT) */ RTC_IRQn = 11, /**< 11 SAME54P20A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAME54P20A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + EIC_0_IRQn = 12, /**< 12 SAME54P20A External Interrupt Controller (EIC) IRQ 0 */
+ EIC_1_IRQn = 13, /**< 13 SAME54P20A External Interrupt Controller (EIC) IRQ 1 */
+ EIC_2_IRQn = 14, /**< 14 SAME54P20A External Interrupt Controller (EIC) IRQ 2 */
+ EIC_3_IRQn = 15, /**< 15 SAME54P20A External Interrupt Controller (EIC) IRQ 3 */
+ EIC_4_IRQn = 16, /**< 16 SAME54P20A External Interrupt Controller (EIC) IRQ 4 */
+ EIC_5_IRQn = 17, /**< 17 SAME54P20A External Interrupt Controller (EIC) IRQ 5 */
+ EIC_6_IRQn = 18, /**< 18 SAME54P20A External Interrupt Controller (EIC) IRQ 6 */
+ EIC_7_IRQn = 19, /**< 19 SAME54P20A External Interrupt Controller (EIC) IRQ 7 */
+ EIC_8_IRQn = 20, /**< 20 SAME54P20A External Interrupt Controller (EIC) IRQ 8 */
+ EIC_9_IRQn = 21, /**< 21 SAME54P20A External Interrupt Controller (EIC) IRQ 9 */
+ EIC_10_IRQn = 22, /**< 22 SAME54P20A External Interrupt Controller (EIC) IRQ 10 */
+ EIC_11_IRQn = 23, /**< 23 SAME54P20A External Interrupt Controller (EIC) IRQ 11 */
+ EIC_12_IRQn = 24, /**< 24 SAME54P20A External Interrupt Controller (EIC) IRQ 12 */
+ EIC_13_IRQn = 25, /**< 25 SAME54P20A External Interrupt Controller (EIC) IRQ 13 */
+ EIC_14_IRQn = 26, /**< 26 SAME54P20A External Interrupt Controller (EIC) IRQ 14 */
+ EIC_15_IRQn = 27, /**< 27 SAME54P20A External Interrupt Controller (EIC) IRQ 15 */
FREQM_IRQn = 28, /**< 28 SAME54P20A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAME54P20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAME54P20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAME54P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAME54P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAME54P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAME54P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAME54P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAME54P20A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAME54P20A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAME54P20A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAME54P20A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAME54P20A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + NVMCTRL_0_IRQn = 29, /**< 29 SAME54P20A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */
+ NVMCTRL_1_IRQn = 30, /**< 30 SAME54P20A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */
+ DMAC_0_IRQn = 31, /**< 31 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 0 */
+ DMAC_1_IRQn = 32, /**< 32 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 1 */
+ DMAC_2_IRQn = 33, /**< 33 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 2 */
+ DMAC_3_IRQn = 34, /**< 34 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 3 */
+ DMAC_4_IRQn = 35, /**< 35 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 4 */
+ EVSYS_0_IRQn = 36, /**< 36 SAME54P20A Event System Interface (EVSYS) IRQ 0 */
+ EVSYS_1_IRQn = 37, /**< 37 SAME54P20A Event System Interface (EVSYS) IRQ 1 */
+ EVSYS_2_IRQn = 38, /**< 38 SAME54P20A Event System Interface (EVSYS) IRQ 2 */
+ EVSYS_3_IRQn = 39, /**< 39 SAME54P20A Event System Interface (EVSYS) IRQ 3 */
+ EVSYS_4_IRQn = 40, /**< 40 SAME54P20A Event System Interface (EVSYS) IRQ 4 */
PAC_IRQn = 41, /**< 41 SAME54P20A Peripheral Access Controller (PAC) */ RAMECC_IRQn = 45, /**< 45 SAME54P20A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAME54P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAME54P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAME54P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAME54P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAME54P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAME54P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAME54P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAME54P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAME54P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAME54P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAME54P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAME54P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAME54P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAME54P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAME54P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAME54P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAME54P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAME54P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAME54P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAME54P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAME54P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAME54P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAME54P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAME54P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - SERCOM6_0_IRQn = 70, /**< 70 SAME54P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ - SERCOM6_1_IRQn = 71, /**< 71 SAME54P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ - SERCOM6_2_IRQn = 72, /**< 72 SAME54P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ - SERCOM6_3_IRQn = 73, /**< 73 SAME54P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ - SERCOM7_0_IRQn = 74, /**< 74 SAME54P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ - SERCOM7_1_IRQn = 75, /**< 75 SAME54P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ - SERCOM7_2_IRQn = 76, /**< 76 SAME54P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ - SERCOM7_3_IRQn = 77, /**< 77 SAME54P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ + SERCOM0_0_IRQn = 46, /**< 46 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 0 */
+ SERCOM0_1_IRQn = 47, /**< 47 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 1 */
+ SERCOM0_2_IRQn = 48, /**< 48 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 2 */
+ SERCOM0_3_IRQn = 49, /**< 49 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 3 */
+ SERCOM1_0_IRQn = 50, /**< 50 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 0 */
+ SERCOM1_1_IRQn = 51, /**< 51 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 1 */
+ SERCOM1_2_IRQn = 52, /**< 52 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 2 */
+ SERCOM1_3_IRQn = 53, /**< 53 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 3 */
+ SERCOM2_0_IRQn = 54, /**< 54 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 0 */
+ SERCOM2_1_IRQn = 55, /**< 55 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 1 */
+ SERCOM2_2_IRQn = 56, /**< 56 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 2 */
+ SERCOM2_3_IRQn = 57, /**< 57 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 3 */
+ SERCOM3_0_IRQn = 58, /**< 58 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 0 */
+ SERCOM3_1_IRQn = 59, /**< 59 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 1 */
+ SERCOM3_2_IRQn = 60, /**< 60 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 2 */
+ SERCOM3_3_IRQn = 61, /**< 61 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 3 */
+ SERCOM4_0_IRQn = 62, /**< 62 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 0 */
+ SERCOM4_1_IRQn = 63, /**< 63 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 1 */
+ SERCOM4_2_IRQn = 64, /**< 64 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 2 */
+ SERCOM4_3_IRQn = 65, /**< 65 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 3 */
+ SERCOM5_0_IRQn = 66, /**< 66 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 0 */
+ SERCOM5_1_IRQn = 67, /**< 67 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 1 */
+ SERCOM5_2_IRQn = 68, /**< 68 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 2 */
+ SERCOM5_3_IRQn = 69, /**< 69 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 3 */
+ SERCOM6_0_IRQn = 70, /**< 70 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 0 */
+ SERCOM6_1_IRQn = 71, /**< 71 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 1 */
+ SERCOM6_2_IRQn = 72, /**< 72 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 2 */
+ SERCOM6_3_IRQn = 73, /**< 73 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 3 */
+ SERCOM7_0_IRQn = 74, /**< 74 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 0 */
+ SERCOM7_1_IRQn = 75, /**< 75 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 1 */
+ SERCOM7_2_IRQn = 76, /**< 76 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 2 */
+ SERCOM7_3_IRQn = 77, /**< 77 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 3 */
CAN0_IRQn = 78, /**< 78 SAME54P20A Control Area Network 0 (CAN0) */ CAN1_IRQn = 79, /**< 79 SAME54P20A Control Area Network 1 (CAN1) */ - USB_0_IRQn = 80, /**< 80 SAME54P20A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAME54P20A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAME54P20A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAME54P20A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + USB_0_IRQn = 80, /**< 80 SAME54P20A Universal Serial Bus (USB) IRQ 0 */
+ USB_1_IRQn = 81, /**< 81 SAME54P20A Universal Serial Bus (USB) IRQ 1 */
+ USB_2_IRQn = 82, /**< 82 SAME54P20A Universal Serial Bus (USB) IRQ 2 */
+ USB_3_IRQn = 83, /**< 83 SAME54P20A Universal Serial Bus (USB) IRQ 3 */
GMAC_IRQn = 84, /**< 84 SAME54P20A Ethernet MAC (GMAC) */ - TCC0_0_IRQn = 85, /**< 85 SAME54P20A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAME54P20A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAME54P20A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAME54P20A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAME54P20A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAME54P20A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAME54P20A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAME54P20A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAME54P20A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAME54P20A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAME54P20A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAME54P20A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAME54P20A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAME54P20A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAME54P20A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAME54P20A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TCC3_0_IRQn = 101, /**< 101 SAME54P20A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - TCC3_1_IRQn = 102, /**< 102 SAME54P20A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ - TCC3_2_IRQn = 103, /**< 103 SAME54P20A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ - TCC4_0_IRQn = 104, /**< 104 SAME54P20A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - TCC4_1_IRQn = 105, /**< 105 SAME54P20A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ - TCC4_2_IRQn = 106, /**< 106 SAME54P20A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ + TCC0_0_IRQn = 85, /**< 85 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 0 */
+ TCC0_1_IRQn = 86, /**< 86 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 1 */
+ TCC0_2_IRQn = 87, /**< 87 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 2 */
+ TCC0_3_IRQn = 88, /**< 88 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 3 */
+ TCC0_4_IRQn = 89, /**< 89 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 4 */
+ TCC0_5_IRQn = 90, /**< 90 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 5 */
+ TCC0_6_IRQn = 91, /**< 91 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 6 */
+ TCC1_0_IRQn = 92, /**< 92 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 0 */
+ TCC1_1_IRQn = 93, /**< 93 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 1 */
+ TCC1_2_IRQn = 94, /**< 94 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 2 */
+ TCC1_3_IRQn = 95, /**< 95 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 3 */
+ TCC1_4_IRQn = 96, /**< 96 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 4 */
+ TCC2_0_IRQn = 97, /**< 97 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 0 */
+ TCC2_1_IRQn = 98, /**< 98 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 1 */
+ TCC2_2_IRQn = 99, /**< 99 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 2 */
+ TCC2_3_IRQn = 100, /**< 100 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 3 */
+ TCC3_0_IRQn = 101, /**< 101 SAME54P20A Timer Counter Control 3 (TCC3) IRQ 0 */
+ TCC3_1_IRQn = 102, /**< 102 SAME54P20A Timer Counter Control 3 (TCC3) IRQ 1 */
+ TCC3_2_IRQn = 103, /**< 103 SAME54P20A Timer Counter Control 3 (TCC3) IRQ 2 */
+ TCC4_0_IRQn = 104, /**< 104 SAME54P20A Timer Counter Control 4 (TCC4) IRQ 0 */
+ TCC4_1_IRQn = 105, /**< 105 SAME54P20A Timer Counter Control 4 (TCC4) IRQ 1 */
+ TCC4_2_IRQn = 106, /**< 106 SAME54P20A Timer Counter Control 4 (TCC4) IRQ 2 */
TC0_IRQn = 107, /**< 107 SAME54P20A Basic Timer Counter 0 (TC0) */ TC1_IRQn = 108, /**< 108 SAME54P20A Basic Timer Counter 1 (TC1) */ TC2_IRQn = 109, /**< 109 SAME54P20A Basic Timer Counter 2 (TC2) */ @@ -213,19 +213,19 @@ typedef enum IRQn TC5_IRQn = 112, /**< 112 SAME54P20A Basic Timer Counter 5 (TC5) */ TC6_IRQn = 113, /**< 113 SAME54P20A Basic Timer Counter 6 (TC6) */ TC7_IRQn = 114, /**< 114 SAME54P20A Basic Timer Counter 7 (TC7) */ - PDEC_0_IRQn = 115, /**< 115 SAME54P20A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAME54P20A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAME54P20A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAME54P20A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAME54P20A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAME54P20A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAME54P20A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + PDEC_0_IRQn = 115, /**< 115 SAME54P20A Quadrature Decodeur (PDEC) IRQ 0 */
+ PDEC_1_IRQn = 116, /**< 116 SAME54P20A Quadrature Decodeur (PDEC) IRQ 1 */
+ PDEC_2_IRQn = 117, /**< 117 SAME54P20A Quadrature Decodeur (PDEC) IRQ 2 */
+ ADC0_0_IRQn = 118, /**< 118 SAME54P20A Analog Digital Converter 0 (ADC0) IRQ 0 */
+ ADC0_1_IRQn = 119, /**< 119 SAME54P20A Analog Digital Converter 0 (ADC0) IRQ 1 */
+ ADC1_0_IRQn = 120, /**< 120 SAME54P20A Analog Digital Converter 1 (ADC1) IRQ 0 */
+ ADC1_1_IRQn = 121, /**< 121 SAME54P20A Analog Digital Converter 1 (ADC1) IRQ 1 */
AC_IRQn = 122, /**< 122 SAME54P20A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAME54P20A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAME54P20A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAME54P20A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAME54P20A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAME54P20A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + DAC_0_IRQn = 123, /**< 123 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 0 */
+ DAC_1_IRQn = 124, /**< 124 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 1 */
+ DAC_2_IRQn = 125, /**< 125 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 2 */
+ DAC_3_IRQn = 126, /**< 126 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 3 */
+ DAC_4_IRQn = 127, /**< 127 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 4 */
I2S_IRQn = 128, /**< 128 SAME54P20A Inter-IC Sound Interface (I2S) */ PCC_IRQn = 129, /**< 129 SAME54P20A Parallel Capture Controller (PCC) */ AES_IRQn = 130, /**< 130 SAME54P20A Advanced Encryption Standard (AES) */ |