1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
|
/**
* \file
*
* \brief Generic CMCC(Cortex M Cache Controller) related functionality.
*
* Copyright (c)2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include <compiler.h>
#include <hpl_cmcc.h>
#include <hpl_cmcc_config.h>
/**
* \brief Initialize Cache Module
*
* This function does low level cache configuration.
*
* \return initialize status
*/
int32_t _cmcc_init(void)
{
int32_t return_value;
_cmcc_disable(CMCC);
if (_is_cache_disabled(CMCC)) {
hri_cmcc_write_CFG_reg(
CMCC,
(CMCC_CFG_CSIZESW(CONF_CMCC_CACHE_SIZE) | (CONF_CMCC_DATA_CACHE_DISABLE << CMCC_CFG_DCDIS_Pos)
| (CONF_CMCC_INST_CACHE_DISABLE << CMCC_CFG_ICDIS_Pos) | (CONF_CMCC_CLK_GATING_DISABLE)));
_cmcc_enable(CMCC);
return_value = _is_cache_enabled(CMCC) == true ? ERR_NONE : ERR_FAILURE;
} else {
return_value = ERR_NOT_INITIALIZED;
}
return return_value;
}
/**
* \brief Configure CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] cache configuration structure pointer
*
* \return status of operation
*/
int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl)
{
int32_t return_value;
_cmcc_disable(hw);
if (_is_cache_disabled(hw)) {
hri_cmcc_write_CFG_reg(
hw,
(CMCC_CFG_CSIZESW(cache_ctrl->cache_size) | (cache_ctrl->data_cache_disable << CMCC_CFG_DCDIS_Pos)
| (cache_ctrl->inst_cache_disable << CMCC_CFG_ICDIS_Pos) | (cache_ctrl->gclk_gate_disable)));
return_value = ERR_NONE;
} else {
return_value = ERR_NOT_INITIALIZED;
}
return return_value;
}
/**
* \brief Enable data cache in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache
*
* \return status of operation
*/
int32_t _cmcc_enable_data_cache(const void *hw, bool value)
{
uint32_t tmp;
int32_t ret;
tmp = hri_cmcc_read_CFG_reg(hw);
tmp &= ~CMCC_CFG_DCDIS;
tmp |= ((!value) << CMCC_CFG_DCDIS_Pos);
ret = _cmcc_disable(hw);
hri_cmcc_write_CFG_reg(hw, tmp);
ret = _cmcc_enable(hw);
return ret;
}
/**
* \brief Enable instruction cache in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache
*
* \return status of operation
*/
int32_t _cmcc_enable_inst_cache(const void *hw, bool value)
{
uint32_t tmp;
int32_t ret;
tmp = hri_cmcc_read_CFG_reg(hw);
tmp &= ~CMCC_CFG_ICDIS;
tmp |= ((!value) << CMCC_CFG_ICDIS_Pos);
ret = _cmcc_disable(hw);
hri_cmcc_write_CFG_reg(hw, tmp);
ret = _cmcc_enable(hw);
return ret;
}
/**
* \brief Enable clock gating in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate
*
* \return status of operation
*/
int32_t _cmcc_enable_clock_gating(const void *hw, bool value)
{
uint32_t tmp;
int32_t ret;
tmp = hri_cmcc_read_CFG_reg(hw);
tmp |= value;
ret = _cmcc_disable(hw);
hri_cmcc_write_CFG_reg(hw, tmp);
ret = _cmcc_enable(hw);
return ret;
}
/**
* \brief Configure the cache size in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from cache size configuration enumerator
* 0->1K, 1->2K, 2->4K(default)
*
* \return status of operation
*/
int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size)
{
uint32_t tmp;
int32_t ret;
tmp = hri_cmcc_read_CFG_reg(hw);
tmp &= (~CMCC_CFG_CSIZESW_Msk);
tmp |= (size << CMCC_CFG_CSIZESW_Pos);
ret = _cmcc_disable(hw);
hri_cmcc_write_CFG_reg(hw, tmp);
ret = _cmcc_enable(hw);
return ret;
}
/**
* \brief Lock the mentioned WAY in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from "way_num_index" enumerator
*
* \return status of operation
*/
int32_t _cmcc_lock_way(const void *hw, enum way_num_index num)
{
uint32_t tmp;
int32_t ret;
tmp = hri_cmcc_read_LCKWAY_reg(hw);
tmp |= CMCC_LCKWAY_LCKWAY(num);
ret = _cmcc_disable(hw);
hri_cmcc_write_LCKWAY_reg(hw, tmp);
ret = _cmcc_enable(hw);
return ret;
}
/**
* \brief Unlock the mentioned WAY in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from "way_num_index" enumerator
*
* \return status of operation
*/
int32_t _cmcc_unlock_way(const void *hw, enum way_num_index num)
{
uint32_t tmp;
int32_t ret;
tmp = hri_cmcc_read_LCKWAY_reg(hw);
tmp &= (~CMCC_LCKWAY_LCKWAY(num));
ret = _cmcc_disable(hw);
hri_cmcc_write_LCKWAY_reg(hw, tmp);
ret = _cmcc_enable(hw);
return ret;
}
/**
* \brief Invalidate the mentioned cache line in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from "way_num" enumerator (valid arg is 0-3)
* \param[in] line number (valid arg is 0-63 as each way will have 64 lines)
*
* \return status of operation
*/
int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num)
{
int32_t return_value;
if ((way_num < CMCC_WAY_NOS) && (line_num < CMCC_LINE_NOS)) {
_cmcc_disable(hw);
while (!(_is_cache_disabled(hw)))
;
hri_cmcc_write_MAINT1_reg(hw, (CMCC_MAINT1_INDEX(line_num) | CMCC_MAINT1_WAY(way_num)));
return_value = ERR_NONE;
} else {
return_value = ERR_INVALID_ARG;
}
return return_value;
}
/**
* \brief Invalidate entire cache entries in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_invalidate_all(const void *hw)
{
int32_t return_value;
_cmcc_disable(hw);
if (_is_cache_disabled(hw)) {
hri_cmcc_write_MAINT0_reg(hw, CMCC_MAINT0_INVALL);
return_value = ERR_NONE;
} else {
return_value = ERR_FAILURE;
}
return return_value;
}
/**
* \brief Configure cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
* \param[in] element from cache monitor configurations enumerator
*
* \return status of operation
*/
int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg)
{
hri_cmcc_write_MCFG_reg(hw, CMCC_MCFG_MODE(monitor_cfg));
return ERR_NONE;
}
/**
* \brief Enable cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_enable_monitor(const void *hw)
{
hri_cmcc_write_MEN_reg(hw, CMCC_MEN_MENABLE);
return ERR_NONE;
}
/**
* \brief Disable cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_disable_monitor(const void *hw)
{
hri_cmcc_write_MEN_reg(hw, (CMCC_MONITOR_DISABLE << CMCC_MEN_MENABLE_Pos));
return ERR_NONE;
}
/**
* \brief Reset cache monitor in CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return status of operation
*/
int32_t _cmcc_reset_monitor(const void *hw)
{
hri_cmcc_write_MCTRL_reg(hw, CMCC_MCTRL_SWRST);
return ERR_NONE;
}
/**
* \brief Get cache monitor event counter value from CMCC module
*
* \param[in] pointer pointing to the starting address of CMCC module
*
* \return event counter value
*/
uint32_t _cmcc_get_monitor_event_count(const void *hw)
{
return hri_cmcc_read_MSR_reg(hw);
}
|
