use USB CDC Echo example project

this is the USB CDC Echo example project source code,
for the Microchip SAM E54 Xplained Pro development board,
based on the ATSAME54P20A micro-controller,
exported from the Atmel START website,
using the ASFv4 library.

Change-Id: Ic0e58e42d1a4076bc84a0a8d3509ec4b09a37f46

43 files changed, 122877 insertions, 0 deletions

diff --git a/hri/hri_ac_e54.h b/hri/hri_ac_e54.h
new file mode 100644
index 0000000..588499e
--- /dev/null
+++ b/hri/hri_ac_e54.h
@@ -0,0 +1,1836 @@
+/**
+ * \file
+ *
+ * \brief SAM AC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_AC_COMPONENT_
+#ifndef _HRI_AC_E54_H_INCLUDED_
+#define _HRI_AC_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_AC_CRITICAL_SECTIONS)
+#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define AC_CRITICAL_SECTION_ENTER()
+#define AC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_ac_calib_reg_t;
+typedef uint16_t hri_ac_evctrl_reg_t;
+typedef uint32_t hri_ac_compctrl_reg_t;
+typedef uint32_t hri_ac_syncbusy_reg_t;
+typedef uint8_t  hri_ac_ctrla_reg_t;
+typedef uint8_t  hri_ac_ctrlb_reg_t;
+typedef uint8_t  hri_ac_dbgctrl_reg_t;
+typedef uint8_t  hri_ac_intenset_reg_t;
+typedef uint8_t  hri_ac_intflag_reg_t;
+typedef uint8_t  hri_ac_scaler_reg_t;
+typedef uint8_t  hri_ac_statusa_reg_t;
+typedef uint8_t  hri_ac_statusb_reg_t;
+typedef uint8_t  hri_ac_winctrl_reg_t;
+
+static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg)
+{
+	while (((Ac *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg)
+{
+	return ((Ac *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos;
+}
+
+static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0;
+}
+
+static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos;
+}
+
+static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1;
+}
+
+static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos;
+}
+
+static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0;
+}
+
+static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos;
+}
+
+static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0;
+}
+
+static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos;
+}
+
+static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1;
+}
+
+static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos;
+}
+
+static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0;
+}
+
+static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Ac *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask)
+{
+	((Ac *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0;
+}
+
+static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos;
+}
+
+static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0;
+	} else {
+		((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0;
+	}
+}
+
+static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0;
+}
+
+static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1;
+}
+
+static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos;
+}
+
+static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1;
+	} else {
+		((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1;
+	}
+}
+
+static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1;
+}
+
+static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0;
+}
+
+static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos;
+}
+
+static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0;
+	} else {
+		((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0;
+	}
+}
+
+static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0;
+}
+
+static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
+{
+	((Ac *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw)
+{
+	return ((Ac *)hw)->INTENSET.reg;
+}
+
+static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data)
+{
+	((Ac *)hw)->INTENSET.reg = data;
+	((Ac *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
+{
+	((Ac *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos;
+}
+
+static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->STATUSA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw)
+{
+	return ((Ac *)hw)->STATUSA.reg;
+}
+
+static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos;
+}
+
+static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos;
+}
+
+static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->STATUSB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw)
+{
+	return ((Ac *)hw)->STATUSB.reg;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos;
+}
+
+static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Ac *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp &= ~AC_CTRLA_ENABLE;
+	tmp |= value << AC_CTRLA_ENABLE_Pos;
+	((Ac *)hw)->CTRLA.reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg |= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg = data;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg &= ~mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg ^= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw)
+{
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	return ((Ac *)hw)->CTRLA.reg;
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEO0;
+	tmp |= value << AC_EVCTRL_COMPEO0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEO1;
+	tmp |= value << AC_EVCTRL_COMPEO1_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_WINEO0;
+	tmp |= value << AC_EVCTRL_WINEO0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEI0;
+	tmp |= value << AC_EVCTRL_COMPEI0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEI1;
+	tmp |= value << AC_EVCTRL_COMPEI1_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_INVEI0;
+	tmp |= value << AC_EVCTRL_INVEI0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_INVEI1;
+	tmp |= value << AC_EVCTRL_INVEI1_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Ac *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->DBGCTRL.reg;
+	tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->DBGCTRL.reg;
+	tmp &= ~AC_DBGCTRL_DBGRUN;
+	tmp |= value << AC_DBGCTRL_DBGRUN_Pos;
+	((Ac *)hw)->DBGCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Ac *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp &= ~AC_WINCTRL_WEN0;
+	tmp |= value << AC_WINCTRL_WEN0_Pos;
+	((Ac *)hw)->WINCTRL.reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp &= ~AC_WINCTRL_WINTSEL0_Msk;
+	tmp |= AC_WINCTRL_WINTSEL0(data);
+	((Ac *)hw)->WINCTRL.reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg |= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg = data;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg &= ~mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg ^= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw)
+{
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	return ((Ac *)hw)->WINCTRL.reg;
+}
+
+static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index,
+                                                             hri_ac_scaler_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp &= ~AC_SCALER_VALUE_Msk;
+	tmp |= AC_SCALER_VALUE(data);
+	((Ac *)hw)->SCALER[index].reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index)
+{
+	return ((Ac *)hw)->SCALER[index].reg;
+}
+
+static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_ENABLE;
+	tmp |= value << AC_COMPCTRL_ENABLE_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_SINGLE;
+	tmp |= value << AC_COMPCTRL_SINGLE_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_RUNSTDBY;
+	tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_SWAP;
+	tmp |= value << AC_COMPCTRL_SWAP_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_HYSTEN;
+	tmp |= value << AC_COMPCTRL_HYSTEN_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index,
+                                                                  hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_INTSEL_Msk;
+	tmp |= AC_COMPCTRL_INTSEL(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index,
+                                                                  hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_MUXNEG_Msk;
+	tmp |= AC_COMPCTRL_MUXNEG(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index,
+                                                                  hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_MUXPOS_Msk;
+	tmp |= AC_COMPCTRL_MUXPOS(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index,
+                                                                 hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_SPEED_Msk;
+	tmp |= AC_COMPCTRL_SPEED(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_HYST_bf(const void *const hw, uint8_t index,
+                                                                hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_HYST(mask)) >> AC_COMPCTRL_HYST_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_HYST_Msk;
+	tmp |= AC_COMPCTRL_HYST(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_HYST_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_HYST_Msk) >> AC_COMPCTRL_HYST_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index,
+                                                                hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_FLEN_Msk;
+	tmp |= AC_COMPCTRL_FLEN(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index,
+                                                               hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_OUT_Msk;
+	tmp |= AC_COMPCTRL_OUT(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg = data;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index)
+{
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	return ((Ac *)hw)->COMPCTRL[index].reg;
+}
+
+static inline void hri_ac_set_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg |= AC_CALIB_BIAS0(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_calib_reg_t hri_ac_get_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->CALIB.reg;
+	tmp = (tmp & AC_CALIB_BIAS0(mask)) >> AC_CALIB_BIAS0_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t data)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->CALIB.reg;
+	tmp &= ~AC_CALIB_BIAS0_Msk;
+	tmp |= AC_CALIB_BIAS0(data);
+	((Ac *)hw)->CALIB.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg &= ~AC_CALIB_BIAS0(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg ^= AC_CALIB_BIAS0(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_calib_reg_t hri_ac_read_CALIB_BIAS0_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->CALIB.reg;
+	tmp = (tmp & AC_CALIB_BIAS0_Msk) >> AC_CALIB_BIAS0_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_calib_reg_t hri_ac_get_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->CALIB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_CALIB_reg(const void *const hw, hri_ac_calib_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CALIB.reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_calib_reg_t hri_ac_read_CALIB_reg(const void *const hw)
+{
+	return ((Ac *)hw)->CALIB.reg;
+}
+
+static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLB.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_AC_E54_H_INCLUDED */
+#endif /* _SAME54_AC_COMPONENT_ */
diff --git a/hri/hri_adc_e54.h b/hri/hri_adc_e54.h
new file mode 100644
index 0000000..7bb7e6f
--- /dev/null
+++ b/hri/hri_adc_e54.h
@@ -0,0 +1,3663 @@
+/**
+ * \file
+ *
+ * \brief SAM ADC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_ADC_COMPONENT_
+#ifndef _HRI_ADC_E54_H_INCLUDED_
+#define _HRI_ADC_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_ADC_CRITICAL_SECTIONS)
+#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define ADC_CRITICAL_SECTION_ENTER()
+#define ADC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_adc_calib_reg_t;
+typedef uint16_t hri_adc_ctrla_reg_t;
+typedef uint16_t hri_adc_ctrlb_reg_t;
+typedef uint16_t hri_adc_gaincorr_reg_t;
+typedef uint16_t hri_adc_inputctrl_reg_t;
+typedef uint16_t hri_adc_offsetcorr_reg_t;
+typedef uint16_t hri_adc_ress_reg_t;
+typedef uint16_t hri_adc_result_reg_t;
+typedef uint16_t hri_adc_winlt_reg_t;
+typedef uint16_t hri_adc_winut_reg_t;
+typedef uint32_t hri_adc_dseqctrl_reg_t;
+typedef uint32_t hri_adc_dseqdata_reg_t;
+typedef uint32_t hri_adc_dseqstat_reg_t;
+typedef uint32_t hri_adc_syncbusy_reg_t;
+typedef uint8_t  hri_adc_avgctrl_reg_t;
+typedef uint8_t  hri_adc_dbgctrl_reg_t;
+typedef uint8_t  hri_adc_evctrl_reg_t;
+typedef uint8_t  hri_adc_intenset_reg_t;
+typedef uint8_t  hri_adc_intflag_reg_t;
+typedef uint8_t  hri_adc_refctrl_reg_t;
+typedef uint8_t  hri_adc_sampctrl_reg_t;
+typedef uint8_t  hri_adc_status_reg_t;
+typedef uint8_t  hri_adc_swtrig_reg_t;
+
+static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg)
+{
+	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg)
+{
+	return ((Adc *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos;
+}
+
+static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY;
+}
+
+static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos;
+}
+
+static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
+}
+
+static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos;
+}
+
+static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON;
+}
+
+static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos;
+}
+
+static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY;
+}
+
+static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos;
+}
+
+static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
+}
+
+static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos;
+}
+
+static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON;
+}
+
+static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Adc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask)
+{
+	((Adc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY;
+}
+
+static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos;
+}
+
+static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY;
+	} else {
+		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY;
+	}
+}
+
+static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY;
+}
+
+static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN;
+}
+
+static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos;
+}
+
+static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN;
+	} else {
+		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN;
+	}
+}
+
+static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN;
+}
+
+static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON;
+}
+
+static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos;
+}
+
+static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON;
+	} else {
+		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON;
+	}
+}
+
+static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON;
+}
+
+static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask)
+{
+	((Adc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw)
+{
+	return ((Adc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data)
+{
+	((Adc *)hw)->INTENSET.reg = data;
+	((Adc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask)
+{
+	((Adc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_adc_get_STATUS_ADCBUSY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->STATUS.reg & ADC_STATUS_ADCBUSY) >> ADC_STATUS_ADCBUSY_Pos;
+}
+
+static inline hri_adc_status_reg_t hri_adc_get_STATUS_WCC_bf(const void *const hw, hri_adc_status_reg_t mask)
+{
+	return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC(mask)) >> ADC_STATUS_WCC_Pos;
+}
+
+static inline hri_adc_status_reg_t hri_adc_read_STATUS_WCC_bf(const void *const hw)
+{
+	return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC_Msk) >> ADC_STATUS_WCC_Pos;
+}
+
+static inline hri_adc_status_reg_t hri_adc_get_STATUS_reg(const void *const hw, hri_adc_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_status_reg_t hri_adc_read_STATUS_reg(const void *const hw)
+{
+	return ((Adc *)hw)->STATUS.reg;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLB) >> ADC_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_REFCTRL_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_REFCTRL) >> ADC_SYNCBUSY_REFCTRL_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos;
+}
+
+static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Adc *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Adc *)hw)->SYNCBUSY.reg;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_INPUTCTRL_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_INPUTCTRL) >> ADC_DSEQSTAT_INPUTCTRL_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_CTRLB_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_CTRLB) >> ADC_DSEQSTAT_CTRLB_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_REFCTRL_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_REFCTRL) >> ADC_DSEQSTAT_REFCTRL_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_AVGCTRL_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_AVGCTRL) >> ADC_DSEQSTAT_AVGCTRL_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_SAMPCTRL_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_SAMPCTRL) >> ADC_DSEQSTAT_SAMPCTRL_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_WINLT_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINLT) >> ADC_DSEQSTAT_WINLT_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_WINUT_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINUT) >> ADC_DSEQSTAT_WINUT_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_GAINCORR_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_GAINCORR) >> ADC_DSEQSTAT_GAINCORR_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_OFFSETCORR_bit(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_OFFSETCORR) >> ADC_DSEQSTAT_OFFSETCORR_Pos;
+}
+
+static inline bool hri_adc_get_DSEQSTAT_BUSY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_BUSY) >> ADC_DSEQSTAT_BUSY_Pos;
+}
+
+static inline hri_adc_dseqstat_reg_t hri_adc_get_DSEQSTAT_reg(const void *const hw, hri_adc_dseqstat_reg_t mask)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQSTAT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_dseqstat_reg_t hri_adc_read_DSEQSTAT_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return ((Adc *)hw)->DSEQSTAT.reg;
+}
+
+static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask)
+{
+	return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos;
+}
+
+static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw)
+{
+	return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos;
+}
+
+static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->RESULT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw)
+{
+	return ((Adc *)hw)->RESULT.reg;
+}
+
+static inline hri_adc_ress_reg_t hri_adc_get_RESS_RESS_bf(const void *const hw, hri_adc_ress_reg_t mask)
+{
+	return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS(mask)) >> ADC_RESS_RESS_Pos;
+}
+
+static inline hri_adc_ress_reg_t hri_adc_read_RESS_RESS_bf(const void *const hw)
+{
+	return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS_Msk) >> ADC_RESS_RESS_Pos;
+}
+
+static inline hri_adc_ress_reg_t hri_adc_get_RESS_reg(const void *const hw, hri_adc_ress_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->RESS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_ress_reg_t hri_adc_read_RESS_reg(const void *const hw)
+{
+	return ((Adc *)hw)->RESS.reg;
+}
+
+static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST);
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_ENABLE;
+	tmp |= value << ADC_CTRLA_ENABLE_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_SLAVEEN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SLAVEEN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_SLAVEEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_SLAVEEN) >> ADC_CTRLA_SLAVEEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_SLAVEEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_SLAVEEN;
+	tmp |= value << ADC_CTRLA_SLAVEEN_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_SLAVEEN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_SLAVEEN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_SLAVEEN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_SLAVEEN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_RUNSTDBY;
+	tmp |= value << ADC_CTRLA_RUNSTDBY_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_ONDEMAND;
+	tmp |= value << ADC_CTRLA_ONDEMAND_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_R2R_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_R2R;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_R2R_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_R2R) >> ADC_CTRLA_R2R_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_R2R_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_R2R;
+	tmp |= value << ADC_CTRLA_R2R_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_R2R_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_R2R;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_R2R_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_R2R;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_DUALSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_DUALSEL(mask)) >> ADC_CTRLA_DUALSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_DUALSEL_Msk;
+	tmp |= ADC_CTRLA_DUALSEL(data);
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_DUALSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_DUALSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_DUALSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_DUALSEL_Msk) >> ADC_CTRLA_DUALSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_PRESCALER(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_PRESCALER(mask)) >> ADC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_PRESCALER_Msk;
+	tmp |= ADC_CTRLA_PRESCALER(data);
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_PRESCALER(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_PRESCALER(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_PRESCALER_Msk) >> ADC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	return ((Adc *)hw)->CTRLA.reg;
+}
+
+static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_FLUSHEI;
+	tmp |= value << ADC_EVCTRL_FLUSHEI_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_STARTEI;
+	tmp |= value << ADC_EVCTRL_STARTEI_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_FLUSHINV;
+	tmp |= value << ADC_EVCTRL_FLUSHINV_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_STARTINV;
+	tmp |= value << ADC_EVCTRL_STARTINV_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_RESRDYEO;
+	tmp |= value << ADC_EVCTRL_RESRDYEO_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_WINMONEO;
+	tmp |= value << ADC_EVCTRL_WINMONEO_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DBGCTRL.reg;
+	tmp &= ~ADC_DBGCTRL_DBGRUN;
+	tmp |= value << ADC_DBGCTRL_DBGRUN_Pos;
+	((Adc *)hw)->DBGCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_adc_set_INPUTCTRL_DIFFMODE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DIFFMODE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_INPUTCTRL_DIFFMODE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_DIFFMODE) >> ADC_INPUTCTRL_DIFFMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_DIFFMODE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_DIFFMODE;
+	tmp |= value << ADC_INPUTCTRL_DIFFMODE_Pos;
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_DIFFMODE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DIFFMODE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_DIFFMODE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DIFFMODE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_INPUTCTRL_DSEQSTOP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DSEQSTOP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_INPUTCTRL_DSEQSTOP_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_DSEQSTOP) >> ADC_INPUTCTRL_DSEQSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_DSEQSTOP_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_DSEQSTOP;
+	tmp |= value << ADC_INPUTCTRL_DSEQSTOP_Pos;
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_DSEQSTOP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DSEQSTOP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_DSEQSTOP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DSEQSTOP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const       hw,
+                                                                      hri_adc_inputctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk;
+	tmp |= ADC_INPUTCTRL_MUXPOS(data);
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const       hw,
+                                                                      hri_adc_inputctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk;
+	tmp |= ADC_INPUTCTRL_MUXNEG(data);
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->INPUTCTRL.reg;
+}
+
+static inline void hri_adc_set_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_LEFTADJ;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_LEFTADJ) >> ADC_CTRLB_LEFTADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_LEFTADJ;
+	tmp |= value << ADC_CTRLB_LEFTADJ_Pos;
+	((Adc *)hw)->CTRLB.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_LEFTADJ;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_LEFTADJ_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_LEFTADJ;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLB_FREERUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_FREERUN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLB_FREERUN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_FREERUN) >> ADC_CTRLB_FREERUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLB_FREERUN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_FREERUN;
+	tmp |= value << ADC_CTRLB_FREERUN_Pos;
+	((Adc *)hw)->CTRLB.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_FREERUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_FREERUN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_FREERUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_FREERUN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLB_CORREN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_CORREN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLB_CORREN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_CORREN) >> ADC_CTRLB_CORREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLB_CORREN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_CORREN;
+	tmp |= value << ADC_CTRLB_CORREN_Pos;
+	((Adc *)hw)->CTRLB.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_CORREN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_CORREN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_CORREN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_CORREN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLB_WINSS_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINSS;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLB_WINSS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_WINSS) >> ADC_CTRLB_WINSS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLB_WINSS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_WINSS;
+	tmp |= value << ADC_CTRLB_WINSS_Pos;
+	((Adc *)hw)->CTRLB.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_WINSS_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINSS;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_WINSS_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINSS;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_RESSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_RESSEL(mask)) >> ADC_CTRLB_RESSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_RESSEL_Msk;
+	tmp |= ADC_CTRLB_RESSEL(data);
+	((Adc *)hw)->CTRLB.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_RESSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_RESSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_RESSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_RESSEL_Msk) >> ADC_CTRLB_RESSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINMODE(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_WINMODE(mask)) >> ADC_CTRLB_WINMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_WINMODE_Msk;
+	tmp |= ADC_CTRLB_WINMODE(data);
+	((Adc *)hw)->CTRLB.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINMODE(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINMODE(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_WINMODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_WINMODE_Msk) >> ADC_CTRLB_WINMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->CTRLB.reg;
+}
+
+static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp &= ~ADC_REFCTRL_REFCOMP;
+	tmp |= value << ADC_REFCTRL_REFCOMP_Pos;
+	((Adc *)hw)->REFCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp &= ~ADC_REFCTRL_REFSEL_Msk;
+	tmp |= ADC_REFCTRL_REFSEL(data);
+	((Adc *)hw)->REFCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->REFCTRL.reg;
+}
+
+static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk;
+	tmp |= ADC_AVGCTRL_SAMPLENUM(data);
+	((Adc *)hw)->AVGCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp &= ~ADC_AVGCTRL_ADJRES_Msk;
+	tmp |= ADC_AVGCTRL_ADJRES(data);
+	((Adc *)hw)->AVGCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->AVGCTRL.reg;
+}
+
+static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp &= ~ADC_SAMPCTRL_OFFCOMP;
+	tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos;
+	((Adc *)hw)->SAMPCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk;
+	tmp |= ADC_SAMPCTRL_SAMPLEN(data);
+	((Adc *)hw)->SAMPCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->SAMPCTRL.reg;
+}
+
+static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp &= ~ADC_WINLT_WINLT_Msk;
+	tmp |= ADC_WINLT_WINLT(data);
+	((Adc *)hw)->WINLT.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	return ((Adc *)hw)->WINLT.reg;
+}
+
+static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp &= ~ADC_WINUT_WINUT_Msk;
+	tmp |= ADC_WINUT_WINUT(data);
+	((Adc *)hw)->WINUT.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	return ((Adc *)hw)->WINUT.reg;
+}
+
+static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp &= ~ADC_GAINCORR_GAINCORR_Msk;
+	tmp |= ADC_GAINCORR_GAINCORR(data);
+	((Adc *)hw)->GAINCORR.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	return ((Adc *)hw)->GAINCORR.reg;
+}
+
+static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const        hw,
+                                                                            hri_adc_offsetcorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk;
+	tmp |= ADC_OFFSETCORR_OFFSETCORR(data);
+	((Adc *)hw)->OFFSETCORR.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	return ((Adc *)hw)->OFFSETCORR.reg;
+}
+
+static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp &= ~ADC_SWTRIG_FLUSH;
+	tmp |= value << ADC_SWTRIG_FLUSH_Pos;
+	((Adc *)hw)->SWTRIG.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp &= ~ADC_SWTRIG_START;
+	tmp |= value << ADC_SWTRIG_START_Pos;
+	((Adc *)hw)->SWTRIG.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->SWTRIG.reg;
+}
+
+static inline void hri_adc_set_DSEQCTRL_INPUTCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_INPUTCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_INPUTCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_INPUTCTRL) >> ADC_DSEQCTRL_INPUTCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_INPUTCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_INPUTCTRL;
+	tmp |= value << ADC_DSEQCTRL_INPUTCTRL_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_INPUTCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_INPUTCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_INPUTCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_INPUTCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_CTRLB_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_CTRLB;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_CTRLB_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_CTRLB) >> ADC_DSEQCTRL_CTRLB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_CTRLB_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_CTRLB;
+	tmp |= value << ADC_DSEQCTRL_CTRLB_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_CTRLB_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_CTRLB;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_CTRLB_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_CTRLB;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_REFCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_REFCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_REFCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_REFCTRL) >> ADC_DSEQCTRL_REFCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_REFCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_REFCTRL;
+	tmp |= value << ADC_DSEQCTRL_REFCTRL_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_REFCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_REFCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_REFCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_REFCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_AVGCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AVGCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_AVGCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_AVGCTRL) >> ADC_DSEQCTRL_AVGCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_AVGCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_AVGCTRL;
+	tmp |= value << ADC_DSEQCTRL_AVGCTRL_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_AVGCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AVGCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_AVGCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AVGCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_SAMPCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_SAMPCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_SAMPCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_SAMPCTRL) >> ADC_DSEQCTRL_SAMPCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_SAMPCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_SAMPCTRL;
+	tmp |= value << ADC_DSEQCTRL_SAMPCTRL_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_SAMPCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_SAMPCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_SAMPCTRL_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_SAMPCTRL;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_WINLT_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINLT;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_WINLT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_WINLT) >> ADC_DSEQCTRL_WINLT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_WINLT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_WINLT;
+	tmp |= value << ADC_DSEQCTRL_WINLT_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_WINLT_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINLT;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_WINLT_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINLT;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_WINUT_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINUT;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_WINUT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_WINUT) >> ADC_DSEQCTRL_WINUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_WINUT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_WINUT;
+	tmp |= value << ADC_DSEQCTRL_WINUT_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_WINUT_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINUT;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_WINUT_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINUT;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_GAINCORR_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_GAINCORR;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_GAINCORR_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_GAINCORR) >> ADC_DSEQCTRL_GAINCORR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_GAINCORR_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_GAINCORR;
+	tmp |= value << ADC_DSEQCTRL_GAINCORR_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_GAINCORR_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_GAINCORR;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_GAINCORR_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_GAINCORR;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_OFFSETCORR_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_OFFSETCORR;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_OFFSETCORR_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_OFFSETCORR) >> ADC_DSEQCTRL_OFFSETCORR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_OFFSETCORR_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_OFFSETCORR;
+	tmp |= value << ADC_DSEQCTRL_OFFSETCORR_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_OFFSETCORR_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_OFFSETCORR;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_OFFSETCORR_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_OFFSETCORR;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_AUTOSTART_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AUTOSTART;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DSEQCTRL_AUTOSTART_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp = (tmp & ADC_DSEQCTRL_AUTOSTART) >> ADC_DSEQCTRL_AUTOSTART_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_AUTOSTART_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= ~ADC_DSEQCTRL_AUTOSTART;
+	tmp |= value << ADC_DSEQCTRL_AUTOSTART_Pos;
+	((Adc *)hw)->DSEQCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_AUTOSTART_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AUTOSTART;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_AUTOSTART_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AUTOSTART;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_dseqctrl_reg_t hri_adc_get_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->DSEQCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg = data;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_dseqctrl_reg_t hri_adc_read_DSEQCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw,
+	                      ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL
+	                          | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR
+	                          | ADC_SYNCBUSY_OFFSETCORR);
+	return ((Adc *)hw)->DSEQCTRL.reg;
+}
+
+static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= ~ADC_CALIB_BIASCOMP_Msk;
+	tmp |= ADC_CALIB_BIASCOMP(data);
+	((Adc *)hw)->CALIB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASR2R(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASR2R(mask)) >> ADC_CALIB_BIASR2R_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= ~ADC_CALIB_BIASR2R_Msk;
+	tmp |= ADC_CALIB_BIASR2R(data);
+	((Adc *)hw)->CALIB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASR2R(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASR2R(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASR2R_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASR2R_Msk) >> ADC_CALIB_BIASR2R_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= ~ADC_CALIB_BIASREFBUF_Msk;
+	tmp |= ADC_CALIB_BIASREFBUF(data);
+	((Adc *)hw)->CALIB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw)
+{
+	return ((Adc *)hw)->CALIB.reg;
+}
+
+static inline void hri_adc_write_DSEQDATA_reg(const void *const hw, hri_adc_dseqdata_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DSEQDATA.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_ADC_E54_H_INCLUDED */
+#endif /* _SAME54_ADC_COMPONENT_ */
diff --git a/hri/hri_aes_e54.h b/hri/hri_aes_e54.h
new file mode 100644
index 0000000..c1070e2
--- /dev/null
+++ b/hri/hri_aes_e54.h
@@ -0,0 +1,1287 @@
+/**
+ * \file
+ *
+ * \brief SAM AES
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_AES_COMPONENT_
+#ifndef _HRI_AES_E54_H_INCLUDED_
+#define _HRI_AES_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_AES_CRITICAL_SECTIONS)
+#define AES_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define AES_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define AES_CRITICAL_SECTION_ENTER()
+#define AES_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_aes_ciplen_reg_t;
+typedef uint32_t hri_aes_ctrla_reg_t;
+typedef uint32_t hri_aes_ghash_reg_t;
+typedef uint32_t hri_aes_hashkey_reg_t;
+typedef uint32_t hri_aes_indata_reg_t;
+typedef uint32_t hri_aes_intvectv_reg_t;
+typedef uint32_t hri_aes_keyword_reg_t;
+typedef uint32_t hri_aes_randseed_reg_t;
+typedef uint8_t  hri_aes_ctrlb_reg_t;
+typedef uint8_t  hri_aes_databufptr_reg_t;
+typedef uint8_t  hri_aes_dbgctrl_reg_t;
+typedef uint8_t  hri_aes_intenset_reg_t;
+typedef uint8_t  hri_aes_intflag_reg_t;
+
+static inline bool hri_aes_get_INTFLAG_ENCCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos;
+}
+
+static inline void hri_aes_clear_INTFLAG_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP;
+}
+
+static inline bool hri_aes_get_INTFLAG_GFMCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos;
+}
+
+static inline void hri_aes_clear_INTFLAG_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP;
+}
+
+static inline bool hri_aes_get_interrupt_ENCCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos;
+}
+
+static inline void hri_aes_clear_interrupt_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP;
+}
+
+static inline bool hri_aes_get_interrupt_GFMCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos;
+}
+
+static inline void hri_aes_clear_interrupt_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP;
+}
+
+static inline hri_aes_intflag_reg_t hri_aes_get_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_aes_intflag_reg_t hri_aes_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Aes *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_aes_clear_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask)
+{
+	((Aes *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_aes_set_INTEN_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP;
+}
+
+static inline bool hri_aes_get_INTEN_ENCCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos;
+}
+
+static inline void hri_aes_write_INTEN_ENCCMP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP;
+	} else {
+		((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP;
+	}
+}
+
+static inline void hri_aes_clear_INTEN_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP;
+}
+
+static inline void hri_aes_set_INTEN_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP;
+}
+
+static inline bool hri_aes_get_INTEN_GFMCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos;
+}
+
+static inline void hri_aes_write_INTEN_GFMCMP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP;
+	} else {
+		((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP;
+	}
+}
+
+static inline void hri_aes_clear_INTEN_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP;
+}
+
+static inline void hri_aes_set_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask)
+{
+	((Aes *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_aes_intenset_reg_t hri_aes_get_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_aes_intenset_reg_t hri_aes_read_INTEN_reg(const void *const hw)
+{
+	return ((Aes *)hw)->INTENSET.reg;
+}
+
+static inline void hri_aes_write_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t data)
+{
+	((Aes *)hw)->INTENSET.reg = data;
+	((Aes *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_aes_clear_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask)
+{
+	((Aes *)hw)->INTENCLR.reg = mask;
+}
+
+static inline void hri_aes_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_SWRST;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_SWRST) >> AES_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_ENABLE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_ENABLE) >> AES_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_ENABLE;
+	tmp |= value << AES_CTRLA_ENABLE_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_ENABLE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_ENABLE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_CIPHER_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CIPHER;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_CIPHER_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CIPHER) >> AES_CTRLA_CIPHER_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_CIPHER_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_CIPHER;
+	tmp |= value << AES_CTRLA_CIPHER_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_CIPHER_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CIPHER;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_CIPHER_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CIPHER;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_STARTMODE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_STARTMODE) >> AES_CTRLA_STARTMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_STARTMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_STARTMODE;
+	tmp |= value << AES_CTRLA_STARTMODE_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_STARTMODE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_STARTMODE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_LOD_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_LOD;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_LOD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_LOD) >> AES_CTRLA_LOD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_LOD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_LOD;
+	tmp |= value << AES_CTRLA_LOD_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_LOD_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_LOD;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_LOD_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_LOD;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYGEN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_KEYGEN) >> AES_CTRLA_KEYGEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_KEYGEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_KEYGEN;
+	tmp |= value << AES_CTRLA_KEYGEN_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYGEN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYGEN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_XORKEY_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_XORKEY;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_XORKEY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_XORKEY) >> AES_CTRLA_XORKEY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_XORKEY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_XORKEY;
+	tmp |= value << AES_CTRLA_XORKEY_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_XORKEY_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_XORKEY;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_XORKEY_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_XORKEY;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_AESMODE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_AESMODE(mask)) >> AES_CTRLA_AESMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_AESMODE_Msk;
+	tmp |= AES_CTRLA_AESMODE(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_AESMODE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_AESMODE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_AESMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_AESMODE_Msk) >> AES_CTRLA_AESMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CFBS(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CFBS(mask)) >> AES_CTRLA_CFBS_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_CFBS_Msk;
+	tmp |= AES_CTRLA_CFBS(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CFBS(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CFBS(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CFBS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CFBS_Msk) >> AES_CTRLA_CFBS_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYSIZE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_KEYSIZE(mask)) >> AES_CTRLA_KEYSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_KEYSIZE_Msk;
+	tmp |= AES_CTRLA_KEYSIZE(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYSIZE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYSIZE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_KEYSIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_KEYSIZE_Msk) >> AES_CTRLA_KEYSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CTYPE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CTYPE(mask)) >> AES_CTRLA_CTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_CTYPE_Msk;
+	tmp |= AES_CTRLA_CTYPE(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CTYPE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CTYPE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CTYPE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CTYPE_Msk) >> AES_CTRLA_CTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_reg(const void *const hw)
+{
+	return ((Aes *)hw)->CTRLA.reg;
+}
+
+static inline void hri_aes_set_CTRLB_START_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_START;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_START_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_START) >> AES_CTRLB_START_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_START_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_START;
+	tmp |= value << AES_CTRLB_START_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_START_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_START;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_START_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_START;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_NEWMSG;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_NEWMSG) >> AES_CTRLB_NEWMSG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_NEWMSG_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_NEWMSG;
+	tmp |= value << AES_CTRLB_NEWMSG_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_NEWMSG;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_NEWMSG;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_EOM_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_EOM;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_EOM_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_EOM) >> AES_CTRLB_EOM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_EOM_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_EOM;
+	tmp |= value << AES_CTRLB_EOM_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_EOM_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_EOM;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_EOM_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_EOM;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_GFMUL_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_GFMUL;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_GFMUL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_GFMUL) >> AES_CTRLB_GFMUL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_GFMUL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_GFMUL;
+	tmp |= value << AES_CTRLB_GFMUL_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_GFMUL_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_GFMUL;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_GFMUL_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_GFMUL;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrlb_reg_t hri_aes_get_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrlb_reg_t hri_aes_read_CTRLB_reg(const void *const hw)
+{
+	return ((Aes *)hw)->CTRLB.reg;
+}
+
+static inline void hri_aes_set_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg |= AES_DATABUFPTR_INDATAPTR(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_INDATAPTR_bf(const void *const        hw,
+                                                                           hri_aes_databufptr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp = (tmp & AES_DATABUFPTR_INDATAPTR(mask)) >> AES_DATABUFPTR_INDATAPTR_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t data)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp &= ~AES_DATABUFPTR_INDATAPTR_Msk;
+	tmp |= AES_DATABUFPTR_INDATAPTR(data);
+	((Aes *)hw)->DATABUFPTR.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg &= ~AES_DATABUFPTR_INDATAPTR(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg ^= AES_DATABUFPTR_INDATAPTR(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_INDATAPTR_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp = (tmp & AES_DATABUFPTR_INDATAPTR_Msk) >> AES_DATABUFPTR_INDATAPTR_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_reg(const void *const hw)
+{
+	return ((Aes *)hw)->DATABUFPTR.reg;
+}
+
+static inline void hri_aes_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg |= AES_DBGCTRL_DBGRUN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DBGCTRL.reg;
+	tmp = (tmp & AES_DBGCTRL_DBGRUN) >> AES_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->DBGCTRL.reg;
+	tmp &= ~AES_DBGCTRL_DBGRUN;
+	tmp |= value << AES_DBGCTRL_DBGRUN_Pos;
+	((Aes *)hw)->DBGCTRL.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg &= ~AES_DBGCTRL_DBGRUN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg ^= AES_DBGCTRL_DBGRUN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_dbgctrl_reg_t hri_aes_get_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_dbgctrl_reg_t hri_aes_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Aes *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_aes_set_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_indata_reg_t hri_aes_get_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->INDATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_INDATA_reg(const void *const hw, hri_aes_indata_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_indata_reg_t hri_aes_read_INDATA_reg(const void *const hw)
+{
+	return ((Aes *)hw)->INDATA.reg;
+}
+
+static inline void hri_aes_set_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_hashkey_reg_t hri_aes_get_HASHKEY_reg(const void *const hw, uint8_t index,
+                                                            hri_aes_hashkey_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->HASHKEY[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_hashkey_reg_t hri_aes_read_HASHKEY_reg(const void *const hw, uint8_t index)
+{
+	return ((Aes *)hw)->HASHKEY[index].reg;
+}
+
+static inline void hri_aes_set_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ghash_reg_t hri_aes_get_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->GHASH[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ghash_reg_t hri_aes_read_GHASH_reg(const void *const hw, uint8_t index)
+{
+	return ((Aes *)hw)->GHASH[index].reg;
+}
+
+static inline void hri_aes_set_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ciplen_reg_t hri_aes_get_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CIPLEN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ciplen_reg_t hri_aes_read_CIPLEN_reg(const void *const hw)
+{
+	return ((Aes *)hw)->CIPLEN.reg;
+}
+
+static inline void hri_aes_set_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_randseed_reg_t hri_aes_get_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->RANDSEED.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_randseed_reg_t hri_aes_read_RANDSEED_reg(const void *const hw)
+{
+	return ((Aes *)hw)->RANDSEED.reg;
+}
+
+static inline void hri_aes_write_KEYWORD_reg(const void *const hw, uint8_t index, hri_aes_keyword_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->KEYWORD[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_write_INTVECTV_reg(const void *const hw, uint8_t index, hri_aes_intvectv_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INTVECTV[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_AES_E54_H_INCLUDED */
+#endif /* _SAME54_AES_COMPONENT_ */
diff --git a/hri/hri_can_e54.h b/hri/hri_can_e54.h
new file mode 100644
index 0000000..2c02884
--- /dev/null
+++ b/hri/hri_can_e54.h
@@ -0,0 +1,16997 @@
+/**
+ * \file
+ *
+ * \brief SAM CAN
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_CAN_COMPONENT_
+#ifndef _HRI_CAN_E54_H_INCLUDED_
+#define _HRI_CAN_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_CAN_CRITICAL_SECTIONS)
+#define CAN_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define CAN_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define CAN_CRITICAL_SECTION_ENTER()
+#define CAN_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_can_cccr_reg_t;
+typedef uint32_t hri_can_crel_reg_t;
+typedef uint32_t hri_can_dbtp_reg_t;
+typedef uint32_t hri_can_ecr_reg_t;
+typedef uint32_t hri_can_endn_reg_t;
+typedef uint32_t hri_can_gfc_reg_t;
+typedef uint32_t hri_can_hpms_reg_t;
+typedef uint32_t hri_can_ie_reg_t;
+typedef uint32_t hri_can_ile_reg_t;
+typedef uint32_t hri_can_ils_reg_t;
+typedef uint32_t hri_can_ir_reg_t;
+typedef uint32_t hri_can_mrcfg_reg_t;
+typedef uint32_t hri_can_nbtp_reg_t;
+typedef uint32_t hri_can_ndat1_reg_t;
+typedef uint32_t hri_can_ndat2_reg_t;
+typedef uint32_t hri_can_psr_reg_t;
+typedef uint32_t hri_can_rwd_reg_t;
+typedef uint32_t hri_can_rxbc_reg_t;
+typedef uint32_t hri_can_rxesc_reg_t;
+typedef uint32_t hri_can_rxf0a_reg_t;
+typedef uint32_t hri_can_rxf0c_reg_t;
+typedef uint32_t hri_can_rxf0s_reg_t;
+typedef uint32_t hri_can_rxf1a_reg_t;
+typedef uint32_t hri_can_rxf1c_reg_t;
+typedef uint32_t hri_can_rxf1s_reg_t;
+typedef uint32_t hri_can_sidfc_reg_t;
+typedef uint32_t hri_can_tdcr_reg_t;
+typedef uint32_t hri_can_test_reg_t;
+typedef uint32_t hri_can_tocc_reg_t;
+typedef uint32_t hri_can_tocv_reg_t;
+typedef uint32_t hri_can_tscc_reg_t;
+typedef uint32_t hri_can_tscv_reg_t;
+typedef uint32_t hri_can_txbar_reg_t;
+typedef uint32_t hri_can_txbc_reg_t;
+typedef uint32_t hri_can_txbcf_reg_t;
+typedef uint32_t hri_can_txbcie_reg_t;
+typedef uint32_t hri_can_txbcr_reg_t;
+typedef uint32_t hri_can_txbrp_reg_t;
+typedef uint32_t hri_can_txbtie_reg_t;
+typedef uint32_t hri_can_txbto_reg_t;
+typedef uint32_t hri_can_txefa_reg_t;
+typedef uint32_t hri_can_txefc_reg_t;
+typedef uint32_t hri_can_txefs_reg_t;
+typedef uint32_t hri_can_txesc_reg_t;
+typedef uint32_t hri_can_txfqs_reg_t;
+typedef uint32_t hri_can_xidam_reg_t;
+typedef uint32_t hri_can_xidfc_reg_t;
+
+static inline hri_can_crel_reg_t hri_can_get_CREL_SUBSTEP_bf(const void *const hw, hri_can_crel_reg_t mask)
+{
+	return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP(mask)) >> CAN_CREL_SUBSTEP_Pos;
+}
+
+static inline hri_can_crel_reg_t hri_can_read_CREL_SUBSTEP_bf(const void *const hw)
+{
+	return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP_Msk) >> CAN_CREL_SUBSTEP_Pos;
+}
+
+static inline hri_can_crel_reg_t hri_can_get_CREL_STEP_bf(const void *const hw, hri_can_crel_reg_t mask)
+{
+	return (((Can *)hw)->CREL.reg & CAN_CREL_STEP(mask)) >> CAN_CREL_STEP_Pos;
+}
+
+static inline hri_can_crel_reg_t hri_can_read_CREL_STEP_bf(const void *const hw)
+{
+	return (((Can *)hw)->CREL.reg & CAN_CREL_STEP_Msk) >> CAN_CREL_STEP_Pos;
+}
+
+static inline hri_can_crel_reg_t hri_can_get_CREL_REL_bf(const void *const hw, hri_can_crel_reg_t mask)
+{
+	return (((Can *)hw)->CREL.reg & CAN_CREL_REL(mask)) >> CAN_CREL_REL_Pos;
+}
+
+static inline hri_can_crel_reg_t hri_can_read_CREL_REL_bf(const void *const hw)
+{
+	return (((Can *)hw)->CREL.reg & CAN_CREL_REL_Msk) >> CAN_CREL_REL_Pos;
+}
+
+static inline hri_can_crel_reg_t hri_can_get_CREL_reg(const void *const hw, hri_can_crel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->CREL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_can_crel_reg_t hri_can_read_CREL_reg(const void *const hw)
+{
+	return ((Can *)hw)->CREL.reg;
+}
+
+static inline hri_can_endn_reg_t hri_can_get_ENDN_ETV_bf(const void *const hw, hri_can_endn_reg_t mask)
+{
+	return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV(mask)) >> CAN_ENDN_ETV_Pos;
+}
+
+static inline hri_can_endn_reg_t hri_can_read_ENDN_ETV_bf(const void *const hw)
+{
+	return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV_Msk) >> CAN_ENDN_ETV_Pos;
+}
+
+static inline hri_can_endn_reg_t hri_can_get_ENDN_reg(const void *const hw, hri_can_endn_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ENDN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_can_endn_reg_t hri_can_read_ENDN_reg(const void *const hw)
+{
+	return ((Can *)hw)->ENDN.reg;
+}
+
+static inline hri_can_tscv_reg_t hri_can_get_TSCV_TSC_bf(const void *const hw, hri_can_tscv_reg_t mask)
+{
+	return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC(mask)) >> CAN_TSCV_TSC_Pos;
+}
+
+static inline hri_can_tscv_reg_t hri_can_read_TSCV_TSC_bf(const void *const hw)
+{
+	return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC_Msk) >> CAN_TSCV_TSC_Pos;
+}
+
+static inline hri_can_tscv_reg_t hri_can_get_TSCV_reg(const void *const hw, hri_can_tscv_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TSCV.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_can_tscv_reg_t hri_can_read_TSCV_reg(const void *const hw)
+{
+	return ((Can *)hw)->TSCV.reg;
+}
+
+static inline bool hri_can_get_ECR_RP_bit(const void *const hw)
+{
+	return (((Can *)hw)->ECR.reg & CAN_ECR_RP) >> CAN_ECR_RP_Pos;
+}
+
+static inline hri_can_ecr_reg_t hri_can_get_ECR_TEC_bf(const void *const hw, hri_can_ecr_reg_t mask)
+{
+	return (((Can *)hw)->ECR.reg & CAN_ECR_TEC(mask)) >> CAN_ECR_TEC_Pos;
+}
+
+static inline hri_can_ecr_reg_t hri_can_read_ECR_TEC_bf(const void *const hw)
+{
+	return (((Can *)hw)->ECR.reg & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos;
+}
+
+static inline hri_can_ecr_reg_t hri_can_get_ECR_REC_bf(const void *const hw, hri_can_ecr_reg_t mask)
+{
+	return (((Can *)hw)->ECR.reg & CAN_ECR_REC(mask)) >> CAN_ECR_REC_Pos;
+}
+
+static inline hri_can_ecr_reg_t hri_can_read_ECR_REC_bf(const void *const hw)
+{
+	return (((Can *)hw)->ECR.reg & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos;
+}
+
+static inline hri_can_ecr_reg_t hri_can_get_ECR_CEL_bf(const void *const hw, hri_can_ecr_reg_t mask)
+{
+	return (((Can *)hw)->ECR.reg & CAN_ECR_CEL(mask)) >> CAN_ECR_CEL_Pos;
+}
+
+static inline hri_can_ecr_reg_t hri_can_read_ECR_CEL_bf(const void *const hw)
+{
+	return (((Can *)hw)->ECR.reg & CAN_ECR_CEL_Msk) >> CAN_ECR_CEL_Pos;
+}
+
+static inline hri_can_ecr_reg_t hri_can_get_ECR_reg(const void *const hw, hri_can_ecr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ECR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_can_ecr_reg_t hri_can_read_ECR_reg(const void *const hw)
+{
+	return ((Can *)hw)->ECR.reg;
+}
+
+static inline bool hri_can_get_PSR_EP_bit(const void *const hw)
+{
+	return (((Can *)hw)->PSR.reg & CAN_PSR_EP) >> CAN_PSR_EP_Pos;
+}
+
+static inline bool hri_can_get_PSR_EW_bit(const void *const hw)
+{
+	return (((Can *)hw)->PSR.reg & CAN_PSR_EW) >> CAN_PSR_EW_Pos;
+}
+
+static inline bool hri_can_get_PSR_BO_bit(const void *const hw)
+{
+	return (((Can *)hw)->PSR.reg & CAN_PSR_BO) >> CAN_PSR_BO_Pos;
+}
+
+static inline bool hri_can_get_PSR_RESI_bit(const void *const hw)
+{
+	return (((Can *)hw)->PSR.reg & CAN_PSR_RESI) >> CAN_PSR_RESI_Pos;
+}
+
+static inline bool hri_can_get_PSR_RBRS_bit(const void *const hw)
+{
+	return (((Can *)hw)->PSR.reg & CAN_PSR_RBRS) >> CAN_PSR_RBRS_Pos;
+}
+
+static inline bool hri_can_get_PSR_RFDF_bit(const void *const hw)
+{
+	return (((Can *)hw)->PSR.reg & CAN_PSR_RFDF) >> CAN_PSR_RFDF_Pos;
+}
+
+static inline bool hri_can_get_PSR_PXE_bit(const void *const hw)
+{
+	return (((Can *)hw)->PSR.reg & CAN_PSR_PXE) >> CAN_PSR_PXE_Pos;
+}
+
+static inline hri_can_psr_reg_t hri_can_get_PSR_LEC_bf(const void *const hw, hri_can_psr_reg_t mask)
+{
+	return (((Can *)hw)->PSR.reg & CAN_PSR_LEC(mask)) >> CAN_PSR_LEC_Pos;
+}
+
+static inline hri_can_psr_reg_t hri_can_read_PSR_LEC_bf(const void *const hw)
+{
+	return (((Can *)hw)->PSR.reg & CAN_PSR_LEC_Msk) >> CAN_PSR_LEC_Pos;
+}
+
+static inline hri_can_psr_reg_t hri_can_get_PSR_ACT_bf(const void *const hw, hri_can_psr_reg_t mask)
+{
+	return (((Can *)hw)->PSR.reg & CAN_PSR_ACT(mask)) >> CAN_PSR_ACT_Pos;
+}
+
+static inline hri_can_psr_reg_t hri_can_read_PSR_ACT_bf(const void *const hw)
+{
+	return (((Can *)hw)->PSR.reg & CAN_PSR_ACT_Msk) >> CAN_PSR_ACT_Pos;
+}
+
+static inline hri_can_psr_reg_t hri_can_get_PSR_DLEC_bf(const void *const hw, hri_can_psr_reg_t mask)
+{
+	return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC(mask)) >> CAN_PSR_DLEC_Pos;
+}
+
+static inline hri_can_psr_reg_t hri_can_read_PSR_DLEC_bf(const void *const hw)
+{
+	return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC_Msk) >> CAN_PSR_DLEC_Pos;
+}
+
+static inline hri_can_psr_reg_t hri_can_get_PSR_TDCV_bf(const void *const hw, hri_can_psr_reg_t mask)
+{
+	return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV(mask)) >> CAN_PSR_TDCV_Pos;
+}
+
+static inline hri_can_psr_reg_t hri_can_read_PSR_TDCV_bf(const void *const hw)
+{
+	return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV_Msk) >> CAN_PSR_TDCV_Pos;
+}
+
+static inline hri_can_psr_reg_t hri_can_get_PSR_reg(const void *const hw, hri_can_psr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->PSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_can_psr_reg_t hri_can_read_PSR_reg(const void *const hw)
+{
+	return ((Can *)hw)->PSR.reg;
+}
+
+static inline bool hri_can_get_HPMS_FLST_bit(const void *const hw)
+{
+	return (((Can *)hw)->HPMS.reg & CAN_HPMS_FLST) >> CAN_HPMS_FLST_Pos;
+}
+
+static inline hri_can_hpms_reg_t hri_can_get_HPMS_BIDX_bf(const void *const hw, hri_can_hpms_reg_t mask)
+{
+	return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX(mask)) >> CAN_HPMS_BIDX_Pos;
+}
+
+static inline hri_can_hpms_reg_t hri_can_read_HPMS_BIDX_bf(const void *const hw)
+{
+	return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX_Msk) >> CAN_HPMS_BIDX_Pos;
+}
+
+static inline hri_can_hpms_reg_t hri_can_get_HPMS_MSI_bf(const void *const hw, hri_can_hpms_reg_t mask)
+{
+	return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI(mask)) >> CAN_HPMS_MSI_Pos;
+}
+
+static inline hri_can_hpms_reg_t hri_can_read_HPMS_MSI_bf(const void *const hw)
+{
+	return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI_Msk) >> CAN_HPMS_MSI_Pos;
+}
+
+static inline hri_can_hpms_reg_t hri_can_get_HPMS_FIDX_bf(const void *const hw, hri_can_hpms_reg_t mask)
+{
+	return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX(mask)) >> CAN_HPMS_FIDX_Pos;
+}
+
+static inline hri_can_hpms_reg_t hri_can_read_HPMS_FIDX_bf(const void *const hw)
+{
+	return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX_Msk) >> CAN_HPMS_FIDX_Pos;
+}
+
+static inline hri_can_hpms_reg_t hri_can_get_HPMS_reg(const void *const hw, hri_can_hpms_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->HPMS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_can_hpms_reg_t hri_can_read_HPMS_reg(const void *const hw)
+{
+	return ((Can *)hw)->HPMS.reg;
+}
+
+static inline bool hri_can_get_RXF0S_F0F_bit(const void *const hw)
+{
+	return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0F) >> CAN_RXF0S_F0F_Pos;
+}
+
+static inline bool hri_can_get_RXF0S_RF0L_bit(const void *const hw)
+{
+	return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_RF0L) >> CAN_RXF0S_RF0L_Pos;
+}
+
+static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0FL_bf(const void *const hw, hri_can_rxf0s_reg_t mask)
+{
+	return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL(mask)) >> CAN_RXF0S_F0FL_Pos;
+}
+
+static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0FL_bf(const void *const hw)
+{
+	return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL_Msk) >> CAN_RXF0S_F0FL_Pos;
+}
+
+static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0GI_bf(const void *const hw, hri_can_rxf0s_reg_t mask)
+{
+	return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI(mask)) >> CAN_RXF0S_F0GI_Pos;
+}
+
+static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0GI_bf(const void *const hw)
+{
+	return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos;
+}
+
+static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0PI_bf(const void *const hw, hri_can_rxf0s_reg_t mask)
+{
+	return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI(mask)) >> CAN_RXF0S_F0PI_Pos;
+}
+
+static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0PI_bf(const void *const hw)
+{
+	return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI_Msk) >> CAN_RXF0S_F0PI_Pos;
+}
+
+static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_reg(const void *const hw, hri_can_rxf0s_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF0S.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_reg(const void *const hw)
+{
+	return ((Can *)hw)->RXF0S.reg;
+}
+
+static inline bool hri_can_get_RXF1S_F1F_bit(const void *const hw)
+{
+	return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1F) >> CAN_RXF1S_F1F_Pos;
+}
+
+static inline bool hri_can_get_RXF1S_RF1L_bit(const void *const hw)
+{
+	return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_RF1L) >> CAN_RXF1S_RF1L_Pos;
+}
+
+static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1FL_bf(const void *const hw, hri_can_rxf1s_reg_t mask)
+{
+	return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL(mask)) >> CAN_RXF1S_F1FL_Pos;
+}
+
+static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1FL_bf(const void *const hw)
+{
+	return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL_Msk) >> CAN_RXF1S_F1FL_Pos;
+}
+
+static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1GI_bf(const void *const hw, hri_can_rxf1s_reg_t mask)
+{
+	return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI(mask)) >> CAN_RXF1S_F1GI_Pos;
+}
+
+static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1GI_bf(const void *const hw)
+{
+	return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI_Msk) >> CAN_RXF1S_F1GI_Pos;
+}
+
+static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1PI_bf(const void *const hw, hri_can_rxf1s_reg_t mask)
+{
+	return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI(mask)) >> CAN_RXF1S_F1PI_Pos;
+}
+
+static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1PI_bf(const void *const hw)
+{
+	return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI_Msk) >> CAN_RXF1S_F1PI_Pos;
+}
+
+static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_DMS_bf(const void *const hw, hri_can_rxf1s_reg_t mask)
+{
+	return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS(mask)) >> CAN_RXF1S_DMS_Pos;
+}
+
+static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_DMS_bf(const void *const hw)
+{
+	return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS_Msk) >> CAN_RXF1S_DMS_Pos;
+}
+
+static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_reg(const void *const hw, hri_can_rxf1s_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF1S.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_reg(const void *const hw)
+{
+	return ((Can *)hw)->RXF1S.reg;
+}
+
+static inline bool hri_can_get_TXFQS_TFQF_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQF) >> CAN_TXFQS_TFQF_Pos;
+}
+
+static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFFL_bf(const void *const hw, hri_can_txfqs_reg_t mask)
+{
+	return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL(mask)) >> CAN_TXFQS_TFFL_Pos;
+}
+
+static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFFL_bf(const void *const hw)
+{
+	return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL_Msk) >> CAN_TXFQS_TFFL_Pos;
+}
+
+static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFGI_bf(const void *const hw, hri_can_txfqs_reg_t mask)
+{
+	return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI(mask)) >> CAN_TXFQS_TFGI_Pos;
+}
+
+static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFGI_bf(const void *const hw)
+{
+	return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI_Msk) >> CAN_TXFQS_TFGI_Pos;
+}
+
+static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFQPI_bf(const void *const hw, hri_can_txfqs_reg_t mask)
+{
+	return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI(mask)) >> CAN_TXFQS_TFQPI_Pos;
+}
+
+static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFQPI_bf(const void *const hw)
+{
+	return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos;
+}
+
+static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_reg(const void *const hw, hri_can_txfqs_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXFQS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_reg(const void *const hw)
+{
+	return ((Can *)hw)->TXFQS.reg;
+}
+
+static inline bool hri_can_get_TXBRP_TRP0_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP0) >> CAN_TXBRP_TRP0_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP1_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP1) >> CAN_TXBRP_TRP1_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP2_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP2) >> CAN_TXBRP_TRP2_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP3_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP3) >> CAN_TXBRP_TRP3_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP4_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP4) >> CAN_TXBRP_TRP4_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP5_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP5) >> CAN_TXBRP_TRP5_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP6_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP6) >> CAN_TXBRP_TRP6_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP7_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP7) >> CAN_TXBRP_TRP7_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP8_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP8) >> CAN_TXBRP_TRP8_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP9_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP9) >> CAN_TXBRP_TRP9_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP10_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP10) >> CAN_TXBRP_TRP10_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP11_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP11) >> CAN_TXBRP_TRP11_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP12_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP12) >> CAN_TXBRP_TRP12_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP13_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP13) >> CAN_TXBRP_TRP13_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP14_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP14) >> CAN_TXBRP_TRP14_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP15_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP15) >> CAN_TXBRP_TRP15_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP16_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP16) >> CAN_TXBRP_TRP16_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP17_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP17) >> CAN_TXBRP_TRP17_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP18_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP18) >> CAN_TXBRP_TRP18_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP19_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP19) >> CAN_TXBRP_TRP19_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP20_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP20) >> CAN_TXBRP_TRP20_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP21_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP21) >> CAN_TXBRP_TRP21_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP22_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP22) >> CAN_TXBRP_TRP22_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP23_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP23) >> CAN_TXBRP_TRP23_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP24_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP24) >> CAN_TXBRP_TRP24_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP25_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP25) >> CAN_TXBRP_TRP25_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP26_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP26) >> CAN_TXBRP_TRP26_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP27_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP27) >> CAN_TXBRP_TRP27_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP28_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP28) >> CAN_TXBRP_TRP28_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP29_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP29) >> CAN_TXBRP_TRP29_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP30_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP30) >> CAN_TXBRP_TRP30_Pos;
+}
+
+static inline bool hri_can_get_TXBRP_TRP31_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP31) >> CAN_TXBRP_TRP31_Pos;
+}
+
+static inline hri_can_txbrp_reg_t hri_can_get_TXBRP_reg(const void *const hw, hri_can_txbrp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBRP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_can_txbrp_reg_t hri_can_read_TXBRP_reg(const void *const hw)
+{
+	return ((Can *)hw)->TXBRP.reg;
+}
+
+static inline bool hri_can_get_TXBTO_TO0_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO0) >> CAN_TXBTO_TO0_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO1_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO1) >> CAN_TXBTO_TO1_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO2_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO2) >> CAN_TXBTO_TO2_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO3_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO3) >> CAN_TXBTO_TO3_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO4_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO4) >> CAN_TXBTO_TO4_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO5_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO5) >> CAN_TXBTO_TO5_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO6_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO6) >> CAN_TXBTO_TO6_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO7_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO7) >> CAN_TXBTO_TO7_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO8_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO8) >> CAN_TXBTO_TO8_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO9_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO9) >> CAN_TXBTO_TO9_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO10_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO10) >> CAN_TXBTO_TO10_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO11_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO11) >> CAN_TXBTO_TO11_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO12_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO12) >> CAN_TXBTO_TO12_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO13_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO13) >> CAN_TXBTO_TO13_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO14_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO14) >> CAN_TXBTO_TO14_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO15_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO15) >> CAN_TXBTO_TO15_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO16_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO16) >> CAN_TXBTO_TO16_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO17_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO17) >> CAN_TXBTO_TO17_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO18_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO18) >> CAN_TXBTO_TO18_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO19_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO19) >> CAN_TXBTO_TO19_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO20_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO20) >> CAN_TXBTO_TO20_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO21_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO21) >> CAN_TXBTO_TO21_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO22_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO22) >> CAN_TXBTO_TO22_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO23_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO23) >> CAN_TXBTO_TO23_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO24_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO24) >> CAN_TXBTO_TO24_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO25_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO25) >> CAN_TXBTO_TO25_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO26_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO26) >> CAN_TXBTO_TO26_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO27_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO27) >> CAN_TXBTO_TO27_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO28_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO28) >> CAN_TXBTO_TO28_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO29_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO29) >> CAN_TXBTO_TO29_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO30_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO30) >> CAN_TXBTO_TO30_Pos;
+}
+
+static inline bool hri_can_get_TXBTO_TO31_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO31) >> CAN_TXBTO_TO31_Pos;
+}
+
+static inline hri_can_txbto_reg_t hri_can_get_TXBTO_reg(const void *const hw, hri_can_txbto_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTO.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_can_txbto_reg_t hri_can_read_TXBTO_reg(const void *const hw)
+{
+	return ((Can *)hw)->TXBTO.reg;
+}
+
+static inline bool hri_can_get_TXBCF_CF0_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF0) >> CAN_TXBCF_CF0_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF1_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF1) >> CAN_TXBCF_CF1_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF2_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF2) >> CAN_TXBCF_CF2_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF3_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF3) >> CAN_TXBCF_CF3_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF4_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF4) >> CAN_TXBCF_CF4_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF5_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF5) >> CAN_TXBCF_CF5_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF6_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF6) >> CAN_TXBCF_CF6_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF7_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF7) >> CAN_TXBCF_CF7_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF8_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF8) >> CAN_TXBCF_CF8_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF9_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF9) >> CAN_TXBCF_CF9_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF10_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF10) >> CAN_TXBCF_CF10_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF11_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF11) >> CAN_TXBCF_CF11_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF12_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF12) >> CAN_TXBCF_CF12_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF13_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF13) >> CAN_TXBCF_CF13_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF14_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF14) >> CAN_TXBCF_CF14_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF15_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF15) >> CAN_TXBCF_CF15_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF16_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF16) >> CAN_TXBCF_CF16_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF17_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF17) >> CAN_TXBCF_CF17_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF18_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF18) >> CAN_TXBCF_CF18_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF19_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF19) >> CAN_TXBCF_CF19_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF20_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF20) >> CAN_TXBCF_CF20_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF21_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF21) >> CAN_TXBCF_CF21_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF22_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF22) >> CAN_TXBCF_CF22_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF23_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF23) >> CAN_TXBCF_CF23_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF24_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF24) >> CAN_TXBCF_CF24_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF25_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF25) >> CAN_TXBCF_CF25_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF26_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF26) >> CAN_TXBCF_CF26_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF27_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF27) >> CAN_TXBCF_CF27_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF28_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF28) >> CAN_TXBCF_CF28_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF29_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF29) >> CAN_TXBCF_CF29_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF30_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF30) >> CAN_TXBCF_CF30_Pos;
+}
+
+static inline bool hri_can_get_TXBCF_CF31_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF31) >> CAN_TXBCF_CF31_Pos;
+}
+
+static inline hri_can_txbcf_reg_t hri_can_get_TXBCF_reg(const void *const hw, hri_can_txbcf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_can_txbcf_reg_t hri_can_read_TXBCF_reg(const void *const hw)
+{
+	return ((Can *)hw)->TXBCF.reg;
+}
+
+static inline bool hri_can_get_TXEFS_EFF_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFF) >> CAN_TXEFS_EFF_Pos;
+}
+
+static inline bool hri_can_get_TXEFS_TEFL_bit(const void *const hw)
+{
+	return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_TEFL) >> CAN_TXEFS_TEFL_Pos;
+}
+
+static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFFL_bf(const void *const hw, hri_can_txefs_reg_t mask)
+{
+	return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL(mask)) >> CAN_TXEFS_EFFL_Pos;
+}
+
+static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFFL_bf(const void *const hw)
+{
+	return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL_Msk) >> CAN_TXEFS_EFFL_Pos;
+}
+
+static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFGI_bf(const void *const hw, hri_can_txefs_reg_t mask)
+{
+	return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI(mask)) >> CAN_TXEFS_EFGI_Pos;
+}
+
+static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFGI_bf(const void *const hw)
+{
+	return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI_Msk) >> CAN_TXEFS_EFGI_Pos;
+}
+
+static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFPI_bf(const void *const hw, hri_can_txefs_reg_t mask)
+{
+	return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI(mask)) >> CAN_TXEFS_EFPI_Pos;
+}
+
+static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFPI_bf(const void *const hw)
+{
+	return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI_Msk) >> CAN_TXEFS_EFPI_Pos;
+}
+
+static inline hri_can_txefs_reg_t hri_can_get_TXEFS_reg(const void *const hw, hri_can_txefs_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXEFS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_can_txefs_reg_t hri_can_read_TXEFS_reg(const void *const hw)
+{
+	return ((Can *)hw)->TXEFS.reg;
+}
+
+static inline void hri_can_set_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->MRCFG.reg |= CAN_MRCFG_QOS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->MRCFG.reg;
+	tmp = (tmp & CAN_MRCFG_QOS(mask)) >> CAN_MRCFG_QOS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->MRCFG.reg;
+	tmp &= ~CAN_MRCFG_QOS_Msk;
+	tmp |= CAN_MRCFG_QOS(data);
+	((Can *)hw)->MRCFG.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->MRCFG.reg &= ~CAN_MRCFG_QOS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->MRCFG.reg ^= CAN_MRCFG_QOS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_QOS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->MRCFG.reg;
+	tmp = (tmp & CAN_MRCFG_QOS_Msk) >> CAN_MRCFG_QOS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->MRCFG.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->MRCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->MRCFG.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->MRCFG.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->MRCFG.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_reg(const void *const hw)
+{
+	return ((Can *)hw)->MRCFG.reg;
+}
+
+static inline void hri_can_set_DBTP_TDC_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->DBTP.reg |= CAN_DBTP_TDC;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_DBTP_TDC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->DBTP.reg;
+	tmp = (tmp & CAN_DBTP_TDC) >> CAN_DBTP_TDC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_DBTP_TDC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->DBTP.reg;
+	tmp &= ~CAN_DBTP_TDC;
+	tmp |= value << CAN_DBTP_TDC_Pos;
+	((Can *)hw)->DBTP.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_DBTP_TDC_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->DBTP.reg &= ~CAN_DBTP_TDC;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_DBTP_TDC_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->DBTP.reg ^= CAN_DBTP_TDC;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->DBTP.reg |= CAN_DBTP_DSJW(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->DBTP.reg;
+	tmp = (tmp & CAN_DBTP_DSJW(mask)) >> CAN_DBTP_DSJW_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->DBTP.reg;
+	tmp &= ~CAN_DBTP_DSJW_Msk;
+	tmp |= CAN_DBTP_DSJW(data);
+	((Can *)hw)->DBTP.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DSJW(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->DBTP.reg ^= CAN_DBTP_DSJW(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DSJW_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->DBTP.reg;
+	tmp = (tmp & CAN_DBTP_DSJW_Msk) >> CAN_DBTP_DSJW_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG2(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->DBTP.reg;
+	tmp = (tmp & CAN_DBTP_DTSEG2(mask)) >> CAN_DBTP_DTSEG2_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->DBTP.reg;
+	tmp &= ~CAN_DBTP_DTSEG2_Msk;
+	tmp |= CAN_DBTP_DTSEG2(data);
+	((Can *)hw)->DBTP.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG2(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG2(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->DBTP.reg;
+	tmp = (tmp & CAN_DBTP_DTSEG2_Msk) >> CAN_DBTP_DTSEG2_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG1(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->DBTP.reg;
+	tmp = (tmp & CAN_DBTP_DTSEG1(mask)) >> CAN_DBTP_DTSEG1_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->DBTP.reg;
+	tmp &= ~CAN_DBTP_DTSEG1_Msk;
+	tmp |= CAN_DBTP_DTSEG1(data);
+	((Can *)hw)->DBTP.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG1(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG1(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->DBTP.reg;
+	tmp = (tmp & CAN_DBTP_DTSEG1_Msk) >> CAN_DBTP_DTSEG1_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->DBTP.reg |= CAN_DBTP_DBRP(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->DBTP.reg;
+	tmp = (tmp & CAN_DBTP_DBRP(mask)) >> CAN_DBTP_DBRP_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->DBTP.reg;
+	tmp &= ~CAN_DBTP_DBRP_Msk;
+	tmp |= CAN_DBTP_DBRP(data);
+	((Can *)hw)->DBTP.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DBRP(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->DBTP.reg ^= CAN_DBTP_DBRP(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DBRP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->DBTP.reg;
+	tmp = (tmp & CAN_DBTP_DBRP_Msk) >> CAN_DBTP_DBRP_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->DBTP.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_dbtp_reg_t hri_can_get_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->DBTP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->DBTP.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->DBTP.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->DBTP.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_dbtp_reg_t hri_can_read_DBTP_reg(const void *const hw)
+{
+	return ((Can *)hw)->DBTP.reg;
+}
+
+static inline void hri_can_set_TEST_LBCK_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TEST.reg |= CAN_TEST_LBCK;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TEST_LBCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TEST.reg;
+	tmp = (tmp & CAN_TEST_LBCK) >> CAN_TEST_LBCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TEST_LBCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TEST.reg;
+	tmp &= ~CAN_TEST_LBCK;
+	tmp |= value << CAN_TEST_LBCK_Pos;
+	((Can *)hw)->TEST.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TEST_LBCK_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TEST.reg &= ~CAN_TEST_LBCK;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TEST_LBCK_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TEST.reg ^= CAN_TEST_LBCK;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TEST_RX_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TEST.reg |= CAN_TEST_RX;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TEST_RX_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TEST.reg;
+	tmp = (tmp & CAN_TEST_RX) >> CAN_TEST_RX_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TEST_RX_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TEST.reg;
+	tmp &= ~CAN_TEST_RX;
+	tmp |= value << CAN_TEST_RX_Pos;
+	((Can *)hw)->TEST.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TEST_RX_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TEST.reg &= ~CAN_TEST_RX;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TEST_RX_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TEST.reg ^= CAN_TEST_RX;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TEST.reg |= CAN_TEST_TX(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_test_reg_t hri_can_get_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TEST.reg;
+	tmp = (tmp & CAN_TEST_TX(mask)) >> CAN_TEST_TX_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_TEST_TX_bf(const void *const hw, hri_can_test_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TEST.reg;
+	tmp &= ~CAN_TEST_TX_Msk;
+	tmp |= CAN_TEST_TX(data);
+	((Can *)hw)->TEST.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TEST.reg &= ~CAN_TEST_TX(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TEST.reg ^= CAN_TEST_TX(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_test_reg_t hri_can_read_TEST_TX_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TEST.reg;
+	tmp = (tmp & CAN_TEST_TX_Msk) >> CAN_TEST_TX_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_TEST_reg(const void *const hw, hri_can_test_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TEST.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_test_reg_t hri_can_get_TEST_reg(const void *const hw, hri_can_test_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TEST.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_TEST_reg(const void *const hw, hri_can_test_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TEST.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TEST_reg(const void *const hw, hri_can_test_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TEST.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TEST_reg(const void *const hw, hri_can_test_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TEST.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_test_reg_t hri_can_read_TEST_reg(const void *const hw)
+{
+	return ((Can *)hw)->TEST.reg;
+}
+
+static inline void hri_can_set_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RWD.reg |= CAN_RWD_WDC(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rwd_reg_t hri_can_get_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RWD.reg;
+	tmp = (tmp & CAN_RWD_WDC(mask)) >> CAN_RWD_WDC_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->RWD.reg;
+	tmp &= ~CAN_RWD_WDC_Msk;
+	tmp |= CAN_RWD_WDC(data);
+	((Can *)hw)->RWD.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RWD.reg &= ~CAN_RWD_WDC(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RWD.reg ^= CAN_RWD_WDC(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rwd_reg_t hri_can_read_RWD_WDC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RWD.reg;
+	tmp = (tmp & CAN_RWD_WDC_Msk) >> CAN_RWD_WDC_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RWD.reg |= CAN_RWD_WDV(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rwd_reg_t hri_can_get_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RWD.reg;
+	tmp = (tmp & CAN_RWD_WDV(mask)) >> CAN_RWD_WDV_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->RWD.reg;
+	tmp &= ~CAN_RWD_WDV_Msk;
+	tmp |= CAN_RWD_WDV(data);
+	((Can *)hw)->RWD.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RWD.reg &= ~CAN_RWD_WDV(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RWD.reg ^= CAN_RWD_WDV(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rwd_reg_t hri_can_read_RWD_WDV_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RWD.reg;
+	tmp = (tmp & CAN_RWD_WDV_Msk) >> CAN_RWD_WDV_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RWD.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rwd_reg_t hri_can_get_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RWD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_RWD_reg(const void *const hw, hri_can_rwd_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RWD.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RWD.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RWD.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rwd_reg_t hri_can_read_RWD_reg(const void *const hw)
+{
+	return ((Can *)hw)->RWD.reg;
+}
+
+static inline void hri_can_set_CCCR_INIT_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg |= CAN_CCCR_INIT;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_CCCR_INIT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp = (tmp & CAN_CCCR_INIT) >> CAN_CCCR_INIT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_CCCR_INIT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp &= ~CAN_CCCR_INIT;
+	tmp |= value << CAN_CCCR_INIT_Pos;
+	((Can *)hw)->CCCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_CCCR_INIT_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg &= ~CAN_CCCR_INIT;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_CCCR_INIT_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg ^= CAN_CCCR_INIT;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_CCCR_CCE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg |= CAN_CCCR_CCE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_CCCR_CCE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp = (tmp & CAN_CCCR_CCE) >> CAN_CCCR_CCE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_CCCR_CCE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp &= ~CAN_CCCR_CCE;
+	tmp |= value << CAN_CCCR_CCE_Pos;
+	((Can *)hw)->CCCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_CCCR_CCE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CCE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_CCCR_CCE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg ^= CAN_CCCR_CCE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_CCCR_ASM_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg |= CAN_CCCR_ASM;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_CCCR_ASM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp = (tmp & CAN_CCCR_ASM) >> CAN_CCCR_ASM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_CCCR_ASM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp &= ~CAN_CCCR_ASM;
+	tmp |= value << CAN_CCCR_ASM_Pos;
+	((Can *)hw)->CCCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_CCCR_ASM_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg &= ~CAN_CCCR_ASM;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_CCCR_ASM_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg ^= CAN_CCCR_ASM;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_CCCR_CSA_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg |= CAN_CCCR_CSA;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_CCCR_CSA_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp = (tmp & CAN_CCCR_CSA) >> CAN_CCCR_CSA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_CCCR_CSA_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp &= ~CAN_CCCR_CSA;
+	tmp |= value << CAN_CCCR_CSA_Pos;
+	((Can *)hw)->CCCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_CCCR_CSA_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSA;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_CCCR_CSA_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSA;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_CCCR_CSR_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg |= CAN_CCCR_CSR;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_CCCR_CSR_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp = (tmp & CAN_CCCR_CSR) >> CAN_CCCR_CSR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_CCCR_CSR_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp &= ~CAN_CCCR_CSR;
+	tmp |= value << CAN_CCCR_CSR_Pos;
+	((Can *)hw)->CCCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_CCCR_CSR_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSR;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_CCCR_CSR_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSR;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_CCCR_MON_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg |= CAN_CCCR_MON;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_CCCR_MON_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp = (tmp & CAN_CCCR_MON) >> CAN_CCCR_MON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_CCCR_MON_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp &= ~CAN_CCCR_MON;
+	tmp |= value << CAN_CCCR_MON_Pos;
+	((Can *)hw)->CCCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_CCCR_MON_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg &= ~CAN_CCCR_MON;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_CCCR_MON_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg ^= CAN_CCCR_MON;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_CCCR_DAR_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg |= CAN_CCCR_DAR;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_CCCR_DAR_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp = (tmp & CAN_CCCR_DAR) >> CAN_CCCR_DAR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_CCCR_DAR_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp &= ~CAN_CCCR_DAR;
+	tmp |= value << CAN_CCCR_DAR_Pos;
+	((Can *)hw)->CCCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_CCCR_DAR_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg &= ~CAN_CCCR_DAR;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_CCCR_DAR_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg ^= CAN_CCCR_DAR;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_CCCR_TEST_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg |= CAN_CCCR_TEST;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_CCCR_TEST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp = (tmp & CAN_CCCR_TEST) >> CAN_CCCR_TEST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_CCCR_TEST_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp &= ~CAN_CCCR_TEST;
+	tmp |= value << CAN_CCCR_TEST_Pos;
+	((Can *)hw)->CCCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_CCCR_TEST_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TEST;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_CCCR_TEST_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg ^= CAN_CCCR_TEST;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_CCCR_FDOE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg |= CAN_CCCR_FDOE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_CCCR_FDOE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp = (tmp & CAN_CCCR_FDOE) >> CAN_CCCR_FDOE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_CCCR_FDOE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp &= ~CAN_CCCR_FDOE;
+	tmp |= value << CAN_CCCR_FDOE_Pos;
+	((Can *)hw)->CCCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_CCCR_FDOE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg &= ~CAN_CCCR_FDOE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_CCCR_FDOE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg ^= CAN_CCCR_FDOE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_CCCR_BRSE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg |= CAN_CCCR_BRSE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_CCCR_BRSE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp = (tmp & CAN_CCCR_BRSE) >> CAN_CCCR_BRSE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_CCCR_BRSE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp &= ~CAN_CCCR_BRSE;
+	tmp |= value << CAN_CCCR_BRSE_Pos;
+	((Can *)hw)->CCCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_CCCR_BRSE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg &= ~CAN_CCCR_BRSE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_CCCR_BRSE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg ^= CAN_CCCR_BRSE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_CCCR_PXHD_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg |= CAN_CCCR_PXHD;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_CCCR_PXHD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp = (tmp & CAN_CCCR_PXHD) >> CAN_CCCR_PXHD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_CCCR_PXHD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp &= ~CAN_CCCR_PXHD;
+	tmp |= value << CAN_CCCR_PXHD_Pos;
+	((Can *)hw)->CCCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_CCCR_PXHD_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg &= ~CAN_CCCR_PXHD;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_CCCR_PXHD_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg ^= CAN_CCCR_PXHD;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_CCCR_EFBI_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg |= CAN_CCCR_EFBI;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_CCCR_EFBI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp = (tmp & CAN_CCCR_EFBI) >> CAN_CCCR_EFBI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_CCCR_EFBI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp &= ~CAN_CCCR_EFBI;
+	tmp |= value << CAN_CCCR_EFBI_Pos;
+	((Can *)hw)->CCCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_CCCR_EFBI_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg &= ~CAN_CCCR_EFBI;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_CCCR_EFBI_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg ^= CAN_CCCR_EFBI;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_CCCR_TXP_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg |= CAN_CCCR_TXP;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_CCCR_TXP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp = (tmp & CAN_CCCR_TXP) >> CAN_CCCR_TXP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_CCCR_TXP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp &= ~CAN_CCCR_TXP;
+	tmp |= value << CAN_CCCR_TXP_Pos;
+	((Can *)hw)->CCCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_CCCR_TXP_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TXP;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_CCCR_TXP_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg ^= CAN_CCCR_TXP;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_CCCR_NISO_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg |= CAN_CCCR_NISO;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_CCCR_NISO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp = (tmp & CAN_CCCR_NISO) >> CAN_CCCR_NISO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_CCCR_NISO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp &= ~CAN_CCCR_NISO;
+	tmp |= value << CAN_CCCR_NISO_Pos;
+	((Can *)hw)->CCCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_CCCR_NISO_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg &= ~CAN_CCCR_NISO;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_CCCR_NISO_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg ^= CAN_CCCR_NISO;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_cccr_reg_t hri_can_get_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->CCCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_CCCR_reg(const void *const hw, hri_can_cccr_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->CCCR.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_cccr_reg_t hri_can_read_CCCR_reg(const void *const hw)
+{
+	return ((Can *)hw)->CCCR.reg;
+}
+
+static inline void hri_can_set_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG2(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NBTP.reg;
+	tmp = (tmp & CAN_NBTP_NTSEG2(mask)) >> CAN_NBTP_NTSEG2_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NBTP.reg;
+	tmp &= ~CAN_NBTP_NTSEG2_Msk;
+	tmp |= CAN_NBTP_NTSEG2(data);
+	((Can *)hw)->NBTP.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG2(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG2(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NBTP.reg;
+	tmp = (tmp & CAN_NBTP_NTSEG2_Msk) >> CAN_NBTP_NTSEG2_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG1(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NBTP.reg;
+	tmp = (tmp & CAN_NBTP_NTSEG1(mask)) >> CAN_NBTP_NTSEG1_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NBTP.reg;
+	tmp &= ~CAN_NBTP_NTSEG1_Msk;
+	tmp |= CAN_NBTP_NTSEG1(data);
+	((Can *)hw)->NBTP.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG1(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG1(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NBTP.reg;
+	tmp = (tmp & CAN_NBTP_NTSEG1_Msk) >> CAN_NBTP_NTSEG1_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NBTP.reg |= CAN_NBTP_NBRP(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NBTP.reg;
+	tmp = (tmp & CAN_NBTP_NBRP(mask)) >> CAN_NBTP_NBRP_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NBTP.reg;
+	tmp &= ~CAN_NBTP_NBRP_Msk;
+	tmp |= CAN_NBTP_NBRP(data);
+	((Can *)hw)->NBTP.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NBRP(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NBTP.reg ^= CAN_NBTP_NBRP(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NBRP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NBTP.reg;
+	tmp = (tmp & CAN_NBTP_NBRP_Msk) >> CAN_NBTP_NBRP_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NBTP.reg |= CAN_NBTP_NSJW(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NBTP.reg;
+	tmp = (tmp & CAN_NBTP_NSJW(mask)) >> CAN_NBTP_NSJW_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NBTP.reg;
+	tmp &= ~CAN_NBTP_NSJW_Msk;
+	tmp |= CAN_NBTP_NSJW(data);
+	((Can *)hw)->NBTP.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NSJW(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NBTP.reg ^= CAN_NBTP_NSJW(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NSJW_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NBTP.reg;
+	tmp = (tmp & CAN_NBTP_NSJW_Msk) >> CAN_NBTP_NSJW_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NBTP.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_nbtp_reg_t hri_can_get_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NBTP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NBTP.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NBTP.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NBTP.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_nbtp_reg_t hri_can_read_NBTP_reg(const void *const hw)
+{
+	return ((Can *)hw)->NBTP.reg;
+}
+
+static inline void hri_can_set_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TSCC.reg |= CAN_TSCC_TSS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tscc_reg_t hri_can_get_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TSCC.reg;
+	tmp = (tmp & CAN_TSCC_TSS(mask)) >> CAN_TSCC_TSS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TSCC.reg;
+	tmp &= ~CAN_TSCC_TSS_Msk;
+	tmp |= CAN_TSCC_TSS(data);
+	((Can *)hw)->TSCC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TSS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TSCC.reg ^= CAN_TSCC_TSS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tscc_reg_t hri_can_read_TSCC_TSS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TSCC.reg;
+	tmp = (tmp & CAN_TSCC_TSS_Msk) >> CAN_TSCC_TSS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TSCC.reg |= CAN_TSCC_TCP(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tscc_reg_t hri_can_get_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TSCC.reg;
+	tmp = (tmp & CAN_TSCC_TCP(mask)) >> CAN_TSCC_TCP_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TSCC.reg;
+	tmp &= ~CAN_TSCC_TCP_Msk;
+	tmp |= CAN_TSCC_TCP(data);
+	((Can *)hw)->TSCC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TCP(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TSCC.reg ^= CAN_TSCC_TCP(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tscc_reg_t hri_can_read_TSCC_TCP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TSCC.reg;
+	tmp = (tmp & CAN_TSCC_TCP_Msk) >> CAN_TSCC_TCP_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TSCC.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tscc_reg_t hri_can_get_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TSCC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_TSCC_reg(const void *const hw, hri_can_tscc_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TSCC.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TSCC.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TSCC.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tscc_reg_t hri_can_read_TSCC_reg(const void *const hw)
+{
+	return ((Can *)hw)->TSCC.reg;
+}
+
+static inline void hri_can_set_TOCC_ETOC_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCC.reg |= CAN_TOCC_ETOC;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TOCC_ETOC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TOCC.reg;
+	tmp = (tmp & CAN_TOCC_ETOC) >> CAN_TOCC_ETOC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TOCC_ETOC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TOCC.reg;
+	tmp &= ~CAN_TOCC_ETOC;
+	tmp |= value << CAN_TOCC_ETOC_Pos;
+	((Can *)hw)->TOCC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TOCC_ETOC_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCC.reg &= ~CAN_TOCC_ETOC;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TOCC_ETOC_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCC.reg ^= CAN_TOCC_ETOC;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCC.reg |= CAN_TOCC_TOS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TOCC.reg;
+	tmp = (tmp & CAN_TOCC_TOS(mask)) >> CAN_TOCC_TOS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TOCC.reg;
+	tmp &= ~CAN_TOCC_TOS_Msk;
+	tmp |= CAN_TOCC_TOS(data);
+	((Can *)hw)->TOCC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TOCC.reg;
+	tmp = (tmp & CAN_TOCC_TOS_Msk) >> CAN_TOCC_TOS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCC.reg |= CAN_TOCC_TOP(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TOCC.reg;
+	tmp = (tmp & CAN_TOCC_TOP(mask)) >> CAN_TOCC_TOP_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TOCC.reg;
+	tmp &= ~CAN_TOCC_TOP_Msk;
+	tmp |= CAN_TOCC_TOP(data);
+	((Can *)hw)->TOCC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOP(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOP(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TOCC.reg;
+	tmp = (tmp & CAN_TOCC_TOP_Msk) >> CAN_TOCC_TOP_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCC.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tocc_reg_t hri_can_get_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TOCC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_TOCC_reg(const void *const hw, hri_can_tocc_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCC.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCC.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCC.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tocc_reg_t hri_can_read_TOCC_reg(const void *const hw)
+{
+	return ((Can *)hw)->TOCC.reg;
+}
+
+static inline void hri_can_set_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCV.reg |= CAN_TOCV_TOC(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tocv_reg_t hri_can_get_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TOCV.reg;
+	tmp = (tmp & CAN_TOCV_TOC(mask)) >> CAN_TOCV_TOC_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TOCV.reg;
+	tmp &= ~CAN_TOCV_TOC_Msk;
+	tmp |= CAN_TOCV_TOC(data);
+	((Can *)hw)->TOCV.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCV.reg &= ~CAN_TOCV_TOC(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCV.reg ^= CAN_TOCV_TOC(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tocv_reg_t hri_can_read_TOCV_TOC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TOCV.reg;
+	tmp = (tmp & CAN_TOCV_TOC_Msk) >> CAN_TOCV_TOC_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCV.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tocv_reg_t hri_can_get_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TOCV.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_TOCV_reg(const void *const hw, hri_can_tocv_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCV.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCV.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TOCV.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tocv_reg_t hri_can_read_TOCV_reg(const void *const hw)
+{
+	return ((Can *)hw)->TOCV.reg;
+}
+
+static inline void hri_can_set_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCF(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TDCR.reg;
+	tmp = (tmp & CAN_TDCR_TDCF(mask)) >> CAN_TDCR_TDCF_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TDCR.reg;
+	tmp &= ~CAN_TDCR_TDCF_Msk;
+	tmp |= CAN_TDCR_TDCF(data);
+	((Can *)hw)->TDCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCF(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCF(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TDCR.reg;
+	tmp = (tmp & CAN_TDCR_TDCF_Msk) >> CAN_TDCR_TDCF_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCO(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TDCR.reg;
+	tmp = (tmp & CAN_TDCR_TDCO(mask)) >> CAN_TDCR_TDCO_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TDCR.reg;
+	tmp &= ~CAN_TDCR_TDCO_Msk;
+	tmp |= CAN_TDCR_TDCO(data);
+	((Can *)hw)->TDCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCO(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCO(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TDCR.reg;
+	tmp = (tmp & CAN_TDCR_TDCO_Msk) >> CAN_TDCR_TDCO_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TDCR.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tdcr_reg_t hri_can_get_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TDCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TDCR.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TDCR.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TDCR.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_tdcr_reg_t hri_can_read_TDCR_reg(const void *const hw)
+{
+	return ((Can *)hw)->TDCR.reg;
+}
+
+static inline void hri_can_set_IR_RF0N_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_RF0N;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_RF0N_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_RF0N) >> CAN_IR_RF0N_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_RF0N_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_RF0N;
+	tmp |= value << CAN_IR_RF0N_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_RF0N_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_RF0N;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_RF0N_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_RF0N;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_RF0W_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_RF0W;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_RF0W_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_RF0W) >> CAN_IR_RF0W_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_RF0W_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_RF0W;
+	tmp |= value << CAN_IR_RF0W_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_RF0W_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_RF0W;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_RF0W_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_RF0W;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_RF0F_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_RF0F;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_RF0F_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_RF0F) >> CAN_IR_RF0F_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_RF0F_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_RF0F;
+	tmp |= value << CAN_IR_RF0F_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_RF0F_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_RF0F;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_RF0F_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_RF0F;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_RF0L_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_RF0L;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_RF0L_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_RF0L) >> CAN_IR_RF0L_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_RF0L_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_RF0L;
+	tmp |= value << CAN_IR_RF0L_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_RF0L_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_RF0L;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_RF0L_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_RF0L;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_RF1N_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_RF1N;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_RF1N_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_RF1N) >> CAN_IR_RF1N_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_RF1N_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_RF1N;
+	tmp |= value << CAN_IR_RF1N_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_RF1N_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_RF1N;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_RF1N_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_RF1N;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_RF1W_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_RF1W;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_RF1W_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_RF1W) >> CAN_IR_RF1W_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_RF1W_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_RF1W;
+	tmp |= value << CAN_IR_RF1W_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_RF1W_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_RF1W;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_RF1W_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_RF1W;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_RF1F_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_RF1F;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_RF1F_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_RF1F) >> CAN_IR_RF1F_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_RF1F_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_RF1F;
+	tmp |= value << CAN_IR_RF1F_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_RF1F_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_RF1F;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_RF1F_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_RF1F;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_RF1L_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_RF1L;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_RF1L_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_RF1L) >> CAN_IR_RF1L_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_RF1L_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_RF1L;
+	tmp |= value << CAN_IR_RF1L_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_RF1L_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_RF1L;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_RF1L_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_RF1L;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_HPM_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_HPM;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_HPM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_HPM) >> CAN_IR_HPM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_HPM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_HPM;
+	tmp |= value << CAN_IR_HPM_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_HPM_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_HPM;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_HPM_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_HPM;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_TC_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_TC;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_TC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_TC) >> CAN_IR_TC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_TC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_TC;
+	tmp |= value << CAN_IR_TC_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_TC_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_TC;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_TC_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_TC;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_TCF_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_TCF;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_TCF_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_TCF) >> CAN_IR_TCF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_TCF_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_TCF;
+	tmp |= value << CAN_IR_TCF_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_TCF_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_TCF;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_TCF_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_TCF;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_TFE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_TFE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_TFE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_TFE) >> CAN_IR_TFE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_TFE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_TFE;
+	tmp |= value << CAN_IR_TFE_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_TFE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_TFE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_TFE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_TFE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_TEFN_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_TEFN;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_TEFN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_TEFN) >> CAN_IR_TEFN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_TEFN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_TEFN;
+	tmp |= value << CAN_IR_TEFN_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_TEFN_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_TEFN;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_TEFN_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_TEFN;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_TEFW_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_TEFW;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_TEFW_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_TEFW) >> CAN_IR_TEFW_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_TEFW_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_TEFW;
+	tmp |= value << CAN_IR_TEFW_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_TEFW_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_TEFW;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_TEFW_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_TEFW;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_TEFF_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_TEFF;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_TEFF_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_TEFF) >> CAN_IR_TEFF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_TEFF_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_TEFF;
+	tmp |= value << CAN_IR_TEFF_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_TEFF_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_TEFF;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_TEFF_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_TEFF;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_TEFL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_TEFL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_TEFL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_TEFL) >> CAN_IR_TEFL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_TEFL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_TEFL;
+	tmp |= value << CAN_IR_TEFL_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_TEFL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_TEFL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_TEFL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_TEFL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_TSW_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_TSW;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_TSW_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_TSW) >> CAN_IR_TSW_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_TSW_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_TSW;
+	tmp |= value << CAN_IR_TSW_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_TSW_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_TSW;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_TSW_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_TSW;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_MRAF_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_MRAF;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_MRAF_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_MRAF) >> CAN_IR_MRAF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_MRAF_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_MRAF;
+	tmp |= value << CAN_IR_MRAF_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_MRAF_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_MRAF;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_MRAF_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_MRAF;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_TOO_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_TOO;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_TOO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_TOO) >> CAN_IR_TOO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_TOO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_TOO;
+	tmp |= value << CAN_IR_TOO_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_TOO_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_TOO;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_TOO_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_TOO;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_DRX_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_DRX;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_DRX_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_DRX) >> CAN_IR_DRX_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_DRX_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_DRX;
+	tmp |= value << CAN_IR_DRX_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_DRX_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_DRX;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_DRX_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_DRX;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_BEC_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_BEC;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_BEC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_BEC) >> CAN_IR_BEC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_BEC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_BEC;
+	tmp |= value << CAN_IR_BEC_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_BEC_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_BEC;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_BEC_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_BEC;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_BEU_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_BEU;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_BEU_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_BEU) >> CAN_IR_BEU_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_BEU_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_BEU;
+	tmp |= value << CAN_IR_BEU_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_BEU_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_BEU;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_BEU_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_BEU;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_ELO_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_ELO;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_ELO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_ELO) >> CAN_IR_ELO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_ELO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_ELO;
+	tmp |= value << CAN_IR_ELO_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_ELO_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_ELO;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_ELO_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_ELO;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_EP_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_EP;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_EP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_EP) >> CAN_IR_EP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_EP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_EP;
+	tmp |= value << CAN_IR_EP_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_EP_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_EP;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_EP_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_EP;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_EW_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_EW;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_EW_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_EW) >> CAN_IR_EW_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_EW_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_EW;
+	tmp |= value << CAN_IR_EW_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_EW_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_EW;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_EW_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_EW;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_BO_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_BO;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_BO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_BO) >> CAN_IR_BO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_BO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_BO;
+	tmp |= value << CAN_IR_BO_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_BO_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_BO;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_BO_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_BO;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_WDI_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_WDI;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_WDI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_WDI) >> CAN_IR_WDI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_WDI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_WDI;
+	tmp |= value << CAN_IR_WDI_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_WDI_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_WDI;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_WDI_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_WDI;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_PEA_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_PEA;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_PEA_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_PEA) >> CAN_IR_PEA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_PEA_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_PEA;
+	tmp |= value << CAN_IR_PEA_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_PEA_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_PEA;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_PEA_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_PEA;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_PED_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_PED;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_PED_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_PED) >> CAN_IR_PED_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_PED_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_PED;
+	tmp |= value << CAN_IR_PED_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_PED_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_PED;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_PED_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_PED;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_ARA_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= CAN_IR_ARA;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IR_ARA_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp = (tmp & CAN_IR_ARA) >> CAN_IR_ARA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IR_ARA_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= ~CAN_IR_ARA;
+	tmp |= value << CAN_IR_ARA_Pos;
+	((Can *)hw)->IR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_ARA_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~CAN_IR_ARA;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_ARA_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= CAN_IR_ARA;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IR_reg(const void *const hw, hri_can_ir_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_ir_reg_t hri_can_get_IR_reg(const void *const hw, hri_can_ir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_IR_reg(const void *const hw, hri_can_ir_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IR_reg(const void *const hw, hri_can_ir_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IR_reg(const void *const hw, hri_can_ir_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IR.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_ir_reg_t hri_can_read_IR_reg(const void *const hw)
+{
+	return ((Can *)hw)->IR.reg;
+}
+
+static inline void hri_can_set_IE_RF0NE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_RF0NE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_RF0NE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_RF0NE) >> CAN_IE_RF0NE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_RF0NE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_RF0NE;
+	tmp |= value << CAN_IE_RF0NE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_RF0NE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_RF0NE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_RF0NE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_RF0NE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_RF0WE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_RF0WE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_RF0WE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_RF0WE) >> CAN_IE_RF0WE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_RF0WE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_RF0WE;
+	tmp |= value << CAN_IE_RF0WE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_RF0WE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_RF0WE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_RF0WE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_RF0WE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_RF0FE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_RF0FE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_RF0FE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_RF0FE) >> CAN_IE_RF0FE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_RF0FE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_RF0FE;
+	tmp |= value << CAN_IE_RF0FE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_RF0FE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_RF0FE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_RF0FE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_RF0FE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_RF0LE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_RF0LE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_RF0LE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_RF0LE) >> CAN_IE_RF0LE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_RF0LE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_RF0LE;
+	tmp |= value << CAN_IE_RF0LE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_RF0LE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_RF0LE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_RF0LE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_RF0LE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_RF1NE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_RF1NE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_RF1NE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_RF1NE) >> CAN_IE_RF1NE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_RF1NE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_RF1NE;
+	tmp |= value << CAN_IE_RF1NE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_RF1NE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_RF1NE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_RF1NE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_RF1NE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_RF1WE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_RF1WE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_RF1WE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_RF1WE) >> CAN_IE_RF1WE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_RF1WE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_RF1WE;
+	tmp |= value << CAN_IE_RF1WE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_RF1WE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_RF1WE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_RF1WE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_RF1WE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_RF1FE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_RF1FE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_RF1FE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_RF1FE) >> CAN_IE_RF1FE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_RF1FE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_RF1FE;
+	tmp |= value << CAN_IE_RF1FE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_RF1FE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_RF1FE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_RF1FE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_RF1FE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_RF1LE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_RF1LE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_RF1LE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_RF1LE) >> CAN_IE_RF1LE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_RF1LE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_RF1LE;
+	tmp |= value << CAN_IE_RF1LE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_RF1LE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_RF1LE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_RF1LE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_RF1LE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_HPME_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_HPME;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_HPME_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_HPME) >> CAN_IE_HPME_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_HPME_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_HPME;
+	tmp |= value << CAN_IE_HPME_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_HPME_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_HPME;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_HPME_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_HPME;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_TCE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_TCE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_TCE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_TCE) >> CAN_IE_TCE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_TCE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_TCE;
+	tmp |= value << CAN_IE_TCE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_TCE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_TCE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_TCE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_TCE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_TCFE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_TCFE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_TCFE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_TCFE) >> CAN_IE_TCFE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_TCFE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_TCFE;
+	tmp |= value << CAN_IE_TCFE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_TCFE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_TCFE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_TCFE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_TCFE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_TFEE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_TFEE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_TFEE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_TFEE) >> CAN_IE_TFEE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_TFEE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_TFEE;
+	tmp |= value << CAN_IE_TFEE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_TFEE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_TFEE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_TFEE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_TFEE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_TEFNE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_TEFNE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_TEFNE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_TEFNE) >> CAN_IE_TEFNE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_TEFNE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_TEFNE;
+	tmp |= value << CAN_IE_TEFNE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_TEFNE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_TEFNE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_TEFNE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_TEFNE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_TEFWE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_TEFWE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_TEFWE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_TEFWE) >> CAN_IE_TEFWE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_TEFWE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_TEFWE;
+	tmp |= value << CAN_IE_TEFWE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_TEFWE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_TEFWE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_TEFWE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_TEFWE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_TEFFE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_TEFFE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_TEFFE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_TEFFE) >> CAN_IE_TEFFE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_TEFFE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_TEFFE;
+	tmp |= value << CAN_IE_TEFFE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_TEFFE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_TEFFE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_TEFFE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_TEFFE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_TEFLE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_TEFLE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_TEFLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_TEFLE) >> CAN_IE_TEFLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_TEFLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_TEFLE;
+	tmp |= value << CAN_IE_TEFLE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_TEFLE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_TEFLE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_TEFLE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_TEFLE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_TSWE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_TSWE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_TSWE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_TSWE) >> CAN_IE_TSWE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_TSWE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_TSWE;
+	tmp |= value << CAN_IE_TSWE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_TSWE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_TSWE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_TSWE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_TSWE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_MRAFE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_MRAFE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_MRAFE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_MRAFE) >> CAN_IE_MRAFE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_MRAFE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_MRAFE;
+	tmp |= value << CAN_IE_MRAFE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_MRAFE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_MRAFE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_MRAFE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_MRAFE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_TOOE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_TOOE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_TOOE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_TOOE) >> CAN_IE_TOOE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_TOOE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_TOOE;
+	tmp |= value << CAN_IE_TOOE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_TOOE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_TOOE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_TOOE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_TOOE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_DRXE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_DRXE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_DRXE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_DRXE) >> CAN_IE_DRXE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_DRXE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_DRXE;
+	tmp |= value << CAN_IE_DRXE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_DRXE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_DRXE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_DRXE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_DRXE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_BECE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_BECE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_BECE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_BECE) >> CAN_IE_BECE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_BECE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_BECE;
+	tmp |= value << CAN_IE_BECE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_BECE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_BECE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_BECE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_BECE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_BEUE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_BEUE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_BEUE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_BEUE) >> CAN_IE_BEUE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_BEUE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_BEUE;
+	tmp |= value << CAN_IE_BEUE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_BEUE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_BEUE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_BEUE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_BEUE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_ELOE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_ELOE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_ELOE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_ELOE) >> CAN_IE_ELOE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_ELOE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_ELOE;
+	tmp |= value << CAN_IE_ELOE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_ELOE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_ELOE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_ELOE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_ELOE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_EPE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_EPE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_EPE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_EPE) >> CAN_IE_EPE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_EPE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_EPE;
+	tmp |= value << CAN_IE_EPE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_EPE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_EPE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_EPE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_EPE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_EWE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_EWE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_EWE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_EWE) >> CAN_IE_EWE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_EWE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_EWE;
+	tmp |= value << CAN_IE_EWE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_EWE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_EWE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_EWE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_EWE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_BOE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_BOE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_BOE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_BOE) >> CAN_IE_BOE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_BOE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_BOE;
+	tmp |= value << CAN_IE_BOE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_BOE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_BOE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_BOE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_BOE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_WDIE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_WDIE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_WDIE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_WDIE) >> CAN_IE_WDIE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_WDIE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_WDIE;
+	tmp |= value << CAN_IE_WDIE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_WDIE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_WDIE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_WDIE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_WDIE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_PEAE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_PEAE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_PEAE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_PEAE) >> CAN_IE_PEAE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_PEAE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_PEAE;
+	tmp |= value << CAN_IE_PEAE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_PEAE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_PEAE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_PEAE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_PEAE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_PEDE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_PEDE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_PEDE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_PEDE) >> CAN_IE_PEDE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_PEDE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_PEDE;
+	tmp |= value << CAN_IE_PEDE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_PEDE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_PEDE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_PEDE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_PEDE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_ARAE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= CAN_IE_ARAE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_IE_ARAE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp = (tmp & CAN_IE_ARAE) >> CAN_IE_ARAE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_IE_ARAE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= ~CAN_IE_ARAE;
+	tmp |= value << CAN_IE_ARAE_Pos;
+	((Can *)hw)->IE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_ARAE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~CAN_IE_ARAE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_ARAE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= CAN_IE_ARAE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_IE_reg(const void *const hw, hri_can_ie_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_ie_reg_t hri_can_get_IE_reg(const void *const hw, hri_can_ie_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->IE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_IE_reg(const void *const hw, hri_can_ie_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_IE_reg(const void *const hw, hri_can_ie_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_IE_reg(const void *const hw, hri_can_ie_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->IE.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_ie_reg_t hri_can_read_IE_reg(const void *const hw)
+{
+	return ((Can *)hw)->IE.reg;
+}
+
+static inline void hri_can_set_ILS_RF0NL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_RF0NL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_RF0NL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_RF0NL) >> CAN_ILS_RF0NL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_RF0NL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_RF0NL;
+	tmp |= value << CAN_ILS_RF0NL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_RF0NL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0NL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_RF0NL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_RF0NL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_RF0WL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_RF0WL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_RF0WL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_RF0WL) >> CAN_ILS_RF0WL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_RF0WL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_RF0WL;
+	tmp |= value << CAN_ILS_RF0WL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_RF0WL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0WL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_RF0WL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_RF0WL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_RF0FL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_RF0FL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_RF0FL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_RF0FL) >> CAN_ILS_RF0FL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_RF0FL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_RF0FL;
+	tmp |= value << CAN_ILS_RF0FL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_RF0FL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0FL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_RF0FL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_RF0FL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_RF0LL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_RF0LL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_RF0LL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_RF0LL) >> CAN_ILS_RF0LL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_RF0LL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_RF0LL;
+	tmp |= value << CAN_ILS_RF0LL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_RF0LL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0LL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_RF0LL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_RF0LL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_RF1NL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_RF1NL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_RF1NL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_RF1NL) >> CAN_ILS_RF1NL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_RF1NL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_RF1NL;
+	tmp |= value << CAN_ILS_RF1NL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_RF1NL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1NL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_RF1NL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_RF1NL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_RF1WL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_RF1WL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_RF1WL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_RF1WL) >> CAN_ILS_RF1WL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_RF1WL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_RF1WL;
+	tmp |= value << CAN_ILS_RF1WL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_RF1WL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1WL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_RF1WL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_RF1WL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_RF1FL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_RF1FL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_RF1FL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_RF1FL) >> CAN_ILS_RF1FL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_RF1FL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_RF1FL;
+	tmp |= value << CAN_ILS_RF1FL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_RF1FL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1FL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_RF1FL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_RF1FL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_RF1LL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_RF1LL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_RF1LL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_RF1LL) >> CAN_ILS_RF1LL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_RF1LL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_RF1LL;
+	tmp |= value << CAN_ILS_RF1LL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_RF1LL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1LL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_RF1LL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_RF1LL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_HPML_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_HPML;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_HPML_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_HPML) >> CAN_ILS_HPML_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_HPML_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_HPML;
+	tmp |= value << CAN_ILS_HPML_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_HPML_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_HPML;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_HPML_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_HPML;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_TCL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_TCL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_TCL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_TCL) >> CAN_ILS_TCL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_TCL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_TCL;
+	tmp |= value << CAN_ILS_TCL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_TCL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_TCL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_TCL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_TCL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_TCFL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_TCFL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_TCFL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_TCFL) >> CAN_ILS_TCFL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_TCFL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_TCFL;
+	tmp |= value << CAN_ILS_TCFL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_TCFL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_TCFL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_TCFL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_TCFL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_TFEL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_TFEL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_TFEL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_TFEL) >> CAN_ILS_TFEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_TFEL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_TFEL;
+	tmp |= value << CAN_ILS_TFEL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_TFEL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_TFEL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_TFEL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_TFEL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_TEFNL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_TEFNL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_TEFNL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_TEFNL) >> CAN_ILS_TEFNL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_TEFNL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_TEFNL;
+	tmp |= value << CAN_ILS_TEFNL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_TEFNL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFNL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_TEFNL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_TEFNL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_TEFWL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_TEFWL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_TEFWL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_TEFWL) >> CAN_ILS_TEFWL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_TEFWL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_TEFWL;
+	tmp |= value << CAN_ILS_TEFWL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_TEFWL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFWL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_TEFWL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_TEFWL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_TEFFL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_TEFFL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_TEFFL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_TEFFL) >> CAN_ILS_TEFFL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_TEFFL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_TEFFL;
+	tmp |= value << CAN_ILS_TEFFL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_TEFFL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFFL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_TEFFL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_TEFFL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_TEFLL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_TEFLL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_TEFLL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_TEFLL) >> CAN_ILS_TEFLL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_TEFLL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_TEFLL;
+	tmp |= value << CAN_ILS_TEFLL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_TEFLL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFLL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_TEFLL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_TEFLL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_TSWL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_TSWL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_TSWL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_TSWL) >> CAN_ILS_TSWL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_TSWL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_TSWL;
+	tmp |= value << CAN_ILS_TSWL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_TSWL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_TSWL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_TSWL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_TSWL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_MRAFL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_MRAFL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_MRAFL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_MRAFL) >> CAN_ILS_MRAFL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_MRAFL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_MRAFL;
+	tmp |= value << CAN_ILS_MRAFL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_MRAFL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_MRAFL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_MRAFL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_MRAFL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_TOOL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_TOOL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_TOOL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_TOOL) >> CAN_ILS_TOOL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_TOOL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_TOOL;
+	tmp |= value << CAN_ILS_TOOL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_TOOL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_TOOL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_TOOL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_TOOL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_DRXL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_DRXL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_DRXL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_DRXL) >> CAN_ILS_DRXL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_DRXL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_DRXL;
+	tmp |= value << CAN_ILS_DRXL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_DRXL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_DRXL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_DRXL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_DRXL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_BECL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_BECL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_BECL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_BECL) >> CAN_ILS_BECL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_BECL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_BECL;
+	tmp |= value << CAN_ILS_BECL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_BECL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_BECL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_BECL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_BECL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_BEUL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_BEUL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_BEUL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_BEUL) >> CAN_ILS_BEUL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_BEUL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_BEUL;
+	tmp |= value << CAN_ILS_BEUL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_BEUL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_BEUL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_BEUL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_BEUL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_ELOL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_ELOL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_ELOL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_ELOL) >> CAN_ILS_ELOL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_ELOL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_ELOL;
+	tmp |= value << CAN_ILS_ELOL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_ELOL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_ELOL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_ELOL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_ELOL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_EPL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_EPL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_EPL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_EPL) >> CAN_ILS_EPL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_EPL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_EPL;
+	tmp |= value << CAN_ILS_EPL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_EPL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_EPL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_EPL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_EPL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_EWL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_EWL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_EWL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_EWL) >> CAN_ILS_EWL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_EWL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_EWL;
+	tmp |= value << CAN_ILS_EWL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_EWL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_EWL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_EWL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_EWL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_BOL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_BOL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_BOL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_BOL) >> CAN_ILS_BOL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_BOL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_BOL;
+	tmp |= value << CAN_ILS_BOL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_BOL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_BOL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_BOL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_BOL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_WDIL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_WDIL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_WDIL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_WDIL) >> CAN_ILS_WDIL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_WDIL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_WDIL;
+	tmp |= value << CAN_ILS_WDIL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_WDIL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_WDIL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_WDIL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_WDIL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_PEAL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_PEAL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_PEAL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_PEAL) >> CAN_ILS_PEAL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_PEAL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_PEAL;
+	tmp |= value << CAN_ILS_PEAL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_PEAL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_PEAL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_PEAL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_PEAL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_PEDL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_PEDL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_PEDL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_PEDL) >> CAN_ILS_PEDL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_PEDL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_PEDL;
+	tmp |= value << CAN_ILS_PEDL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_PEDL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_PEDL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_PEDL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_PEDL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_ARAL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= CAN_ILS_ARAL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILS_ARAL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp = (tmp & CAN_ILS_ARAL) >> CAN_ILS_ARAL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILS_ARAL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= ~CAN_ILS_ARAL;
+	tmp |= value << CAN_ILS_ARAL_Pos;
+	((Can *)hw)->ILS.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_ARAL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~CAN_ILS_ARAL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_ARAL_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= CAN_ILS_ARAL;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILS_reg(const void *const hw, hri_can_ils_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_ils_reg_t hri_can_get_ILS_reg(const void *const hw, hri_can_ils_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_ILS_reg(const void *const hw, hri_can_ils_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILS_reg(const void *const hw, hri_can_ils_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILS_reg(const void *const hw, hri_can_ils_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILS.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_ils_reg_t hri_can_read_ILS_reg(const void *const hw)
+{
+	return ((Can *)hw)->ILS.reg;
+}
+
+static inline void hri_can_set_ILE_EINT0_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILE.reg |= CAN_ILE_EINT0;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILE_EINT0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILE.reg;
+	tmp = (tmp & CAN_ILE_EINT0) >> CAN_ILE_EINT0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILE_EINT0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILE.reg;
+	tmp &= ~CAN_ILE_EINT0;
+	tmp |= value << CAN_ILE_EINT0_Pos;
+	((Can *)hw)->ILE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILE_EINT0_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT0;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILE_EINT0_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILE.reg ^= CAN_ILE_EINT0;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILE_EINT1_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILE.reg |= CAN_ILE_EINT1;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_ILE_EINT1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILE.reg;
+	tmp = (tmp & CAN_ILE_EINT1) >> CAN_ILE_EINT1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_ILE_EINT1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->ILE.reg;
+	tmp &= ~CAN_ILE_EINT1;
+	tmp |= value << CAN_ILE_EINT1_Pos;
+	((Can *)hw)->ILE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILE_EINT1_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT1;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILE_EINT1_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILE.reg ^= CAN_ILE_EINT1;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_ILE_reg(const void *const hw, hri_can_ile_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILE.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_ile_reg_t hri_can_get_ILE_reg(const void *const hw, hri_can_ile_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->ILE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_ILE_reg(const void *const hw, hri_can_ile_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILE.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_ILE_reg(const void *const hw, hri_can_ile_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILE.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_ILE_reg(const void *const hw, hri_can_ile_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->ILE.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_ile_reg_t hri_can_read_ILE_reg(const void *const hw)
+{
+	return ((Can *)hw)->ILE.reg;
+}
+
+static inline void hri_can_set_GFC_RRFE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->GFC.reg |= CAN_GFC_RRFE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_GFC_RRFE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->GFC.reg;
+	tmp = (tmp & CAN_GFC_RRFE) >> CAN_GFC_RRFE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_GFC_RRFE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->GFC.reg;
+	tmp &= ~CAN_GFC_RRFE;
+	tmp |= value << CAN_GFC_RRFE_Pos;
+	((Can *)hw)->GFC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_GFC_RRFE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_GFC_RRFE_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->GFC.reg ^= CAN_GFC_RRFE;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_GFC_RRFS_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->GFC.reg |= CAN_GFC_RRFS;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_GFC_RRFS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->GFC.reg;
+	tmp = (tmp & CAN_GFC_RRFS) >> CAN_GFC_RRFS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_GFC_RRFS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->GFC.reg;
+	tmp &= ~CAN_GFC_RRFS;
+	tmp |= value << CAN_GFC_RRFS_Pos;
+	((Can *)hw)->GFC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_GFC_RRFS_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFS;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_GFC_RRFS_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->GFC.reg ^= CAN_GFC_RRFS;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->GFC.reg |= CAN_GFC_ANFE(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->GFC.reg;
+	tmp = (tmp & CAN_GFC_ANFE(mask)) >> CAN_GFC_ANFE_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->GFC.reg;
+	tmp &= ~CAN_GFC_ANFE_Msk;
+	tmp |= CAN_GFC_ANFE(data);
+	((Can *)hw)->GFC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFE(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->GFC.reg ^= CAN_GFC_ANFE(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->GFC.reg;
+	tmp = (tmp & CAN_GFC_ANFE_Msk) >> CAN_GFC_ANFE_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->GFC.reg |= CAN_GFC_ANFS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->GFC.reg;
+	tmp = (tmp & CAN_GFC_ANFS(mask)) >> CAN_GFC_ANFS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->GFC.reg;
+	tmp &= ~CAN_GFC_ANFS_Msk;
+	tmp |= CAN_GFC_ANFS(data);
+	((Can *)hw)->GFC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->GFC.reg ^= CAN_GFC_ANFS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->GFC.reg;
+	tmp = (tmp & CAN_GFC_ANFS_Msk) >> CAN_GFC_ANFS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->GFC.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_gfc_reg_t hri_can_get_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->GFC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_GFC_reg(const void *const hw, hri_can_gfc_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->GFC.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->GFC.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->GFC.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_gfc_reg_t hri_can_read_GFC_reg(const void *const hw)
+{
+	return ((Can *)hw)->GFC.reg;
+}
+
+static inline void hri_can_set_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->SIDFC.reg |= CAN_SIDFC_FLSSA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->SIDFC.reg;
+	tmp = (tmp & CAN_SIDFC_FLSSA(mask)) >> CAN_SIDFC_FLSSA_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->SIDFC.reg;
+	tmp &= ~CAN_SIDFC_FLSSA_Msk;
+	tmp |= CAN_SIDFC_FLSSA(data);
+	((Can *)hw)->SIDFC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_FLSSA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_FLSSA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_FLSSA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->SIDFC.reg;
+	tmp = (tmp & CAN_SIDFC_FLSSA_Msk) >> CAN_SIDFC_FLSSA_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->SIDFC.reg |= CAN_SIDFC_LSS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->SIDFC.reg;
+	tmp = (tmp & CAN_SIDFC_LSS(mask)) >> CAN_SIDFC_LSS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->SIDFC.reg;
+	tmp &= ~CAN_SIDFC_LSS_Msk;
+	tmp |= CAN_SIDFC_LSS(data);
+	((Can *)hw)->SIDFC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_LSS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_LSS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_LSS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->SIDFC.reg;
+	tmp = (tmp & CAN_SIDFC_LSS_Msk) >> CAN_SIDFC_LSS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->SIDFC.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->SIDFC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->SIDFC.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->SIDFC.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->SIDFC.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_reg(const void *const hw)
+{
+	return ((Can *)hw)->SIDFC.reg;
+}
+
+static inline void hri_can_set_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->XIDFC.reg |= CAN_XIDFC_FLESA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->XIDFC.reg;
+	tmp = (tmp & CAN_XIDFC_FLESA(mask)) >> CAN_XIDFC_FLESA_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->XIDFC.reg;
+	tmp &= ~CAN_XIDFC_FLESA_Msk;
+	tmp |= CAN_XIDFC_FLESA(data);
+	((Can *)hw)->XIDFC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_FLESA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_FLESA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_FLESA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->XIDFC.reg;
+	tmp = (tmp & CAN_XIDFC_FLESA_Msk) >> CAN_XIDFC_FLESA_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->XIDFC.reg |= CAN_XIDFC_LSE(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->XIDFC.reg;
+	tmp = (tmp & CAN_XIDFC_LSE(mask)) >> CAN_XIDFC_LSE_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->XIDFC.reg;
+	tmp &= ~CAN_XIDFC_LSE_Msk;
+	tmp |= CAN_XIDFC_LSE(data);
+	((Can *)hw)->XIDFC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_LSE(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_LSE(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_LSE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->XIDFC.reg;
+	tmp = (tmp & CAN_XIDFC_LSE_Msk) >> CAN_XIDFC_LSE_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->XIDFC.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->XIDFC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->XIDFC.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->XIDFC.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->XIDFC.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_reg(const void *const hw)
+{
+	return ((Can *)hw)->XIDFC.reg;
+}
+
+static inline void hri_can_set_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->XIDAM.reg |= CAN_XIDAM_EIDM(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_xidam_reg_t hri_can_get_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->XIDAM.reg;
+	tmp = (tmp & CAN_XIDAM_EIDM(mask)) >> CAN_XIDAM_EIDM_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->XIDAM.reg;
+	tmp &= ~CAN_XIDAM_EIDM_Msk;
+	tmp |= CAN_XIDAM_EIDM(data);
+	((Can *)hw)->XIDAM.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->XIDAM.reg &= ~CAN_XIDAM_EIDM(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->XIDAM.reg ^= CAN_XIDAM_EIDM(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_xidam_reg_t hri_can_read_XIDAM_EIDM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->XIDAM.reg;
+	tmp = (tmp & CAN_XIDAM_EIDM_Msk) >> CAN_XIDAM_EIDM_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->XIDAM.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_xidam_reg_t hri_can_get_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->XIDAM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->XIDAM.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->XIDAM.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->XIDAM.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_xidam_reg_t hri_can_read_XIDAM_reg(const void *const hw)
+{
+	return ((Can *)hw)->XIDAM.reg;
+}
+
+static inline void hri_can_set_NDAT1_ND0_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND0;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND0) >> CAN_NDAT1_ND0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND0;
+	tmp |= value << CAN_NDAT1_ND0_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND0_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND0;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND0_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND0;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND1_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND1;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND1) >> CAN_NDAT1_ND1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND1;
+	tmp |= value << CAN_NDAT1_ND1_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND1_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND1;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND1_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND1;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND2_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND2;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND2) >> CAN_NDAT1_ND2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND2;
+	tmp |= value << CAN_NDAT1_ND2_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND2_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND2;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND2_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND2;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND3_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND3;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND3) >> CAN_NDAT1_ND3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND3;
+	tmp |= value << CAN_NDAT1_ND3_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND3_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND3;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND3_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND3;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND4_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND4;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND4) >> CAN_NDAT1_ND4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND4;
+	tmp |= value << CAN_NDAT1_ND4_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND4_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND4;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND4_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND4;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND5_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND5;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND5) >> CAN_NDAT1_ND5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND5;
+	tmp |= value << CAN_NDAT1_ND5_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND5_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND5;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND5_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND5;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND6_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND6;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND6) >> CAN_NDAT1_ND6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND6;
+	tmp |= value << CAN_NDAT1_ND6_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND6_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND6;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND6_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND6;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND7_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND7;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND7) >> CAN_NDAT1_ND7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND7;
+	tmp |= value << CAN_NDAT1_ND7_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND7_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND7;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND7_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND7;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND8_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND8;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND8_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND8) >> CAN_NDAT1_ND8_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND8_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND8;
+	tmp |= value << CAN_NDAT1_ND8_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND8_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND8;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND8_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND8;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND9_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND9;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND9_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND9) >> CAN_NDAT1_ND9_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND9_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND9;
+	tmp |= value << CAN_NDAT1_ND9_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND9_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND9;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND9_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND9;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND10_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND10;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND10_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND10) >> CAN_NDAT1_ND10_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND10_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND10;
+	tmp |= value << CAN_NDAT1_ND10_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND10_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND10;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND10_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND10;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND11_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND11;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND11_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND11) >> CAN_NDAT1_ND11_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND11_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND11;
+	tmp |= value << CAN_NDAT1_ND11_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND11_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND11;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND11_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND11;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND12_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND12;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND12_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND12) >> CAN_NDAT1_ND12_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND12_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND12;
+	tmp |= value << CAN_NDAT1_ND12_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND12_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND12;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND12_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND12;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND13_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND13;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND13_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND13) >> CAN_NDAT1_ND13_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND13_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND13;
+	tmp |= value << CAN_NDAT1_ND13_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND13_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND13;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND13_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND13;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND14_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND14;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND14_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND14) >> CAN_NDAT1_ND14_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND14_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND14;
+	tmp |= value << CAN_NDAT1_ND14_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND14_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND14;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND14_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND14;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND15_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND15;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND15_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND15) >> CAN_NDAT1_ND15_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND15_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND15;
+	tmp |= value << CAN_NDAT1_ND15_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND15_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND15;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND15_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND15;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND16_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND16;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND16_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND16) >> CAN_NDAT1_ND16_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND16_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND16;
+	tmp |= value << CAN_NDAT1_ND16_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND16_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND16;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND16_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND16;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND17_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND17;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND17_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND17) >> CAN_NDAT1_ND17_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND17_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND17;
+	tmp |= value << CAN_NDAT1_ND17_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND17_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND17;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND17_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND17;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND18_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND18;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND18_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND18) >> CAN_NDAT1_ND18_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND18_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND18;
+	tmp |= value << CAN_NDAT1_ND18_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND18_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND18;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND18_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND18;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND19_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND19;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND19_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND19) >> CAN_NDAT1_ND19_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND19_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND19;
+	tmp |= value << CAN_NDAT1_ND19_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND19_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND19;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND19_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND19;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND20_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND20;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND20_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND20) >> CAN_NDAT1_ND20_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND20_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND20;
+	tmp |= value << CAN_NDAT1_ND20_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND20_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND20;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND20_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND20;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND21_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND21;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND21_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND21) >> CAN_NDAT1_ND21_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND21_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND21;
+	tmp |= value << CAN_NDAT1_ND21_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND21_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND21;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND21_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND21;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND22_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND22;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND22_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND22) >> CAN_NDAT1_ND22_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND22_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND22;
+	tmp |= value << CAN_NDAT1_ND22_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND22_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND22;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND22_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND22;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND23_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND23;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND23_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND23) >> CAN_NDAT1_ND23_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND23_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND23;
+	tmp |= value << CAN_NDAT1_ND23_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND23_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND23;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND23_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND23;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND24_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND24;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND24_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND24) >> CAN_NDAT1_ND24_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND24_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND24;
+	tmp |= value << CAN_NDAT1_ND24_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND24_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND24;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND24_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND24;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND25_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND25;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND25_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND25) >> CAN_NDAT1_ND25_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND25_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND25;
+	tmp |= value << CAN_NDAT1_ND25_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND25_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND25;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND25_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND25;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND26_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND26;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND26_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND26) >> CAN_NDAT1_ND26_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND26_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND26;
+	tmp |= value << CAN_NDAT1_ND26_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND26_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND26;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND26_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND26;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND27_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND27;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND27_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND27) >> CAN_NDAT1_ND27_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND27_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND27;
+	tmp |= value << CAN_NDAT1_ND27_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND27_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND27;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND27_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND27;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND28_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND28;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND28_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND28) >> CAN_NDAT1_ND28_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND28_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND28;
+	tmp |= value << CAN_NDAT1_ND28_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND28_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND28;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND28_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND28;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND29_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND29;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND29_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND29) >> CAN_NDAT1_ND29_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND29_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND29;
+	tmp |= value << CAN_NDAT1_ND29_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND29_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND29;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND29_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND29;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND30_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND30;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND30_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND30) >> CAN_NDAT1_ND30_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND30_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND30;
+	tmp |= value << CAN_NDAT1_ND30_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND30_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND30;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND30_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND30;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_ND31_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND31;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT1_ND31_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp = (tmp & CAN_NDAT1_ND31) >> CAN_NDAT1_ND31_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT1_ND31_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= ~CAN_NDAT1_ND31;
+	tmp |= value << CAN_NDAT1_ND31_Pos;
+	((Can *)hw)->NDAT1.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_ND31_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND31;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_ND31_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND31;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_ndat1_reg_t hri_can_get_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT1.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_ndat1_reg_t hri_can_read_NDAT1_reg(const void *const hw)
+{
+	return ((Can *)hw)->NDAT1.reg;
+}
+
+static inline void hri_can_set_NDAT2_ND32_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND32;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND32_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND32) >> CAN_NDAT2_ND32_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND32_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND32;
+	tmp |= value << CAN_NDAT2_ND32_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND32_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND32;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND32_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND32;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND33_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND33;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND33_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND33) >> CAN_NDAT2_ND33_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND33_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND33;
+	tmp |= value << CAN_NDAT2_ND33_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND33_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND33;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND33_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND33;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND34_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND34;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND34_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND34) >> CAN_NDAT2_ND34_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND34_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND34;
+	tmp |= value << CAN_NDAT2_ND34_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND34_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND34;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND34_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND34;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND35_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND35;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND35_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND35) >> CAN_NDAT2_ND35_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND35_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND35;
+	tmp |= value << CAN_NDAT2_ND35_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND35_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND35;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND35_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND35;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND36_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND36;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND36_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND36) >> CAN_NDAT2_ND36_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND36_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND36;
+	tmp |= value << CAN_NDAT2_ND36_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND36_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND36;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND36_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND36;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND37_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND37;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND37_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND37) >> CAN_NDAT2_ND37_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND37_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND37;
+	tmp |= value << CAN_NDAT2_ND37_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND37_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND37;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND37_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND37;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND38_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND38;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND38_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND38) >> CAN_NDAT2_ND38_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND38_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND38;
+	tmp |= value << CAN_NDAT2_ND38_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND38_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND38;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND38_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND38;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND39_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND39;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND39_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND39) >> CAN_NDAT2_ND39_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND39_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND39;
+	tmp |= value << CAN_NDAT2_ND39_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND39_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND39;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND39_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND39;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND40_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND40;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND40_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND40) >> CAN_NDAT2_ND40_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND40_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND40;
+	tmp |= value << CAN_NDAT2_ND40_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND40_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND40;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND40_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND40;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND41_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND41;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND41_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND41) >> CAN_NDAT2_ND41_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND41_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND41;
+	tmp |= value << CAN_NDAT2_ND41_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND41_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND41;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND41_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND41;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND42_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND42;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND42_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND42) >> CAN_NDAT2_ND42_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND42_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND42;
+	tmp |= value << CAN_NDAT2_ND42_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND42_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND42;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND42_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND42;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND43_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND43;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND43_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND43) >> CAN_NDAT2_ND43_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND43_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND43;
+	tmp |= value << CAN_NDAT2_ND43_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND43_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND43;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND43_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND43;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND44_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND44;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND44_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND44) >> CAN_NDAT2_ND44_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND44_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND44;
+	tmp |= value << CAN_NDAT2_ND44_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND44_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND44;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND44_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND44;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND45_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND45;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND45_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND45) >> CAN_NDAT2_ND45_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND45_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND45;
+	tmp |= value << CAN_NDAT2_ND45_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND45_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND45;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND45_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND45;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND46_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND46;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND46_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND46) >> CAN_NDAT2_ND46_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND46_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND46;
+	tmp |= value << CAN_NDAT2_ND46_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND46_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND46;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND46_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND46;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND47_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND47;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND47_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND47) >> CAN_NDAT2_ND47_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND47_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND47;
+	tmp |= value << CAN_NDAT2_ND47_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND47_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND47;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND47_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND47;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND48_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND48;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND48_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND48) >> CAN_NDAT2_ND48_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND48_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND48;
+	tmp |= value << CAN_NDAT2_ND48_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND48_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND48;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND48_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND48;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND49_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND49;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND49_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND49) >> CAN_NDAT2_ND49_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND49_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND49;
+	tmp |= value << CAN_NDAT2_ND49_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND49_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND49;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND49_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND49;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND50_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND50;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND50_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND50) >> CAN_NDAT2_ND50_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND50_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND50;
+	tmp |= value << CAN_NDAT2_ND50_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND50_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND50;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND50_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND50;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND51_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND51;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND51_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND51) >> CAN_NDAT2_ND51_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND51_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND51;
+	tmp |= value << CAN_NDAT2_ND51_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND51_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND51;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND51_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND51;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND52_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND52;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND52_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND52) >> CAN_NDAT2_ND52_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND52_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND52;
+	tmp |= value << CAN_NDAT2_ND52_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND52_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND52;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND52_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND52;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND53_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND53;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND53_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND53) >> CAN_NDAT2_ND53_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND53_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND53;
+	tmp |= value << CAN_NDAT2_ND53_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND53_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND53;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND53_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND53;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND54_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND54;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND54_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND54) >> CAN_NDAT2_ND54_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND54_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND54;
+	tmp |= value << CAN_NDAT2_ND54_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND54_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND54;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND54_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND54;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND55_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND55;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND55_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND55) >> CAN_NDAT2_ND55_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND55_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND55;
+	tmp |= value << CAN_NDAT2_ND55_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND55_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND55;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND55_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND55;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND56_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND56;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND56_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND56) >> CAN_NDAT2_ND56_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND56_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND56;
+	tmp |= value << CAN_NDAT2_ND56_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND56_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND56;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND56_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND56;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND57_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND57;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND57_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND57) >> CAN_NDAT2_ND57_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND57_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND57;
+	tmp |= value << CAN_NDAT2_ND57_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND57_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND57;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND57_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND57;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND58_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND58;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND58_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND58) >> CAN_NDAT2_ND58_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND58_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND58;
+	tmp |= value << CAN_NDAT2_ND58_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND58_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND58;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND58_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND58;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND59_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND59;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND59_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND59) >> CAN_NDAT2_ND59_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND59_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND59;
+	tmp |= value << CAN_NDAT2_ND59_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND59_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND59;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND59_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND59;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND60_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND60;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND60_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND60) >> CAN_NDAT2_ND60_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND60_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND60;
+	tmp |= value << CAN_NDAT2_ND60_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND60_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND60;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND60_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND60;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND61_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND61;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND61_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND61) >> CAN_NDAT2_ND61_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND61_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND61;
+	tmp |= value << CAN_NDAT2_ND61_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND61_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND61;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND61_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND61;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND62_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND62;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND62_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND62) >> CAN_NDAT2_ND62_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND62_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND62;
+	tmp |= value << CAN_NDAT2_ND62_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND62_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND62;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND62_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND62;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_ND63_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND63;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_NDAT2_ND63_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp = (tmp & CAN_NDAT2_ND63) >> CAN_NDAT2_ND63_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_NDAT2_ND63_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= ~CAN_NDAT2_ND63;
+	tmp |= value << CAN_NDAT2_ND63_Pos;
+	((Can *)hw)->NDAT2.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_ND63_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND63;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_ND63_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND63;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_ndat2_reg_t hri_can_get_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->NDAT2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->NDAT2.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_ndat2_reg_t hri_can_read_NDAT2_reg(const void *const hw)
+{
+	return ((Can *)hw)->NDAT2.reg;
+}
+
+static inline void hri_can_set_RXF0C_F0OM_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0OM;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_RXF0C_F0OM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF0C.reg;
+	tmp = (tmp & CAN_RXF0C_F0OM) >> CAN_RXF0C_F0OM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_RXF0C_F0OM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->RXF0C.reg;
+	tmp &= ~CAN_RXF0C_F0OM;
+	tmp |= value << CAN_RXF0C_F0OM_Pos;
+	((Can *)hw)->RXF0C.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXF0C_F0OM_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0OM;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXF0C_F0OM_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0OM;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0SA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF0C.reg;
+	tmp = (tmp & CAN_RXF0C_F0SA(mask)) >> CAN_RXF0C_F0SA_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->RXF0C.reg;
+	tmp &= ~CAN_RXF0C_F0SA_Msk;
+	tmp |= CAN_RXF0C_F0SA(data);
+	((Can *)hw)->RXF0C.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0SA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0SA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0SA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF0C.reg;
+	tmp = (tmp & CAN_RXF0C_F0SA_Msk) >> CAN_RXF0C_F0SA_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0S(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF0C.reg;
+	tmp = (tmp & CAN_RXF0C_F0S(mask)) >> CAN_RXF0C_F0S_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->RXF0C.reg;
+	tmp &= ~CAN_RXF0C_F0S_Msk;
+	tmp |= CAN_RXF0C_F0S(data);
+	((Can *)hw)->RXF0C.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0S(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0S(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0S_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF0C.reg;
+	tmp = (tmp & CAN_RXF0C_F0S_Msk) >> CAN_RXF0C_F0S_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0WM(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF0C.reg;
+	tmp = (tmp & CAN_RXF0C_F0WM(mask)) >> CAN_RXF0C_F0WM_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->RXF0C.reg;
+	tmp &= ~CAN_RXF0C_F0WM_Msk;
+	tmp |= CAN_RXF0C_F0WM(data);
+	((Can *)hw)->RXF0C.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0WM(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0WM(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0WM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF0C.reg;
+	tmp = (tmp & CAN_RXF0C_F0WM_Msk) >> CAN_RXF0C_F0WM_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0C.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF0C.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0C.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0C.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0C.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_reg(const void *const hw)
+{
+	return ((Can *)hw)->RXF0C.reg;
+}
+
+static inline void hri_can_set_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0A.reg |= CAN_RXF0A_F0AI(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF0A.reg;
+	tmp = (tmp & CAN_RXF0A_F0AI(mask)) >> CAN_RXF0A_F0AI_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->RXF0A.reg;
+	tmp &= ~CAN_RXF0A_F0AI_Msk;
+	tmp |= CAN_RXF0A_F0AI(data);
+	((Can *)hw)->RXF0A.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0A.reg &= ~CAN_RXF0A_F0AI(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0A.reg ^= CAN_RXF0A_F0AI(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_F0AI_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF0A.reg;
+	tmp = (tmp & CAN_RXF0A_F0AI_Msk) >> CAN_RXF0A_F0AI_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0A.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF0A.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0A.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0A.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF0A.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_reg(const void *const hw)
+{
+	return ((Can *)hw)->RXF0A.reg;
+}
+
+static inline void hri_can_set_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXBC.reg |= CAN_RXBC_RBSA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxbc_reg_t hri_can_get_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXBC.reg;
+	tmp = (tmp & CAN_RXBC_RBSA(mask)) >> CAN_RXBC_RBSA_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->RXBC.reg;
+	tmp &= ~CAN_RXBC_RBSA_Msk;
+	tmp |= CAN_RXBC_RBSA(data);
+	((Can *)hw)->RXBC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXBC.reg &= ~CAN_RXBC_RBSA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXBC.reg ^= CAN_RXBC_RBSA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxbc_reg_t hri_can_read_RXBC_RBSA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXBC.reg;
+	tmp = (tmp & CAN_RXBC_RBSA_Msk) >> CAN_RXBC_RBSA_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXBC.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxbc_reg_t hri_can_get_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXBC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXBC.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXBC.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXBC.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxbc_reg_t hri_can_read_RXBC_reg(const void *const hw)
+{
+	return ((Can *)hw)->RXBC.reg;
+}
+
+static inline void hri_can_set_RXF1C_F1OM_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1OM;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_RXF1C_F1OM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF1C.reg;
+	tmp = (tmp & CAN_RXF1C_F1OM) >> CAN_RXF1C_F1OM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_RXF1C_F1OM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->RXF1C.reg;
+	tmp &= ~CAN_RXF1C_F1OM;
+	tmp |= value << CAN_RXF1C_F1OM_Pos;
+	((Can *)hw)->RXF1C.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXF1C_F1OM_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1OM;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXF1C_F1OM_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1OM;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1SA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF1C.reg;
+	tmp = (tmp & CAN_RXF1C_F1SA(mask)) >> CAN_RXF1C_F1SA_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->RXF1C.reg;
+	tmp &= ~CAN_RXF1C_F1SA_Msk;
+	tmp |= CAN_RXF1C_F1SA(data);
+	((Can *)hw)->RXF1C.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1SA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1SA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1SA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF1C.reg;
+	tmp = (tmp & CAN_RXF1C_F1SA_Msk) >> CAN_RXF1C_F1SA_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1S(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF1C.reg;
+	tmp = (tmp & CAN_RXF1C_F1S(mask)) >> CAN_RXF1C_F1S_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->RXF1C.reg;
+	tmp &= ~CAN_RXF1C_F1S_Msk;
+	tmp |= CAN_RXF1C_F1S(data);
+	((Can *)hw)->RXF1C.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1S(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1S(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1S_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF1C.reg;
+	tmp = (tmp & CAN_RXF1C_F1S_Msk) >> CAN_RXF1C_F1S_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1WM(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF1C.reg;
+	tmp = (tmp & CAN_RXF1C_F1WM(mask)) >> CAN_RXF1C_F1WM_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->RXF1C.reg;
+	tmp &= ~CAN_RXF1C_F1WM_Msk;
+	tmp |= CAN_RXF1C_F1WM(data);
+	((Can *)hw)->RXF1C.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1WM(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1WM(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1WM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF1C.reg;
+	tmp = (tmp & CAN_RXF1C_F1WM_Msk) >> CAN_RXF1C_F1WM_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1C.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF1C.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1C.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1C.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1C.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_reg(const void *const hw)
+{
+	return ((Can *)hw)->RXF1C.reg;
+}
+
+static inline void hri_can_set_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1A.reg |= CAN_RXF1A_F1AI(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF1A.reg;
+	tmp = (tmp & CAN_RXF1A_F1AI(mask)) >> CAN_RXF1A_F1AI_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->RXF1A.reg;
+	tmp &= ~CAN_RXF1A_F1AI_Msk;
+	tmp |= CAN_RXF1A_F1AI(data);
+	((Can *)hw)->RXF1A.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1A.reg &= ~CAN_RXF1A_F1AI(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1A.reg ^= CAN_RXF1A_F1AI(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_F1AI_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF1A.reg;
+	tmp = (tmp & CAN_RXF1A_F1AI_Msk) >> CAN_RXF1A_F1AI_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1A.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXF1A.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1A.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1A.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXF1A.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_reg(const void *const hw)
+{
+	return ((Can *)hw)->RXF1A.reg;
+}
+
+static inline void hri_can_set_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXESC.reg |= CAN_RXESC_F0DS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXESC.reg;
+	tmp = (tmp & CAN_RXESC_F0DS(mask)) >> CAN_RXESC_F0DS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->RXESC.reg;
+	tmp &= ~CAN_RXESC_F0DS_Msk;
+	tmp |= CAN_RXESC_F0DS(data);
+	((Can *)hw)->RXESC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F0DS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXESC.reg ^= CAN_RXESC_F0DS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F0DS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXESC.reg;
+	tmp = (tmp & CAN_RXESC_F0DS_Msk) >> CAN_RXESC_F0DS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXESC.reg |= CAN_RXESC_F1DS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXESC.reg;
+	tmp = (tmp & CAN_RXESC_F1DS(mask)) >> CAN_RXESC_F1DS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->RXESC.reg;
+	tmp &= ~CAN_RXESC_F1DS_Msk;
+	tmp |= CAN_RXESC_F1DS(data);
+	((Can *)hw)->RXESC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F1DS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXESC.reg ^= CAN_RXESC_F1DS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F1DS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXESC.reg;
+	tmp = (tmp & CAN_RXESC_F1DS_Msk) >> CAN_RXESC_F1DS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXESC.reg |= CAN_RXESC_RBDS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxesc_reg_t hri_can_get_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXESC.reg;
+	tmp = (tmp & CAN_RXESC_RBDS(mask)) >> CAN_RXESC_RBDS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->RXESC.reg;
+	tmp &= ~CAN_RXESC_RBDS_Msk;
+	tmp |= CAN_RXESC_RBDS(data);
+	((Can *)hw)->RXESC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXESC.reg &= ~CAN_RXESC_RBDS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXESC.reg ^= CAN_RXESC_RBDS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxesc_reg_t hri_can_read_RXESC_RBDS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXESC.reg;
+	tmp = (tmp & CAN_RXESC_RBDS_Msk) >> CAN_RXESC_RBDS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXESC.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxesc_reg_t hri_can_get_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->RXESC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXESC.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXESC.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->RXESC.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_rxesc_reg_t hri_can_read_RXESC_reg(const void *const hw)
+{
+	return ((Can *)hw)->RXESC.reg;
+}
+
+static inline void hri_can_set_TXBC_TFQM_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQM;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBC_TFQM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBC.reg;
+	tmp = (tmp & CAN_TXBC_TFQM) >> CAN_TXBC_TFQM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBC_TFQM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBC.reg;
+	tmp &= ~CAN_TXBC_TFQM;
+	tmp |= value << CAN_TXBC_TFQM_Pos;
+	((Can *)hw)->TXBC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBC_TFQM_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQM;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBC_TFQM_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQM;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBC.reg |= CAN_TXBC_TBSA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txbc_reg_t hri_can_get_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBC.reg;
+	tmp = (tmp & CAN_TXBC_TBSA(mask)) >> CAN_TXBC_TBSA_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBC.reg;
+	tmp &= ~CAN_TXBC_TBSA_Msk;
+	tmp |= CAN_TXBC_TBSA(data);
+	((Can *)hw)->TXBC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TBSA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBC.reg ^= CAN_TXBC_TBSA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txbc_reg_t hri_can_read_TXBC_TBSA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBC.reg;
+	tmp = (tmp & CAN_TXBC_TBSA_Msk) >> CAN_TXBC_TBSA_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBC.reg |= CAN_TXBC_NDTB(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txbc_reg_t hri_can_get_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBC.reg;
+	tmp = (tmp & CAN_TXBC_NDTB(mask)) >> CAN_TXBC_NDTB_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBC.reg;
+	tmp &= ~CAN_TXBC_NDTB_Msk;
+	tmp |= CAN_TXBC_NDTB(data);
+	((Can *)hw)->TXBC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBC.reg &= ~CAN_TXBC_NDTB(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBC.reg ^= CAN_TXBC_NDTB(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txbc_reg_t hri_can_read_TXBC_NDTB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBC.reg;
+	tmp = (tmp & CAN_TXBC_NDTB_Msk) >> CAN_TXBC_NDTB_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txbc_reg_t hri_can_get_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBC.reg;
+	tmp = (tmp & CAN_TXBC_TFQS(mask)) >> CAN_TXBC_TFQS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBC.reg;
+	tmp &= ~CAN_TXBC_TFQS_Msk;
+	tmp |= CAN_TXBC_TFQS(data);
+	((Can *)hw)->TXBC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txbc_reg_t hri_can_read_TXBC_TFQS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBC.reg;
+	tmp = (tmp & CAN_TXBC_TFQS_Msk) >> CAN_TXBC_TFQS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBC.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txbc_reg_t hri_can_get_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_TXBC_reg(const void *const hw, hri_can_txbc_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBC.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBC.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBC.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txbc_reg_t hri_can_read_TXBC_reg(const void *const hw)
+{
+	return ((Can *)hw)->TXBC.reg;
+}
+
+static inline void hri_can_set_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXESC.reg |= CAN_TXESC_TBDS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txesc_reg_t hri_can_get_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXESC.reg;
+	tmp = (tmp & CAN_TXESC_TBDS(mask)) >> CAN_TXESC_TBDS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXESC.reg;
+	tmp &= ~CAN_TXESC_TBDS_Msk;
+	tmp |= CAN_TXESC_TBDS(data);
+	((Can *)hw)->TXESC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXESC.reg &= ~CAN_TXESC_TBDS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXESC.reg ^= CAN_TXESC_TBDS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txesc_reg_t hri_can_read_TXESC_TBDS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXESC.reg;
+	tmp = (tmp & CAN_TXESC_TBDS_Msk) >> CAN_TXESC_TBDS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXESC.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txesc_reg_t hri_can_get_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXESC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_TXESC_reg(const void *const hw, hri_can_txesc_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXESC.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXESC.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXESC.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txesc_reg_t hri_can_read_TXESC_reg(const void *const hw)
+{
+	return ((Can *)hw)->TXESC.reg;
+}
+
+static inline void hri_can_set_TXBAR_AR0_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR0;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR0) >> CAN_TXBAR_AR0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR0;
+	tmp |= value << CAN_TXBAR_AR0_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR0_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR0;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR0_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR0;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR1_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR1;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR1) >> CAN_TXBAR_AR1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR1;
+	tmp |= value << CAN_TXBAR_AR1_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR1_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR1;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR1_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR1;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR2_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR2;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR2) >> CAN_TXBAR_AR2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR2;
+	tmp |= value << CAN_TXBAR_AR2_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR2_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR2;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR2_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR2;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR3_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR3;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR3) >> CAN_TXBAR_AR3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR3;
+	tmp |= value << CAN_TXBAR_AR3_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR3_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR3;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR3_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR3;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR4_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR4;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR4) >> CAN_TXBAR_AR4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR4;
+	tmp |= value << CAN_TXBAR_AR4_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR4_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR4;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR4_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR4;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR5_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR5;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR5) >> CAN_TXBAR_AR5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR5;
+	tmp |= value << CAN_TXBAR_AR5_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR5_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR5;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR5_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR5;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR6_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR6;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR6) >> CAN_TXBAR_AR6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR6;
+	tmp |= value << CAN_TXBAR_AR6_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR6_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR6;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR6_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR6;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR7_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR7;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR7) >> CAN_TXBAR_AR7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR7;
+	tmp |= value << CAN_TXBAR_AR7_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR7_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR7;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR7_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR7;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR8_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR8;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR8_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR8) >> CAN_TXBAR_AR8_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR8_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR8;
+	tmp |= value << CAN_TXBAR_AR8_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR8_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR8;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR8_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR8;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR9_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR9;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR9_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR9) >> CAN_TXBAR_AR9_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR9_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR9;
+	tmp |= value << CAN_TXBAR_AR9_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR9_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR9;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR9_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR9;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR10_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR10;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR10_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR10) >> CAN_TXBAR_AR10_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR10_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR10;
+	tmp |= value << CAN_TXBAR_AR10_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR10_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR10;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR10_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR10;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR11_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR11;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR11_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR11) >> CAN_TXBAR_AR11_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR11_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR11;
+	tmp |= value << CAN_TXBAR_AR11_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR11_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR11;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR11_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR11;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR12_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR12;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR12_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR12) >> CAN_TXBAR_AR12_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR12_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR12;
+	tmp |= value << CAN_TXBAR_AR12_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR12_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR12;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR12_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR12;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR13_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR13;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR13_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR13) >> CAN_TXBAR_AR13_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR13_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR13;
+	tmp |= value << CAN_TXBAR_AR13_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR13_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR13;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR13_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR13;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR14_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR14;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR14_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR14) >> CAN_TXBAR_AR14_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR14_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR14;
+	tmp |= value << CAN_TXBAR_AR14_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR14_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR14;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR14_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR14;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR15_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR15;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR15_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR15) >> CAN_TXBAR_AR15_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR15_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR15;
+	tmp |= value << CAN_TXBAR_AR15_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR15_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR15;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR15_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR15;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR16_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR16;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR16_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR16) >> CAN_TXBAR_AR16_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR16_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR16;
+	tmp |= value << CAN_TXBAR_AR16_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR16_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR16;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR16_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR16;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR17_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR17;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR17_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR17) >> CAN_TXBAR_AR17_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR17_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR17;
+	tmp |= value << CAN_TXBAR_AR17_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR17_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR17;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR17_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR17;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR18_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR18;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR18_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR18) >> CAN_TXBAR_AR18_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR18_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR18;
+	tmp |= value << CAN_TXBAR_AR18_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR18_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR18;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR18_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR18;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR19_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR19;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR19_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR19) >> CAN_TXBAR_AR19_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR19_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR19;
+	tmp |= value << CAN_TXBAR_AR19_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR19_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR19;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR19_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR19;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR20_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR20;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR20_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR20) >> CAN_TXBAR_AR20_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR20_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR20;
+	tmp |= value << CAN_TXBAR_AR20_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR20_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR20;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR20_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR20;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR21_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR21;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR21_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR21) >> CAN_TXBAR_AR21_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR21_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR21;
+	tmp |= value << CAN_TXBAR_AR21_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR21_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR21;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR21_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR21;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR22_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR22;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR22_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR22) >> CAN_TXBAR_AR22_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR22_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR22;
+	tmp |= value << CAN_TXBAR_AR22_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR22_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR22;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR22_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR22;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR23_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR23;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR23_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR23) >> CAN_TXBAR_AR23_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR23_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR23;
+	tmp |= value << CAN_TXBAR_AR23_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR23_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR23;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR23_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR23;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR24_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR24;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR24_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR24) >> CAN_TXBAR_AR24_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR24_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR24;
+	tmp |= value << CAN_TXBAR_AR24_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR24_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR24;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR24_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR24;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR25_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR25;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR25_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR25) >> CAN_TXBAR_AR25_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR25_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR25;
+	tmp |= value << CAN_TXBAR_AR25_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR25_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR25;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR25_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR25;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR26_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR26;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR26_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR26) >> CAN_TXBAR_AR26_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR26_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR26;
+	tmp |= value << CAN_TXBAR_AR26_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR26_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR26;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR26_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR26;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR27_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR27;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR27_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR27) >> CAN_TXBAR_AR27_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR27_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR27;
+	tmp |= value << CAN_TXBAR_AR27_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR27_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR27;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR27_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR27;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR28_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR28;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR28_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR28) >> CAN_TXBAR_AR28_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR28_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR28;
+	tmp |= value << CAN_TXBAR_AR28_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR28_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR28;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR28_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR28;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR29_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR29;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR29_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR29) >> CAN_TXBAR_AR29_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR29_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR29;
+	tmp |= value << CAN_TXBAR_AR29_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR29_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR29;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR29_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR29;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR30_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR30;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR30_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR30) >> CAN_TXBAR_AR30_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR30_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR30;
+	tmp |= value << CAN_TXBAR_AR30_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR30_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR30;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR30_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR30;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_AR31_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR31;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBAR_AR31_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp = (tmp & CAN_TXBAR_AR31) >> CAN_TXBAR_AR31_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBAR_AR31_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= ~CAN_TXBAR_AR31;
+	tmp |= value << CAN_TXBAR_AR31_Pos;
+	((Can *)hw)->TXBAR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_AR31_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR31;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_AR31_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR31;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txbar_reg_t hri_can_get_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBAR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBAR.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txbar_reg_t hri_can_read_TXBAR_reg(const void *const hw)
+{
+	return ((Can *)hw)->TXBAR.reg;
+}
+
+static inline void hri_can_set_TXBCR_CR0_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR0;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR0) >> CAN_TXBCR_CR0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR0;
+	tmp |= value << CAN_TXBCR_CR0_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR0_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR0;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR0_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR0;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR1_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR1;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR1) >> CAN_TXBCR_CR1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR1;
+	tmp |= value << CAN_TXBCR_CR1_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR1_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR1;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR1_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR1;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR2_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR2;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR2) >> CAN_TXBCR_CR2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR2;
+	tmp |= value << CAN_TXBCR_CR2_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR2_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR2;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR2_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR2;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR3_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR3;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR3) >> CAN_TXBCR_CR3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR3;
+	tmp |= value << CAN_TXBCR_CR3_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR3_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR3;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR3_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR3;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR4_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR4;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR4) >> CAN_TXBCR_CR4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR4;
+	tmp |= value << CAN_TXBCR_CR4_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR4_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR4;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR4_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR4;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR5_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR5;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR5) >> CAN_TXBCR_CR5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR5;
+	tmp |= value << CAN_TXBCR_CR5_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR5_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR5;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR5_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR5;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR6_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR6;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR6) >> CAN_TXBCR_CR6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR6;
+	tmp |= value << CAN_TXBCR_CR6_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR6_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR6;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR6_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR6;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR7_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR7;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR7) >> CAN_TXBCR_CR7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR7;
+	tmp |= value << CAN_TXBCR_CR7_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR7_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR7;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR7_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR7;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR8_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR8;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR8_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR8) >> CAN_TXBCR_CR8_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR8_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR8;
+	tmp |= value << CAN_TXBCR_CR8_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR8_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR8;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR8_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR8;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR9_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR9;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR9_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR9) >> CAN_TXBCR_CR9_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR9_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR9;
+	tmp |= value << CAN_TXBCR_CR9_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR9_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR9;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR9_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR9;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR10_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR10;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR10_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR10) >> CAN_TXBCR_CR10_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR10_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR10;
+	tmp |= value << CAN_TXBCR_CR10_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR10_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR10;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR10_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR10;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR11_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR11;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR11_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR11) >> CAN_TXBCR_CR11_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR11_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR11;
+	tmp |= value << CAN_TXBCR_CR11_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR11_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR11;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR11_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR11;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR12_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR12;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR12_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR12) >> CAN_TXBCR_CR12_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR12_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR12;
+	tmp |= value << CAN_TXBCR_CR12_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR12_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR12;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR12_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR12;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR13_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR13;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR13_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR13) >> CAN_TXBCR_CR13_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR13_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR13;
+	tmp |= value << CAN_TXBCR_CR13_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR13_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR13;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR13_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR13;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR14_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR14;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR14_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR14) >> CAN_TXBCR_CR14_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR14_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR14;
+	tmp |= value << CAN_TXBCR_CR14_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR14_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR14;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR14_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR14;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR15_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR15;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR15_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR15) >> CAN_TXBCR_CR15_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR15_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR15;
+	tmp |= value << CAN_TXBCR_CR15_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR15_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR15;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR15_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR15;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR16_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR16;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR16_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR16) >> CAN_TXBCR_CR16_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR16_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR16;
+	tmp |= value << CAN_TXBCR_CR16_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR16_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR16;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR16_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR16;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR17_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR17;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR17_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR17) >> CAN_TXBCR_CR17_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR17_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR17;
+	tmp |= value << CAN_TXBCR_CR17_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR17_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR17;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR17_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR17;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR18_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR18;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR18_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR18) >> CAN_TXBCR_CR18_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR18_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR18;
+	tmp |= value << CAN_TXBCR_CR18_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR18_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR18;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR18_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR18;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR19_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR19;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR19_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR19) >> CAN_TXBCR_CR19_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR19_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR19;
+	tmp |= value << CAN_TXBCR_CR19_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR19_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR19;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR19_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR19;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR20_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR20;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR20_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR20) >> CAN_TXBCR_CR20_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR20_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR20;
+	tmp |= value << CAN_TXBCR_CR20_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR20_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR20;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR20_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR20;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR21_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR21;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR21_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR21) >> CAN_TXBCR_CR21_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR21_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR21;
+	tmp |= value << CAN_TXBCR_CR21_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR21_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR21;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR21_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR21;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR22_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR22;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR22_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR22) >> CAN_TXBCR_CR22_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR22_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR22;
+	tmp |= value << CAN_TXBCR_CR22_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR22_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR22;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR22_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR22;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR23_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR23;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR23_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR23) >> CAN_TXBCR_CR23_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR23_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR23;
+	tmp |= value << CAN_TXBCR_CR23_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR23_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR23;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR23_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR23;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR24_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR24;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR24_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR24) >> CAN_TXBCR_CR24_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR24_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR24;
+	tmp |= value << CAN_TXBCR_CR24_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR24_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR24;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR24_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR24;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR25_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR25;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR25_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR25) >> CAN_TXBCR_CR25_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR25_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR25;
+	tmp |= value << CAN_TXBCR_CR25_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR25_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR25;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR25_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR25;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR26_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR26;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR26_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR26) >> CAN_TXBCR_CR26_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR26_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR26;
+	tmp |= value << CAN_TXBCR_CR26_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR26_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR26;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR26_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR26;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR27_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR27;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR27_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR27) >> CAN_TXBCR_CR27_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR27_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR27;
+	tmp |= value << CAN_TXBCR_CR27_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR27_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR27;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR27_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR27;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR28_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR28;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR28_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR28) >> CAN_TXBCR_CR28_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR28_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR28;
+	tmp |= value << CAN_TXBCR_CR28_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR28_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR28;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR28_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR28;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR29_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR29;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR29_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR29) >> CAN_TXBCR_CR29_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR29_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR29;
+	tmp |= value << CAN_TXBCR_CR29_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR29_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR29;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR29_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR29;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR30_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR30;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR30_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR30) >> CAN_TXBCR_CR30_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR30_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR30;
+	tmp |= value << CAN_TXBCR_CR30_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR30_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR30;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR30_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR30;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_CR31_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR31;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCR_CR31_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp = (tmp & CAN_TXBCR_CR31) >> CAN_TXBCR_CR31_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCR_CR31_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= ~CAN_TXBCR_CR31;
+	tmp |= value << CAN_TXBCR_CR31_Pos;
+	((Can *)hw)->TXBCR.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_CR31_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR31;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_CR31_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR31;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txbcr_reg_t hri_can_get_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCR.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txbcr_reg_t hri_can_read_TXBCR_reg(const void *const hw)
+{
+	return ((Can *)hw)->TXBCR.reg;
+}
+
+static inline void hri_can_set_TXBTIE_TIE0_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE0;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE0) >> CAN_TXBTIE_TIE0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE0;
+	tmp |= value << CAN_TXBTIE_TIE0_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE0_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE0;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE0_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE0;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE1_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE1;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE1) >> CAN_TXBTIE_TIE1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE1;
+	tmp |= value << CAN_TXBTIE_TIE1_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE1_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE1;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE1_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE1;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE2_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE2;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE2) >> CAN_TXBTIE_TIE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE2;
+	tmp |= value << CAN_TXBTIE_TIE2_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE2_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE2;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE2_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE2;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE3_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE3;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE3) >> CAN_TXBTIE_TIE3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE3;
+	tmp |= value << CAN_TXBTIE_TIE3_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE3_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE3;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE3_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE3;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE4_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE4;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE4) >> CAN_TXBTIE_TIE4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE4;
+	tmp |= value << CAN_TXBTIE_TIE4_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE4_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE4;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE4_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE4;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE5_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE5;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE5) >> CAN_TXBTIE_TIE5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE5;
+	tmp |= value << CAN_TXBTIE_TIE5_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE5_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE5;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE5_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE5;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE6_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE6;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE6) >> CAN_TXBTIE_TIE6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE6;
+	tmp |= value << CAN_TXBTIE_TIE6_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE6_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE6;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE6_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE6;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE7_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE7;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE7) >> CAN_TXBTIE_TIE7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE7;
+	tmp |= value << CAN_TXBTIE_TIE7_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE7_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE7;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE7_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE7;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE8_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE8;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE8_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE8) >> CAN_TXBTIE_TIE8_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE8_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE8;
+	tmp |= value << CAN_TXBTIE_TIE8_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE8_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE8;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE8_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE8;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE9_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE9;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE9_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE9) >> CAN_TXBTIE_TIE9_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE9_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE9;
+	tmp |= value << CAN_TXBTIE_TIE9_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE9_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE9;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE9_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE9;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE10_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE10;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE10_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE10) >> CAN_TXBTIE_TIE10_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE10_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE10;
+	tmp |= value << CAN_TXBTIE_TIE10_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE10_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE10;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE10_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE10;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE11_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE11;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE11_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE11) >> CAN_TXBTIE_TIE11_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE11_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE11;
+	tmp |= value << CAN_TXBTIE_TIE11_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE11_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE11;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE11_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE11;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE12_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE12;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE12_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE12) >> CAN_TXBTIE_TIE12_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE12_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE12;
+	tmp |= value << CAN_TXBTIE_TIE12_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE12_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE12;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE12_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE12;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE13_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE13;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE13_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE13) >> CAN_TXBTIE_TIE13_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE13_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE13;
+	tmp |= value << CAN_TXBTIE_TIE13_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE13_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE13;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE13_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE13;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE14_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE14;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE14_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE14) >> CAN_TXBTIE_TIE14_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE14_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE14;
+	tmp |= value << CAN_TXBTIE_TIE14_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE14_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE14;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE14_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE14;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE15_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE15;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE15_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE15) >> CAN_TXBTIE_TIE15_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE15_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE15;
+	tmp |= value << CAN_TXBTIE_TIE15_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE15_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE15;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE15_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE15;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE16_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE16;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE16_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE16) >> CAN_TXBTIE_TIE16_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE16_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE16;
+	tmp |= value << CAN_TXBTIE_TIE16_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE16_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE16;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE16_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE16;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE17_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE17;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE17_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE17) >> CAN_TXBTIE_TIE17_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE17_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE17;
+	tmp |= value << CAN_TXBTIE_TIE17_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE17_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE17;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE17_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE17;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE18_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE18;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE18_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE18) >> CAN_TXBTIE_TIE18_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE18_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE18;
+	tmp |= value << CAN_TXBTIE_TIE18_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE18_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE18;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE18_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE18;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE19_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE19;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE19_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE19) >> CAN_TXBTIE_TIE19_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE19_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE19;
+	tmp |= value << CAN_TXBTIE_TIE19_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE19_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE19;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE19_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE19;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE20_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE20;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE20_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE20) >> CAN_TXBTIE_TIE20_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE20_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE20;
+	tmp |= value << CAN_TXBTIE_TIE20_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE20_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE20;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE20_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE20;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE21_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE21;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE21_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE21) >> CAN_TXBTIE_TIE21_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE21_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE21;
+	tmp |= value << CAN_TXBTIE_TIE21_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE21_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE21;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE21_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE21;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE22_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE22;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE22_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE22) >> CAN_TXBTIE_TIE22_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE22_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE22;
+	tmp |= value << CAN_TXBTIE_TIE22_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE22_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE22;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE22_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE22;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE23_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE23;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE23_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE23) >> CAN_TXBTIE_TIE23_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE23_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE23;
+	tmp |= value << CAN_TXBTIE_TIE23_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE23_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE23;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE23_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE23;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE24_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE24;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE24_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE24) >> CAN_TXBTIE_TIE24_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE24_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE24;
+	tmp |= value << CAN_TXBTIE_TIE24_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE24_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE24;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE24_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE24;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE25_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE25;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE25_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE25) >> CAN_TXBTIE_TIE25_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE25_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE25;
+	tmp |= value << CAN_TXBTIE_TIE25_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE25_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE25;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE25_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE25;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE26_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE26;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE26_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE26) >> CAN_TXBTIE_TIE26_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE26_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE26;
+	tmp |= value << CAN_TXBTIE_TIE26_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE26_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE26;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE26_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE26;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE27_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE27;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE27_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE27) >> CAN_TXBTIE_TIE27_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE27_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE27;
+	tmp |= value << CAN_TXBTIE_TIE27_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE27_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE27;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE27_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE27;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE28_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE28;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE28_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE28) >> CAN_TXBTIE_TIE28_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE28_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE28;
+	tmp |= value << CAN_TXBTIE_TIE28_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE28_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE28;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE28_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE28;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE29_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE29;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE29_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE29) >> CAN_TXBTIE_TIE29_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE29_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE29;
+	tmp |= value << CAN_TXBTIE_TIE29_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE29_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE29;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE29_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE29;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE30_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE30;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE30_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE30) >> CAN_TXBTIE_TIE30_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE30_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE30;
+	tmp |= value << CAN_TXBTIE_TIE30_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE30_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE30;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE30_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE30;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_TIE31_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE31;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBTIE_TIE31_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp = (tmp & CAN_TXBTIE_TIE31) >> CAN_TXBTIE_TIE31_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBTIE_TIE31_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= ~CAN_TXBTIE_TIE31;
+	tmp |= value << CAN_TXBTIE_TIE31_Pos;
+	((Can *)hw)->TXBTIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_TIE31_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE31;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_TIE31_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE31;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txbtie_reg_t hri_can_get_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBTIE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBTIE.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txbtie_reg_t hri_can_read_TXBTIE_reg(const void *const hw)
+{
+	return ((Can *)hw)->TXBTIE.reg;
+}
+
+static inline void hri_can_set_TXBCIE_CFIE0_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE0;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE0) >> CAN_TXBCIE_CFIE0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE0;
+	tmp |= value << CAN_TXBCIE_CFIE0_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE0_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE0;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE0_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE0;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE1_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE1;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE1) >> CAN_TXBCIE_CFIE1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE1;
+	tmp |= value << CAN_TXBCIE_CFIE1_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE1_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE1;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE1_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE1;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE2_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE2;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE2) >> CAN_TXBCIE_CFIE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE2;
+	tmp |= value << CAN_TXBCIE_CFIE2_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE2_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE2;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE2_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE2;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE3_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE3;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE3) >> CAN_TXBCIE_CFIE3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE3;
+	tmp |= value << CAN_TXBCIE_CFIE3_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE3_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE3;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE3_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE3;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE4_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE4;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE4) >> CAN_TXBCIE_CFIE4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE4;
+	tmp |= value << CAN_TXBCIE_CFIE4_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE4_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE4;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE4_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE4;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE5_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE5;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE5) >> CAN_TXBCIE_CFIE5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE5;
+	tmp |= value << CAN_TXBCIE_CFIE5_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE5_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE5;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE5_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE5;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE6_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE6;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE6) >> CAN_TXBCIE_CFIE6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE6;
+	tmp |= value << CAN_TXBCIE_CFIE6_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE6_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE6;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE6_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE6;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE7_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE7;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE7) >> CAN_TXBCIE_CFIE7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE7;
+	tmp |= value << CAN_TXBCIE_CFIE7_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE7_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE7;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE7_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE7;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE8_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE8;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE8_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE8) >> CAN_TXBCIE_CFIE8_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE8_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE8;
+	tmp |= value << CAN_TXBCIE_CFIE8_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE8_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE8;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE8_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE8;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE9_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE9;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE9_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE9) >> CAN_TXBCIE_CFIE9_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE9_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE9;
+	tmp |= value << CAN_TXBCIE_CFIE9_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE9_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE9;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE9_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE9;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE10_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE10;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE10_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE10) >> CAN_TXBCIE_CFIE10_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE10_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE10;
+	tmp |= value << CAN_TXBCIE_CFIE10_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE10_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE10;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE10_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE10;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE11_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE11;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE11_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE11) >> CAN_TXBCIE_CFIE11_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE11_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE11;
+	tmp |= value << CAN_TXBCIE_CFIE11_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE11_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE11;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE11_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE11;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE12_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE12;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE12_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE12) >> CAN_TXBCIE_CFIE12_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE12_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE12;
+	tmp |= value << CAN_TXBCIE_CFIE12_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE12_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE12;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE12_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE12;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE13_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE13;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE13_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE13) >> CAN_TXBCIE_CFIE13_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE13_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE13;
+	tmp |= value << CAN_TXBCIE_CFIE13_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE13_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE13;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE13_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE13;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE14_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE14;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE14_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE14) >> CAN_TXBCIE_CFIE14_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE14_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE14;
+	tmp |= value << CAN_TXBCIE_CFIE14_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE14_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE14;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE14_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE14;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE15_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE15;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE15_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE15) >> CAN_TXBCIE_CFIE15_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE15_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE15;
+	tmp |= value << CAN_TXBCIE_CFIE15_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE15_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE15;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE15_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE15;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE16_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE16;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE16_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE16) >> CAN_TXBCIE_CFIE16_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE16_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE16;
+	tmp |= value << CAN_TXBCIE_CFIE16_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE16_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE16;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE16_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE16;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE17_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE17;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE17_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE17) >> CAN_TXBCIE_CFIE17_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE17_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE17;
+	tmp |= value << CAN_TXBCIE_CFIE17_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE17_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE17;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE17_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE17;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE18_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE18;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE18_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE18) >> CAN_TXBCIE_CFIE18_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE18_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE18;
+	tmp |= value << CAN_TXBCIE_CFIE18_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE18_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE18;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE18_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE18;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE19_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE19;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE19_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE19) >> CAN_TXBCIE_CFIE19_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE19_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE19;
+	tmp |= value << CAN_TXBCIE_CFIE19_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE19_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE19;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE19_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE19;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE20_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE20;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE20_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE20) >> CAN_TXBCIE_CFIE20_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE20_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE20;
+	tmp |= value << CAN_TXBCIE_CFIE20_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE20_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE20;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE20_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE20;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE21_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE21;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE21_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE21) >> CAN_TXBCIE_CFIE21_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE21_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE21;
+	tmp |= value << CAN_TXBCIE_CFIE21_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE21_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE21;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE21_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE21;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE22_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE22;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE22_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE22) >> CAN_TXBCIE_CFIE22_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE22_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE22;
+	tmp |= value << CAN_TXBCIE_CFIE22_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE22_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE22;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE22_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE22;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE23_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE23;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE23_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE23) >> CAN_TXBCIE_CFIE23_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE23_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE23;
+	tmp |= value << CAN_TXBCIE_CFIE23_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE23_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE23;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE23_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE23;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE24_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE24;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE24_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE24) >> CAN_TXBCIE_CFIE24_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE24_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE24;
+	tmp |= value << CAN_TXBCIE_CFIE24_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE24_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE24;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE24_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE24;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE25_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE25;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE25_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE25) >> CAN_TXBCIE_CFIE25_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE25_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE25;
+	tmp |= value << CAN_TXBCIE_CFIE25_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE25_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE25;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE25_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE25;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE26_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE26;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE26_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE26) >> CAN_TXBCIE_CFIE26_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE26_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE26;
+	tmp |= value << CAN_TXBCIE_CFIE26_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE26_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE26;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE26_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE26;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE27_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE27;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE27_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE27) >> CAN_TXBCIE_CFIE27_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE27_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE27;
+	tmp |= value << CAN_TXBCIE_CFIE27_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE27_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE27;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE27_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE27;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE28_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE28;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE28_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE28) >> CAN_TXBCIE_CFIE28_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE28_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE28;
+	tmp |= value << CAN_TXBCIE_CFIE28_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE28_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE28;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE28_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE28;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE29_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE29;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE29_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE29) >> CAN_TXBCIE_CFIE29_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE29_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE29;
+	tmp |= value << CAN_TXBCIE_CFIE29_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE29_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE29;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE29_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE29;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE30_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE30;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE30_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE30) >> CAN_TXBCIE_CFIE30_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE30_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE30;
+	tmp |= value << CAN_TXBCIE_CFIE30_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE30_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE30;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE30_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE30;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_CFIE31_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE31;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_can_get_TXBCIE_CFIE31_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp = (tmp & CAN_TXBCIE_CFIE31) >> CAN_TXBCIE_CFIE31_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_can_write_TXBCIE_CFIE31_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= ~CAN_TXBCIE_CFIE31;
+	tmp |= value << CAN_TXBCIE_CFIE31_Pos;
+	((Can *)hw)->TXBCIE.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_CFIE31_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE31;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_CFIE31_bit(const void *const hw)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE31;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_set_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txbcie_reg_t hri_can_get_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXBCIE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXBCIE.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txbcie_reg_t hri_can_read_TXBCIE_reg(const void *const hw)
+{
+	return ((Can *)hw)->TXBCIE.reg;
+}
+
+static inline void hri_can_set_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFSA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXEFC.reg;
+	tmp = (tmp & CAN_TXEFC_EFSA(mask)) >> CAN_TXEFC_EFSA_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXEFC.reg;
+	tmp &= ~CAN_TXEFC_EFSA_Msk;
+	tmp |= CAN_TXEFC_EFSA(data);
+	((Can *)hw)->TXEFC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFSA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFSA(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFSA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXEFC.reg;
+	tmp = (tmp & CAN_TXEFC_EFSA_Msk) >> CAN_TXEFC_EFSA_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXEFC.reg;
+	tmp = (tmp & CAN_TXEFC_EFS(mask)) >> CAN_TXEFC_EFS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXEFC.reg;
+	tmp &= ~CAN_TXEFC_EFS_Msk;
+	tmp |= CAN_TXEFC_EFS(data);
+	((Can *)hw)->TXEFC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFS(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXEFC.reg;
+	tmp = (tmp & CAN_TXEFC_EFS_Msk) >> CAN_TXEFC_EFS_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFWM(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXEFC.reg;
+	tmp = (tmp & CAN_TXEFC_EFWM(mask)) >> CAN_TXEFC_EFWM_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXEFC.reg;
+	tmp &= ~CAN_TXEFC_EFWM_Msk;
+	tmp |= CAN_TXEFC_EFWM(data);
+	((Can *)hw)->TXEFC.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFWM(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFWM(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFWM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXEFC.reg;
+	tmp = (tmp & CAN_TXEFC_EFWM_Msk) >> CAN_TXEFC_EFWM_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFC.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txefc_reg_t hri_can_get_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXEFC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFC.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFC.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFC.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txefc_reg_t hri_can_read_TXEFC_reg(const void *const hw)
+{
+	return ((Can *)hw)->TXEFC.reg;
+}
+
+static inline void hri_can_set_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFA.reg |= CAN_TXEFA_EFAI(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txefa_reg_t hri_can_get_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXEFA.reg;
+	tmp = (tmp & CAN_TXEFA_EFAI(mask)) >> CAN_TXEFA_EFAI_Pos;
+	return tmp;
+}
+
+static inline void hri_can_write_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t data)
+{
+	uint32_t tmp;
+	CAN_CRITICAL_SECTION_ENTER();
+	tmp = ((Can *)hw)->TXEFA.reg;
+	tmp &= ~CAN_TXEFA_EFAI_Msk;
+	tmp |= CAN_TXEFA_EFAI(data);
+	((Can *)hw)->TXEFA.reg = tmp;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFA.reg &= ~CAN_TXEFA_EFAI(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFA.reg ^= CAN_TXEFA_EFAI(mask);
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txefa_reg_t hri_can_read_TXEFA_EFAI_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXEFA.reg;
+	tmp = (tmp & CAN_TXEFA_EFAI_Msk) >> CAN_TXEFA_EFAI_Pos;
+	return tmp;
+}
+
+static inline void hri_can_set_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFA.reg |= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txefa_reg_t hri_can_get_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Can *)hw)->TXEFA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_can_write_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t data)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFA.reg = data;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_clear_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFA.reg &= ~mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_can_toggle_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask)
+{
+	CAN_CRITICAL_SECTION_ENTER();
+	((Can *)hw)->TXEFA.reg ^= mask;
+	CAN_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_can_txefa_reg_t hri_can_read_TXEFA_reg(const void *const hw)
+{
+	return ((Can *)hw)->TXEFA.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_CAN_E54_H_INCLUDED */
+#endif /* _SAME54_CAN_COMPONENT_ */
diff --git a/hri/hri_ccl_e54.h b/hri/hri_ccl_e54.h
new file mode 100644
index 0000000..c5c4867
--- /dev/null
+++ b/hri/hri_ccl_e54.h
@@ -0,0 +1,776 @@
+/**
+ * \file
+ *
+ * \brief SAM CCL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_CCL_COMPONENT_
+#ifndef _HRI_CCL_E54_H_INCLUDED_
+#define _HRI_CCL_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_CCL_CRITICAL_SECTIONS)
+#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define CCL_CRITICAL_SECTION_ENTER()
+#define CCL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_ccl_lutctrl_reg_t;
+typedef uint8_t  hri_ccl_ctrl_reg_t;
+typedef uint8_t  hri_ccl_seqctrl_reg_t;
+
+static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp &= ~CCL_CTRL_ENABLE;
+	tmp |= value << CCL_CTRL_ENABLE_Pos;
+	((Ccl *)hw)->CTRL.reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp &= ~CCL_CTRL_RUNSTDBY;
+	tmp |= value << CCL_CTRL_RUNSTDBY_Pos;
+	((Ccl *)hw)->CTRL.reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg = data;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg &= ~mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg ^= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw)
+{
+	return ((Ccl *)hw)->CTRL.reg;
+}
+
+static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_seqctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data)
+{
+	uint8_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp &= ~CCL_SEQCTRL_SEQSEL_Msk;
+	tmp |= CCL_SEQCTRL_SEQSEL(data);
+	((Ccl *)hw)->SEQCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg |= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_ccl_seqctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg = data;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg &= ~mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg ^= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((Ccl *)hw)->SEQCTRL[index].reg;
+}
+
+static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_ENABLE;
+	tmp |= value << CCL_LUTCTRL_ENABLE_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_EDGESEL;
+	tmp |= value << CCL_LUTCTRL_EDGESEL_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INVEI;
+	tmp |= value << CCL_LUTCTRL_INVEI_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_LUTEI;
+	tmp |= value << CCL_LUTCTRL_LUTEI_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_LUTEO;
+	tmp |= value << CCL_LUTCTRL_LUTEO_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index,
+                                                                   hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_FILTSEL_Msk;
+	tmp |= CCL_LUTCTRL_FILTSEL(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INSEL0_Msk;
+	tmp |= CCL_LUTCTRL_INSEL0(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INSEL1_Msk;
+	tmp |= CCL_LUTCTRL_INSEL1(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INSEL2_Msk;
+	tmp |= CCL_LUTCTRL_INSEL2(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index,
+                                                                 hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_TRUTH_Msk;
+	tmp |= CCL_LUTCTRL_TRUTH(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg = data;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((Ccl *)hw)->LUTCTRL[index].reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_CCL_E54_H_INCLUDED */
+#endif /* _SAME54_CCL_COMPONENT_ */
diff --git a/hri/hri_cmcc_e54.h b/hri/hri_cmcc_e54.h
new file mode 100644
index 0000000..c973d35
--- /dev/null
+++ b/hri/hri_cmcc_e54.h
@@ -0,0 +1,361 @@
+/**
+ * \file
+ *
+ * \brief SAM CMCC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_CMCC_COMPONENT_
+#ifndef _HRI_CMCC_E54_H_INCLUDED_
+#define _HRI_CMCC_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_CMCC_CRITICAL_SECTIONS)
+#define CMCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define CMCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define CMCC_CRITICAL_SECTION_ENTER()
+#define CMCC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_cmcc_cfg_reg_t;
+typedef uint32_t hri_cmcc_ctrl_reg_t;
+typedef uint32_t hri_cmcc_lckway_reg_t;
+typedef uint32_t hri_cmcc_maint0_reg_t;
+typedef uint32_t hri_cmcc_maint1_reg_t;
+typedef uint32_t hri_cmcc_mcfg_reg_t;
+typedef uint32_t hri_cmcc_mctrl_reg_t;
+typedef uint32_t hri_cmcc_men_reg_t;
+typedef uint32_t hri_cmcc_msr_reg_t;
+typedef uint32_t hri_cmcc_sr_reg_t;
+typedef uint32_t hri_cmcc_type_reg_t;
+
+static inline bool hri_cmcc_get_TYPE_GCLK_bit(const void *const hw)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_GCLK) >> CMCC_TYPE_GCLK_Pos;
+}
+
+static inline bool hri_cmcc_get_TYPE_RRP_bit(const void *const hw)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_RRP) >> CMCC_TYPE_RRP_Pos;
+}
+
+static inline bool hri_cmcc_get_TYPE_LCKDOWN_bit(const void *const hw)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_LCKDOWN) >> CMCC_TYPE_LCKDOWN_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_WAYNUM_bf(const void *const hw, hri_cmcc_type_reg_t mask)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM(mask)) >> CMCC_TYPE_WAYNUM_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_WAYNUM_bf(const void *const hw)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM_Msk) >> CMCC_TYPE_WAYNUM_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE(mask)) >> CMCC_TYPE_CSIZE_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CSIZE_bf(const void *const hw)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE_Msk) >> CMCC_TYPE_CSIZE_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CLSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE(mask)) >> CMCC_TYPE_CLSIZE_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CLSIZE_bf(const void *const hw)
+{
+	return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE_Msk) >> CMCC_TYPE_CLSIZE_Pos;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_reg(const void *const hw, hri_cmcc_type_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->TYPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->TYPE.reg;
+}
+
+static inline bool hri_cmcc_get_SR_CSTS_bit(const void *const hw)
+{
+	return (((Cmcc *)hw)->SR.reg & CMCC_SR_CSTS) >> CMCC_SR_CSTS_Pos;
+}
+
+static inline hri_cmcc_sr_reg_t hri_cmcc_get_SR_reg(const void *const hw, hri_cmcc_sr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->SR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_cmcc_sr_reg_t hri_cmcc_read_SR_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->SR.reg;
+}
+
+static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_EVENT_CNT_bf(const void *const hw, hri_cmcc_msr_reg_t mask)
+{
+	return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT(mask)) >> CMCC_MSR_EVENT_CNT_Pos;
+}
+
+static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_EVENT_CNT_bf(const void *const hw)
+{
+	return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT_Msk) >> CMCC_MSR_EVENT_CNT_Pos;
+}
+
+static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_reg(const void *const hw, hri_cmcc_msr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->MSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->MSR.reg;
+}
+
+static inline void hri_cmcc_set_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->CFG.reg |= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_cfg_reg_t hri_cmcc_get_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->CFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_cmcc_write_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->CFG.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_clear_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->CFG.reg &= ~mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_toggle_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->CFG.reg ^= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_cfg_reg_t hri_cmcc_read_CFG_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->CFG.reg;
+}
+
+static inline void hri_cmcc_set_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->LCKWAY.reg |= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_lckway_reg_t hri_cmcc_get_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->LCKWAY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_cmcc_write_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->LCKWAY.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_clear_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->LCKWAY.reg &= ~mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_toggle_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->LCKWAY.reg ^= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_lckway_reg_t hri_cmcc_read_LCKWAY_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->LCKWAY.reg;
+}
+
+static inline void hri_cmcc_set_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MCFG.reg |= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_mcfg_reg_t hri_cmcc_get_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->MCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_cmcc_write_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MCFG.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_clear_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MCFG.reg &= ~mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_toggle_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MCFG.reg ^= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_mcfg_reg_t hri_cmcc_read_MCFG_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->MCFG.reg;
+}
+
+static inline void hri_cmcc_set_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MEN.reg |= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_men_reg_t hri_cmcc_get_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Cmcc *)hw)->MEN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_cmcc_write_MEN_reg(const void *const hw, hri_cmcc_men_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MEN.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_clear_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MEN.reg &= ~mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_toggle_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MEN.reg ^= mask;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_cmcc_men_reg_t hri_cmcc_read_MEN_reg(const void *const hw)
+{
+	return ((Cmcc *)hw)->MEN.reg;
+}
+
+static inline void hri_cmcc_write_CTRL_reg(const void *const hw, hri_cmcc_ctrl_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->CTRL.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_write_MAINT0_reg(const void *const hw, hri_cmcc_maint0_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MAINT0.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_write_MAINT1_reg(const void *const hw, hri_cmcc_maint1_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MAINT1.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_cmcc_write_MCTRL_reg(const void *const hw, hri_cmcc_mctrl_reg_t data)
+{
+	CMCC_CRITICAL_SECTION_ENTER();
+	((Cmcc *)hw)->MCTRL.reg = data;
+	CMCC_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_CMCC_E54_H_INCLUDED */
+#endif /* _SAME54_CMCC_COMPONENT_ */
diff --git a/hri/hri_dac_e54.h b/hri/hri_dac_e54.h
new file mode 100644
index 0000000..911dd52
--- /dev/null
+++ b/hri/hri_dac_e54.h
@@ -0,0 +1,1706 @@
+/**
+ * \file
+ *
+ * \brief SAM DAC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_DAC_COMPONENT_
+#ifndef _HRI_DAC_E54_H_INCLUDED_
+#define _HRI_DAC_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_DAC_CRITICAL_SECTIONS)
+#define DAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define DAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define DAC_CRITICAL_SECTION_ENTER()
+#define DAC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_dac_dacctrl_reg_t;
+typedef uint16_t hri_dac_data_reg_t;
+typedef uint16_t hri_dac_databuf_reg_t;
+typedef uint16_t hri_dac_result_reg_t;
+typedef uint32_t hri_dac_syncbusy_reg_t;
+typedef uint8_t  hri_dac_ctrla_reg_t;
+typedef uint8_t  hri_dac_ctrlb_reg_t;
+typedef uint8_t  hri_dac_dbgctrl_reg_t;
+typedef uint8_t  hri_dac_evctrl_reg_t;
+typedef uint8_t  hri_dac_intenset_reg_t;
+typedef uint8_t  hri_dac_intflag_reg_t;
+typedef uint8_t  hri_dac_status_reg_t;
+
+static inline void hri_dac_wait_for_sync(const void *const hw, hri_dac_syncbusy_reg_t reg)
+{
+	while (((Dac *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_dac_is_syncing(const void *const hw, hri_dac_syncbusy_reg_t reg)
+{
+	return ((Dac *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_dac_get_INTFLAG_UNDERRUN0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_UNDERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0;
+}
+
+static inline bool hri_dac_get_INTFLAG_UNDERRUN1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_UNDERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1;
+}
+
+static inline bool hri_dac_get_INTFLAG_EMPTY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_EMPTY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0;
+}
+
+static inline bool hri_dac_get_INTFLAG_EMPTY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_EMPTY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1;
+}
+
+static inline bool hri_dac_get_INTFLAG_RESRDY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_RESRDY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0;
+}
+
+static inline bool hri_dac_get_INTFLAG_RESRDY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_RESRDY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1;
+}
+
+static inline bool hri_dac_get_INTFLAG_OVERRUN0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_OVERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0;
+}
+
+static inline bool hri_dac_get_INTFLAG_OVERRUN1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos;
+}
+
+static inline void hri_dac_clear_INTFLAG_OVERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1;
+}
+
+static inline bool hri_dac_get_interrupt_UNDERRUN0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_UNDERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0;
+}
+
+static inline bool hri_dac_get_interrupt_UNDERRUN1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_UNDERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1;
+}
+
+static inline bool hri_dac_get_interrupt_EMPTY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_EMPTY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0;
+}
+
+static inline bool hri_dac_get_interrupt_EMPTY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_EMPTY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1;
+}
+
+static inline bool hri_dac_get_interrupt_RESRDY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_RESRDY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0;
+}
+
+static inline bool hri_dac_get_interrupt_RESRDY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_RESRDY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1;
+}
+
+static inline bool hri_dac_get_interrupt_OVERRUN0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_OVERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0;
+}
+
+static inline bool hri_dac_get_interrupt_OVERRUN1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos;
+}
+
+static inline void hri_dac_clear_interrupt_OVERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1;
+}
+
+static inline hri_dac_intflag_reg_t hri_dac_get_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dac_intflag_reg_t hri_dac_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Dac *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_dac_clear_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask)
+{
+	((Dac *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_dac_set_INTEN_UNDERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0;
+}
+
+static inline bool hri_dac_get_INTEN_UNDERRUN0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN0) >> DAC_INTENSET_UNDERRUN0_Pos;
+}
+
+static inline void hri_dac_write_INTEN_UNDERRUN0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_UNDERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0;
+}
+
+static inline void hri_dac_set_INTEN_UNDERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1;
+}
+
+static inline bool hri_dac_get_INTEN_UNDERRUN1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN1) >> DAC_INTENSET_UNDERRUN1_Pos;
+}
+
+static inline void hri_dac_write_INTEN_UNDERRUN1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_UNDERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1;
+}
+
+static inline void hri_dac_set_INTEN_EMPTY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0;
+}
+
+static inline bool hri_dac_get_INTEN_EMPTY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY0) >> DAC_INTENSET_EMPTY0_Pos;
+}
+
+static inline void hri_dac_write_INTEN_EMPTY0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_EMPTY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0;
+}
+
+static inline void hri_dac_set_INTEN_EMPTY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1;
+}
+
+static inline bool hri_dac_get_INTEN_EMPTY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY1) >> DAC_INTENSET_EMPTY1_Pos;
+}
+
+static inline void hri_dac_write_INTEN_EMPTY1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_EMPTY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1;
+}
+
+static inline void hri_dac_set_INTEN_RESRDY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0;
+}
+
+static inline bool hri_dac_get_INTEN_RESRDY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY0) >> DAC_INTENSET_RESRDY0_Pos;
+}
+
+static inline void hri_dac_write_INTEN_RESRDY0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_RESRDY0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0;
+}
+
+static inline void hri_dac_set_INTEN_RESRDY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1;
+}
+
+static inline bool hri_dac_get_INTEN_RESRDY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY1) >> DAC_INTENSET_RESRDY1_Pos;
+}
+
+static inline void hri_dac_write_INTEN_RESRDY1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_RESRDY1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1;
+}
+
+static inline void hri_dac_set_INTEN_OVERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0;
+}
+
+static inline bool hri_dac_get_INTEN_OVERRUN0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN0) >> DAC_INTENSET_OVERRUN0_Pos;
+}
+
+static inline void hri_dac_write_INTEN_OVERRUN0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_OVERRUN0_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0;
+}
+
+static inline void hri_dac_set_INTEN_OVERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1;
+}
+
+static inline bool hri_dac_get_INTEN_OVERRUN1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN1) >> DAC_INTENSET_OVERRUN1_Pos;
+}
+
+static inline void hri_dac_write_INTEN_OVERRUN1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1;
+	} else {
+		((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1;
+	}
+}
+
+static inline void hri_dac_clear_INTEN_OVERRUN1_bit(const void *const hw)
+{
+	((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1;
+}
+
+static inline void hri_dac_set_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask)
+{
+	((Dac *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_dac_intenset_reg_t hri_dac_get_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dac_intenset_reg_t hri_dac_read_INTEN_reg(const void *const hw)
+{
+	return ((Dac *)hw)->INTENSET.reg;
+}
+
+static inline void hri_dac_write_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t data)
+{
+	((Dac *)hw)->INTENSET.reg = data;
+	((Dac *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_dac_clear_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask)
+{
+	((Dac *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_dac_get_STATUS_READY0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY0) >> DAC_STATUS_READY0_Pos;
+}
+
+static inline bool hri_dac_get_STATUS_READY1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY1) >> DAC_STATUS_READY1_Pos;
+}
+
+static inline bool hri_dac_get_STATUS_EOC0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC0) >> DAC_STATUS_EOC0_Pos;
+}
+
+static inline bool hri_dac_get_STATUS_EOC1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC1) >> DAC_STATUS_EOC1_Pos;
+}
+
+static inline hri_dac_status_reg_t hri_dac_get_STATUS_reg(const void *const hw, hri_dac_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dac_status_reg_t hri_dac_read_STATUS_reg(const void *const hw)
+{
+	return ((Dac *)hw)->STATUS.reg;
+}
+
+static inline bool hri_dac_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) >> DAC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_dac_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_ENABLE) >> DAC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_dac_get_SYNCBUSY_DATA0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA0) >> DAC_SYNCBUSY_DATA0_Pos;
+}
+
+static inline bool hri_dac_get_SYNCBUSY_DATA1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA1) >> DAC_SYNCBUSY_DATA1_Pos;
+}
+
+static inline bool hri_dac_get_SYNCBUSY_DATABUF0_bit(const void *const hw)
+{
+	return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF0) >> DAC_SYNCBUSY_DATABUF0_Pos;
+}
+
+static inline bool hri_dac_get_SYNCBUSY_DATABUF1_bit(const void *const hw)
+{
+	return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF1) >> DAC_SYNCBUSY_DATABUF1_Pos;
+}
+
+static inline hri_dac_syncbusy_reg_t hri_dac_get_SYNCBUSY_reg(const void *const hw, hri_dac_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dac *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dac_syncbusy_reg_t hri_dac_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Dac *)hw)->SYNCBUSY.reg;
+}
+
+static inline hri_dac_result_reg_t hri_dac_get_RESULT_RESULT_bf(const void *const hw, uint8_t index,
+                                                                hri_dac_result_reg_t mask)
+{
+	return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT(mask)) >> DAC_RESULT_RESULT_Pos;
+}
+
+static inline hri_dac_result_reg_t hri_dac_read_RESULT_RESULT_bf(const void *const hw, uint8_t index)
+{
+	return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT_Msk) >> DAC_RESULT_RESULT_Pos;
+}
+
+static inline hri_dac_result_reg_t hri_dac_get_RESULT_reg(const void *const hw, uint8_t index,
+                                                          hri_dac_result_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->RESULT[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dac_result_reg_t hri_dac_read_RESULT_reg(const void *const hw, uint8_t index)
+{
+	return ((Dac *)hw)->RESULT[index].reg;
+}
+
+static inline void hri_dac_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST);
+	tmp = ((Dac *)hw)->CTRLA.reg;
+	tmp = (tmp & DAC_CTRLA_SWRST) >> DAC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	tmp = ((Dac *)hw)->CTRLA.reg;
+	tmp = (tmp & DAC_CTRLA_ENABLE) >> DAC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->CTRLA.reg;
+	tmp &= ~DAC_CTRLA_ENABLE;
+	tmp |= value << DAC_CTRLA_ENABLE_Pos;
+	((Dac *)hw)->CTRLA.reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg |= mask;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrla_reg_t hri_dac_get_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	tmp = ((Dac *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg = data;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg &= ~mask;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLA.reg ^= mask;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrla_reg_t hri_dac_read_CTRLA_reg(const void *const hw)
+{
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE);
+	return ((Dac *)hw)->CTRLA.reg;
+}
+
+static inline void hri_dac_set_CTRLB_DIFF_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_DIFF;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_CTRLB_DIFF_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp = (tmp & DAC_CTRLB_DIFF) >> DAC_CTRLB_DIFF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_CTRLB_DIFF_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp &= ~DAC_CTRLB_DIFF;
+	tmp |= value << DAC_CTRLB_DIFF_Pos;
+	((Dac *)hw)->CTRLB.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLB_DIFF_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_DIFF;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLB_DIFF_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_DIFF;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp = (tmp & DAC_CTRLB_REFSEL(mask)) >> DAC_CTRLB_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_write_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t data)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp &= ~DAC_CTRLB_REFSEL_Msk;
+	tmp |= DAC_CTRLB_REFSEL(data);
+	((Dac *)hw)->CTRLB.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_REFSEL(mask);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_REFSEL(mask);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_REFSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp = (tmp & DAC_CTRLB_REFSEL_Msk) >> DAC_CTRLB_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_set_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg |= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg = data;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg &= ~mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->CTRLB.reg ^= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_reg(const void *const hw)
+{
+	return ((Dac *)hw)->CTRLB.reg;
+}
+
+static inline void hri_dac_set_EVCTRL_STARTEI0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_STARTEI0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_STARTEI0) >> DAC_EVCTRL_STARTEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_STARTEI0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_STARTEI0;
+	tmp |= value << DAC_EVCTRL_STARTEI0_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_STARTEI0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_STARTEI0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_STARTEI1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_STARTEI1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_STARTEI1) >> DAC_EVCTRL_STARTEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_STARTEI1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_STARTEI1;
+	tmp |= value << DAC_EVCTRL_STARTEI1_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_STARTEI1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_STARTEI1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_EMPTYEO0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_EMPTYEO0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_EMPTYEO0) >> DAC_EVCTRL_EMPTYEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_EMPTYEO0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_EMPTYEO0;
+	tmp |= value << DAC_EVCTRL_EMPTYEO0_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_EMPTYEO0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_EMPTYEO0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_EMPTYEO1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_EMPTYEO1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_EMPTYEO1) >> DAC_EVCTRL_EMPTYEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_EMPTYEO1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_EMPTYEO1;
+	tmp |= value << DAC_EVCTRL_EMPTYEO1_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_EMPTYEO1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_EMPTYEO1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_INVEI0) >> DAC_EVCTRL_INVEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_INVEI0;
+	tmp |= value << DAC_EVCTRL_INVEI0_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_INVEI1) >> DAC_EVCTRL_INVEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_INVEI1;
+	tmp |= value << DAC_EVCTRL_INVEI1_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_RESRDYEO0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_RESRDYEO0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_RESRDYEO0) >> DAC_EVCTRL_RESRDYEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_RESRDYEO0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_RESRDYEO0;
+	tmp |= value << DAC_EVCTRL_RESRDYEO0_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_RESRDYEO0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_RESRDYEO0_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO0;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_RESRDYEO1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_EVCTRL_RESRDYEO1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp = (tmp & DAC_EVCTRL_RESRDYEO1) >> DAC_EVCTRL_RESRDYEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_RESRDYEO1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= ~DAC_EVCTRL_RESRDYEO1;
+	tmp |= value << DAC_EVCTRL_RESRDYEO1_Pos;
+	((Dac *)hw)->EVCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_RESRDYEO1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_RESRDYEO1_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO1;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg |= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_evctrl_reg_t hri_dac_get_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg = data;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg &= ~mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->EVCTRL.reg ^= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_evctrl_reg_t hri_dac_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Dac *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_dac_set_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_LEFTADJ;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_LEFTADJ) >> DAC_DACCTRL_LEFTADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_LEFTADJ;
+	tmp |= value << DAC_DACCTRL_LEFTADJ_Pos;
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_LEFTADJ;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_LEFTADJ;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_ENABLE;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_ENABLE) >> DAC_DACCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_ENABLE;
+	tmp |= value << DAC_DACCTRL_ENABLE_Pos;
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_ENABLE;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_ENABLE;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_DACCTRL_FEXT_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_FEXT;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_DACCTRL_FEXT_bit(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_FEXT) >> DAC_DACCTRL_FEXT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_FEXT_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_FEXT;
+	tmp |= value << DAC_DACCTRL_FEXT_Pos;
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_FEXT_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_FEXT;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_FEXT_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_FEXT;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_RUNSTDBY;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_RUNSTDBY) >> DAC_DACCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_RUNSTDBY;
+	tmp |= value << DAC_DACCTRL_RUNSTDBY_Pos;
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_RUNSTDBY;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_RUNSTDBY;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_DACCTRL_DITHER_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_DITHER;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_DACCTRL_DITHER_bit(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_DITHER) >> DAC_DACCTRL_DITHER_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_DITHER_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_DITHER;
+	tmp |= value << DAC_DACCTRL_DITHER_Pos;
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_DITHER_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_DITHER;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_DITHER_bit(const void *const hw, uint8_t index)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_DITHER;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_CCTRL(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index,
+                                                                 hri_dac_dacctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_CCTRL(mask)) >> DAC_DACCTRL_CCTRL_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_CCTRL_Msk;
+	tmp |= DAC_DACCTRL_CCTRL(data);
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_CCTRL(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_CCTRL(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_CCTRL_Msk) >> DAC_DACCTRL_CCTRL_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_set_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_REFRESH(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index,
+                                                                   hri_dac_dacctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_REFRESH(mask)) >> DAC_DACCTRL_REFRESH_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_REFRESH_Msk;
+	tmp |= DAC_DACCTRL_REFRESH(data);
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_REFRESH(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_REFRESH(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_REFRESH_Msk) >> DAC_DACCTRL_REFRESH_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_set_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_OSR(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_OSR_bf(const void *const hw, uint8_t index,
+                                                               hri_dac_dacctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_OSR(mask)) >> DAC_DACCTRL_OSR_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data)
+{
+	uint16_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= ~DAC_DACCTRL_OSR_Msk;
+	tmp |= DAC_DACCTRL_OSR(data);
+	((Dac *)hw)->DACCTRL[index].reg = tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_OSR(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_OSR(mask);
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_OSR_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp = (tmp & DAC_DACCTRL_OSR_Msk) >> DAC_DACCTRL_OSR_Pos;
+	return tmp;
+}
+
+static inline void hri_dac_set_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg |= mask;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_dac_dacctrl_reg_t mask)
+{
+	uint16_t tmp;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	tmp = ((Dac *)hw)->DACCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg = data;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg &= ~mask;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DACCTRL[index].reg ^= mask;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_reg(const void *const hw, uint8_t index)
+{
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE);
+	return ((Dac *)hw)->DACCTRL[index].reg;
+}
+
+static inline void hri_dac_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg |= DAC_DBGCTRL_DBGRUN;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dac_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->DBGCTRL.reg;
+	tmp = (tmp & DAC_DBGCTRL_DBGRUN) >> DAC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dac *)hw)->DBGCTRL.reg;
+	tmp &= ~DAC_DBGCTRL_DBGRUN;
+	tmp |= value << DAC_DBGCTRL_DBGRUN_Pos;
+	((Dac *)hw)->DBGCTRL.reg = tmp;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg &= ~DAC_DBGCTRL_DBGRUN;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg ^= DAC_DBGCTRL_DBGRUN;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_set_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg |= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dbgctrl_reg_t hri_dac_get_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dac *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dac_write_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg = data;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_clear_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg &= ~mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_toggle_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DBGCTRL.reg ^= mask;
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dac_dbgctrl_reg_t hri_dac_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Dac *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_dac_write_DATA_reg(const void *const hw, uint8_t index, hri_dac_data_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DATA[index].reg = data;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATA0 | DAC_SYNCBUSY_DATA1);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dac_write_DATABUF_reg(const void *const hw, uint8_t index, hri_dac_databuf_reg_t data)
+{
+	DAC_CRITICAL_SECTION_ENTER();
+	((Dac *)hw)->DATABUF[index].reg = data;
+	hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATABUF0 | DAC_SYNCBUSY_DATABUF1);
+	DAC_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_DAC_E54_H_INCLUDED */
+#endif /* _SAME54_DAC_COMPONENT_ */
diff --git a/hri/hri_dmac_e54.h b/hri/hri_dmac_e54.h
new file mode 100644
index 0000000..b4a6ba1
--- /dev/null
+++ b/hri/hri_dmac_e54.h
@@ -0,0 +1,6800 @@
+/**
+ * \file
+ *
+ * \brief SAM DMAC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_DMAC_COMPONENT_
+#ifndef _HRI_DMAC_E54_H_INCLUDED_
+#define _HRI_DMAC_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_DMAC_CRITICAL_SECTIONS)
+#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define DMAC_CRITICAL_SECTION_ENTER()
+#define DMAC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_dmac_crcctrl_reg_t;
+typedef uint16_t hri_dmac_ctrl_reg_t;
+typedef uint16_t hri_dmac_intpend_reg_t;
+typedef uint16_t hri_dmacdescriptor_btcnt_reg_t;
+typedef uint16_t hri_dmacdescriptor_btctrl_reg_t;
+typedef uint32_t hri_dmac_active_reg_t;
+typedef uint32_t hri_dmac_baseaddr_reg_t;
+typedef uint32_t hri_dmac_busych_reg_t;
+typedef uint32_t hri_dmac_chctrla_reg_t;
+typedef uint32_t hri_dmac_crcchksum_reg_t;
+typedef uint32_t hri_dmac_crcdatain_reg_t;
+typedef uint32_t hri_dmac_intstatus_reg_t;
+typedef uint32_t hri_dmac_pendch_reg_t;
+typedef uint32_t hri_dmac_prictrl0_reg_t;
+typedef uint32_t hri_dmac_swtrigctrl_reg_t;
+typedef uint32_t hri_dmac_wrbaddr_reg_t;
+typedef uint32_t hri_dmacchannel_chctrla_reg_t;
+typedef uint32_t hri_dmacdescriptor_descaddr_reg_t;
+typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t;
+typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t;
+typedef uint8_t  hri_dmac_chctrlb_reg_t;
+typedef uint8_t  hri_dmac_chevctrl_reg_t;
+typedef uint8_t  hri_dmac_chintenset_reg_t;
+typedef uint8_t  hri_dmac_chintflag_reg_t;
+typedef uint8_t  hri_dmac_chprilvl_reg_t;
+typedef uint8_t  hri_dmac_chstatus_reg_t;
+typedef uint8_t  hri_dmac_crcstatus_reg_t;
+typedef uint8_t  hri_dmac_dbgctrl_reg_t;
+typedef uint8_t  hri_dmacchannel_chctrlb_reg_t;
+typedef uint8_t  hri_dmacchannel_chevctrl_reg_t;
+typedef uint8_t  hri_dmacchannel_chintenset_reg_t;
+typedef uint8_t  hri_dmacchannel_chintflag_reg_t;
+typedef uint8_t  hri_dmacchannel_chprilvl_reg_t;
+typedef uint8_t  hri_dmacchannel_chstatus_reg_t;
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT12_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT12) >> DMAC_INTSTATUS_CHINT12_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT13_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT13) >> DMAC_INTSTATUS_CHINT13_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT14_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT14) >> DMAC_INTSTATUS_CHINT14_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT15_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT15) >> DMAC_INTSTATUS_CHINT15_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT16_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT16) >> DMAC_INTSTATUS_CHINT16_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT17_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT17) >> DMAC_INTSTATUS_CHINT17_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT18_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT18) >> DMAC_INTSTATUS_CHINT18_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT19_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT19) >> DMAC_INTSTATUS_CHINT19_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT20_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT20) >> DMAC_INTSTATUS_CHINT20_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT21_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT21) >> DMAC_INTSTATUS_CHINT21_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT22_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT22) >> DMAC_INTSTATUS_CHINT22_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT23_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT23) >> DMAC_INTSTATUS_CHINT23_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT24_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT24) >> DMAC_INTSTATUS_CHINT24_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT25_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT25) >> DMAC_INTSTATUS_CHINT25_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT26_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT26) >> DMAC_INTSTATUS_CHINT26_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT27_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT27) >> DMAC_INTSTATUS_CHINT27_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT28_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT28) >> DMAC_INTSTATUS_CHINT28_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT29_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT29) >> DMAC_INTSTATUS_CHINT29_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT30_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT30) >> DMAC_INTSTATUS_CHINT30_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT31_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT31) >> DMAC_INTSTATUS_CHINT31_Pos;
+}
+
+static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->INTSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->INTSTATUS.reg;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH12_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH12) >> DMAC_BUSYCH_BUSYCH12_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH13_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH13) >> DMAC_BUSYCH_BUSYCH13_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH14_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH14) >> DMAC_BUSYCH_BUSYCH14_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH15_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH15) >> DMAC_BUSYCH_BUSYCH15_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH16_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH16) >> DMAC_BUSYCH_BUSYCH16_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH17_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH17) >> DMAC_BUSYCH_BUSYCH17_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH18_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH18) >> DMAC_BUSYCH_BUSYCH18_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH19_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH19) >> DMAC_BUSYCH_BUSYCH19_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH20_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH20) >> DMAC_BUSYCH_BUSYCH20_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH21_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH21) >> DMAC_BUSYCH_BUSYCH21_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH22_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH22) >> DMAC_BUSYCH_BUSYCH22_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH23_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH23) >> DMAC_BUSYCH_BUSYCH23_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH24_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH24) >> DMAC_BUSYCH_BUSYCH24_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH25_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH25) >> DMAC_BUSYCH_BUSYCH25_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH26_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH26) >> DMAC_BUSYCH_BUSYCH26_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH27_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH27) >> DMAC_BUSYCH_BUSYCH27_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH28_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH28) >> DMAC_BUSYCH_BUSYCH28_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH29_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH29) >> DMAC_BUSYCH_BUSYCH29_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH30_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH30) >> DMAC_BUSYCH_BUSYCH30_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH31_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH31) >> DMAC_BUSYCH_BUSYCH31_Pos;
+}
+
+static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BUSYCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->BUSYCH.reg;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH12_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH12) >> DMAC_PENDCH_PENDCH12_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH13_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH13) >> DMAC_PENDCH_PENDCH13_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH14_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH14) >> DMAC_PENDCH_PENDCH14_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH15_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH15) >> DMAC_PENDCH_PENDCH15_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH16_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH16) >> DMAC_PENDCH_PENDCH16_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH17_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH17) >> DMAC_PENDCH_PENDCH17_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH18_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH18) >> DMAC_PENDCH_PENDCH18_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH19_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH19) >> DMAC_PENDCH_PENDCH19_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH20_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH20) >> DMAC_PENDCH_PENDCH20_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH21_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH21) >> DMAC_PENDCH_PENDCH21_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH22_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH22) >> DMAC_PENDCH_PENDCH22_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH23_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH23) >> DMAC_PENDCH_PENDCH23_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH24_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH24) >> DMAC_PENDCH_PENDCH24_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH25_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH25) >> DMAC_PENDCH_PENDCH25_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH26_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH26) >> DMAC_PENDCH_PENDCH26_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH27_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH27) >> DMAC_PENDCH_PENDCH27_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH28_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH28) >> DMAC_PENDCH_PENDCH28_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH29_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH29) >> DMAC_PENDCH_PENDCH29_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH30_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH30) >> DMAC_PENDCH_PENDCH30_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH31_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH31) >> DMAC_PENDCH_PENDCH31_Pos;
+}
+
+static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PENDCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->PENDCH.reg;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->ACTIVE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->ACTIVE.reg;
+}
+
+static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_DMAENABLE;
+	tmp |= value << DMAC_CTRL_DMAENABLE_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN0;
+	tmp |= value << DMAC_CTRL_LVLEN0_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN1;
+	tmp |= value << DMAC_CTRL_LVLEN1_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN2;
+	tmp |= value << DMAC_CTRL_LVLEN2_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN3;
+	tmp |= value << DMAC_CTRL_LVLEN3_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CTRL.reg;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const      hw,
+                                                                         hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk;
+	tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk;
+	tmp |= DMAC_CRCCTRL_CRCPOLY(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk;
+	tmp |= DMAC_CRCCTRL_CRCSRC(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCMODE(mask)) >> DMAC_CRCCTRL_CRCMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCMODE_Msk;
+	tmp |= DMAC_CRCCTRL_CRCMODE(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCMODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCMODE_Msk) >> DMAC_CRCCTRL_CRCMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCCTRL.reg;
+}
+
+static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const        hw,
+                                                                           hri_dmac_crcdatain_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk;
+	tmp |= DMAC_CRCDATAIN_CRCDATAIN(data);
+	((Dmac *)hw)->CRCDATAIN.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCDATAIN.reg;
+}
+
+static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const        hw,
+                                                                           hri_dmac_crcchksum_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk;
+	tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data);
+	((Dmac *)hw)->CRCCHKSUM.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCCHKSUM.reg;
+}
+
+static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->DBGCTRL.reg;
+	tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->DBGCTRL.reg;
+	tmp &= ~DMAC_DBGCTRL_DBGRUN;
+	tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos;
+	((Dmac *)hw)->DBGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG12;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG12) >> DMAC_SWTRIGCTRL_SWTRIG12_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG12;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG12_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG12;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG12;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG13;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG13) >> DMAC_SWTRIGCTRL_SWTRIG13_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG13;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG13_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG13;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG13;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG14;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG14) >> DMAC_SWTRIGCTRL_SWTRIG14_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG14;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG14_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG14;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG14;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG15;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG15) >> DMAC_SWTRIGCTRL_SWTRIG15_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG15;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG15_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG15;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG15;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG16_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG16;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG16_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG16) >> DMAC_SWTRIGCTRL_SWTRIG16_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG16_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG16;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG16_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG16_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG16;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG16_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG16;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG17_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG17;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG17_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG17) >> DMAC_SWTRIGCTRL_SWTRIG17_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG17_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG17;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG17_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG17_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG17;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG17_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG17;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG18_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG18;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG18_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG18) >> DMAC_SWTRIGCTRL_SWTRIG18_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG18_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG18;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG18_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG18_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG18;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG18_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG18;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG19_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG19;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG19_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG19) >> DMAC_SWTRIGCTRL_SWTRIG19_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG19_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG19;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG19_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG19_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG19;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG19_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG19;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG20_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG20;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG20_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG20) >> DMAC_SWTRIGCTRL_SWTRIG20_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG20_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG20;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG20_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG20_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG20;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG20_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG20;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG21_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG21;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG21_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG21) >> DMAC_SWTRIGCTRL_SWTRIG21_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG21_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG21;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG21_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG21_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG21;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG21_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG21;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG22_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG22;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG22_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG22) >> DMAC_SWTRIGCTRL_SWTRIG22_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG22_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG22;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG22_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG22_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG22;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG22_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG22;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG23_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG23;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG23_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG23) >> DMAC_SWTRIGCTRL_SWTRIG23_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG23_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG23;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG23_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG23_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG23;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG23_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG23;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG24_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG24;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG24_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG24) >> DMAC_SWTRIGCTRL_SWTRIG24_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG24_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG24;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG24_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG24_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG24;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG24_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG24;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG25_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG25;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG25_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG25) >> DMAC_SWTRIGCTRL_SWTRIG25_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG25_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG25;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG25_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG25_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG25;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG25_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG25;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG26_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG26;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG26_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG26) >> DMAC_SWTRIGCTRL_SWTRIG26_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG26_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG26;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG26_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG26_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG26;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG26_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG26;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG27_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG27;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG27_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG27) >> DMAC_SWTRIGCTRL_SWTRIG27_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG27_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG27;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG27_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG27_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG27;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG27_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG27;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG28_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG28;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG28_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG28) >> DMAC_SWTRIGCTRL_SWTRIG28_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG28_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG28;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG28_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG28_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG28;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG28_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG28;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG29_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG29;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG29_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG29) >> DMAC_SWTRIGCTRL_SWTRIG29_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG29_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG29;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG29_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG29_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG29;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG29_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG29;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG30_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG30;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG30_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG30) >> DMAC_SWTRIGCTRL_SWTRIG30_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG30_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG30;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG30_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG30_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG30;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG30_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG30;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG31_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG31;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG31_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG31) >> DMAC_SWTRIGCTRL_SWTRIG31_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG31_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG31;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG31_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG31_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG31;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG31_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG31;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const         hw,
+                                                                    hri_dmac_swtrigctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->SWTRIGCTRL.reg;
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN0;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN1;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN2;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN3;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI0(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS0(mask)) >> DMAC_PRICTRL0_QOS0_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_QOS0_Msk;
+	tmp |= DMAC_PRICTRL0_QOS0(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS0_Msk) >> DMAC_PRICTRL0_QOS0_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI1(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS1(mask)) >> DMAC_PRICTRL0_QOS1_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_QOS1_Msk;
+	tmp |= DMAC_PRICTRL0_QOS1(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS1_Msk) >> DMAC_PRICTRL0_QOS1_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI2(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS2(mask)) >> DMAC_PRICTRL0_QOS2_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_QOS2_Msk;
+	tmp |= DMAC_PRICTRL0_QOS2(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS2_Msk) >> DMAC_PRICTRL0_QOS2_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI3(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS3(mask)) >> DMAC_PRICTRL0_QOS3_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_QOS3_Msk;
+	tmp |= DMAC_PRICTRL0_QOS3(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_QOS3_Msk) >> DMAC_PRICTRL0_QOS3_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->PRICTRL0.reg;
+}
+
+static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_TERR;
+	tmp |= value << DMAC_INTPEND_TERR_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_TCMPL;
+	tmp |= value << DMAC_INTPEND_TCMPL_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_SUSP;
+	tmp |= value << DMAC_INTPEND_SUSP_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_CRCERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_CRCERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_CRCERR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_CRCERR) >> DMAC_INTPEND_CRCERR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_CRCERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_CRCERR;
+	tmp |= value << DMAC_INTPEND_CRCERR_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_CRCERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_CRCERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_CRCERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_CRCERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_FERR;
+	tmp |= value << DMAC_INTPEND_FERR_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_BUSY;
+	tmp |= value << DMAC_INTPEND_BUSY_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_PEND;
+	tmp |= value << DMAC_INTPEND_PEND_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_ID_Msk;
+	tmp |= DMAC_INTPEND_ID(data);
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->INTPEND.reg;
+}
+
+static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const       hw,
+                                                                        hri_dmac_baseaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp &= ~DMAC_BASEADDR_BASEADDR_Msk;
+	tmp |= DMAC_BASEADDR_BASEADDR(data);
+	((Dmac *)hw)->BASEADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->BASEADDR.reg;
+}
+
+static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp &= ~DMAC_WRBADDR_WRBADDR_Msk;
+	tmp |= DMAC_WRBADDR_WRBADDR(data);
+	((Dmac *)hw)->WRBADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->WRBADDR.reg;
+}
+
+static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CRCSTATUS_CRCERR_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCERR) >> DMAC_CRCSTATUS_CRCERR_Pos;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_CRCERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CRCSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCSTATUS.reg;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_VALID;
+	tmp |= value << DMAC_BTCTRL_VALID_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_SRCINC;
+	tmp |= value << DMAC_BTCTRL_SRCINC_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_DSTINC;
+	tmp |= value << DMAC_BTCTRL_DSTINC_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_STEPSEL;
+	tmp |= value << DMAC_BTCTRL_STEPSEL_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_EVOSEL_Msk;
+	tmp |= DMAC_BTCTRL_EVOSEL(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const               hw,
+                                                              hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk;
+	tmp |= DMAC_BTCTRL_BLOCKACT(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const               hw,
+                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk;
+	tmp |= DMAC_BTCTRL_BEATSIZE(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const               hw,
+                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk;
+	tmp |= DMAC_BTCTRL_STEPSIZE(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const               hw,
+                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const               hw,
+                                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->BTCTRL.reg;
+}
+
+static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const              hw,
+                                                                                   hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp &= ~DMAC_BTCNT_BTCNT_Msk;
+	tmp |= DMAC_BTCNT_BTCNT(data);
+	((DmacDescriptor *)hw)->BTCNT.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const              hw,
+                                                                              hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->BTCNT.reg;
+}
+
+static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                             hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t
+hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_srcaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp &= ~DMAC_SRCADDR_SRCADDR_Msk;
+	tmp |= DMAC_SRCADDR_SRCADDR(data);
+	((DmacDescriptor *)hw)->SRCADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                                hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const                hw,
+                                                                                  hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->SRCADDR.reg;
+}
+
+static inline void hri_dmacdescriptor_set_DSTADDR_CRC_CHKINIT_bf(const void *const                hw,
+                                                                 hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_CRC_CHKINIT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t
+hri_dmacdescriptor_get_DSTADDR_CRC_CHKINIT_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT(mask)) >> DMAC_DSTADDR_CRC_CHKINIT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DSTADDR_CRC_CHKINIT_bf(const void *const                hw,
+                                                                   hri_dmacdescriptor_dstaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp &= ~DMAC_DSTADDR_CRC_CHKINIT_Msk;
+	tmp |= DMAC_DSTADDR_CRC_CHKINIT(data);
+	((DmacDescriptor *)hw)->DSTADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DSTADDR_CRC_CHKINIT_bf(const void *const                hw,
+                                                                   hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_CRC_CHKINIT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DSTADDR_CRC_CHKINIT_bf(const void *const                hw,
+                                                                    hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_CRC_CHKINIT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_CRC_CHKINIT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT_Msk) >> DMAC_DSTADDR_CRC_CHKINIT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                             hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t
+hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_dstaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp &= ~DMAC_DSTADDR_DSTADDR_Msk;
+	tmp |= DMAC_DSTADDR_DSTADDR(data);
+	((DmacDescriptor *)hw)->DSTADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                                hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const                hw,
+                                                                                  hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->DSTADDR.reg;
+}
+
+static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                               hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t
+hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                                 hri_dmacdescriptor_descaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp &= ~DMAC_DESCADDR_DESCADDR_Msk;
+	tmp |= DMAC_DESCADDR_DESCADDR(data);
+	((DmacDescriptor *)hw)->DESCADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                                 hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                                  hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t
+hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->DESCADDR.reg;
+}
+
+static inline bool hri_dmacchannel_get_CHINTFLAG_TERR_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHINTFLAG_TERR_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
+}
+
+static inline bool hri_dmacchannel_get_CHINTFLAG_TCMPL_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHINTFLAG_TCMPL_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
+}
+
+static inline bool hri_dmacchannel_get_CHINTFLAG_SUSP_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHINTFLAG_SUSP_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
+}
+
+static inline bool hri_dmacchannel_get_interrupt_TERR_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
+}
+
+static inline void hri_dmacchannel_clear_interrupt_TERR_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
+}
+
+static inline bool hri_dmacchannel_get_interrupt_TCMPL_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
+}
+
+static inline void hri_dmacchannel_clear_interrupt_TCMPL_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
+}
+
+static inline bool hri_dmacchannel_get_interrupt_SUSP_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
+}
+
+static inline void hri_dmacchannel_clear_interrupt_SUSP_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
+}
+
+static inline hri_dmac_chintflag_reg_t hri_dmacchannel_get_CHINTFLAG_reg(const void *const        hw,
+                                                                         hri_dmac_chintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chintflag_reg_t hri_dmacchannel_read_CHINTFLAG_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHINTFLAG.reg;
+}
+
+static inline void hri_dmacchannel_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask)
+{
+	((DmacChannel *)hw)->CHINTFLAG.reg = mask;
+}
+
+static inline void hri_dmacchannel_set_CHINTEN_TERR_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR;
+}
+
+static inline bool hri_dmacchannel_get_CHINTEN_TERR_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos;
+}
+
+static inline void hri_dmacchannel_write_CHINTEN_TERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
+	} else {
+		((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR;
+	}
+}
+
+static inline void hri_dmacchannel_clear_CHINTEN_TERR_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
+}
+
+static inline void hri_dmacchannel_set_CHINTEN_TCMPL_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
+}
+
+static inline bool hri_dmacchannel_get_CHINTEN_TCMPL_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos;
+}
+
+static inline void hri_dmacchannel_write_CHINTEN_TCMPL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
+	} else {
+		((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
+	}
+}
+
+static inline void hri_dmacchannel_clear_CHINTEN_TCMPL_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
+}
+
+static inline void hri_dmacchannel_set_CHINTEN_SUSP_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
+}
+
+static inline bool hri_dmacchannel_get_CHINTEN_SUSP_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos;
+}
+
+static inline void hri_dmacchannel_write_CHINTEN_SUSP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
+	} else {
+		((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
+	}
+}
+
+static inline void hri_dmacchannel_clear_CHINTEN_SUSP_bit(const void *const hw)
+{
+	((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
+}
+
+static inline void hri_dmacchannel_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask)
+{
+	((DmacChannel *)hw)->CHINTENSET.reg = mask;
+}
+
+static inline hri_dmac_chintenset_reg_t hri_dmacchannel_get_CHINTEN_reg(const void *const         hw,
+                                                                        hri_dmac_chintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chintenset_reg_t hri_dmacchannel_read_CHINTEN_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHINTENSET.reg;
+}
+
+static inline void hri_dmacchannel_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data)
+{
+	((DmacChannel *)hw)->CHINTENSET.reg = data;
+	((DmacChannel *)hw)->CHINTENCLR.reg = ~data;
+}
+
+static inline void hri_dmacchannel_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask)
+{
+	((DmacChannel *)hw)->CHINTENCLR.reg = mask;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_SWRST_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHCTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_ENABLE;
+	tmp |= value << DMAC_CHCTRLA_ENABLE_Pos;
+	((DmacChannel *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_RUNSTDBY;
+	tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos;
+	((DmacChannel *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGSRC_bf(const void *const      hw,
+                                                                            hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk;
+	tmp |= DMAC_CHCTRLA_TRIGSRC(data);
+	((DmacChannel *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGSRC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGACT_bf(const void *const      hw,
+                                                                            hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk;
+	tmp |= DMAC_CHCTRLA_TRIGACT(data);
+	((DmacChannel *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_BURSTLEN_bf(const void *const      hw,
+                                                                             hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk;
+	tmp |= DMAC_CHCTRLA_BURSTLEN(data);
+	((DmacChannel *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_BURSTLEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_THRESHOLD_bf(const void *const      hw,
+                                                                              hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk;
+	tmp |= DMAC_CHCTRLA_THRESHOLD(data);
+	((DmacChannel *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_THRESHOLD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLA.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHCTRLA.reg;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_CMD_bf(const void *const      hw,
+                                                                        hri_dmac_chctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_CMD_Msk;
+	tmp |= DMAC_CHCTRLB_CMD(data);
+	((DmacChannel *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_CMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHCTRLB.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHCTRLB.reg;
+}
+
+static inline void hri_dmacchannel_set_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_PRILVL_bf(const void *const       hw,
+                                                                             hri_dmac_chprilvl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHPRILVL.reg;
+	tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHPRILVL.reg;
+	tmp &= ~DMAC_CHPRILVL_PRILVL_Msk;
+	tmp |= DMAC_CHPRILVL_PRILVL(data);
+	((DmacChannel *)hw)->CHPRILVL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_PRILVL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHPRILVL.reg;
+	tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_reg(const void *const       hw,
+                                                                       hri_dmac_chprilvl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHPRILVL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHPRILVL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHPRILVL.reg;
+}
+
+static inline void hri_dmacchannel_set_CHEVCTRL_EVIE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHEVCTRL_EVIE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacchannel_write_CHEVCTRL_EVIE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVIE;
+	tmp |= value << DMAC_CHEVCTRL_EVIE_Pos;
+	((DmacChannel *)hw)->CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHEVCTRL_EVIE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHEVCTRL_EVIE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_set_CHEVCTRL_EVOE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHEVCTRL_EVOE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacchannel_write_CHEVCTRL_EVOE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVOE;
+	tmp |= value << DMAC_CHEVCTRL_EVOE_Pos;
+	((DmacChannel *)hw)->CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHEVCTRL_EVOE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_set_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVACT_bf(const void *const       hw,
+                                                                            hri_dmac_chevctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVACT_Msk;
+	tmp |= DMAC_CHEVCTRL_EVACT(data);
+	((DmacChannel *)hw)->CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVACT_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVOMODE_bf(const void *const       hw,
+                                                                              hri_dmac_chevctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk;
+	tmp |= DMAC_CHEVCTRL_EVOMODE(data);
+	((DmacChannel *)hw)->CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVOMODE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_set_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_reg(const void *const       hw,
+                                                                       hri_dmac_chevctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHEVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_write_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_clear_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacchannel_toggle_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHEVCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHEVCTRL.reg;
+}
+
+static inline bool hri_dmacchannel_get_CHSTATUS_PEND_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHSTATUS_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHSTATUS_BUSY_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHSTATUS_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHSTATUS_FERR_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHSTATUS_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacchannel_get_CHSTATUS_CRCERR_bit(const void *const hw)
+{
+	return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos;
+}
+
+static inline void hri_dmacchannel_clear_CHSTATUS_CRCERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_CRCERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chstatus_reg_t hri_dmacchannel_get_CHSTATUS_reg(const void *const       hw,
+                                                                       hri_dmac_chstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((DmacChannel *)hw)->CHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacchannel_clear_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacChannel *)hw)->CHSTATUS.reg = mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chstatus_reg_t hri_dmacchannel_read_CHSTATUS_reg(const void *const hw)
+{
+	return ((DmacChannel *)hw)->CHSTATUS.reg;
+}
+
+static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
+}
+
+static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
+}
+
+static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
+}
+
+static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
+}
+
+static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
+}
+
+static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
+}
+
+static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
+}
+
+static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
+}
+
+static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
+}
+
+static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                                  hri_dmac_chintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_dmac_chintflag_reg_t mask)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask;
+}
+
+static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR;
+}
+
+static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos;
+}
+
+static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
+	} else {
+		((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR;
+	}
+}
+
+static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
+}
+
+static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
+}
+
+static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos;
+}
+
+static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
+	} else {
+		((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
+	}
+}
+
+static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
+}
+
+static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
+}
+
+static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos;
+}
+
+static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
+	} else {
+		((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
+	}
+}
+
+static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
+}
+
+static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                            hri_dmac_chintenset_reg_t mask)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = mask;
+}
+
+static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                                 hri_dmac_chintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg;
+}
+
+static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_dmac_chintenset_reg_t data)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = data;
+	((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data;
+}
+
+static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_dmac_chintenset_reg_t mask)
+{
+	((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask;
+}
+
+static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_SWRST;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_ENABLE;
+	tmp |= value << DMAC_CHCTRLA_ENABLE_Pos;
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_RUNSTDBY;
+	tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos;
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk;
+	tmp |= DMAC_CHCTRLA_TRIGSRC(data);
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk;
+	tmp |= DMAC_CHCTRLA_TRIGACT(data);
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk;
+	tmp |= DMAC_CHCTRLA_BURSTLEN(data);
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_dmac_chctrla_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk;
+	tmp |= DMAC_CHCTRLA_THRESHOLD(data);
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_dmac_chctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_dmac_chctrla_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg;
+}
+
+static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_dmac_chctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_dmac_chctrlb_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_CMD_Msk;
+	tmp |= DMAC_CHCTRLB_CMD(data);
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_dmac_chctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_dmac_chctrlb_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg;
+}
+
+static inline void hri_dmac_set_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_dmac_chprilvl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg;
+	tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chprilvl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg;
+	tmp &= ~DMAC_CHPRILVL_PRILVL_Msk;
+	tmp |= DMAC_CHPRILVL_PRILVL(data);
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg;
+	tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHPRILVL_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_dmac_chprilvl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHPRILVL_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chprilvl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHPRILVL_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHPRILVL_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_dmac_chprilvl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg;
+}
+
+static inline void hri_dmac_set_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVIE;
+	tmp |= value << DMAC_CHEVCTRL_EVIE_Pos;
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVOE;
+	tmp |= value << DMAC_CHEVCTRL_EVOE_Pos;
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_dmac_chevctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_dmac_chevctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVACT_Msk;
+	tmp |= DMAC_CHEVCTRL_EVACT(data);
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_dmac_chevctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chevctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk;
+	tmp |= DMAC_CHEVCTRL_EVOMODE(data);
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_dmac_chevctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chevctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_dmac_chevctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg;
+}
+
+static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos;
+}
+
+static inline void hri_dmac_clear_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos;
+}
+
+static inline void hri_dmac_clear_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos;
+}
+
+static inline void hri_dmac_clear_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos;
+}
+
+static inline void hri_dmac_clear_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_CRCERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_dmac_chstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_clear_CHSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_dmac_chstatus_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_dmacdescriptor_set_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_set_DSTADDR_reg(a, b)
+#define hri_dmacdescriptor_get_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_get_DSTADDR_reg(a, b)
+#define hri_dmacdescriptor_write_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_write_DSTADDR_reg(a, b)
+#define hri_dmacdescriptor_clear_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_clear_DSTADDR_reg(a, b)
+#define hri_dmacdescriptor_toggle_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_toggle_DSTADDR_reg(a, b)
+#define hri_dmacdescriptor_read_DSTADDR_CRC_reg(a) hri_dmacdescriptor_read_DSTADDR_reg(a)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_DMAC_E54_H_INCLUDED */
+#endif /* _SAME54_DMAC_COMPONENT_ */
diff --git a/hri/hri_dsu_e54.h b/hri/hri_dsu_e54.h
new file mode 100644
index 0000000..82e24b6
--- /dev/null
+++ b/hri/hri_dsu_e54.h
@@ -0,0 +1,1356 @@
+/**
+ * \file
+ *
+ * \brief SAM DSU
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_DSU_COMPONENT_
+#ifndef _HRI_DSU_E54_H_INCLUDED_
+#define _HRI_DSU_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_DSU_CRITICAL_SECTIONS)
+#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define DSU_CRITICAL_SECTION_ENTER()
+#define DSU_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_dsu_addr_reg_t;
+typedef uint32_t hri_dsu_cfg_reg_t;
+typedef uint32_t hri_dsu_cid0_reg_t;
+typedef uint32_t hri_dsu_cid1_reg_t;
+typedef uint32_t hri_dsu_cid2_reg_t;
+typedef uint32_t hri_dsu_cid3_reg_t;
+typedef uint32_t hri_dsu_data_reg_t;
+typedef uint32_t hri_dsu_dcc_reg_t;
+typedef uint32_t hri_dsu_dcfg_reg_t;
+typedef uint32_t hri_dsu_did_reg_t;
+typedef uint32_t hri_dsu_end_reg_t;
+typedef uint32_t hri_dsu_entry0_reg_t;
+typedef uint32_t hri_dsu_entry1_reg_t;
+typedef uint32_t hri_dsu_length_reg_t;
+typedef uint32_t hri_dsu_memtype_reg_t;
+typedef uint32_t hri_dsu_pid0_reg_t;
+typedef uint32_t hri_dsu_pid1_reg_t;
+typedef uint32_t hri_dsu_pid2_reg_t;
+typedef uint32_t hri_dsu_pid3_reg_t;
+typedef uint32_t hri_dsu_pid4_reg_t;
+typedef uint32_t hri_dsu_pid5_reg_t;
+typedef uint32_t hri_dsu_pid6_reg_t;
+typedef uint32_t hri_dsu_pid7_reg_t;
+typedef uint8_t  hri_dsu_ctrl_reg_t;
+typedef uint8_t  hri_dsu_statusa_reg_t;
+typedef uint8_t  hri_dsu_statusb_reg_t;
+
+static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_CELCK_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_CELCK) >> DSU_STATUSB_CELCK_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_TDCCD0_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_TDCCD0) >> DSU_STATUSB_TDCCD0_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_TDCCD1_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_TDCCD1) >> DSU_STATUSB_TDCCD1_Pos;
+}
+
+static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dsu *)hw)->STATUSB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->STATUSB.reg;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->DID.reg;
+}
+
+static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos;
+}
+
+static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ENTRY0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->ENTRY0.reg;
+}
+
+static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ENTRY1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->ENTRY1.reg;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask)
+{
+	return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->END.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->END.reg;
+}
+
+static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos;
+}
+
+static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->MEMTYPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->MEMTYPE.reg;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID4.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID4.reg;
+}
+
+static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID5.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID5.reg;
+}
+
+static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID6.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID6.reg;
+}
+
+static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID7.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID7.reg;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask)
+{
+	return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID0.reg;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID1.reg;
+}
+
+static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID2.reg;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID3.reg;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask)
+{
+	return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID0.reg;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID1.reg;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask)
+{
+	return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID2.reg;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask)
+{
+	return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID3.reg;
+}
+
+static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp &= ~DSU_ADDR_AMOD_Msk;
+	tmp |= DSU_ADDR_AMOD(data);
+	((Dsu *)hw)->ADDR.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp &= ~DSU_ADDR_ADDR_Msk;
+	tmp |= DSU_ADDR_ADDR(data);
+	((Dsu *)hw)->ADDR.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->ADDR.reg;
+}
+
+static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp &= ~DSU_LENGTH_LENGTH_Msk;
+	tmp |= DSU_LENGTH_LENGTH(data);
+	((Dsu *)hw)->LENGTH.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->LENGTH.reg;
+}
+
+static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp &= ~DSU_DATA_DATA_Msk;
+	tmp |= DSU_DATA_DATA(data);
+	((Dsu *)hw)->DATA.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->DATA.reg;
+}
+
+static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp &= ~DSU_DCC_DATA_Msk;
+	tmp |= DSU_DCC_DATA(data);
+	((Dsu *)hw)->DCC[index].reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index)
+{
+	return ((Dsu *)hw)->DCC[index].reg;
+}
+
+static inline void hri_dsu_set_CFG_ETBRAMEN_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg |= DSU_CFG_ETBRAMEN;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_CFG_ETBRAMEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp = (tmp & DSU_CFG_ETBRAMEN) >> DSU_CFG_ETBRAMEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dsu_write_CFG_ETBRAMEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp &= ~DSU_CFG_ETBRAMEN;
+	tmp |= value << DSU_CFG_ETBRAMEN_Pos;
+	((Dsu *)hw)->CFG.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_CFG_ETBRAMEN_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg &= ~DSU_CFG_ETBRAMEN;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_CFG_ETBRAMEN_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg ^= DSU_CFG_ETBRAMEN;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_set_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg |= DSU_CFG_LQOS(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp = (tmp & DSU_CFG_LQOS(mask)) >> DSU_CFG_LQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp &= ~DSU_CFG_LQOS_Msk;
+	tmp |= DSU_CFG_LQOS(data);
+	((Dsu *)hw)->CFG.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg &= ~DSU_CFG_LQOS(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg ^= DSU_CFG_LQOS(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_LQOS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp = (tmp & DSU_CFG_LQOS_Msk) >> DSU_CFG_LQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg |= DSU_CFG_DCCDMALEVEL(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp = (tmp & DSU_CFG_DCCDMALEVEL(mask)) >> DSU_CFG_DCCDMALEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp &= ~DSU_CFG_DCCDMALEVEL_Msk;
+	tmp |= DSU_CFG_DCCDMALEVEL(data);
+	((Dsu *)hw)->CFG.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg &= ~DSU_CFG_DCCDMALEVEL(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg ^= DSU_CFG_DCCDMALEVEL(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_DCCDMALEVEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp = (tmp & DSU_CFG_DCCDMALEVEL_Msk) >> DSU_CFG_DCCDMALEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CFG.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CFG.reg;
+}
+
+static inline void hri_dsu_set_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg |= DSU_DCFG_DCFG(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCFG[index].reg;
+	tmp = (tmp & DSU_DCFG_DCFG(mask)) >> DSU_DCFG_DCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->DCFG[index].reg;
+	tmp &= ~DSU_DCFG_DCFG_Msk;
+	tmp |= DSU_DCFG_DCFG(data);
+	((Dsu *)hw)->DCFG[index].reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg &= ~DSU_DCFG_DCFG(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg ^= DSU_DCFG_DCFG(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_DCFG_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCFG[index].reg;
+	tmp = (tmp & DSU_DCFG_DCFG_Msk) >> DSU_DCFG_DCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCFG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_reg(const void *const hw, uint8_t index)
+{
+	return ((Dsu *)hw)->DCFG[index].reg;
+}
+
+static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dsu *)hw)->STATUSA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->STATUSA.reg;
+}
+
+static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CTRL.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_DSU_E54_H_INCLUDED */
+#endif /* _SAME54_DSU_COMPONENT_ */
diff --git a/hri/hri_e54.h b/hri/hri_e54.h
new file mode 100644
index 0000000..a562a2d
--- /dev/null
+++ b/hri/hri_e54.h
@@ -0,0 +1,80 @@
+/**
+ * \file
+ *
+ * \brief SAM E54 HRI top-level header file
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ */
+
+#ifndef _HRI_E54_H_INCLUDED_
+#define _HRI_E54_H_INCLUDED_
+
+#include <sam.h>
+#include <hri_ac_e54.h>
+#include <hri_adc_e54.h>
+#include <hri_aes_e54.h>
+#include <hri_can_e54.h>
+#include <hri_ccl_e54.h>
+#include <hri_cmcc_e54.h>
+#include <hri_dac_e54.h>
+#include <hri_dmac_e54.h>
+#include <hri_dsu_e54.h>
+#include <hri_eic_e54.h>
+#include <hri_evsys_e54.h>
+#include <hri_freqm_e54.h>
+#include <hri_gclk_e54.h>
+#include <hri_gmac_e54.h>
+#include <hri_hmatrixb_e54.h>
+#include <hri_i2s_e54.h>
+#include <hri_icm_e54.h>
+#include <hri_mclk_e54.h>
+#include <hri_mpu_e54.h>
+#include <hri_nvic_e54.h>
+#include <hri_nvmctrl_e54.h>
+#include <hri_osc32kctrl_e54.h>
+#include <hri_oscctrl_e54.h>
+#include <hri_pac_e54.h>
+#include <hri_pcc_e54.h>
+#include <hri_pdec_e54.h>
+#include <hri_pm_e54.h>
+#include <hri_port_e54.h>
+#include <hri_qspi_e54.h>
+#include <hri_ramecc_e54.h>
+#include <hri_rstc_e54.h>
+#include <hri_rtc_e54.h>
+#include <hri_sdhc_e54.h>
+#include <hri_sercom_e54.h>
+#include <hri_supc_e54.h>
+#include <hri_systemcontrol_e54.h>
+#include <hri_systick_e54.h>
+#include <hri_tc_e54.h>
+#include <hri_tcc_e54.h>
+#include <hri_trng_e54.h>
+#include <hri_usb_e54.h>
+#include <hri_wdt_e54.h>
+
+#endif /* _HRI_E54_H_INCLUDED_ */
diff --git a/hri/hri_eic_e54.h b/hri/hri_eic_e54.h
new file mode 100644
index 0000000..f86e452
--- /dev/null
+++ b/hri/hri_eic_e54.h
@@ -0,0 +1,1838 @@
+/**
+ * \file
+ *
+ * \brief SAM EIC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_EIC_COMPONENT_
+#ifndef _HRI_EIC_E54_H_INCLUDED_
+#define _HRI_EIC_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_EIC_CRITICAL_SECTIONS)
+#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define EIC_CRITICAL_SECTION_ENTER()
+#define EIC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_eic_nmiflag_reg_t;
+typedef uint32_t hri_eic_asynch_reg_t;
+typedef uint32_t hri_eic_config_reg_t;
+typedef uint32_t hri_eic_debouncen_reg_t;
+typedef uint32_t hri_eic_dprescaler_reg_t;
+typedef uint32_t hri_eic_evctrl_reg_t;
+typedef uint32_t hri_eic_intenset_reg_t;
+typedef uint32_t hri_eic_intflag_reg_t;
+typedef uint32_t hri_eic_pinstate_reg_t;
+typedef uint32_t hri_eic_syncbusy_reg_t;
+typedef uint8_t  hri_eic_ctrla_reg_t;
+typedef uint8_t  hri_eic_nmictrl_reg_t;
+
+static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg)
+{
+	while (((Eic *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg)
+{
+	return ((Eic *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw)
+{
+	return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos;
+}
+
+static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw)
+{
+	((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI;
+}
+
+static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Eic *)hw)->NMIFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw)
+{
+	return ((Eic *)hw)->NMIFLAG.reg;
+}
+
+static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask)
+{
+	((Eic *)hw)->NMIFLAG.reg = mask;
+}
+
+static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Eic *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask)
+{
+	((Eic *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask);
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTENSET.reg;
+	tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos;
+	return tmp;
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTENSET.reg;
+	tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data);
+	((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data);
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask);
+}
+
+static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw)
+{
+	return ((Eic *)hw)->INTENSET.reg;
+}
+
+static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data)
+{
+	((Eic *)hw)->INTENSET.reg = data;
+	((Eic *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Eic *)hw)->SYNCBUSY.reg;
+}
+
+static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_PINSTATE_bf(const void *const hw, hri_eic_pinstate_reg_t mask)
+{
+	return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE(mask)) >> EIC_PINSTATE_PINSTATE_Pos;
+}
+
+static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_PINSTATE_bf(const void *const hw)
+{
+	return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE_Msk) >> EIC_PINSTATE_PINSTATE_Pos;
+}
+
+static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_reg(const void *const hw, hri_eic_pinstate_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->PINSTATE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_reg(const void *const hw)
+{
+	return ((Eic *)hw)->PINSTATE.reg;
+}
+
+static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST);
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp &= ~EIC_CTRLA_ENABLE;
+	tmp |= value << EIC_CTRLA_ENABLE_Pos;
+	((Eic *)hw)->CTRLA.reg = tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp &= ~EIC_CTRLA_CKSEL;
+	tmp |= value << EIC_CTRLA_CKSEL_Pos;
+	((Eic *)hw)->CTRLA.reg = tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= mask;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg = data;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg &= ~mask;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg ^= mask;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw)
+{
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	return ((Eic *)hw)->CTRLA.reg;
+}
+
+static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= ~EIC_NMICTRL_NMIFILTEN;
+	tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos;
+	((Eic *)hw)->NMICTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= ~EIC_NMICTRL_NMIASYNCH;
+	tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos;
+	((Eic *)hw)->NMICTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= ~EIC_NMICTRL_NMISENSE_Msk;
+	tmp |= EIC_NMICTRL_NMISENSE(data);
+	((Eic *)hw)->NMICTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw)
+{
+	return ((Eic *)hw)->NMICTRL.reg;
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO_Msk;
+	tmp |= EIC_EVCTRL_EXTINTEO(data);
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Eic *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp &= ~EIC_ASYNCH_ASYNCH_Msk;
+	tmp |= EIC_ASYNCH_ASYNCH(data);
+	((Eic *)hw)->ASYNCH.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw)
+{
+	return ((Eic *)hw)->ASYNCH.reg;
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN0;
+	tmp |= value << EIC_CONFIG_FILTEN0_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN1;
+	tmp |= value << EIC_CONFIG_FILTEN1_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN2;
+	tmp |= value << EIC_CONFIG_FILTEN2_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN3;
+	tmp |= value << EIC_CONFIG_FILTEN3_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN4;
+	tmp |= value << EIC_CONFIG_FILTEN4_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN5;
+	tmp |= value << EIC_CONFIG_FILTEN5_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN6;
+	tmp |= value << EIC_CONFIG_FILTEN6_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN7;
+	tmp |= value << EIC_CONFIG_FILTEN7_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE0_Msk;
+	tmp |= EIC_CONFIG_SENSE0(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE1_Msk;
+	tmp |= EIC_CONFIG_SENSE1(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE2_Msk;
+	tmp |= EIC_CONFIG_SENSE2(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE3_Msk;
+	tmp |= EIC_CONFIG_SENSE3(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE4_Msk;
+	tmp |= EIC_CONFIG_SENSE4(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE5_Msk;
+	tmp |= EIC_CONFIG_SENSE5(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE6_Msk;
+	tmp |= EIC_CONFIG_SENSE6(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE7_Msk;
+	tmp |= EIC_CONFIG_SENSE7(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index,
+                                                          hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index)
+{
+	return ((Eic *)hw)->CONFIG[index].reg;
+}
+
+static inline void hri_eic_set_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg |= EIC_DEBOUNCEN_DEBOUNCEN(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_DEBOUNCEN_bf(const void *const       hw,
+                                                                         hri_eic_debouncen_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DEBOUNCEN.reg;
+	tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN(mask)) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->DEBOUNCEN.reg;
+	tmp &= ~EIC_DEBOUNCEN_DEBOUNCEN_Msk;
+	tmp |= EIC_DEBOUNCEN_DEBOUNCEN(data);
+	((Eic *)hw)->DEBOUNCEN.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg &= ~EIC_DEBOUNCEN_DEBOUNCEN(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg ^= EIC_DEBOUNCEN_DEBOUNCEN(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DEBOUNCEN.reg;
+	tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN_Msk) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DEBOUNCEN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DEBOUNCEN.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_reg(const void *const hw)
+{
+	return ((Eic *)hw)->DEBOUNCEN.reg;
+}
+
+static inline void hri_eic_set_DPRESCALER_STATES0_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_DPRESCALER_STATES0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_STATES0) >> EIC_DPRESCALER_STATES0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_DPRESCALER_STATES0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp &= ~EIC_DPRESCALER_STATES0;
+	tmp |= value << EIC_DPRESCALER_STATES0_Pos;
+	((Eic *)hw)->DPRESCALER.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DPRESCALER_STATES0_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DPRESCALER_STATES0_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_DPRESCALER_STATES1_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_DPRESCALER_STATES1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_STATES1) >> EIC_DPRESCALER_STATES1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_DPRESCALER_STATES1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp &= ~EIC_DPRESCALER_STATES1;
+	tmp |= value << EIC_DPRESCALER_STATES1_Pos;
+	((Eic *)hw)->DPRESCALER.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DPRESCALER_STATES1_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DPRESCALER_STATES1_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_DPRESCALER_TICKON_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_TICKON;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_DPRESCALER_TICKON_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_TICKON) >> EIC_DPRESCALER_TICKON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_DPRESCALER_TICKON_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp &= ~EIC_DPRESCALER_TICKON;
+	tmp |= value << EIC_DPRESCALER_TICKON_Pos;
+	((Eic *)hw)->DPRESCALER.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DPRESCALER_TICKON_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_TICKON;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DPRESCALER_TICKON_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_TICKON;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER0_bf(const void *const        hw,
+                                                                            hri_eic_dprescaler_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_PRESCALER0(mask)) >> EIC_DPRESCALER_PRESCALER0_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp &= ~EIC_DPRESCALER_PRESCALER0_Msk;
+	tmp |= EIC_DPRESCALER_PRESCALER0(data);
+	((Eic *)hw)->DPRESCALER.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_PRESCALER0_Msk) >> EIC_DPRESCALER_PRESCALER0_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER1_bf(const void *const        hw,
+                                                                            hri_eic_dprescaler_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_PRESCALER1(mask)) >> EIC_DPRESCALER_PRESCALER1_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp &= ~EIC_DPRESCALER_PRESCALER1_Msk;
+	tmp |= EIC_DPRESCALER_PRESCALER1(data);
+	((Eic *)hw)->DPRESCALER.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp = (tmp & EIC_DPRESCALER_PRESCALER1_Msk) >> EIC_DPRESCALER_PRESCALER1_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->DPRESCALER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->DPRESCALER.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_reg(const void *const hw)
+{
+	return ((Eic *)hw)->DPRESCALER.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_EIC_E54_H_INCLUDED */
+#endif /* _SAME54_EIC_COMPONENT_ */
diff --git a/hri/hri_evsys_e54.h b/hri/hri_evsys_e54.h
new file mode 100644
index 0000000..cd4a98a
--- /dev/null
+++ b/hri/hri_evsys_e54.h
@@ -0,0 +1,1707 @@
+/**
+ * \file
+ *
+ * \brief SAM EVSYS
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_EVSYS_COMPONENT_
+#ifndef _HRI_EVSYS_E54_H_INCLUDED_
+#define _HRI_EVSYS_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS)
+#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define EVSYS_CRITICAL_SECTION_ENTER()
+#define EVSYS_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_evsys_intpend_reg_t;
+typedef uint32_t hri_evsys_busych_reg_t;
+typedef uint32_t hri_evsys_channel_reg_t;
+typedef uint32_t hri_evsys_intstatus_reg_t;
+typedef uint32_t hri_evsys_readyusr_reg_t;
+typedef uint32_t hri_evsys_swevt_reg_t;
+typedef uint32_t hri_evsys_user_reg_t;
+typedef uint32_t hri_evsyschannel_channel_reg_t;
+typedef uint8_t  hri_evsys_chintenset_reg_t;
+typedef uint8_t  hri_evsys_chintflag_reg_t;
+typedef uint8_t  hri_evsys_chstatus_reg_t;
+typedef uint8_t  hri_evsys_ctrla_reg_t;
+typedef uint8_t  hri_evsys_prictrl_reg_t;
+typedef uint8_t  hri_evsyschannel_chintenset_reg_t;
+typedef uint8_t  hri_evsyschannel_chintflag_reg_t;
+typedef uint8_t  hri_evsyschannel_chstatus_reg_t;
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT0) >> EVSYS_INTSTATUS_CHINT0_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT1) >> EVSYS_INTSTATUS_CHINT1_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT2) >> EVSYS_INTSTATUS_CHINT2_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT3) >> EVSYS_INTSTATUS_CHINT3_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT4) >> EVSYS_INTSTATUS_CHINT4_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT5) >> EVSYS_INTSTATUS_CHINT5_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT6) >> EVSYS_INTSTATUS_CHINT6_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT7) >> EVSYS_INTSTATUS_CHINT7_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT8_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT8) >> EVSYS_INTSTATUS_CHINT8_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT9_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT9) >> EVSYS_INTSTATUS_CHINT9_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT10_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT10) >> EVSYS_INTSTATUS_CHINT10_Pos;
+}
+
+static inline bool hri_evsys_get_INTSTATUS_CHINT11_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT11) >> EVSYS_INTSTATUS_CHINT11_Pos;
+}
+
+static inline hri_evsys_intstatus_reg_t hri_evsys_get_INTSTATUS_reg(const void *const         hw,
+                                                                    hri_evsys_intstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->INTSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_intstatus_reg_t hri_evsys_read_INTSTATUS_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->INTSTATUS.reg;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH0) >> EVSYS_BUSYCH_BUSYCH0_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH1) >> EVSYS_BUSYCH_BUSYCH1_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH2) >> EVSYS_BUSYCH_BUSYCH2_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH3) >> EVSYS_BUSYCH_BUSYCH3_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH4) >> EVSYS_BUSYCH_BUSYCH4_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH5) >> EVSYS_BUSYCH_BUSYCH5_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH6) >> EVSYS_BUSYCH_BUSYCH6_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH7) >> EVSYS_BUSYCH_BUSYCH7_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH8_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH8) >> EVSYS_BUSYCH_BUSYCH8_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH9_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH9) >> EVSYS_BUSYCH_BUSYCH9_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH10_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH10) >> EVSYS_BUSYCH_BUSYCH10_Pos;
+}
+
+static inline bool hri_evsys_get_BUSYCH_BUSYCH11_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH11) >> EVSYS_BUSYCH_BUSYCH11_Pos;
+}
+
+static inline hri_evsys_busych_reg_t hri_evsys_get_BUSYCH_reg(const void *const hw, hri_evsys_busych_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->BUSYCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_busych_reg_t hri_evsys_read_BUSYCH_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->BUSYCH.reg;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR0) >> EVSYS_READYUSR_READYUSR0_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR1) >> EVSYS_READYUSR_READYUSR1_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR2) >> EVSYS_READYUSR_READYUSR2_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR3) >> EVSYS_READYUSR_READYUSR3_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR4) >> EVSYS_READYUSR_READYUSR4_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR5) >> EVSYS_READYUSR_READYUSR5_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR6) >> EVSYS_READYUSR_READYUSR6_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR7) >> EVSYS_READYUSR_READYUSR7_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR8_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR8) >> EVSYS_READYUSR_READYUSR8_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR9_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR9) >> EVSYS_READYUSR_READYUSR9_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR10_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR10) >> EVSYS_READYUSR_READYUSR10_Pos;
+}
+
+static inline bool hri_evsys_get_READYUSR_READYUSR11_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR11) >> EVSYS_READYUSR_READYUSR11_Pos;
+}
+
+static inline hri_evsys_readyusr_reg_t hri_evsys_get_READYUSR_reg(const void *const hw, hri_evsys_readyusr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->READYUSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_readyusr_reg_t hri_evsys_read_READYUSR_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->READYUSR.reg;
+}
+
+static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->CTRLA.reg;
+	tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->CTRLA.reg;
+}
+
+static inline void hri_evsys_set_PRICTRL_RREN_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_RREN;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_PRICTRL_RREN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->PRICTRL.reg;
+	tmp = (tmp & EVSYS_PRICTRL_RREN) >> EVSYS_PRICTRL_RREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_PRICTRL_RREN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->PRICTRL.reg;
+	tmp &= ~EVSYS_PRICTRL_RREN;
+	tmp |= value << EVSYS_PRICTRL_RREN_Pos;
+	((Evsys *)hw)->PRICTRL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_PRICTRL_RREN_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_RREN;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_PRICTRL_RREN_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_RREN;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_PRI(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->PRICTRL.reg;
+	tmp = (tmp & EVSYS_PRICTRL_PRI(mask)) >> EVSYS_PRICTRL_PRI_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t data)
+{
+	uint8_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->PRICTRL.reg;
+	tmp &= ~EVSYS_PRICTRL_PRI_Msk;
+	tmp |= EVSYS_PRICTRL_PRI(data);
+	((Evsys *)hw)->PRICTRL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_PRI(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_PRI(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_PRI_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->PRICTRL.reg;
+	tmp = (tmp & EVSYS_PRICTRL_PRI_Msk) >> EVSYS_PRICTRL_PRI_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->PRICTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->PRICTRL.reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->PRICTRL.reg;
+}
+
+static inline void hri_evsys_set_INTPEND_OVR_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_OVR;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_INTPEND_OVR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp = (tmp & EVSYS_INTPEND_OVR) >> EVSYS_INTPEND_OVR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_INTPEND_OVR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp &= ~EVSYS_INTPEND_OVR;
+	tmp |= value << EVSYS_INTPEND_OVR_Pos;
+	((Evsys *)hw)->INTPEND.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_INTPEND_OVR_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_OVR;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_INTPEND_OVR_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_OVR;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_INTPEND_EVD_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_EVD;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_INTPEND_EVD_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp = (tmp & EVSYS_INTPEND_EVD) >> EVSYS_INTPEND_EVD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_INTPEND_EVD_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp &= ~EVSYS_INTPEND_EVD;
+	tmp |= value << EVSYS_INTPEND_EVD_Pos;
+	((Evsys *)hw)->INTPEND.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_INTPEND_EVD_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_EVD;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_INTPEND_EVD_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_EVD;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_INTPEND_READY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_READY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_INTPEND_READY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp = (tmp & EVSYS_INTPEND_READY) >> EVSYS_INTPEND_READY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_INTPEND_READY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp &= ~EVSYS_INTPEND_READY;
+	tmp |= value << EVSYS_INTPEND_READY_Pos;
+	((Evsys *)hw)->INTPEND.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_INTPEND_READY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_READY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_INTPEND_READY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_READY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_INTPEND_BUSY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_BUSY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_INTPEND_BUSY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp = (tmp & EVSYS_INTPEND_BUSY) >> EVSYS_INTPEND_BUSY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_INTPEND_BUSY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp &= ~EVSYS_INTPEND_BUSY;
+	tmp |= value << EVSYS_INTPEND_BUSY_Pos;
+	((Evsys *)hw)->INTPEND.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_INTPEND_BUSY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_BUSY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_INTPEND_BUSY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_BUSY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_ID(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp = (tmp & EVSYS_INTPEND_ID(mask)) >> EVSYS_INTPEND_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t data)
+{
+	uint16_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp &= ~EVSYS_INTPEND_ID_Msk;
+	tmp |= EVSYS_INTPEND_ID(data);
+	((Evsys *)hw)->INTPEND.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_ID(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_ID(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_ID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp = (tmp & EVSYS_INTPEND_ID_Msk) >> EVSYS_INTPEND_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Evsys *)hw)->INTPEND.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->INTPEND.reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->INTPEND.reg;
+}
+
+static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index,
+                                                                 hri_evsys_user_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp &= ~EVSYS_USER_CHANNEL_Msk;
+	tmp |= EVSYS_USER_CHANNEL(data);
+	((Evsys *)hw)->USER[index].reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index,
+                                                          hri_evsys_user_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index)
+{
+	return ((Evsys *)hw)->USER[index].reg;
+}
+
+static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->SWEVT.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsyschannel_get_CHINTFLAG_OVR_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos;
+}
+
+static inline void hri_evsyschannel_clear_CHINTFLAG_OVR_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR;
+}
+
+static inline bool hri_evsyschannel_get_CHINTFLAG_EVD_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos;
+}
+
+static inline void hri_evsyschannel_clear_CHINTFLAG_EVD_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD;
+}
+
+static inline bool hri_evsyschannel_get_interrupt_OVR_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos;
+}
+
+static inline void hri_evsyschannel_clear_interrupt_OVR_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR;
+}
+
+static inline bool hri_evsyschannel_get_interrupt_EVD_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos;
+}
+
+static inline void hri_evsyschannel_clear_interrupt_EVD_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD;
+}
+
+static inline hri_evsys_chintflag_reg_t hri_evsyschannel_get_CHINTFLAG_reg(const void *const         hw,
+                                                                           hri_evsys_chintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chintflag_reg_t hri_evsyschannel_read_CHINTFLAG_reg(const void *const hw)
+{
+	return ((EvsysChannel *)hw)->CHINTFLAG.reg;
+}
+
+static inline void hri_evsyschannel_clear_CHINTFLAG_reg(const void *const hw, hri_evsys_chintflag_reg_t mask)
+{
+	((EvsysChannel *)hw)->CHINTFLAG.reg = mask;
+}
+
+static inline void hri_evsyschannel_set_CHINTEN_OVR_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR;
+}
+
+static inline bool hri_evsyschannel_get_CHINTEN_OVR_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos;
+}
+
+static inline void hri_evsyschannel_write_CHINTEN_OVR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR;
+	} else {
+		((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR;
+	}
+}
+
+static inline void hri_evsyschannel_clear_CHINTEN_OVR_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR;
+}
+
+static inline void hri_evsyschannel_set_CHINTEN_EVD_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD;
+}
+
+static inline bool hri_evsyschannel_get_CHINTEN_EVD_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos;
+}
+
+static inline void hri_evsyschannel_write_CHINTEN_EVD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD;
+	} else {
+		((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD;
+	}
+}
+
+static inline void hri_evsyschannel_clear_CHINTEN_EVD_bit(const void *const hw)
+{
+	((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD;
+}
+
+static inline void hri_evsyschannel_set_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask)
+{
+	((EvsysChannel *)hw)->CHINTENSET.reg = mask;
+}
+
+static inline hri_evsys_chintenset_reg_t hri_evsyschannel_get_CHINTEN_reg(const void *const          hw,
+                                                                          hri_evsys_chintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chintenset_reg_t hri_evsyschannel_read_CHINTEN_reg(const void *const hw)
+{
+	return ((EvsysChannel *)hw)->CHINTENSET.reg;
+}
+
+static inline void hri_evsyschannel_write_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t data)
+{
+	((EvsysChannel *)hw)->CHINTENSET.reg = data;
+	((EvsysChannel *)hw)->CHINTENCLR.reg = ~data;
+}
+
+static inline void hri_evsyschannel_clear_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask)
+{
+	((EvsysChannel *)hw)->CHINTENCLR.reg = mask;
+}
+
+static inline bool hri_evsyschannel_get_CHSTATUS_RDYUSR_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos;
+}
+
+static inline bool hri_evsyschannel_get_CHSTATUS_BUSYCH_bit(const void *const hw)
+{
+	return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos;
+}
+
+static inline hri_evsys_chstatus_reg_t hri_evsyschannel_get_CHSTATUS_reg(const void *const        hw,
+                                                                         hri_evsys_chstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chstatus_reg_t hri_evsyschannel_read_CHSTATUS_reg(const void *const hw)
+{
+	return ((EvsysChannel *)hw)->CHSTATUS.reg;
+}
+
+static inline void hri_evsyschannel_set_CHANNEL_RUNSTDBY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsyschannel_get_CHANNEL_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsyschannel_write_CHANNEL_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_RUNSTDBY;
+	tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos;
+	((EvsysChannel *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_clear_CHANNEL_RUNSTDBY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_set_CHANNEL_ONDEMAND_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsyschannel_get_CHANNEL_ONDEMAND_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsyschannel_write_CHANNEL_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_ONDEMAND;
+	tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos;
+	((EvsysChannel *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_clear_CHANNEL_ONDEMAND_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_toggle_CHANNEL_ONDEMAND_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_set_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EVGEN_bf(const void *const       hw,
+                                                                            hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_write_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_EVGEN_Msk;
+	tmp |= EVSYS_CHANNEL_EVGEN(data);
+	((EvsysChannel *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_clear_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_toggle_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EVGEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_set_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_PATH_bf(const void *const       hw,
+                                                                           hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_write_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_PATH_Msk;
+	tmp |= EVSYS_CHANNEL_PATH(data);
+	((EvsysChannel *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_clear_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_toggle_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_PATH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_set_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EDGSEL_bf(const void *const       hw,
+                                                                             hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_write_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk;
+	tmp |= EVSYS_CHANNEL_EDGSEL(data);
+	((EvsysChannel *)hw)->CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_clear_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_toggle_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EDGSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_set_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_reg(const void *const       hw,
+                                                                       hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((EvsysChannel *)hw)->CHANNEL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsyschannel_write_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_clear_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsyschannel_toggle_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((EvsysChannel *)hw)->CHANNEL.reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_reg(const void *const hw)
+{
+	return ((EvsysChannel *)hw)->CHANNEL.reg;
+}
+
+static inline bool hri_evsys_get_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos;
+}
+
+static inline void hri_evsys_clear_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR;
+}
+
+static inline bool hri_evsys_get_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos;
+}
+
+static inline void hri_evsys_clear_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD;
+}
+
+static inline hri_evsys_chintflag_reg_t hri_evsys_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                                    hri_evsys_chintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chintflag_reg_t hri_evsys_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg;
+}
+
+static inline void hri_evsys_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_evsys_chintflag_reg_t mask)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask;
+}
+
+static inline void hri_evsys_set_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR;
+}
+
+static inline bool hri_evsys_get_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos;
+}
+
+static inline void hri_evsys_write_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR;
+	} else {
+		((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR;
+	}
+}
+
+static inline void hri_evsys_clear_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR;
+}
+
+static inline void hri_evsys_set_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD;
+}
+
+static inline bool hri_evsys_get_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos;
+}
+
+static inline void hri_evsys_write_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD;
+	} else {
+		((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD;
+	}
+}
+
+static inline void hri_evsys_clear_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD;
+}
+
+static inline void hri_evsys_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_evsys_chintenset_reg_t mask)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = mask;
+}
+
+static inline hri_evsys_chintenset_reg_t hri_evsys_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                                   hri_evsys_chintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chintenset_reg_t hri_evsys_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg;
+}
+
+static inline void hri_evsys_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_evsys_chintenset_reg_t data)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = data;
+	((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data;
+}
+
+static inline void hri_evsys_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_evsys_chintenset_reg_t mask)
+{
+	((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_RDYUSR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_BUSYCH_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos;
+}
+
+static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                  hri_evsys_chstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg;
+}
+
+static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_RUNSTDBY;
+	tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos;
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_ONDEMAND;
+	tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos;
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_EVGEN_Msk;
+	tmp |= EVSYS_CHANNEL_EVGEN(data);
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_PATH_Msk;
+	tmp |= EVSYS_CHANNEL_PATH(data);
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk;
+	tmp |= EVSYS_CHANNEL_EDGSEL(data);
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_evsys_channel_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_EVSYS_E54_H_INCLUDED */
+#endif /* _SAME54_EVSYS_COMPONENT_ */
diff --git a/hri/hri_freqm_e54.h b/hri/hri_freqm_e54.h
new file mode 100644
index 0000000..8cbc484
--- /dev/null
+++ b/hri/hri_freqm_e54.h
@@ -0,0 +1,464 @@
+/**
+ * \file
+ *
+ * \brief SAM FREQM
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_FREQM_COMPONENT_
+#ifndef _HRI_FREQM_E54_H_INCLUDED_
+#define _HRI_FREQM_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_FREQM_CRITICAL_SECTIONS)
+#define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define FREQM_CRITICAL_SECTION_ENTER()
+#define FREQM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_freqm_cfga_reg_t;
+typedef uint32_t hri_freqm_syncbusy_reg_t;
+typedef uint32_t hri_freqm_value_reg_t;
+typedef uint8_t  hri_freqm_ctrla_reg_t;
+typedef uint8_t  hri_freqm_ctrlb_reg_t;
+typedef uint8_t  hri_freqm_intenset_reg_t;
+typedef uint8_t  hri_freqm_intflag_reg_t;
+typedef uint8_t  hri_freqm_status_reg_t;
+
+static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg)
+{
+	while (((Freqm *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg)
+{
+	return ((Freqm *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos;
+}
+
+static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE;
+}
+
+static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos;
+}
+
+static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE;
+}
+
+static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Freqm *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask)
+{
+	((Freqm *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE;
+}
+
+static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos;
+}
+
+static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE;
+	} else {
+		((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE;
+	}
+}
+
+static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE;
+}
+
+static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
+{
+	((Freqm *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Freqm *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->INTENSET.reg;
+}
+
+static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data)
+{
+	((Freqm *)hw)->INTENSET.reg = data;
+	((Freqm *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
+{
+	((Freqm *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Freqm *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->SYNCBUSY.reg;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask)
+{
+	return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw)
+{
+	return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Freqm *)hw)->VALUE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->VALUE.reg;
+}
+
+static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST);
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	FREQM_CRITICAL_SECTION_ENTER();
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp &= ~FREQM_CTRLA_ENABLE;
+	tmp |= value << FREQM_CTRLA_ENABLE_Pos;
+	((Freqm *)hw)->CTRLA.reg = tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg |= mask;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg = data;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg &= ~mask;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg ^= mask;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw)
+{
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	return ((Freqm *)hw)->CTRLA.reg;
+}
+
+static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data)
+{
+	uint16_t tmp;
+	FREQM_CRITICAL_SECTION_ENTER();
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp &= ~FREQM_CFGA_REFNUM_Msk;
+	tmp |= FREQM_CFGA_REFNUM(data);
+	((Freqm *)hw)->CFGA.reg = tmp;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg |= mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg = data;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg &= ~mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg ^= mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->CFGA.reg;
+}
+
+static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos;
+}
+
+static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos;
+}
+
+static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Freqm *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->STATUS.reg = mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->STATUS.reg;
+}
+
+static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLB.reg = data;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_FREQM_E54_H_INCLUDED */
+#endif /* _SAME54_FREQM_COMPONENT_ */
diff --git a/hri/hri_gclk_e54.h b/hri/hri_gclk_e54.h
new file mode 100644
index 0000000..f83af2a
--- /dev/null
+++ b/hri/hri_gclk_e54.h
@@ -0,0 +1,805 @@
+/**
+ * \file
+ *
+ * \brief SAM GCLK
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_GCLK_COMPONENT_
+#ifndef _HRI_GCLK_E54_H_INCLUDED_
+#define _HRI_GCLK_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_GCLK_CRITICAL_SECTIONS)
+#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define GCLK_CRITICAL_SECTION_ENTER()
+#define GCLK_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_gclk_genctrl_reg_t;
+typedef uint32_t hri_gclk_pchctrl_reg_t;
+typedef uint32_t hri_gclk_syncbusy_reg_t;
+typedef uint8_t  hri_gclk_ctrla_reg_t;
+
+static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg)
+{
+	while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg)
+{
+	return ((Gclk *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL5_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL6_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6) >> GCLK_SYNCBUSY_GENCTRL6_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL7_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL7) >> GCLK_SYNCBUSY_GENCTRL7_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL8_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL8) >> GCLK_SYNCBUSY_GENCTRL8_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL9_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL9) >> GCLK_SYNCBUSY_GENCTRL9_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL10_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL10) >> GCLK_SYNCBUSY_GENCTRL10_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL11_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL11) >> GCLK_SYNCBUSY_GENCTRL11_Pos;
+}
+
+static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Gclk *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	tmp = ((Gclk *)hw)->CTRLA.reg;
+	tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg |= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	tmp = ((Gclk *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg = data;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg &= ~mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg ^= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw)
+{
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	return ((Gclk *)hw)->CTRLA.reg;
+}
+
+static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_GENEN;
+	tmp |= value << GCLK_GENCTRL_GENEN_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_IDC;
+	tmp |= value << GCLK_GENCTRL_IDC_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_OOV;
+	tmp |= value << GCLK_GENCTRL_OOV_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_OE;
+	tmp |= value << GCLK_GENCTRL_OE_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_DIVSEL;
+	tmp |= value << GCLK_GENCTRL_DIVSEL_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_RUNSTDBY;
+	tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index,
+                                                                 hri_gclk_genctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_SRC_Msk;
+	tmp |= GCLK_GENCTRL_SRC(data);
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index,
+                                                                 hri_gclk_genctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_DIV_Msk;
+	tmp |= GCLK_GENCTRL_DIV(data);
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index,
+                                                              hri_gclk_genctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg = data;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index)
+{
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	return ((Gclk *)hw)->GENCTRL[index].reg;
+}
+
+static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= ~GCLK_PCHCTRL_CHEN;
+	tmp |= value << GCLK_PCHCTRL_CHEN_Pos;
+	((Gclk *)hw)->PCHCTRL[index].reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= ~GCLK_PCHCTRL_WRTLOCK;
+	tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos;
+	((Gclk *)hw)->PCHCTRL[index].reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index,
+                                                                 hri_gclk_pchctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= ~GCLK_PCHCTRL_GEN_Msk;
+	tmp |= GCLK_PCHCTRL_GEN(data);
+	((Gclk *)hw)->PCHCTRL[index].reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index,
+                                                              hri_gclk_pchctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg = data;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((Gclk *)hw)->PCHCTRL[index].reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_GCLK_E54_H_INCLUDED */
+#endif /* _SAME54_GCLK_COMPONENT_ */
diff --git a/hri/hri_gmac_e54.h b/hri/hri_gmac_e54.h
new file mode 100644
index 0000000..2875061
--- /dev/null
+++ b/hri/hri_gmac_e54.h
@@ -0,0 +1,3766 @@
+/**
+ * \file
+ *
+ * \brief SAM GMAC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_GMAC_COMPONENT_
+#ifndef _HRI_GMAC_E54_H_INCLUDED_
+#define _HRI_GMAC_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_GMAC_CRITICAL_SECTIONS)
+#define GMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define GMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define GMAC_CRITICAL_SECTION_ENTER()
+#define GMAC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_gmac_ae_reg_t;
+typedef uint32_t hri_gmac_bcfr_reg_t;
+typedef uint32_t hri_gmac_bcft_reg_t;
+typedef uint32_t hri_gmac_bfr64_reg_t;
+typedef uint32_t hri_gmac_bft64_reg_t;
+typedef uint32_t hri_gmac_cse_reg_t;
+typedef uint32_t hri_gmac_dcfgr_reg_t;
+typedef uint32_t hri_gmac_dtf_reg_t;
+typedef uint32_t hri_gmac_ec_reg_t;
+typedef uint32_t hri_gmac_efrn_reg_t;
+typedef uint32_t hri_gmac_efrsh_reg_t;
+typedef uint32_t hri_gmac_efrsl_reg_t;
+typedef uint32_t hri_gmac_eftn_reg_t;
+typedef uint32_t hri_gmac_eftsh_reg_t;
+typedef uint32_t hri_gmac_eftsl_reg_t;
+typedef uint32_t hri_gmac_fcse_reg_t;
+typedef uint32_t hri_gmac_fr_reg_t;
+typedef uint32_t hri_gmac_ft_reg_t;
+typedef uint32_t hri_gmac_gtbft1518_reg_t;
+typedef uint32_t hri_gmac_hrb_reg_t;
+typedef uint32_t hri_gmac_hrt_reg_t;
+typedef uint32_t hri_gmac_ihce_reg_t;
+typedef uint32_t hri_gmac_imr_reg_t;
+typedef uint32_t hri_gmac_ipgs_reg_t;
+typedef uint32_t hri_gmac_isr_reg_t;
+typedef uint32_t hri_gmac_jr_reg_t;
+typedef uint32_t hri_gmac_lc_reg_t;
+typedef uint32_t hri_gmac_lffe_reg_t;
+typedef uint32_t hri_gmac_man_reg_t;
+typedef uint32_t hri_gmac_mcf_reg_t;
+typedef uint32_t hri_gmac_mfr_reg_t;
+typedef uint32_t hri_gmac_mft_reg_t;
+typedef uint32_t hri_gmac_ncfgr_reg_t;
+typedef uint32_t hri_gmac_ncr_reg_t;
+typedef uint32_t hri_gmac_nsc_reg_t;
+typedef uint32_t hri_gmac_nsr_reg_t;
+typedef uint32_t hri_gmac_ofr_reg_t;
+typedef uint32_t hri_gmac_orhi_reg_t;
+typedef uint32_t hri_gmac_orlo_reg_t;
+typedef uint32_t hri_gmac_othi_reg_t;
+typedef uint32_t hri_gmac_otlo_reg_t;
+typedef uint32_t hri_gmac_pefrn_reg_t;
+typedef uint32_t hri_gmac_pefrsh_reg_t;
+typedef uint32_t hri_gmac_pefrsl_reg_t;
+typedef uint32_t hri_gmac_peftn_reg_t;
+typedef uint32_t hri_gmac_peftsh_reg_t;
+typedef uint32_t hri_gmac_peftsl_reg_t;
+typedef uint32_t hri_gmac_pfr_reg_t;
+typedef uint32_t hri_gmac_pft_reg_t;
+typedef uint32_t hri_gmac_rbqb_reg_t;
+typedef uint32_t hri_gmac_rjfml_reg_t;
+typedef uint32_t hri_gmac_rlpiti_reg_t;
+typedef uint32_t hri_gmac_rlpitr_reg_t;
+typedef uint32_t hri_gmac_roe_reg_t;
+typedef uint32_t hri_gmac_rpq_reg_t;
+typedef uint32_t hri_gmac_rpsf_reg_t;
+typedef uint32_t hri_gmac_rre_reg_t;
+typedef uint32_t hri_gmac_rse_reg_t;
+typedef uint32_t hri_gmac_rsr_reg_t;
+typedef uint32_t hri_gmac_sab_reg_t;
+typedef uint32_t hri_gmac_samb1_reg_t;
+typedef uint32_t hri_gmac_samt1_reg_t;
+typedef uint32_t hri_gmac_sat_reg_t;
+typedef uint32_t hri_gmac_scf_reg_t;
+typedef uint32_t hri_gmac_sch_reg_t;
+typedef uint32_t hri_gmac_scl_reg_t;
+typedef uint32_t hri_gmac_svlan_reg_t;
+typedef uint32_t hri_gmac_ta_reg_t;
+typedef uint32_t hri_gmac_tbfr1023_reg_t;
+typedef uint32_t hri_gmac_tbfr127_reg_t;
+typedef uint32_t hri_gmac_tbfr1518_reg_t;
+typedef uint32_t hri_gmac_tbfr255_reg_t;
+typedef uint32_t hri_gmac_tbfr511_reg_t;
+typedef uint32_t hri_gmac_tbft1023_reg_t;
+typedef uint32_t hri_gmac_tbft127_reg_t;
+typedef uint32_t hri_gmac_tbft1518_reg_t;
+typedef uint32_t hri_gmac_tbft255_reg_t;
+typedef uint32_t hri_gmac_tbft511_reg_t;
+typedef uint32_t hri_gmac_tbqb_reg_t;
+typedef uint32_t hri_gmac_tce_reg_t;
+typedef uint32_t hri_gmac_ti_reg_t;
+typedef uint32_t hri_gmac_tidm_reg_t;
+typedef uint32_t hri_gmac_tisubn_reg_t;
+typedef uint32_t hri_gmac_tlpiti_reg_t;
+typedef uint32_t hri_gmac_tlpitr_reg_t;
+typedef uint32_t hri_gmac_tmxbfr_reg_t;
+typedef uint32_t hri_gmac_tn_reg_t;
+typedef uint32_t hri_gmac_tpfcp_reg_t;
+typedef uint32_t hri_gmac_tpq_reg_t;
+typedef uint32_t hri_gmac_tpsf_reg_t;
+typedef uint32_t hri_gmac_tsh_reg_t;
+typedef uint32_t hri_gmac_tsl_reg_t;
+typedef uint32_t hri_gmac_tsr_reg_t;
+typedef uint32_t hri_gmac_tssn_reg_t;
+typedef uint32_t hri_gmac_tsssl_reg_t;
+typedef uint32_t hri_gmac_tur_reg_t;
+typedef uint32_t hri_gmac_uce_reg_t;
+typedef uint32_t hri_gmac_ufr_reg_t;
+typedef uint32_t hri_gmac_ur_reg_t;
+typedef uint32_t hri_gmac_wol_reg_t;
+typedef uint32_t hri_gmacsa_sab_reg_t;
+typedef uint32_t hri_gmacsa_sat_reg_t;
+
+static inline void hri_gmacsa_set_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((GmacSa *)hw)->SAB.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sab_reg_t hri_gmacsa_get_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((GmacSa *)hw)->SAB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmacsa_write_SAB_reg(const void *const hw, hri_gmac_sab_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((GmacSa *)hw)->SAB.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmacsa_clear_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((GmacSa *)hw)->SAB.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmacsa_toggle_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((GmacSa *)hw)->SAB.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sab_reg_t hri_gmacsa_read_SAB_reg(const void *const hw)
+{
+	return ((GmacSa *)hw)->SAB.reg;
+}
+
+static inline void hri_gmacsa_set_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((GmacSa *)hw)->SAT.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sat_reg_t hri_gmacsa_get_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((GmacSa *)hw)->SAT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmacsa_write_SAT_reg(const void *const hw, hri_gmac_sat_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((GmacSa *)hw)->SAT.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmacsa_clear_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((GmacSa *)hw)->SAT.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmacsa_toggle_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((GmacSa *)hw)->SAT.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sat_reg_t hri_gmacsa_read_SAT_reg(const void *const hw)
+{
+	return ((GmacSa *)hw)->SAT.reg;
+}
+
+static inline void hri_gmac_set_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->Sa[submodule_index].SAB.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sab_reg_t hri_gmac_get_SAB_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_gmac_sab_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->Sa[submodule_index].SAB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->Sa[submodule_index].SAB.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->Sa[submodule_index].SAB.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->Sa[submodule_index].SAB.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sab_reg_t hri_gmac_read_SAB_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Gmac *)hw)->Sa[submodule_index].SAB.reg;
+}
+
+static inline void hri_gmac_set_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->Sa[submodule_index].SAT.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sat_reg_t hri_gmac_get_SAT_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_gmac_sat_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->Sa[submodule_index].SAT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->Sa[submodule_index].SAT.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->Sa[submodule_index].SAT.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->Sa[submodule_index].SAT.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sat_reg_t hri_gmac_read_SAT_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Gmac *)hw)->Sa[submodule_index].SAT.reg;
+}
+
+static inline void hri_gmac_set_IMR_MFS_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_MFS;
+}
+
+static inline bool hri_gmac_get_IMR_MFS_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_MFS) >> GMAC_IMR_MFS_Pos;
+}
+
+static inline void hri_gmac_write_IMR_MFS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_MFS;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_MFS;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_MFS_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_MFS;
+}
+
+static inline void hri_gmac_set_IMR_RCOMP_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_RCOMP;
+}
+
+static inline bool hri_gmac_get_IMR_RCOMP_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RCOMP) >> GMAC_IMR_RCOMP_Pos;
+}
+
+static inline void hri_gmac_write_IMR_RCOMP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_RCOMP;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_RCOMP;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_RCOMP_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_RCOMP;
+}
+
+static inline void hri_gmac_set_IMR_RXUBR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_RXUBR;
+}
+
+static inline bool hri_gmac_get_IMR_RXUBR_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RXUBR) >> GMAC_IMR_RXUBR_Pos;
+}
+
+static inline void hri_gmac_write_IMR_RXUBR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_RXUBR;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_RXUBR;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_RXUBR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_RXUBR;
+}
+
+static inline void hri_gmac_set_IMR_TXUBR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_TXUBR;
+}
+
+static inline bool hri_gmac_get_IMR_TXUBR_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TXUBR) >> GMAC_IMR_TXUBR_Pos;
+}
+
+static inline void hri_gmac_write_IMR_TXUBR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_TXUBR;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_TXUBR;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_TXUBR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_TXUBR;
+}
+
+static inline void hri_gmac_set_IMR_TUR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_TUR;
+}
+
+static inline bool hri_gmac_get_IMR_TUR_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TUR) >> GMAC_IMR_TUR_Pos;
+}
+
+static inline void hri_gmac_write_IMR_TUR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_TUR;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_TUR;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_TUR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_TUR;
+}
+
+static inline void hri_gmac_set_IMR_RLEX_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_RLEX;
+}
+
+static inline bool hri_gmac_get_IMR_RLEX_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RLEX) >> GMAC_IMR_RLEX_Pos;
+}
+
+static inline void hri_gmac_write_IMR_RLEX_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_RLEX;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_RLEX;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_RLEX_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_RLEX;
+}
+
+static inline void hri_gmac_set_IMR_TFC_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_TFC;
+}
+
+static inline bool hri_gmac_get_IMR_TFC_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TFC) >> GMAC_IMR_TFC_Pos;
+}
+
+static inline void hri_gmac_write_IMR_TFC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_TFC;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_TFC;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_TFC_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_TFC;
+}
+
+static inline void hri_gmac_set_IMR_TCOMP_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_TCOMP;
+}
+
+static inline bool hri_gmac_get_IMR_TCOMP_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TCOMP) >> GMAC_IMR_TCOMP_Pos;
+}
+
+static inline void hri_gmac_write_IMR_TCOMP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_TCOMP;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_TCOMP;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_TCOMP_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_TCOMP;
+}
+
+static inline void hri_gmac_set_IMR_ROVR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_ROVR;
+}
+
+static inline bool hri_gmac_get_IMR_ROVR_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_ROVR) >> GMAC_IMR_ROVR_Pos;
+}
+
+static inline void hri_gmac_write_IMR_ROVR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_ROVR;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_ROVR;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_ROVR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_ROVR;
+}
+
+static inline void hri_gmac_set_IMR_HRESP_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_HRESP;
+}
+
+static inline bool hri_gmac_get_IMR_HRESP_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_HRESP) >> GMAC_IMR_HRESP_Pos;
+}
+
+static inline void hri_gmac_write_IMR_HRESP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_HRESP;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_HRESP;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_HRESP_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_HRESP;
+}
+
+static inline void hri_gmac_set_IMR_PFNZ_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_PFNZ;
+}
+
+static inline bool hri_gmac_get_IMR_PFNZ_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PFNZ) >> GMAC_IMR_PFNZ_Pos;
+}
+
+static inline void hri_gmac_write_IMR_PFNZ_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_PFNZ;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_PFNZ;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_PFNZ_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_PFNZ;
+}
+
+static inline void hri_gmac_set_IMR_PTZ_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_PTZ;
+}
+
+static inline bool hri_gmac_get_IMR_PTZ_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PTZ) >> GMAC_IMR_PTZ_Pos;
+}
+
+static inline void hri_gmac_write_IMR_PTZ_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_PTZ;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_PTZ;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_PTZ_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_PTZ;
+}
+
+static inline void hri_gmac_set_IMR_PFTR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_PFTR;
+}
+
+static inline bool hri_gmac_get_IMR_PFTR_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PFTR) >> GMAC_IMR_PFTR_Pos;
+}
+
+static inline void hri_gmac_write_IMR_PFTR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_PFTR;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_PFTR;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_PFTR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_PFTR;
+}
+
+static inline void hri_gmac_set_IMR_EXINT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_EXINT;
+}
+
+static inline bool hri_gmac_get_IMR_EXINT_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_EXINT) >> GMAC_IMR_EXINT_Pos;
+}
+
+static inline void hri_gmac_write_IMR_EXINT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_EXINT;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_EXINT;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_EXINT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_EXINT;
+}
+
+static inline void hri_gmac_set_IMR_DRQFR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFR;
+}
+
+static inline bool hri_gmac_get_IMR_DRQFR_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_DRQFR) >> GMAC_IMR_DRQFR_Pos;
+}
+
+static inline void hri_gmac_write_IMR_DRQFR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFR;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFR;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_DRQFR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFR;
+}
+
+static inline void hri_gmac_set_IMR_SFR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_SFR;
+}
+
+static inline bool hri_gmac_get_IMR_SFR_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SFR) >> GMAC_IMR_SFR_Pos;
+}
+
+static inline void hri_gmac_write_IMR_SFR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_SFR;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_SFR;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_SFR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_SFR;
+}
+
+static inline void hri_gmac_set_IMR_DRQFT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFT;
+}
+
+static inline bool hri_gmac_get_IMR_DRQFT_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_DRQFT) >> GMAC_IMR_DRQFT_Pos;
+}
+
+static inline void hri_gmac_write_IMR_DRQFT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFT;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFT;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_DRQFT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFT;
+}
+
+static inline void hri_gmac_set_IMR_SFT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_SFT;
+}
+
+static inline bool hri_gmac_get_IMR_SFT_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SFT) >> GMAC_IMR_SFT_Pos;
+}
+
+static inline void hri_gmac_write_IMR_SFT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_SFT;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_SFT;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_SFT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_SFT;
+}
+
+static inline void hri_gmac_set_IMR_PDRQFR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFR;
+}
+
+static inline bool hri_gmac_get_IMR_PDRQFR_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRQFR) >> GMAC_IMR_PDRQFR_Pos;
+}
+
+static inline void hri_gmac_write_IMR_PDRQFR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFR;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFR;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_PDRQFR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFR;
+}
+
+static inline void hri_gmac_set_IMR_PDRSFR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFR;
+}
+
+static inline bool hri_gmac_get_IMR_PDRSFR_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRSFR) >> GMAC_IMR_PDRSFR_Pos;
+}
+
+static inline void hri_gmac_write_IMR_PDRSFR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFR;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFR;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_PDRSFR_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFR;
+}
+
+static inline void hri_gmac_set_IMR_PDRQFT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFT;
+}
+
+static inline bool hri_gmac_get_IMR_PDRQFT_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRQFT) >> GMAC_IMR_PDRQFT_Pos;
+}
+
+static inline void hri_gmac_write_IMR_PDRQFT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFT;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFT;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_PDRQFT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFT;
+}
+
+static inline void hri_gmac_set_IMR_PDRSFT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFT;
+}
+
+static inline bool hri_gmac_get_IMR_PDRSFT_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRSFT) >> GMAC_IMR_PDRSFT_Pos;
+}
+
+static inline void hri_gmac_write_IMR_PDRSFT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFT;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFT;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_PDRSFT_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFT;
+}
+
+static inline void hri_gmac_set_IMR_SRI_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_SRI;
+}
+
+static inline bool hri_gmac_get_IMR_SRI_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SRI) >> GMAC_IMR_SRI_Pos;
+}
+
+static inline void hri_gmac_write_IMR_SRI_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_SRI;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_SRI;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_SRI_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_SRI;
+}
+
+static inline void hri_gmac_set_IMR_WOL_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_WOL;
+}
+
+static inline bool hri_gmac_get_IMR_WOL_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_WOL) >> GMAC_IMR_WOL_Pos;
+}
+
+static inline void hri_gmac_write_IMR_WOL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_WOL;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_WOL;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_WOL_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_WOL;
+}
+
+static inline void hri_gmac_set_IMR_TSUCMP_bit(const void *const hw)
+{
+	((Gmac *)hw)->IER.reg = GMAC_IMR_TSUCMP;
+}
+
+static inline bool hri_gmac_get_IMR_TSUCMP_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TSUCMP) >> GMAC_IMR_TSUCMP_Pos;
+}
+
+static inline void hri_gmac_write_IMR_TSUCMP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Gmac *)hw)->IDR.reg = GMAC_IMR_TSUCMP;
+	} else {
+		((Gmac *)hw)->IER.reg = GMAC_IMR_TSUCMP;
+	}
+}
+
+static inline void hri_gmac_clear_IMR_TSUCMP_bit(const void *const hw)
+{
+	((Gmac *)hw)->IDR.reg = GMAC_IMR_TSUCMP;
+}
+
+static inline void hri_gmac_set_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask)
+{
+	((Gmac *)hw)->IER.reg = mask;
+}
+
+static inline hri_gmac_imr_reg_t hri_gmac_get_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->IMR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_imr_reg_t hri_gmac_read_IMR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->IMR.reg;
+}
+
+static inline void hri_gmac_write_IMR_reg(const void *const hw, hri_gmac_imr_reg_t data)
+{
+	((Gmac *)hw)->IER.reg = data;
+	((Gmac *)hw)->IDR.reg = ~data;
+}
+
+static inline void hri_gmac_clear_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask)
+{
+	((Gmac *)hw)->IDR.reg = mask;
+}
+
+static inline bool hri_gmac_get_NSR_MDIO_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->NSR.reg & GMAC_NSR_MDIO) >> GMAC_NSR_MDIO_Pos;
+}
+
+static inline bool hri_gmac_get_NSR_IDLE_bit(const void *const hw)
+{
+	return (((Gmac *)hw)->NSR.reg & GMAC_NSR_IDLE) >> GMAC_NSR_IDLE_Pos;
+}
+
+static inline hri_gmac_nsr_reg_t hri_gmac_get_NSR_reg(const void *const hw, hri_gmac_nsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->NSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_nsr_reg_t hri_gmac_read_NSR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->NSR.reg;
+}
+
+static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_RPQ_bf(const void *const hw, hri_gmac_rpq_reg_t mask)
+{
+	return (((Gmac *)hw)->RPQ.reg & GMAC_RPQ_RPQ(mask)) >> GMAC_RPQ_RPQ_Pos;
+}
+
+static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_RPQ_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->RPQ.reg & GMAC_RPQ_RPQ_Msk) >> GMAC_RPQ_RPQ_Pos;
+}
+
+static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_reg(const void *const hw, hri_gmac_rpq_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->RPQ.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->RPQ.reg;
+}
+
+static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_RUD_bf(const void *const hw, hri_gmac_eftsh_reg_t mask)
+{
+	return (((Gmac *)hw)->EFTSH.reg & GMAC_EFTSH_RUD(mask)) >> GMAC_EFTSH_RUD_Pos;
+}
+
+static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->EFTSH.reg & GMAC_EFTSH_RUD_Msk) >> GMAC_EFTSH_RUD_Pos;
+}
+
+static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_reg(const void *const hw, hri_gmac_eftsh_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->EFTSH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->EFTSH.reg;
+}
+
+static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_RUD_bf(const void *const hw, hri_gmac_efrsh_reg_t mask)
+{
+	return (((Gmac *)hw)->EFRSH.reg & GMAC_EFRSH_RUD(mask)) >> GMAC_EFRSH_RUD_Pos;
+}
+
+static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->EFRSH.reg & GMAC_EFRSH_RUD_Msk) >> GMAC_EFRSH_RUD_Pos;
+}
+
+static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_reg(const void *const hw, hri_gmac_efrsh_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->EFRSH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->EFRSH.reg;
+}
+
+static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_RUD_bf(const void *const hw, hri_gmac_peftsh_reg_t mask)
+{
+	return (((Gmac *)hw)->PEFTSH.reg & GMAC_PEFTSH_RUD(mask)) >> GMAC_PEFTSH_RUD_Pos;
+}
+
+static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->PEFTSH.reg & GMAC_PEFTSH_RUD_Msk) >> GMAC_PEFTSH_RUD_Pos;
+}
+
+static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_reg(const void *const hw, hri_gmac_peftsh_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->PEFTSH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->PEFTSH.reg;
+}
+
+static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_RUD_bf(const void *const hw, hri_gmac_pefrsh_reg_t mask)
+{
+	return (((Gmac *)hw)->PEFRSH.reg & GMAC_PEFRSH_RUD(mask)) >> GMAC_PEFRSH_RUD_Pos;
+}
+
+static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->PEFRSH.reg & GMAC_PEFRSH_RUD_Msk) >> GMAC_PEFRSH_RUD_Pos;
+}
+
+static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_reg(const void *const hw, hri_gmac_pefrsh_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->PEFRSH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->PEFRSH.reg;
+}
+
+static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_TXO_bf(const void *const hw, hri_gmac_otlo_reg_t mask)
+{
+	return (((Gmac *)hw)->OTLO.reg & GMAC_OTLO_TXO(mask)) >> GMAC_OTLO_TXO_Pos;
+}
+
+static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_TXO_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->OTLO.reg & GMAC_OTLO_TXO_Msk) >> GMAC_OTLO_TXO_Pos;
+}
+
+static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_reg(const void *const hw, hri_gmac_otlo_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->OTLO.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->OTLO.reg;
+}
+
+static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_TXO_bf(const void *const hw, hri_gmac_othi_reg_t mask)
+{
+	return (((Gmac *)hw)->OTHI.reg & GMAC_OTHI_TXO(mask)) >> GMAC_OTHI_TXO_Pos;
+}
+
+static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_TXO_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->OTHI.reg & GMAC_OTHI_TXO_Msk) >> GMAC_OTHI_TXO_Pos;
+}
+
+static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_reg(const void *const hw, hri_gmac_othi_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->OTHI.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->OTHI.reg;
+}
+
+static inline hri_gmac_ft_reg_t hri_gmac_get_FT_FTX_bf(const void *const hw, hri_gmac_ft_reg_t mask)
+{
+	return (((Gmac *)hw)->FT.reg & GMAC_FT_FTX(mask)) >> GMAC_FT_FTX_Pos;
+}
+
+static inline hri_gmac_ft_reg_t hri_gmac_read_FT_FTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->FT.reg & GMAC_FT_FTX_Msk) >> GMAC_FT_FTX_Pos;
+}
+
+static inline hri_gmac_ft_reg_t hri_gmac_get_FT_reg(const void *const hw, hri_gmac_ft_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->FT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_ft_reg_t hri_gmac_read_FT_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->FT.reg;
+}
+
+static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_BFTX_bf(const void *const hw, hri_gmac_bcft_reg_t mask)
+{
+	return (((Gmac *)hw)->BCFT.reg & GMAC_BCFT_BFTX(mask)) >> GMAC_BCFT_BFTX_Pos;
+}
+
+static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_BFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->BCFT.reg & GMAC_BCFT_BFTX_Msk) >> GMAC_BCFT_BFTX_Pos;
+}
+
+static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_reg(const void *const hw, hri_gmac_bcft_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->BCFT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->BCFT.reg;
+}
+
+static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_MFTX_bf(const void *const hw, hri_gmac_mft_reg_t mask)
+{
+	return (((Gmac *)hw)->MFT.reg & GMAC_MFT_MFTX(mask)) >> GMAC_MFT_MFTX_Pos;
+}
+
+static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_MFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->MFT.reg & GMAC_MFT_MFTX_Msk) >> GMAC_MFT_MFTX_Pos;
+}
+
+static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_reg(const void *const hw, hri_gmac_mft_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->MFT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->MFT.reg;
+}
+
+static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_PFTX_bf(const void *const hw, hri_gmac_pft_reg_t mask)
+{
+	return (((Gmac *)hw)->PFT.reg & GMAC_PFT_PFTX(mask)) >> GMAC_PFT_PFTX_Pos;
+}
+
+static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_PFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->PFT.reg & GMAC_PFT_PFTX_Msk) >> GMAC_PFT_PFTX_Pos;
+}
+
+static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_reg(const void *const hw, hri_gmac_pft_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->PFT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->PFT.reg;
+}
+
+static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_NFTX_bf(const void *const hw, hri_gmac_bft64_reg_t mask)
+{
+	return (((Gmac *)hw)->BFT64.reg & GMAC_BFT64_NFTX(mask)) >> GMAC_BFT64_NFTX_Pos;
+}
+
+static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_NFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->BFT64.reg & GMAC_BFT64_NFTX_Msk) >> GMAC_BFT64_NFTX_Pos;
+}
+
+static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_reg(const void *const hw, hri_gmac_bft64_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->BFT64.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->BFT64.reg;
+}
+
+static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_NFTX_bf(const void *const hw, hri_gmac_tbft127_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFT127.reg & GMAC_TBFT127_NFTX(mask)) >> GMAC_TBFT127_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_NFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFT127.reg & GMAC_TBFT127_NFTX_Msk) >> GMAC_TBFT127_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_reg(const void *const hw, hri_gmac_tbft127_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFT127.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFT127.reg;
+}
+
+static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_NFTX_bf(const void *const hw, hri_gmac_tbft255_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFT255.reg & GMAC_TBFT255_NFTX(mask)) >> GMAC_TBFT255_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_NFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFT255.reg & GMAC_TBFT255_NFTX_Msk) >> GMAC_TBFT255_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_reg(const void *const hw, hri_gmac_tbft255_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFT255.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFT255.reg;
+}
+
+static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_NFTX_bf(const void *const hw, hri_gmac_tbft511_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFT511.reg & GMAC_TBFT511_NFTX(mask)) >> GMAC_TBFT511_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_NFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFT511.reg & GMAC_TBFT511_NFTX_Msk) >> GMAC_TBFT511_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_reg(const void *const hw, hri_gmac_tbft511_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFT511.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFT511.reg;
+}
+
+static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_NFTX_bf(const void *const hw, hri_gmac_tbft1023_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFT1023.reg & GMAC_TBFT1023_NFTX(mask)) >> GMAC_TBFT1023_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_NFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFT1023.reg & GMAC_TBFT1023_NFTX_Msk) >> GMAC_TBFT1023_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_reg(const void *const hw, hri_gmac_tbft1023_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFT1023.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFT1023.reg;
+}
+
+static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_NFTX_bf(const void *const hw, hri_gmac_tbft1518_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFT1518.reg & GMAC_TBFT1518_NFTX(mask)) >> GMAC_TBFT1518_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_NFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFT1518.reg & GMAC_TBFT1518_NFTX_Msk) >> GMAC_TBFT1518_NFTX_Pos;
+}
+
+static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_reg(const void *const hw, hri_gmac_tbft1518_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFT1518.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFT1518.reg;
+}
+
+static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_NFTX_bf(const void *const        hw,
+                                                                      hri_gmac_gtbft1518_reg_t mask)
+{
+	return (((Gmac *)hw)->GTBFT1518.reg & GMAC_GTBFT1518_NFTX(mask)) >> GMAC_GTBFT1518_NFTX_Pos;
+}
+
+static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_NFTX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->GTBFT1518.reg & GMAC_GTBFT1518_NFTX_Msk) >> GMAC_GTBFT1518_NFTX_Pos;
+}
+
+static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_reg(const void *const hw, hri_gmac_gtbft1518_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->GTBFT1518.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->GTBFT1518.reg;
+}
+
+static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_TXUNR_bf(const void *const hw, hri_gmac_tur_reg_t mask)
+{
+	return (((Gmac *)hw)->TUR.reg & GMAC_TUR_TXUNR(mask)) >> GMAC_TUR_TXUNR_Pos;
+}
+
+static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_TXUNR_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TUR.reg & GMAC_TUR_TXUNR_Msk) >> GMAC_TUR_TXUNR_Pos;
+}
+
+static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_reg(const void *const hw, hri_gmac_tur_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TUR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TUR.reg;
+}
+
+static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_SCOL_bf(const void *const hw, hri_gmac_scf_reg_t mask)
+{
+	return (((Gmac *)hw)->SCF.reg & GMAC_SCF_SCOL(mask)) >> GMAC_SCF_SCOL_Pos;
+}
+
+static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_SCOL_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->SCF.reg & GMAC_SCF_SCOL_Msk) >> GMAC_SCF_SCOL_Pos;
+}
+
+static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_reg(const void *const hw, hri_gmac_scf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->SCF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->SCF.reg;
+}
+
+static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_MCOL_bf(const void *const hw, hri_gmac_mcf_reg_t mask)
+{
+	return (((Gmac *)hw)->MCF.reg & GMAC_MCF_MCOL(mask)) >> GMAC_MCF_MCOL_Pos;
+}
+
+static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_MCOL_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->MCF.reg & GMAC_MCF_MCOL_Msk) >> GMAC_MCF_MCOL_Pos;
+}
+
+static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_reg(const void *const hw, hri_gmac_mcf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->MCF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->MCF.reg;
+}
+
+static inline hri_gmac_ec_reg_t hri_gmac_get_EC_XCOL_bf(const void *const hw, hri_gmac_ec_reg_t mask)
+{
+	return (((Gmac *)hw)->EC.reg & GMAC_EC_XCOL(mask)) >> GMAC_EC_XCOL_Pos;
+}
+
+static inline hri_gmac_ec_reg_t hri_gmac_read_EC_XCOL_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->EC.reg & GMAC_EC_XCOL_Msk) >> GMAC_EC_XCOL_Pos;
+}
+
+static inline hri_gmac_ec_reg_t hri_gmac_get_EC_reg(const void *const hw, hri_gmac_ec_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->EC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_ec_reg_t hri_gmac_read_EC_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->EC.reg;
+}
+
+static inline hri_gmac_lc_reg_t hri_gmac_get_LC_LCOL_bf(const void *const hw, hri_gmac_lc_reg_t mask)
+{
+	return (((Gmac *)hw)->LC.reg & GMAC_LC_LCOL(mask)) >> GMAC_LC_LCOL_Pos;
+}
+
+static inline hri_gmac_lc_reg_t hri_gmac_read_LC_LCOL_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->LC.reg & GMAC_LC_LCOL_Msk) >> GMAC_LC_LCOL_Pos;
+}
+
+static inline hri_gmac_lc_reg_t hri_gmac_get_LC_reg(const void *const hw, hri_gmac_lc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->LC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_lc_reg_t hri_gmac_read_LC_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->LC.reg;
+}
+
+static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_DEFT_bf(const void *const hw, hri_gmac_dtf_reg_t mask)
+{
+	return (((Gmac *)hw)->DTF.reg & GMAC_DTF_DEFT(mask)) >> GMAC_DTF_DEFT_Pos;
+}
+
+static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_DEFT_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->DTF.reg & GMAC_DTF_DEFT_Msk) >> GMAC_DTF_DEFT_Pos;
+}
+
+static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_reg(const void *const hw, hri_gmac_dtf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->DTF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->DTF.reg;
+}
+
+static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_CSR_bf(const void *const hw, hri_gmac_cse_reg_t mask)
+{
+	return (((Gmac *)hw)->CSE.reg & GMAC_CSE_CSR(mask)) >> GMAC_CSE_CSR_Pos;
+}
+
+static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_CSR_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->CSE.reg & GMAC_CSE_CSR_Msk) >> GMAC_CSE_CSR_Pos;
+}
+
+static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_reg(const void *const hw, hri_gmac_cse_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->CSE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->CSE.reg;
+}
+
+static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_RXO_bf(const void *const hw, hri_gmac_orlo_reg_t mask)
+{
+	return (((Gmac *)hw)->ORLO.reg & GMAC_ORLO_RXO(mask)) >> GMAC_ORLO_RXO_Pos;
+}
+
+static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_RXO_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->ORLO.reg & GMAC_ORLO_RXO_Msk) >> GMAC_ORLO_RXO_Pos;
+}
+
+static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_reg(const void *const hw, hri_gmac_orlo_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->ORLO.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->ORLO.reg;
+}
+
+static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_RXO_bf(const void *const hw, hri_gmac_orhi_reg_t mask)
+{
+	return (((Gmac *)hw)->ORHI.reg & GMAC_ORHI_RXO(mask)) >> GMAC_ORHI_RXO_Pos;
+}
+
+static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_RXO_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->ORHI.reg & GMAC_ORHI_RXO_Msk) >> GMAC_ORHI_RXO_Pos;
+}
+
+static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_reg(const void *const hw, hri_gmac_orhi_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->ORHI.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->ORHI.reg;
+}
+
+static inline hri_gmac_fr_reg_t hri_gmac_get_FR_FRX_bf(const void *const hw, hri_gmac_fr_reg_t mask)
+{
+	return (((Gmac *)hw)->FR.reg & GMAC_FR_FRX(mask)) >> GMAC_FR_FRX_Pos;
+}
+
+static inline hri_gmac_fr_reg_t hri_gmac_read_FR_FRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->FR.reg & GMAC_FR_FRX_Msk) >> GMAC_FR_FRX_Pos;
+}
+
+static inline hri_gmac_fr_reg_t hri_gmac_get_FR_reg(const void *const hw, hri_gmac_fr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->FR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_fr_reg_t hri_gmac_read_FR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->FR.reg;
+}
+
+static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_BFRX_bf(const void *const hw, hri_gmac_bcfr_reg_t mask)
+{
+	return (((Gmac *)hw)->BCFR.reg & GMAC_BCFR_BFRX(mask)) >> GMAC_BCFR_BFRX_Pos;
+}
+
+static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_BFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->BCFR.reg & GMAC_BCFR_BFRX_Msk) >> GMAC_BCFR_BFRX_Pos;
+}
+
+static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_reg(const void *const hw, hri_gmac_bcfr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->BCFR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->BCFR.reg;
+}
+
+static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_MFRX_bf(const void *const hw, hri_gmac_mfr_reg_t mask)
+{
+	return (((Gmac *)hw)->MFR.reg & GMAC_MFR_MFRX(mask)) >> GMAC_MFR_MFRX_Pos;
+}
+
+static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_MFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->MFR.reg & GMAC_MFR_MFRX_Msk) >> GMAC_MFR_MFRX_Pos;
+}
+
+static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_reg(const void *const hw, hri_gmac_mfr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->MFR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->MFR.reg;
+}
+
+static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_PFRX_bf(const void *const hw, hri_gmac_pfr_reg_t mask)
+{
+	return (((Gmac *)hw)->PFR.reg & GMAC_PFR_PFRX(mask)) >> GMAC_PFR_PFRX_Pos;
+}
+
+static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_PFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->PFR.reg & GMAC_PFR_PFRX_Msk) >> GMAC_PFR_PFRX_Pos;
+}
+
+static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_reg(const void *const hw, hri_gmac_pfr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->PFR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->PFR.reg;
+}
+
+static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_NFRX_bf(const void *const hw, hri_gmac_bfr64_reg_t mask)
+{
+	return (((Gmac *)hw)->BFR64.reg & GMAC_BFR64_NFRX(mask)) >> GMAC_BFR64_NFRX_Pos;
+}
+
+static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_NFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->BFR64.reg & GMAC_BFR64_NFRX_Msk) >> GMAC_BFR64_NFRX_Pos;
+}
+
+static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_reg(const void *const hw, hri_gmac_bfr64_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->BFR64.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->BFR64.reg;
+}
+
+static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_NFRX_bf(const void *const hw, hri_gmac_tbfr127_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFR127.reg & GMAC_TBFR127_NFRX(mask)) >> GMAC_TBFR127_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_NFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFR127.reg & GMAC_TBFR127_NFRX_Msk) >> GMAC_TBFR127_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_reg(const void *const hw, hri_gmac_tbfr127_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFR127.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFR127.reg;
+}
+
+static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_NFRX_bf(const void *const hw, hri_gmac_tbfr255_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFR255.reg & GMAC_TBFR255_NFRX(mask)) >> GMAC_TBFR255_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_NFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFR255.reg & GMAC_TBFR255_NFRX_Msk) >> GMAC_TBFR255_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_reg(const void *const hw, hri_gmac_tbfr255_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFR255.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFR255.reg;
+}
+
+static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_NFRX_bf(const void *const hw, hri_gmac_tbfr511_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFR511.reg & GMAC_TBFR511_NFRX(mask)) >> GMAC_TBFR511_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_NFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFR511.reg & GMAC_TBFR511_NFRX_Msk) >> GMAC_TBFR511_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_reg(const void *const hw, hri_gmac_tbfr511_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFR511.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFR511.reg;
+}
+
+static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_NFRX_bf(const void *const hw, hri_gmac_tbfr1023_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFR1023.reg & GMAC_TBFR1023_NFRX(mask)) >> GMAC_TBFR1023_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_NFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFR1023.reg & GMAC_TBFR1023_NFRX_Msk) >> GMAC_TBFR1023_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_reg(const void *const hw, hri_gmac_tbfr1023_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFR1023.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFR1023.reg;
+}
+
+static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_NFRX_bf(const void *const hw, hri_gmac_tbfr1518_reg_t mask)
+{
+	return (((Gmac *)hw)->TBFR1518.reg & GMAC_TBFR1518_NFRX(mask)) >> GMAC_TBFR1518_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_NFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TBFR1518.reg & GMAC_TBFR1518_NFRX_Msk) >> GMAC_TBFR1518_NFRX_Pos;
+}
+
+static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_reg(const void *const hw, hri_gmac_tbfr1518_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBFR1518.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBFR1518.reg;
+}
+
+static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_NFRX_bf(const void *const hw, hri_gmac_tmxbfr_reg_t mask)
+{
+	return (((Gmac *)hw)->TMXBFR.reg & GMAC_TMXBFR_NFRX(mask)) >> GMAC_TMXBFR_NFRX_Pos;
+}
+
+static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_NFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TMXBFR.reg & GMAC_TMXBFR_NFRX_Msk) >> GMAC_TMXBFR_NFRX_Pos;
+}
+
+static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_reg(const void *const hw, hri_gmac_tmxbfr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TMXBFR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TMXBFR.reg;
+}
+
+static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_UFRX_bf(const void *const hw, hri_gmac_ufr_reg_t mask)
+{
+	return (((Gmac *)hw)->UFR.reg & GMAC_UFR_UFRX(mask)) >> GMAC_UFR_UFRX_Pos;
+}
+
+static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_UFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->UFR.reg & GMAC_UFR_UFRX_Msk) >> GMAC_UFR_UFRX_Pos;
+}
+
+static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_reg(const void *const hw, hri_gmac_ufr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->UFR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->UFR.reg;
+}
+
+static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_OFRX_bf(const void *const hw, hri_gmac_ofr_reg_t mask)
+{
+	return (((Gmac *)hw)->OFR.reg & GMAC_OFR_OFRX(mask)) >> GMAC_OFR_OFRX_Pos;
+}
+
+static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_OFRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->OFR.reg & GMAC_OFR_OFRX_Msk) >> GMAC_OFR_OFRX_Pos;
+}
+
+static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_reg(const void *const hw, hri_gmac_ofr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->OFR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->OFR.reg;
+}
+
+static inline hri_gmac_jr_reg_t hri_gmac_get_JR_JRX_bf(const void *const hw, hri_gmac_jr_reg_t mask)
+{
+	return (((Gmac *)hw)->JR.reg & GMAC_JR_JRX(mask)) >> GMAC_JR_JRX_Pos;
+}
+
+static inline hri_gmac_jr_reg_t hri_gmac_read_JR_JRX_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->JR.reg & GMAC_JR_JRX_Msk) >> GMAC_JR_JRX_Pos;
+}
+
+static inline hri_gmac_jr_reg_t hri_gmac_get_JR_reg(const void *const hw, hri_gmac_jr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->JR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_jr_reg_t hri_gmac_read_JR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->JR.reg;
+}
+
+static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_FCKR_bf(const void *const hw, hri_gmac_fcse_reg_t mask)
+{
+	return (((Gmac *)hw)->FCSE.reg & GMAC_FCSE_FCKR(mask)) >> GMAC_FCSE_FCKR_Pos;
+}
+
+static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_FCKR_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->FCSE.reg & GMAC_FCSE_FCKR_Msk) >> GMAC_FCSE_FCKR_Pos;
+}
+
+static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_reg(const void *const hw, hri_gmac_fcse_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->FCSE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->FCSE.reg;
+}
+
+static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_LFER_bf(const void *const hw, hri_gmac_lffe_reg_t mask)
+{
+	return (((Gmac *)hw)->LFFE.reg & GMAC_LFFE_LFER(mask)) >> GMAC_LFFE_LFER_Pos;
+}
+
+static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_LFER_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->LFFE.reg & GMAC_LFFE_LFER_Msk) >> GMAC_LFFE_LFER_Pos;
+}
+
+static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_reg(const void *const hw, hri_gmac_lffe_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->LFFE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->LFFE.reg;
+}
+
+static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_RXSE_bf(const void *const hw, hri_gmac_rse_reg_t mask)
+{
+	return (((Gmac *)hw)->RSE.reg & GMAC_RSE_RXSE(mask)) >> GMAC_RSE_RXSE_Pos;
+}
+
+static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_RXSE_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->RSE.reg & GMAC_RSE_RXSE_Msk) >> GMAC_RSE_RXSE_Pos;
+}
+
+static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_reg(const void *const hw, hri_gmac_rse_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->RSE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->RSE.reg;
+}
+
+static inline hri_gmac_ae_reg_t hri_gmac_get_AE_AER_bf(const void *const hw, hri_gmac_ae_reg_t mask)
+{
+	return (((Gmac *)hw)->AE.reg & GMAC_AE_AER(mask)) >> GMAC_AE_AER_Pos;
+}
+
+static inline hri_gmac_ae_reg_t hri_gmac_read_AE_AER_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->AE.reg & GMAC_AE_AER_Msk) >> GMAC_AE_AER_Pos;
+}
+
+static inline hri_gmac_ae_reg_t hri_gmac_get_AE_reg(const void *const hw, hri_gmac_ae_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->AE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_ae_reg_t hri_gmac_read_AE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->AE.reg;
+}
+
+static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_RXRER_bf(const void *const hw, hri_gmac_rre_reg_t mask)
+{
+	return (((Gmac *)hw)->RRE.reg & GMAC_RRE_RXRER(mask)) >> GMAC_RRE_RXRER_Pos;
+}
+
+static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_RXRER_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->RRE.reg & GMAC_RRE_RXRER_Msk) >> GMAC_RRE_RXRER_Pos;
+}
+
+static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_reg(const void *const hw, hri_gmac_rre_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->RRE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->RRE.reg;
+}
+
+static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_RXOVR_bf(const void *const hw, hri_gmac_roe_reg_t mask)
+{
+	return (((Gmac *)hw)->ROE.reg & GMAC_ROE_RXOVR(mask)) >> GMAC_ROE_RXOVR_Pos;
+}
+
+static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_RXOVR_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->ROE.reg & GMAC_ROE_RXOVR_Msk) >> GMAC_ROE_RXOVR_Pos;
+}
+
+static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_reg(const void *const hw, hri_gmac_roe_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->ROE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->ROE.reg;
+}
+
+static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_HCKER_bf(const void *const hw, hri_gmac_ihce_reg_t mask)
+{
+	return (((Gmac *)hw)->IHCE.reg & GMAC_IHCE_HCKER(mask)) >> GMAC_IHCE_HCKER_Pos;
+}
+
+static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_HCKER_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->IHCE.reg & GMAC_IHCE_HCKER_Msk) >> GMAC_IHCE_HCKER_Pos;
+}
+
+static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_reg(const void *const hw, hri_gmac_ihce_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->IHCE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->IHCE.reg;
+}
+
+static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_TCKER_bf(const void *const hw, hri_gmac_tce_reg_t mask)
+{
+	return (((Gmac *)hw)->TCE.reg & GMAC_TCE_TCKER(mask)) >> GMAC_TCE_TCKER_Pos;
+}
+
+static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_TCKER_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TCE.reg & GMAC_TCE_TCKER_Msk) >> GMAC_TCE_TCKER_Pos;
+}
+
+static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_reg(const void *const hw, hri_gmac_tce_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TCE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TCE.reg;
+}
+
+static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_UCKER_bf(const void *const hw, hri_gmac_uce_reg_t mask)
+{
+	return (((Gmac *)hw)->UCE.reg & GMAC_UCE_UCKER(mask)) >> GMAC_UCE_UCKER_Pos;
+}
+
+static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_UCKER_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->UCE.reg & GMAC_UCE_UCKER_Msk) >> GMAC_UCE_UCKER_Pos;
+}
+
+static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_reg(const void *const hw, hri_gmac_uce_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->UCE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->UCE.reg;
+}
+
+static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_RUD_bf(const void *const hw, hri_gmac_eftsl_reg_t mask)
+{
+	return (((Gmac *)hw)->EFTSL.reg & GMAC_EFTSL_RUD(mask)) >> GMAC_EFTSL_RUD_Pos;
+}
+
+static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->EFTSL.reg & GMAC_EFTSL_RUD_Msk) >> GMAC_EFTSL_RUD_Pos;
+}
+
+static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_reg(const void *const hw, hri_gmac_eftsl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->EFTSL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->EFTSL.reg;
+}
+
+static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_RUD_bf(const void *const hw, hri_gmac_eftn_reg_t mask)
+{
+	return (((Gmac *)hw)->EFTN.reg & GMAC_EFTN_RUD(mask)) >> GMAC_EFTN_RUD_Pos;
+}
+
+static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->EFTN.reg & GMAC_EFTN_RUD_Msk) >> GMAC_EFTN_RUD_Pos;
+}
+
+static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_reg(const void *const hw, hri_gmac_eftn_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->EFTN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->EFTN.reg;
+}
+
+static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_RUD_bf(const void *const hw, hri_gmac_efrsl_reg_t mask)
+{
+	return (((Gmac *)hw)->EFRSL.reg & GMAC_EFRSL_RUD(mask)) >> GMAC_EFRSL_RUD_Pos;
+}
+
+static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->EFRSL.reg & GMAC_EFRSL_RUD_Msk) >> GMAC_EFRSL_RUD_Pos;
+}
+
+static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_reg(const void *const hw, hri_gmac_efrsl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->EFRSL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->EFRSL.reg;
+}
+
+static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_RUD_bf(const void *const hw, hri_gmac_efrn_reg_t mask)
+{
+	return (((Gmac *)hw)->EFRN.reg & GMAC_EFRN_RUD(mask)) >> GMAC_EFRN_RUD_Pos;
+}
+
+static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->EFRN.reg & GMAC_EFRN_RUD_Msk) >> GMAC_EFRN_RUD_Pos;
+}
+
+static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_reg(const void *const hw, hri_gmac_efrn_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->EFRN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->EFRN.reg;
+}
+
+static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_RUD_bf(const void *const hw, hri_gmac_peftsl_reg_t mask)
+{
+	return (((Gmac *)hw)->PEFTSL.reg & GMAC_PEFTSL_RUD(mask)) >> GMAC_PEFTSL_RUD_Pos;
+}
+
+static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->PEFTSL.reg & GMAC_PEFTSL_RUD_Msk) >> GMAC_PEFTSL_RUD_Pos;
+}
+
+static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_reg(const void *const hw, hri_gmac_peftsl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->PEFTSL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->PEFTSL.reg;
+}
+
+static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_RUD_bf(const void *const hw, hri_gmac_peftn_reg_t mask)
+{
+	return (((Gmac *)hw)->PEFTN.reg & GMAC_PEFTN_RUD(mask)) >> GMAC_PEFTN_RUD_Pos;
+}
+
+static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->PEFTN.reg & GMAC_PEFTN_RUD_Msk) >> GMAC_PEFTN_RUD_Pos;
+}
+
+static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_reg(const void *const hw, hri_gmac_peftn_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->PEFTN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->PEFTN.reg;
+}
+
+static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_RUD_bf(const void *const hw, hri_gmac_pefrsl_reg_t mask)
+{
+	return (((Gmac *)hw)->PEFRSL.reg & GMAC_PEFRSL_RUD(mask)) >> GMAC_PEFRSL_RUD_Pos;
+}
+
+static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->PEFRSL.reg & GMAC_PEFRSL_RUD_Msk) >> GMAC_PEFRSL_RUD_Pos;
+}
+
+static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_reg(const void *const hw, hri_gmac_pefrsl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->PEFRSL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->PEFRSL.reg;
+}
+
+static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_RUD_bf(const void *const hw, hri_gmac_pefrn_reg_t mask)
+{
+	return (((Gmac *)hw)->PEFRN.reg & GMAC_PEFRN_RUD(mask)) >> GMAC_PEFRN_RUD_Pos;
+}
+
+static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_RUD_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->PEFRN.reg & GMAC_PEFRN_RUD_Msk) >> GMAC_PEFRN_RUD_Pos;
+}
+
+static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_reg(const void *const hw, hri_gmac_pefrn_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->PEFRN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->PEFRN.reg;
+}
+
+static inline hri_gmac_rlpitr_reg_t hri_gmac_get_RLPITR_RLPITR_bf(const void *const hw, hri_gmac_rlpitr_reg_t mask)
+{
+	return (((Gmac *)hw)->RLPITR.reg & GMAC_RLPITR_RLPITR(mask)) >> GMAC_RLPITR_RLPITR_Pos;
+}
+
+static inline hri_gmac_rlpitr_reg_t hri_gmac_read_RLPITR_RLPITR_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->RLPITR.reg & GMAC_RLPITR_RLPITR_Msk) >> GMAC_RLPITR_RLPITR_Pos;
+}
+
+static inline hri_gmac_rlpitr_reg_t hri_gmac_get_RLPITR_reg(const void *const hw, hri_gmac_rlpitr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->RLPITR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_rlpitr_reg_t hri_gmac_read_RLPITR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->RLPITR.reg;
+}
+
+static inline hri_gmac_rlpiti_reg_t hri_gmac_get_RLPITI_RLPITI_bf(const void *const hw, hri_gmac_rlpiti_reg_t mask)
+{
+	return (((Gmac *)hw)->RLPITI.reg & GMAC_RLPITI_RLPITI(mask)) >> GMAC_RLPITI_RLPITI_Pos;
+}
+
+static inline hri_gmac_rlpiti_reg_t hri_gmac_read_RLPITI_RLPITI_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->RLPITI.reg & GMAC_RLPITI_RLPITI_Msk) >> GMAC_RLPITI_RLPITI_Pos;
+}
+
+static inline hri_gmac_rlpiti_reg_t hri_gmac_get_RLPITI_reg(const void *const hw, hri_gmac_rlpiti_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->RLPITI.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_rlpiti_reg_t hri_gmac_read_RLPITI_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->RLPITI.reg;
+}
+
+static inline hri_gmac_tlpitr_reg_t hri_gmac_get_TLPITR_TLPITR_bf(const void *const hw, hri_gmac_tlpitr_reg_t mask)
+{
+	return (((Gmac *)hw)->TLPITR.reg & GMAC_TLPITR_TLPITR(mask)) >> GMAC_TLPITR_TLPITR_Pos;
+}
+
+static inline hri_gmac_tlpitr_reg_t hri_gmac_read_TLPITR_TLPITR_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TLPITR.reg & GMAC_TLPITR_TLPITR_Msk) >> GMAC_TLPITR_TLPITR_Pos;
+}
+
+static inline hri_gmac_tlpitr_reg_t hri_gmac_get_TLPITR_reg(const void *const hw, hri_gmac_tlpitr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TLPITR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tlpitr_reg_t hri_gmac_read_TLPITR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TLPITR.reg;
+}
+
+static inline hri_gmac_tlpiti_reg_t hri_gmac_get_TLPITI_TLPITI_bf(const void *const hw, hri_gmac_tlpiti_reg_t mask)
+{
+	return (((Gmac *)hw)->TLPITI.reg & GMAC_TLPITI_TLPITI(mask)) >> GMAC_TLPITI_TLPITI_Pos;
+}
+
+static inline hri_gmac_tlpiti_reg_t hri_gmac_read_TLPITI_TLPITI_bf(const void *const hw)
+{
+	return (((Gmac *)hw)->TLPITI.reg & GMAC_TLPITI_TLPITI_Msk) >> GMAC_TLPITI_TLPITI_Pos;
+}
+
+static inline hri_gmac_tlpiti_reg_t hri_gmac_get_TLPITI_reg(const void *const hw, hri_gmac_tlpiti_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TLPITI.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gmac_tlpiti_reg_t hri_gmac_read_TLPITI_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TLPITI.reg;
+}
+
+static inline void hri_gmac_set_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NCR.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ncr_reg_t hri_gmac_get_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->NCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NCR.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NCR.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NCR.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ncr_reg_t hri_gmac_read_NCR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->NCR.reg;
+}
+
+static inline void hri_gmac_set_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NCFGR.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ncfgr_reg_t hri_gmac_get_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->NCFGR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NCFGR.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NCFGR.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NCFGR.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ncfgr_reg_t hri_gmac_read_NCFGR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->NCFGR.reg;
+}
+
+static inline void hri_gmac_set_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->UR.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ur_reg_t hri_gmac_get_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->UR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_UR_reg(const void *const hw, hri_gmac_ur_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->UR.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->UR.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->UR.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ur_reg_t hri_gmac_read_UR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->UR.reg;
+}
+
+static inline void hri_gmac_set_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->DCFGR.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_dcfgr_reg_t hri_gmac_get_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->DCFGR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->DCFGR.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->DCFGR.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->DCFGR.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_dcfgr_reg_t hri_gmac_read_DCFGR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->DCFGR.reg;
+}
+
+static inline void hri_gmac_set_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSR.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tsr_reg_t hri_gmac_get_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSR.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSR.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSR.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tsr_reg_t hri_gmac_read_TSR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TSR.reg;
+}
+
+static inline void hri_gmac_set_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RBQB.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_rbqb_reg_t hri_gmac_get_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->RBQB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RBQB.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RBQB.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RBQB.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_rbqb_reg_t hri_gmac_read_RBQB_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->RBQB.reg;
+}
+
+static inline void hri_gmac_set_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TBQB.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tbqb_reg_t hri_gmac_get_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TBQB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TBQB.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TBQB.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TBQB.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tbqb_reg_t hri_gmac_read_TBQB_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TBQB.reg;
+}
+
+static inline void hri_gmac_set_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RSR.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_rsr_reg_t hri_gmac_get_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->RSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RSR.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RSR.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RSR.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_rsr_reg_t hri_gmac_read_RSR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->RSR.reg;
+}
+
+static inline void hri_gmac_set_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->ISR.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_isr_reg_t hri_gmac_get_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->ISR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_ISR_reg(const void *const hw, hri_gmac_isr_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->ISR.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->ISR.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->ISR.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_isr_reg_t hri_gmac_read_ISR_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->ISR.reg;
+}
+
+static inline void hri_gmac_set_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->MAN.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_man_reg_t hri_gmac_get_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->MAN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_MAN_reg(const void *const hw, hri_gmac_man_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->MAN.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->MAN.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->MAN.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_man_reg_t hri_gmac_read_MAN_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->MAN.reg;
+}
+
+static inline void hri_gmac_set_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPQ.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tpq_reg_t hri_gmac_get_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TPQ.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPQ.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPQ.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPQ.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tpq_reg_t hri_gmac_read_TPQ_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TPQ.reg;
+}
+
+static inline void hri_gmac_set_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPSF.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tpsf_reg_t hri_gmac_get_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TPSF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPSF.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPSF.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPSF.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tpsf_reg_t hri_gmac_read_TPSF_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TPSF.reg;
+}
+
+static inline void hri_gmac_set_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RPSF.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_rpsf_reg_t hri_gmac_get_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->RPSF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RPSF.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RPSF.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RPSF.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_rpsf_reg_t hri_gmac_read_RPSF_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->RPSF.reg;
+}
+
+static inline void hri_gmac_set_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RJFML.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_rjfml_reg_t hri_gmac_get_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->RJFML.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RJFML.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RJFML.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->RJFML.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_rjfml_reg_t hri_gmac_read_RJFML_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->RJFML.reg;
+}
+
+static inline void hri_gmac_set_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->HRB.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_hrb_reg_t hri_gmac_get_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->HRB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->HRB.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->HRB.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->HRB.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_hrb_reg_t hri_gmac_read_HRB_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->HRB.reg;
+}
+
+static inline void hri_gmac_set_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->HRT.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_hrt_reg_t hri_gmac_get_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->HRT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->HRT.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->HRT.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->HRT.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_hrt_reg_t hri_gmac_read_HRT_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->HRT.reg;
+}
+
+static inline void hri_gmac_set_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TIDM[index].reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tidm_reg_t hri_gmac_get_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TIDM[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TIDM[index].reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TIDM[index].reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TIDM[index].reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tidm_reg_t hri_gmac_read_TIDM_reg(const void *const hw, uint8_t index)
+{
+	return ((Gmac *)hw)->TIDM[index].reg;
+}
+
+static inline void hri_gmac_set_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->WOL.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_wol_reg_t hri_gmac_get_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->WOL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_WOL_reg(const void *const hw, hri_gmac_wol_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->WOL.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->WOL.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->WOL.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_wol_reg_t hri_gmac_read_WOL_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->WOL.reg;
+}
+
+static inline void hri_gmac_set_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->IPGS.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ipgs_reg_t hri_gmac_get_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->IPGS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->IPGS.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->IPGS.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->IPGS.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ipgs_reg_t hri_gmac_read_IPGS_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->IPGS.reg;
+}
+
+static inline void hri_gmac_set_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SVLAN.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_svlan_reg_t hri_gmac_get_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->SVLAN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SVLAN.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SVLAN.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SVLAN.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_svlan_reg_t hri_gmac_read_SVLAN_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->SVLAN.reg;
+}
+
+static inline void hri_gmac_set_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPFCP.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tpfcp_reg_t hri_gmac_get_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TPFCP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPFCP.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPFCP.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TPFCP.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tpfcp_reg_t hri_gmac_read_TPFCP_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TPFCP.reg;
+}
+
+static inline void hri_gmac_set_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SAMB1.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_samb1_reg_t hri_gmac_get_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->SAMB1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SAMB1.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SAMB1.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SAMB1.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_samb1_reg_t hri_gmac_read_SAMB1_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->SAMB1.reg;
+}
+
+static inline void hri_gmac_set_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SAMT1.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_samt1_reg_t hri_gmac_get_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->SAMT1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SAMT1.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SAMT1.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SAMT1.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_samt1_reg_t hri_gmac_read_SAMT1_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->SAMT1.reg;
+}
+
+static inline void hri_gmac_set_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NSC.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_nsc_reg_t hri_gmac_get_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->NSC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NSC.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NSC.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->NSC.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_nsc_reg_t hri_gmac_read_NSC_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->NSC.reg;
+}
+
+static inline void hri_gmac_set_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SCL.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_scl_reg_t hri_gmac_get_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->SCL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_SCL_reg(const void *const hw, hri_gmac_scl_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SCL.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SCL.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SCL.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_scl_reg_t hri_gmac_read_SCL_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->SCL.reg;
+}
+
+static inline void hri_gmac_set_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SCH.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sch_reg_t hri_gmac_get_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->SCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_SCH_reg(const void *const hw, hri_gmac_sch_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SCH.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SCH.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->SCH.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_sch_reg_t hri_gmac_read_SCH_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->SCH.reg;
+}
+
+static inline void hri_gmac_set_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TISUBN.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tisubn_reg_t hri_gmac_get_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TISUBN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TISUBN.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TISUBN.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TISUBN.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tisubn_reg_t hri_gmac_read_TISUBN_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TISUBN.reg;
+}
+
+static inline void hri_gmac_set_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSH.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tsh_reg_t hri_gmac_get_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TSH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSH.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSH.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSH.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tsh_reg_t hri_gmac_read_TSH_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TSH.reg;
+}
+
+static inline void hri_gmac_set_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSSSL.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tsssl_reg_t hri_gmac_get_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TSSSL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSSSL.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSSSL.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSSSL.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tsssl_reg_t hri_gmac_read_TSSSL_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TSSSL.reg;
+}
+
+static inline void hri_gmac_set_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSSN.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tssn_reg_t hri_gmac_get_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TSSN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSSN.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSSN.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSSN.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tssn_reg_t hri_gmac_read_TSSN_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TSSN.reg;
+}
+
+static inline void hri_gmac_set_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSL.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tsl_reg_t hri_gmac_get_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TSL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSL.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSL.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TSL.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tsl_reg_t hri_gmac_read_TSL_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TSL.reg;
+}
+
+static inline void hri_gmac_set_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TN.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tn_reg_t hri_gmac_get_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TN_reg(const void *const hw, hri_gmac_tn_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TN.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TN.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TN.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_tn_reg_t hri_gmac_read_TN_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TN.reg;
+}
+
+static inline void hri_gmac_set_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TI.reg |= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ti_reg_t hri_gmac_get_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gmac *)hw)->TI.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gmac_write_TI_reg(const void *const hw, hri_gmac_ti_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TI.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_clear_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TI.reg &= ~mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gmac_toggle_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TI.reg ^= mask;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gmac_ti_reg_t hri_gmac_read_TI_reg(const void *const hw)
+{
+	return ((Gmac *)hw)->TI.reg;
+}
+
+static inline void hri_gmac_write_TA_reg(const void *const hw, hri_gmac_ta_reg_t data)
+{
+	GMAC_CRITICAL_SECTION_ENTER();
+	((Gmac *)hw)->TA.reg = data;
+	GMAC_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_GMAC_E54_H_INCLUDED */
+#endif /* _SAME54_GMAC_COMPONENT_ */
diff --git a/hri/hri_hmatrixb_e54.h b/hri/hri_hmatrixb_e54.h
new file mode 100644
index 0000000..2ef0684
--- /dev/null
+++ b/hri/hri_hmatrixb_e54.h
@@ -0,0 +1,237 @@
+/**
+ * \file
+ *
+ * \brief SAM HMATRIXB
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_HMATRIXB_COMPONENT_
+#ifndef _HRI_HMATRIXB_E54_H_INCLUDED_
+#define _HRI_HMATRIXB_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_HMATRIXB_CRITICAL_SECTIONS)
+#define HMATRIXB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define HMATRIXB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define HMATRIXB_CRITICAL_SECTION_ENTER()
+#define HMATRIXB_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_hmatrixb_pras_reg_t;
+typedef uint32_t hri_hmatrixb_prbs_reg_t;
+typedef uint32_t hri_hmatrixbprs_pras_reg_t;
+typedef uint32_t hri_hmatrixbprs_prbs_reg_t;
+
+static inline void hri_hmatrixbprs_set_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRAS.reg |= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_get_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((HmatrixbPrs *)hw)->PRAS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_hmatrixbprs_write_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t data)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRAS.reg = data;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixbprs_clear_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRAS.reg &= ~mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixbprs_toggle_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRAS.reg ^= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_read_PRAS_reg(const void *const hw)
+{
+	return ((HmatrixbPrs *)hw)->PRAS.reg;
+}
+
+static inline void hri_hmatrixbprs_set_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRBS.reg |= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_get_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((HmatrixbPrs *)hw)->PRBS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_hmatrixbprs_write_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t data)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRBS.reg = data;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixbprs_clear_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRBS.reg &= ~mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixbprs_toggle_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((HmatrixbPrs *)hw)->PRBS.reg ^= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_read_PRBS_reg(const void *const hw)
+{
+	return ((HmatrixbPrs *)hw)->PRBS.reg;
+}
+
+static inline void hri_hmatrixb_set_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg |= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_get_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_hmatrixb_pras_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_hmatrixb_write_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_hmatrixb_pras_reg_t data)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg = data;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixb_clear_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg &= ~mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixb_toggle_PRAS_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_hmatrixb_pras_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg ^= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_read_PRAS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg;
+}
+
+static inline void hri_hmatrixb_set_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg |= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_get_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_hmatrixb_prbs_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_hmatrixb_write_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_hmatrixb_prbs_reg_t data)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg = data;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixb_clear_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg &= ~mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_hmatrixb_toggle_PRBS_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_hmatrixb_prbs_reg_t mask)
+{
+	HMATRIXB_CRITICAL_SECTION_ENTER();
+	((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg ^= mask;
+	HMATRIXB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_read_PRBS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_HMATRIXB_E54_H_INCLUDED */
+#endif /* _SAME54_HMATRIXB_COMPONENT_ */
diff --git a/hri/hri_i2s_e54.h b/hri/hri_i2s_e54.h
new file mode 100644
index 0000000..42b88dc
--- /dev/null
+++ b/hri/hri_i2s_e54.h
@@ -0,0 +1,3032 @@
+/**
+ * \file
+ *
+ * \brief SAM I2S
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_I2S_COMPONENT_
+#ifndef _HRI_I2S_E54_H_INCLUDED_
+#define _HRI_I2S_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_I2S_CRITICAL_SECTIONS)
+#define I2S_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define I2S_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define I2S_CRITICAL_SECTION_ENTER()
+#define I2S_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_i2s_intenset_reg_t;
+typedef uint16_t hri_i2s_intflag_reg_t;
+typedef uint16_t hri_i2s_syncbusy_reg_t;
+typedef uint32_t hri_i2s_clkctrl_reg_t;
+typedef uint32_t hri_i2s_rxctrl_reg_t;
+typedef uint32_t hri_i2s_rxdata_reg_t;
+typedef uint32_t hri_i2s_txctrl_reg_t;
+typedef uint32_t hri_i2s_txdata_reg_t;
+typedef uint8_t  hri_i2s_ctrla_reg_t;
+
+static inline void hri_i2s_wait_for_sync(const void *const hw, hri_i2s_syncbusy_reg_t reg)
+{
+	while (((I2s *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_i2s_is_syncing(const void *const hw, hri_i2s_syncbusy_reg_t reg)
+{
+	return ((I2s *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_i2s_get_INTFLAG_RXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_RXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0;
+}
+
+static inline bool hri_i2s_get_INTFLAG_RXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_RXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1;
+}
+
+static inline bool hri_i2s_get_INTFLAG_RXOR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_RXOR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0;
+}
+
+static inline bool hri_i2s_get_INTFLAG_RXOR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_RXOR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1;
+}
+
+static inline bool hri_i2s_get_INTFLAG_TXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_TXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0;
+}
+
+static inline bool hri_i2s_get_INTFLAG_TXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_TXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1;
+}
+
+static inline bool hri_i2s_get_INTFLAG_TXUR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_TXUR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0;
+}
+
+static inline bool hri_i2s_get_INTFLAG_TXUR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos;
+}
+
+static inline void hri_i2s_clear_INTFLAG_TXUR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1;
+}
+
+static inline bool hri_i2s_get_interrupt_RXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_RXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0;
+}
+
+static inline bool hri_i2s_get_interrupt_RXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_RXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1;
+}
+
+static inline bool hri_i2s_get_interrupt_RXOR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_RXOR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0;
+}
+
+static inline bool hri_i2s_get_interrupt_RXOR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_RXOR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1;
+}
+
+static inline bool hri_i2s_get_interrupt_TXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_TXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0;
+}
+
+static inline bool hri_i2s_get_interrupt_TXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_TXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1;
+}
+
+static inline bool hri_i2s_get_interrupt_TXUR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_TXUR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0;
+}
+
+static inline bool hri_i2s_get_interrupt_TXUR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos;
+}
+
+static inline void hri_i2s_clear_interrupt_TXUR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1;
+}
+
+static inline hri_i2s_intflag_reg_t hri_i2s_get_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((I2s *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_i2s_intflag_reg_t hri_i2s_read_INTFLAG_reg(const void *const hw)
+{
+	return ((I2s *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_i2s_clear_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask)
+{
+	((I2s *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_i2s_set_INTEN_RXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0;
+}
+
+static inline bool hri_i2s_get_INTEN_RXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY0) >> I2S_INTENSET_RXRDY0_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_RXRDY0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_RXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0;
+}
+
+static inline void hri_i2s_set_INTEN_RXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1;
+}
+
+static inline bool hri_i2s_get_INTEN_RXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY1) >> I2S_INTENSET_RXRDY1_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_RXRDY1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_RXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1;
+}
+
+static inline void hri_i2s_set_INTEN_RXOR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0;
+}
+
+static inline bool hri_i2s_get_INTEN_RXOR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR0) >> I2S_INTENSET_RXOR0_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_RXOR0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_RXOR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0;
+}
+
+static inline void hri_i2s_set_INTEN_RXOR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1;
+}
+
+static inline bool hri_i2s_get_INTEN_RXOR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR1) >> I2S_INTENSET_RXOR1_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_RXOR1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_RXOR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1;
+}
+
+static inline void hri_i2s_set_INTEN_TXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0;
+}
+
+static inline bool hri_i2s_get_INTEN_TXRDY0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY0) >> I2S_INTENSET_TXRDY0_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_TXRDY0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_TXRDY0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0;
+}
+
+static inline void hri_i2s_set_INTEN_TXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1;
+}
+
+static inline bool hri_i2s_get_INTEN_TXRDY1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY1) >> I2S_INTENSET_TXRDY1_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_TXRDY1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_TXRDY1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1;
+}
+
+static inline void hri_i2s_set_INTEN_TXUR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0;
+}
+
+static inline bool hri_i2s_get_INTEN_TXUR0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR0) >> I2S_INTENSET_TXUR0_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_TXUR0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_TXUR0_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0;
+}
+
+static inline void hri_i2s_set_INTEN_TXUR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1;
+}
+
+static inline bool hri_i2s_get_INTEN_TXUR1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR1) >> I2S_INTENSET_TXUR1_Pos;
+}
+
+static inline void hri_i2s_write_INTEN_TXUR1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1;
+	} else {
+		((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1;
+	}
+}
+
+static inline void hri_i2s_clear_INTEN_TXUR1_bit(const void *const hw)
+{
+	((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1;
+}
+
+static inline void hri_i2s_set_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask)
+{
+	((I2s *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_i2s_intenset_reg_t hri_i2s_get_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((I2s *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_i2s_intenset_reg_t hri_i2s_read_INTEN_reg(const void *const hw)
+{
+	return ((I2s *)hw)->INTENSET.reg;
+}
+
+static inline void hri_i2s_write_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t data)
+{
+	((I2s *)hw)->INTENSET.reg = data;
+	((I2s *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_i2s_clear_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask)
+{
+	((I2s *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SWRST) >> I2S_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) >> I2S_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_CKEN0_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN0) >> I2S_SYNCBUSY_CKEN0_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_CKEN1_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN1) >> I2S_SYNCBUSY_CKEN1_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_TXEN_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXEN) >> I2S_SYNCBUSY_TXEN_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_RXEN_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXEN) >> I2S_SYNCBUSY_RXEN_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_TXDATA_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXDATA) >> I2S_SYNCBUSY_TXDATA_Pos;
+}
+
+static inline bool hri_i2s_get_SYNCBUSY_RXDATA_bit(const void *const hw)
+{
+	return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXDATA) >> I2S_SYNCBUSY_RXDATA_Pos;
+}
+
+static inline hri_i2s_syncbusy_reg_t hri_i2s_get_SYNCBUSY_reg(const void *const hw, hri_i2s_syncbusy_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((I2s *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_i2s_syncbusy_reg_t hri_i2s_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((I2s *)hw)->SYNCBUSY.reg;
+}
+
+static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_DATA_bf(const void *const hw, hri_i2s_rxdata_reg_t mask)
+{
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA(mask)) >> I2S_RXDATA_DATA_Pos;
+}
+
+static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_DATA_bf(const void *const hw)
+{
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA_Msk) >> I2S_RXDATA_DATA_Pos;
+}
+
+static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_reg(const void *const hw, hri_i2s_rxdata_reg_t mask)
+{
+	uint32_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	tmp = ((I2s *)hw)->RXDATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_reg(const void *const hw)
+{
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	return ((I2s *)hw)->RXDATA.reg;
+}
+
+static inline void hri_i2s_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SWRST;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_SWRST) >> I2S_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_ENABLE;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_ENABLE) >> I2S_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_ENABLE;
+	tmp |= value << I2S_CTRLA_ENABLE_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_ENABLE;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_ENABLE;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_CKEN0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN0;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_CKEN0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_CKEN0) >> I2S_CTRLA_CKEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_CKEN0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_CKEN0;
+	tmp |= value << I2S_CTRLA_CKEN0_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_CKEN0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN0;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_CKEN0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN0;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_CKEN1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN1;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_CKEN1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_CKEN1) >> I2S_CTRLA_CKEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_CKEN1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_CKEN1;
+	tmp |= value << I2S_CTRLA_CKEN1_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_CKEN1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN1;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_CKEN1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN1;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_TXEN_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_TXEN;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_TXEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_TXEN) >> I2S_CTRLA_TXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_TXEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_TXEN;
+	tmp |= value << I2S_CTRLA_TXEN_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_TXEN_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_TXEN;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_TXEN_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_TXEN;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_RXEN_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_RXEN;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CTRLA_RXEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp = (tmp & I2S_CTRLA_RXEN) >> I2S_CTRLA_RXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_RXEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= ~I2S_CTRLA_RXEN;
+	tmp |= value << I2S_CTRLA_RXEN_Pos;
+	((I2s *)hw)->CTRLA.reg = tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_RXEN_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_RXEN;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_RXEN_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_RXEN;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg |= mask;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_ctrla_reg_t hri_i2s_get_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	tmp = ((I2s *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t data)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg = data;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg &= ~mask;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CTRLA.reg ^= mask;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_ctrla_reg_t hri_i2s_read_CTRLA_reg(const void *const hw)
+{
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
+	return ((I2s *)hw)->CTRLA.reg;
+}
+
+static inline void hri_i2s_set_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_BITDELAY;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_BITDELAY) >> I2S_CLKCTRL_BITDELAY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_BITDELAY;
+	tmp |= value << I2S_CLKCTRL_BITDELAY_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_BITDELAY;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_BITDELAY;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSSEL) >> I2S_CLKCTRL_FSSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_FSSEL;
+	tmp |= value << I2S_CLKCTRL_FSSEL_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSINV) >> I2S_CLKCTRL_FSINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_FSINV;
+	tmp |= value << I2S_CLKCTRL_FSINV_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSOUTINV) >> I2S_CLKCTRL_FSOUTINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_FSOUTINV;
+	tmp |= value << I2S_CLKCTRL_FSOUTINV_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_SCKSEL) >> I2S_CLKCTRL_SCKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_SCKSEL;
+	tmp |= value << I2S_CLKCTRL_SCKSEL_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_SCKOUTINV) >> I2S_CLKCTRL_SCKOUTINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_SCKOUTINV;
+	tmp |= value << I2S_CLKCTRL_SCKOUTINV_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKSEL) >> I2S_CLKCTRL_MCKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKSEL;
+	tmp |= value << I2S_CLKCTRL_MCKSEL_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKEN;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKEN) >> I2S_CLKCTRL_MCKEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKEN;
+	tmp |= value << I2S_CLKCTRL_MCKEN_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKEN;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKEN;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKOUTINV) >> I2S_CLKCTRL_MCKOUTINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKOUTINV;
+	tmp |= value << I2S_CLKCTRL_MCKOUTINV_Pos;
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTINV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SLOTSIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index,
+                                                                    hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_SLOTSIZE(mask)) >> I2S_CLKCTRL_SLOTSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_SLOTSIZE_Msk;
+	tmp |= I2S_CLKCTRL_SLOTSIZE(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SLOTSIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SLOTSIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_SLOTSIZE_Msk) >> I2S_CLKCTRL_SLOTSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_NBSLOTS(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index,
+                                                                   hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_NBSLOTS(mask)) >> I2S_CLKCTRL_NBSLOTS_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_NBSLOTS_Msk;
+	tmp |= I2S_CLKCTRL_NBSLOTS(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_NBSLOTS(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_NBSLOTS(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_NBSLOTS_Msk) >> I2S_CLKCTRL_NBSLOTS_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSWIDTH(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index,
+                                                                   hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSWIDTH(mask)) >> I2S_CLKCTRL_FSWIDTH_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_FSWIDTH_Msk;
+	tmp |= I2S_CLKCTRL_FSWIDTH(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSWIDTH(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSWIDTH(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_FSWIDTH_Msk) >> I2S_CLKCTRL_FSWIDTH_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index,
+                                                                  hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKDIV(mask)) >> I2S_CLKCTRL_MCKDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKDIV_Msk;
+	tmp |= I2S_CLKCTRL_MCKDIV(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKDIV_Msk) >> I2S_CLKCTRL_MCKDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index,
+                                                                     hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV(mask)) >> I2S_CLKCTRL_MCKOUTDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= ~I2S_CLKCTRL_MCKOUTDIV_Msk;
+	tmp |= I2S_CLKCTRL_MCKOUTDIV(data);
+	((I2s *)hw)->CLKCTRL[index].reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTDIV(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV_Msk) >> I2S_CLKCTRL_MCKOUTDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg |= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_i2s_clkctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->CLKCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_i2s_write_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg = data;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg &= ~mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->CLKCTRL[index].reg ^= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((I2s *)hw)->CLKCTRL[index].reg;
+}
+
+static inline void hri_i2s_set_TXCTRL_TXSAME_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXSAME;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_TXSAME_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_TXSAME) >> I2S_TXCTRL_TXSAME_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_TXSAME_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_TXSAME;
+	tmp |= value << I2S_TXCTRL_TXSAME_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_TXSAME_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXSAME;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_TXSAME_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXSAME;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTADJ) >> I2S_TXCTRL_SLOTADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTADJ_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTADJ;
+	tmp |= value << I2S_TXCTRL_SLOTADJ_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_WORDADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_WORDADJ_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_WORDADJ) >> I2S_TXCTRL_WORDADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_WORDADJ_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_WORDADJ;
+	tmp |= value << I2S_TXCTRL_WORDADJ_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_WORDADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_WORDADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_BITREV_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_BITREV_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_BITREV) >> I2S_TXCTRL_BITREV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_BITREV_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_BITREV;
+	tmp |= value << I2S_TXCTRL_BITREV_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_BITREV_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_BITREV_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS0) >> I2S_TXCTRL_SLOTDIS0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS0;
+	tmp |= value << I2S_TXCTRL_SLOTDIS0_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS1) >> I2S_TXCTRL_SLOTDIS1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS1;
+	tmp |= value << I2S_TXCTRL_SLOTDIS1_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS2) >> I2S_TXCTRL_SLOTDIS2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS2;
+	tmp |= value << I2S_TXCTRL_SLOTDIS2_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS3) >> I2S_TXCTRL_SLOTDIS3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS3;
+	tmp |= value << I2S_TXCTRL_SLOTDIS3_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS4) >> I2S_TXCTRL_SLOTDIS4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS4;
+	tmp |= value << I2S_TXCTRL_SLOTDIS4_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS5) >> I2S_TXCTRL_SLOTDIS5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS5;
+	tmp |= value << I2S_TXCTRL_SLOTDIS5_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS6) >> I2S_TXCTRL_SLOTDIS6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS6;
+	tmp |= value << I2S_TXCTRL_SLOTDIS6_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_SLOTDIS7) >> I2S_TXCTRL_SLOTDIS7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_SLOTDIS7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_SLOTDIS7;
+	tmp |= value << I2S_TXCTRL_SLOTDIS7_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_MONO_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_MONO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_MONO) >> I2S_TXCTRL_MONO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_MONO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_MONO;
+	tmp |= value << I2S_TXCTRL_MONO_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_MONO_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_MONO_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_DMA_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_TXCTRL_DMA_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_DMA) >> I2S_TXCTRL_DMA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_DMA_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_DMA;
+	tmp |= value << I2S_TXCTRL_DMA_Pos;
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_DMA_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_DMA_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXDEFAULT(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_TXDEFAULT(mask)) >> I2S_TXCTRL_TXDEFAULT_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_TXDEFAULT_Msk;
+	tmp |= I2S_TXCTRL_TXDEFAULT(data);
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXDEFAULT(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXDEFAULT(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_TXDEFAULT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_TXDEFAULT_Msk) >> I2S_TXCTRL_TXDEFAULT_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_DATASIZE(mask)) >> I2S_TXCTRL_DATASIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_DATASIZE_Msk;
+	tmp |= I2S_TXCTRL_DATASIZE(data);
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_DATASIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_DATASIZE_Msk) >> I2S_TXCTRL_DATASIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_EXTEND(mask)) >> I2S_TXCTRL_EXTEND_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= ~I2S_TXCTRL_EXTEND_Msk;
+	tmp |= I2S_TXCTRL_EXTEND(data);
+	((I2s *)hw)->TXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_EXTEND_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp = (tmp & I2S_TXCTRL_EXTEND_Msk) >> I2S_TXCTRL_EXTEND_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg |= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->TXCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_i2s_write_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t data)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg = data;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg &= ~mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXCTRL.reg ^= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_reg(const void *const hw)
+{
+	return ((I2s *)hw)->TXCTRL.reg;
+}
+
+static inline void hri_i2s_set_RXCTRL_CLKSEL_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_CLKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_CLKSEL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_CLKSEL) >> I2S_RXCTRL_CLKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_CLKSEL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_CLKSEL;
+	tmp |= value << I2S_RXCTRL_CLKSEL_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_CLKSEL_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_CLKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_CLKSEL_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_CLKSEL;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTADJ) >> I2S_RXCTRL_SLOTADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTADJ_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTADJ;
+	tmp |= value << I2S_RXCTRL_SLOTADJ_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_WORDADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_WORDADJ_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_WORDADJ) >> I2S_RXCTRL_WORDADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_WORDADJ_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_WORDADJ;
+	tmp |= value << I2S_RXCTRL_WORDADJ_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_WORDADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_WORDADJ_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_WORDADJ;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_BITREV_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_BITREV_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_BITREV) >> I2S_RXCTRL_BITREV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_BITREV_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_BITREV;
+	tmp |= value << I2S_RXCTRL_BITREV_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_BITREV_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_BITREV_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_BITREV;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS0) >> I2S_RXCTRL_SLOTDIS0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS0;
+	tmp |= value << I2S_RXCTRL_SLOTDIS0_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS0_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS0;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS1) >> I2S_RXCTRL_SLOTDIS1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS1;
+	tmp |= value << I2S_RXCTRL_SLOTDIS1_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS1_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS1;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS2) >> I2S_RXCTRL_SLOTDIS2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS2;
+	tmp |= value << I2S_RXCTRL_SLOTDIS2_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS2_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS2;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS3) >> I2S_RXCTRL_SLOTDIS3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS3;
+	tmp |= value << I2S_RXCTRL_SLOTDIS3_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS3_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS3;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS4) >> I2S_RXCTRL_SLOTDIS4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS4;
+	tmp |= value << I2S_RXCTRL_SLOTDIS4_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS4_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS4;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS5) >> I2S_RXCTRL_SLOTDIS5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS5;
+	tmp |= value << I2S_RXCTRL_SLOTDIS5_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS5_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS5;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS6) >> I2S_RXCTRL_SLOTDIS6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS6;
+	tmp |= value << I2S_RXCTRL_SLOTDIS6_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS6_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS6;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SLOTDIS7) >> I2S_RXCTRL_SLOTDIS7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SLOTDIS7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SLOTDIS7;
+	tmp |= value << I2S_RXCTRL_SLOTDIS7_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SLOTDIS7_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS7;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_MONO_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_MONO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_MONO) >> I2S_RXCTRL_MONO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_MONO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_MONO;
+	tmp |= value << I2S_RXCTRL_MONO_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_MONO_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_MONO_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_MONO;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_DMA_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_DMA_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_DMA) >> I2S_RXCTRL_DMA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_DMA_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_DMA;
+	tmp |= value << I2S_RXCTRL_DMA_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_DMA_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_DMA_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DMA;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_RXLOOP_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_RXLOOP;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_i2s_get_RXCTRL_RXLOOP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_RXLOOP) >> I2S_RXCTRL_RXLOOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_RXLOOP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_RXLOOP;
+	tmp |= value << I2S_RXCTRL_RXLOOP_Pos;
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_RXLOOP_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_RXLOOP;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_RXLOOP_bit(const void *const hw)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_RXLOOP;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_set_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SERMODE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SERMODE(mask)) >> I2S_RXCTRL_SERMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_SERMODE_Msk;
+	tmp |= I2S_RXCTRL_SERMODE(data);
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SERMODE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SERMODE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_SERMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_SERMODE_Msk) >> I2S_RXCTRL_SERMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_DATASIZE(mask)) >> I2S_RXCTRL_DATASIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_DATASIZE_Msk;
+	tmp |= I2S_RXCTRL_DATASIZE(data);
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DATASIZE(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_DATASIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_DATASIZE_Msk) >> I2S_RXCTRL_DATASIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_EXTEND(mask)) >> I2S_RXCTRL_EXTEND_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t data)
+{
+	uint32_t tmp;
+	I2S_CRITICAL_SECTION_ENTER();
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= ~I2S_RXCTRL_EXTEND_Msk;
+	tmp |= I2S_RXCTRL_EXTEND(data);
+	((I2s *)hw)->RXCTRL.reg = tmp;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_EXTEND(mask);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_EXTEND_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp = (tmp & I2S_RXCTRL_EXTEND_Msk) >> I2S_RXCTRL_EXTEND_Pos;
+	return tmp;
+}
+
+static inline void hri_i2s_set_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg |= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((I2s *)hw)->RXCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_i2s_write_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t data)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg = data;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_clear_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg &= ~mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_i2s_toggle_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->RXCTRL.reg ^= mask;
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_reg(const void *const hw)
+{
+	return ((I2s *)hw)->RXCTRL.reg;
+}
+
+static inline void hri_i2s_write_TXDATA_reg(const void *const hw, hri_i2s_txdata_reg_t data)
+{
+	I2S_CRITICAL_SECTION_ENTER();
+	((I2s *)hw)->TXDATA.reg = data;
+	hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
+	I2S_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_I2S_E54_H_INCLUDED */
+#endif /* _SAME54_I2S_COMPONENT_ */
diff --git a/hri/hri_icm_e54.h b/hri/hri_icm_e54.h
new file mode 100644
index 0000000..374caa4
--- /dev/null
+++ b/hri/hri_icm_e54.h
@@ -0,0 +1,761 @@
+/**
+ * \file
+ *
+ * \brief SAM ICM
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_ICM_COMPONENT_
+#ifndef _HRI_ICM_E54_H_INCLUDED_
+#define _HRI_ICM_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_ICM_CRITICAL_SECTIONS)
+#define ICM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define ICM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define ICM_CRITICAL_SECTION_ENTER()
+#define ICM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_icm_cfg_reg_t;
+typedef uint32_t hri_icm_ctrl_reg_t;
+typedef uint32_t hri_icm_dscr_reg_t;
+typedef uint32_t hri_icm_hash_reg_t;
+typedef uint32_t hri_icm_imr_reg_t;
+typedef uint32_t hri_icm_isr_reg_t;
+typedef uint32_t hri_icm_sr_reg_t;
+typedef uint32_t hri_icm_uasr_reg_t;
+typedef uint32_t hri_icm_uihval_reg_t;
+typedef uint32_t hri_icmdescriptor_raddr_reg_t;
+typedef uint32_t hri_icmdescriptor_rcfg_reg_t;
+typedef uint32_t hri_icmdescriptor_rctrl_reg_t;
+typedef uint32_t hri_icmdescriptor_rnext_reg_t;
+
+static inline void hri_icmdescriptor_set_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RADDR.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_get_RADDR_reg(const void *const             hw,
+                                                                            hri_icmdescriptor_raddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((IcmDescriptor *)hw)->RADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icmdescriptor_write_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RADDR.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_clear_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RADDR.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_toggle_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RADDR.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_read_RADDR_reg(const void *const hw)
+{
+	return ((IcmDescriptor *)hw)->RADDR.reg;
+}
+
+static inline void hri_icmdescriptor_set_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCFG.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_get_RCFG_reg(const void *const            hw,
+                                                                          hri_icmdescriptor_rcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((IcmDescriptor *)hw)->RCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icmdescriptor_write_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCFG.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_clear_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCFG.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_toggle_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCFG.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_read_RCFG_reg(const void *const hw)
+{
+	return ((IcmDescriptor *)hw)->RCFG.reg;
+}
+
+static inline void hri_icmdescriptor_set_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCTRL.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_get_RCTRL_reg(const void *const             hw,
+                                                                            hri_icmdescriptor_rctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((IcmDescriptor *)hw)->RCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icmdescriptor_write_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCTRL.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_clear_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCTRL.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_toggle_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RCTRL.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_read_RCTRL_reg(const void *const hw)
+{
+	return ((IcmDescriptor *)hw)->RCTRL.reg;
+}
+
+static inline void hri_icmdescriptor_set_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RNEXT.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_get_RNEXT_reg(const void *const             hw,
+                                                                            hri_icmdescriptor_rnext_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((IcmDescriptor *)hw)->RNEXT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icmdescriptor_write_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RNEXT.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_clear_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RNEXT.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icmdescriptor_toggle_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((IcmDescriptor *)hw)->RNEXT.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_read_RNEXT_reg(const void *const hw)
+{
+	return ((IcmDescriptor *)hw)->RNEXT.reg;
+}
+
+static inline void hri_icm_set_IMR_URAD_bit(const void *const hw)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_URAD;
+}
+
+static inline bool hri_icm_get_IMR_URAD_bit(const void *const hw)
+{
+	return (((Icm *)hw)->IMR.reg & ICM_IMR_URAD) >> ICM_IMR_URAD_Pos;
+}
+
+static inline void hri_icm_write_IMR_URAD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Icm *)hw)->IDR.reg = ICM_IMR_URAD;
+	} else {
+		((Icm *)hw)->IER.reg = ICM_IMR_URAD;
+	}
+}
+
+static inline void hri_icm_clear_IMR_URAD_bit(const void *const hw)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_URAD;
+}
+
+static inline void hri_icm_set_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RHC(mask);
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RHC(mask)) >> ICM_IMR_RHC_Pos;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_RHC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RHC_Msk) >> ICM_IMR_RHC_Pos;
+	return tmp;
+}
+
+static inline void hri_icm_write_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RHC(data);
+	((Icm *)hw)->IDR.reg = ~ICM_IMR_RHC(data);
+}
+
+static inline void hri_icm_clear_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_RHC(mask);
+}
+
+static inline void hri_icm_set_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RDM(mask);
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RDM(mask)) >> ICM_IMR_RDM_Pos;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_RDM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RDM_Msk) >> ICM_IMR_RDM_Pos;
+	return tmp;
+}
+
+static inline void hri_icm_write_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RDM(data);
+	((Icm *)hw)->IDR.reg = ~ICM_IMR_RDM(data);
+}
+
+static inline void hri_icm_clear_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_RDM(mask);
+}
+
+static inline void hri_icm_set_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RBE(mask);
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RBE(mask)) >> ICM_IMR_RBE_Pos;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_RBE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RBE_Msk) >> ICM_IMR_RBE_Pos;
+	return tmp;
+}
+
+static inline void hri_icm_write_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RBE(data);
+	((Icm *)hw)->IDR.reg = ~ICM_IMR_RBE(data);
+}
+
+static inline void hri_icm_clear_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_RBE(mask);
+}
+
+static inline void hri_icm_set_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RWC(mask);
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RWC(mask)) >> ICM_IMR_RWC_Pos;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_RWC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RWC_Msk) >> ICM_IMR_RWC_Pos;
+	return tmp;
+}
+
+static inline void hri_icm_write_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RWC(data);
+	((Icm *)hw)->IDR.reg = ~ICM_IMR_RWC(data);
+}
+
+static inline void hri_icm_clear_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_RWC(mask);
+}
+
+static inline void hri_icm_set_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_REC(mask);
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_REC(mask)) >> ICM_IMR_REC_Pos;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_REC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_REC_Msk) >> ICM_IMR_REC_Pos;
+	return tmp;
+}
+
+static inline void hri_icm_write_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_REC(data);
+	((Icm *)hw)->IDR.reg = ~ICM_IMR_REC(data);
+}
+
+static inline void hri_icm_clear_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_REC(mask);
+}
+
+static inline void hri_icm_set_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RSU(mask);
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RSU(mask)) >> ICM_IMR_RSU_Pos;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_RSU_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp = (tmp & ICM_IMR_RSU_Msk) >> ICM_IMR_RSU_Pos;
+	return tmp;
+}
+
+static inline void hri_icm_write_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = ICM_IMR_RSU(data);
+	((Icm *)hw)->IDR.reg = ~ICM_IMR_RSU(data);
+}
+
+static inline void hri_icm_clear_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = ICM_IMR_RSU(mask);
+}
+
+static inline void hri_icm_set_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IER.reg = mask;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_get_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->IMR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_icm_imr_reg_t hri_icm_read_IMR_reg(const void *const hw)
+{
+	return ((Icm *)hw)->IMR.reg;
+}
+
+static inline void hri_icm_write_IMR_reg(const void *const hw, hri_icm_imr_reg_t data)
+{
+	((Icm *)hw)->IER.reg = data;
+	((Icm *)hw)->IDR.reg = ~data;
+}
+
+static inline void hri_icm_clear_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask)
+{
+	((Icm *)hw)->IDR.reg = mask;
+}
+
+static inline bool hri_icm_get_SR_ENABLE_bit(const void *const hw)
+{
+	return (((Icm *)hw)->SR.reg & ICM_SR_ENABLE) >> ICM_SR_ENABLE_Pos;
+}
+
+static inline hri_icm_sr_reg_t hri_icm_get_SR_RAWRMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask)
+{
+	return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS(mask)) >> ICM_SR_RAWRMDIS_Pos;
+}
+
+static inline hri_icm_sr_reg_t hri_icm_read_SR_RAWRMDIS_bf(const void *const hw)
+{
+	return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS_Msk) >> ICM_SR_RAWRMDIS_Pos;
+}
+
+static inline hri_icm_sr_reg_t hri_icm_get_SR_RMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask)
+{
+	return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS(mask)) >> ICM_SR_RMDIS_Pos;
+}
+
+static inline hri_icm_sr_reg_t hri_icm_read_SR_RMDIS_bf(const void *const hw)
+{
+	return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS_Msk) >> ICM_SR_RMDIS_Pos;
+}
+
+static inline hri_icm_sr_reg_t hri_icm_get_SR_reg(const void *const hw, hri_icm_sr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->SR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_icm_sr_reg_t hri_icm_read_SR_reg(const void *const hw)
+{
+	return ((Icm *)hw)->SR.reg;
+}
+
+static inline bool hri_icm_get_ISR_URAD_bit(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_URAD) >> ICM_ISR_URAD_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_RHC_bf(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC(mask)) >> ICM_ISR_RHC_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_RHC_bf(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC_Msk) >> ICM_ISR_RHC_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_RDM_bf(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM(mask)) >> ICM_ISR_RDM_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_RDM_bf(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM_Msk) >> ICM_ISR_RDM_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_RBE_bf(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE(mask)) >> ICM_ISR_RBE_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_RBE_bf(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE_Msk) >> ICM_ISR_RBE_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_RWC_bf(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC(mask)) >> ICM_ISR_RWC_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_RWC_bf(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC_Msk) >> ICM_ISR_RWC_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_REC_bf(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_REC(mask)) >> ICM_ISR_REC_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_REC_bf(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_REC_Msk) >> ICM_ISR_REC_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_RSU_bf(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU(mask)) >> ICM_ISR_RSU_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_RSU_bf(const void *const hw)
+{
+	return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU_Msk) >> ICM_ISR_RSU_Pos;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_get_ISR_reg(const void *const hw, hri_icm_isr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->ISR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_icm_isr_reg_t hri_icm_read_ISR_reg(const void *const hw)
+{
+	return ((Icm *)hw)->ISR.reg;
+}
+
+static inline hri_icm_uasr_reg_t hri_icm_get_UASR_URAT_bf(const void *const hw, hri_icm_uasr_reg_t mask)
+{
+	return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT(mask)) >> ICM_UASR_URAT_Pos;
+}
+
+static inline hri_icm_uasr_reg_t hri_icm_read_UASR_URAT_bf(const void *const hw)
+{
+	return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT_Msk) >> ICM_UASR_URAT_Pos;
+}
+
+static inline hri_icm_uasr_reg_t hri_icm_get_UASR_reg(const void *const hw, hri_icm_uasr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->UASR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_icm_uasr_reg_t hri_icm_read_UASR_reg(const void *const hw)
+{
+	return ((Icm *)hw)->UASR.reg;
+}
+
+static inline void hri_icm_set_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->CFG.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icm_cfg_reg_t hri_icm_get_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->CFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icm_write_CFG_reg(const void *const hw, hri_icm_cfg_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->CFG.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_clear_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->CFG.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_toggle_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->CFG.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icm_cfg_reg_t hri_icm_read_CFG_reg(const void *const hw)
+{
+	return ((Icm *)hw)->CFG.reg;
+}
+
+static inline void hri_icm_set_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->DSCR.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icm_dscr_reg_t hri_icm_get_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->DSCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icm_write_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->DSCR.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_clear_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->DSCR.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_toggle_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->DSCR.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icm_dscr_reg_t hri_icm_read_DSCR_reg(const void *const hw)
+{
+	return ((Icm *)hw)->DSCR.reg;
+}
+
+static inline void hri_icm_set_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->HASH.reg |= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icm_hash_reg_t hri_icm_get_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Icm *)hw)->HASH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_icm_write_HASH_reg(const void *const hw, hri_icm_hash_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->HASH.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_clear_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->HASH.reg &= ~mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_toggle_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->HASH.reg ^= mask;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_icm_hash_reg_t hri_icm_read_HASH_reg(const void *const hw)
+{
+	return ((Icm *)hw)->HASH.reg;
+}
+
+static inline void hri_icm_write_CTRL_reg(const void *const hw, hri_icm_ctrl_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->CTRL.reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_icm_write_UIHVAL_reg(const void *const hw, uint8_t index, hri_icm_uihval_reg_t data)
+{
+	ICM_CRITICAL_SECTION_ENTER();
+	((Icm *)hw)->UIHVAL[index].reg = data;
+	ICM_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_ICM_E54_H_INCLUDED */
+#endif /* _SAME54_ICM_COMPONENT_ */
diff --git a/hri/hri_mclk_e54.h b/hri/hri_mclk_e54.h
new file mode 100644
index 0000000..7e3963b
--- /dev/null
+++ b/hri/hri_mclk_e54.h
@@ -0,0 +1,3556 @@
+/**
+ * \file
+ *
+ * \brief SAM MCLK
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_MCLK_COMPONENT_
+#ifndef _HRI_MCLK_E54_H_INCLUDED_
+#define _HRI_MCLK_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_MCLK_CRITICAL_SECTIONS)
+#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define MCLK_CRITICAL_SECTION_ENTER()
+#define MCLK_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_mclk_ahbmask_reg_t;
+typedef uint32_t hri_mclk_apbamask_reg_t;
+typedef uint32_t hri_mclk_apbbmask_reg_t;
+typedef uint32_t hri_mclk_apbcmask_reg_t;
+typedef uint32_t hri_mclk_apbdmask_reg_t;
+typedef uint8_t  hri_mclk_cpudiv_reg_t;
+typedef uint8_t  hri_mclk_hsdiv_reg_t;
+typedef uint8_t  hri_mclk_intenset_reg_t;
+typedef uint8_t  hri_mclk_intflag_reg_t;
+
+static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw)
+{
+	return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos;
+}
+
+static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY;
+}
+
+static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw)
+{
+	return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos;
+}
+
+static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY;
+}
+
+static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask)
+{
+	((Mclk *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY;
+}
+
+static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw)
+{
+	return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos;
+}
+
+static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY;
+	} else {
+		((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY;
+	}
+}
+
+static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY;
+}
+
+static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
+{
+	((Mclk *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->INTENSET.reg;
+}
+
+static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data)
+{
+	((Mclk *)hw)->INTENSET.reg = data;
+	((Mclk *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
+{
+	((Mclk *)hw)->INTENCLR.reg = mask;
+}
+
+static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_DIV_bf(const void *const hw, hri_mclk_hsdiv_reg_t mask)
+{
+	return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV(mask)) >> MCLK_HSDIV_DIV_Pos;
+}
+
+static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_DIV_bf(const void *const hw)
+{
+	return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV_Msk) >> MCLK_HSDIV_DIV_Pos;
+}
+
+static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_reg(const void *const hw, hri_mclk_hsdiv_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->HSDIV.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->HSDIV.reg;
+}
+
+static inline void hri_mclk_set_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_DIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp = (tmp & MCLK_CPUDIV_DIV(mask)) >> MCLK_CPUDIV_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_mclk_write_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data)
+{
+	uint8_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp &= ~MCLK_CPUDIV_DIV_Msk;
+	tmp |= MCLK_CPUDIV_DIV(data);
+	((Mclk *)hw)->CPUDIV.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_DIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_DIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_DIV_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp = (tmp & MCLK_CPUDIV_DIV_Msk) >> MCLK_CPUDIV_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->CPUDIV.reg;
+}
+
+static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HPB0;
+	tmp |= value << MCLK_AHBMASK_HPB0_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HPB1;
+	tmp |= value << MCLK_AHBMASK_HPB1_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HPB2;
+	tmp |= value << MCLK_AHBMASK_HPB2_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HPB3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HPB3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HPB3) >> MCLK_AHBMASK_HPB3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HPB3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HPB3;
+	tmp |= value << MCLK_AHBMASK_HPB3_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HPB3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HPB3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_DSU;
+	tmp |= value << MCLK_AHBMASK_DSU_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HMATRIX_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HMATRIX;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HMATRIX_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HMATRIX) >> MCLK_AHBMASK_HMATRIX_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HMATRIX_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HMATRIX;
+	tmp |= value << MCLK_AHBMASK_HMATRIX_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HMATRIX_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HMATRIX;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HMATRIX_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HMATRIX;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_NVMCTRL;
+	tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HSRAM;
+	tmp |= value << MCLK_AHBMASK_HSRAM_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_CMCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CMCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_CMCC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_CMCC) >> MCLK_AHBMASK_CMCC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_CMCC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_CMCC;
+	tmp |= value << MCLK_AHBMASK_CMCC_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_CMCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CMCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_CMCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CMCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_DMAC;
+	tmp |= value << MCLK_AHBMASK_DMAC_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_USB_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_USB) >> MCLK_AHBMASK_USB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_USB_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_USB;
+	tmp |= value << MCLK_AHBMASK_USB_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_BKUPRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_BKUPRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_BKUPRAM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_BKUPRAM) >> MCLK_AHBMASK_BKUPRAM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_BKUPRAM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_BKUPRAM;
+	tmp |= value << MCLK_AHBMASK_BKUPRAM_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_BKUPRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_BKUPRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_BKUPRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_BKUPRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_PAC;
+	tmp |= value << MCLK_AHBMASK_PAC_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_QSPI_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_QSPI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_QSPI) >> MCLK_AHBMASK_QSPI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_QSPI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_QSPI;
+	tmp |= value << MCLK_AHBMASK_QSPI_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_QSPI_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_QSPI_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_GMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_GMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_GMAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_GMAC) >> MCLK_AHBMASK_GMAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_GMAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_GMAC;
+	tmp |= value << MCLK_AHBMASK_GMAC_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_GMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_GMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_GMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_GMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_SDHC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_SDHC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_SDHC0) >> MCLK_AHBMASK_SDHC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_SDHC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_SDHC0;
+	tmp |= value << MCLK_AHBMASK_SDHC0_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_SDHC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_SDHC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_SDHC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_SDHC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_SDHC1) >> MCLK_AHBMASK_SDHC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_SDHC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_SDHC1;
+	tmp |= value << MCLK_AHBMASK_SDHC1_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_SDHC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_SDHC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_CAN0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_CAN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_CAN0) >> MCLK_AHBMASK_CAN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_CAN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_CAN0;
+	tmp |= value << MCLK_AHBMASK_CAN0_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_CAN0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_CAN0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_CAN1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_CAN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_CAN1) >> MCLK_AHBMASK_CAN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_CAN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_CAN1;
+	tmp |= value << MCLK_AHBMASK_CAN1_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_CAN1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_CAN1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_ICM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_ICM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_ICM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_ICM) >> MCLK_AHBMASK_ICM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_ICM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_ICM;
+	tmp |= value << MCLK_AHBMASK_ICM_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_ICM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_ICM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_ICM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_ICM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_PUKCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PUKCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_PUKCC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_PUKCC) >> MCLK_AHBMASK_PUKCC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_PUKCC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_PUKCC;
+	tmp |= value << MCLK_AHBMASK_PUKCC_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_PUKCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PUKCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_PUKCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PUKCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_QSPI_2X_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI_2X;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_QSPI_2X_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_QSPI_2X) >> MCLK_AHBMASK_QSPI_2X_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_QSPI_2X_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_QSPI_2X;
+	tmp |= value << MCLK_AHBMASK_QSPI_2X_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_QSPI_2X_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI_2X;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_QSPI_2X_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI_2X;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_SMEEPROM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_NVMCTRL_SMEEPROM) >> MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM;
+	tmp |= value << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_SMEEPROM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_CACHE;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_NVMCTRL_CACHE) >> MCLK_AHBMASK_NVMCTRL_CACHE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_NVMCTRL_CACHE;
+	tmp |= value << MCLK_AHBMASK_NVMCTRL_CACHE_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_CACHE;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_CACHE;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->AHBMASK.reg;
+}
+
+static inline void hri_mclk_set_APBAMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_PAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_PAC) >> MCLK_APBAMASK_PAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_PAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_PAC;
+	tmp |= value << MCLK_APBAMASK_PAC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_PM;
+	tmp |= value << MCLK_APBAMASK_PM_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_MCLK;
+	tmp |= value << MCLK_APBAMASK_MCLK_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_RSTC;
+	tmp |= value << MCLK_APBAMASK_RSTC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_OSCCTRL;
+	tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_OSC32KCTRL;
+	tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_SUPC;
+	tmp |= value << MCLK_APBAMASK_SUPC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_GCLK;
+	tmp |= value << MCLK_APBAMASK_GCLK_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_WDT;
+	tmp |= value << MCLK_APBAMASK_WDT_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_RTC;
+	tmp |= value << MCLK_APBAMASK_RTC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_EIC;
+	tmp |= value << MCLK_APBAMASK_EIC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_FREQM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_FREQM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_FREQM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_FREQM) >> MCLK_APBAMASK_FREQM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_FREQM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_FREQM;
+	tmp |= value << MCLK_APBAMASK_FREQM_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_FREQM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_FREQM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_FREQM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_FREQM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_SERCOM0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_SERCOM0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_SERCOM0) >> MCLK_APBAMASK_SERCOM0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_SERCOM0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_SERCOM0;
+	tmp |= value << MCLK_APBAMASK_SERCOM0_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_SERCOM0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_SERCOM0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_SERCOM1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_SERCOM1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_SERCOM1) >> MCLK_APBAMASK_SERCOM1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_SERCOM1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_SERCOM1;
+	tmp |= value << MCLK_APBAMASK_SERCOM1_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_SERCOM1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_SERCOM1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_TC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_TC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_TC0) >> MCLK_APBAMASK_TC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_TC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_TC0;
+	tmp |= value << MCLK_APBAMASK_TC0_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_TC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_TC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_TC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_TC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_TC1) >> MCLK_APBAMASK_TC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_TC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_TC1;
+	tmp |= value << MCLK_APBAMASK_TC1_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_TC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_TC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->APBAMASK.reg;
+}
+
+static inline void hri_mclk_set_APBBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_USB_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_USB) >> MCLK_APBBMASK_USB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_USB_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_USB;
+	tmp |= value << MCLK_APBBMASK_USB_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_DSU;
+	tmp |= value << MCLK_APBBMASK_DSU_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_NVMCTRL;
+	tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_PORT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_PORT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_PORT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_PORT) >> MCLK_APBBMASK_PORT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_PORT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_PORT;
+	tmp |= value << MCLK_APBBMASK_PORT_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_PORT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_PORT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_PORT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_PORT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_HMATRIX_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_HMATRIX;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_HMATRIX_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_HMATRIX) >> MCLK_APBBMASK_HMATRIX_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_HMATRIX_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_HMATRIX;
+	tmp |= value << MCLK_APBBMASK_HMATRIX_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_HMATRIX_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_HMATRIX;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_HMATRIX_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_HMATRIX;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_EVSYS_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_EVSYS;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_EVSYS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_EVSYS) >> MCLK_APBBMASK_EVSYS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_EVSYS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_EVSYS;
+	tmp |= value << MCLK_APBBMASK_EVSYS_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_EVSYS_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_EVSYS;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_EVSYS_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_EVSYS;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_SERCOM2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_SERCOM2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_SERCOM2) >> MCLK_APBBMASK_SERCOM2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_SERCOM2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_SERCOM2;
+	tmp |= value << MCLK_APBBMASK_SERCOM2_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_SERCOM2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_SERCOM2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_SERCOM3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_SERCOM3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_SERCOM3) >> MCLK_APBBMASK_SERCOM3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_SERCOM3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_SERCOM3;
+	tmp |= value << MCLK_APBBMASK_SERCOM3_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_SERCOM3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_SERCOM3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_TCC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_TCC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_TCC0) >> MCLK_APBBMASK_TCC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_TCC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_TCC0;
+	tmp |= value << MCLK_APBBMASK_TCC0_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_TCC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_TCC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_TCC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_TCC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_TCC1) >> MCLK_APBBMASK_TCC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_TCC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_TCC1;
+	tmp |= value << MCLK_APBBMASK_TCC1_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_TCC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_TCC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_TC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_TC2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_TC2) >> MCLK_APBBMASK_TC2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_TC2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_TC2;
+	tmp |= value << MCLK_APBBMASK_TC2_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_TC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_TC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_TC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_TC3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_TC3) >> MCLK_APBBMASK_TC3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_TC3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_TC3;
+	tmp |= value << MCLK_APBBMASK_TC3_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_TC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_TC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_RAMECC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_RAMECC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_RAMECC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_RAMECC) >> MCLK_APBBMASK_RAMECC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_RAMECC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_RAMECC;
+	tmp |= value << MCLK_APBBMASK_RAMECC_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_RAMECC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_RAMECC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_RAMECC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_RAMECC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->APBBMASK.reg;
+}
+
+static inline void hri_mclk_set_APBCMASK_GMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_GMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_GMAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_GMAC) >> MCLK_APBCMASK_GMAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_GMAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_GMAC;
+	tmp |= value << MCLK_APBCMASK_GMAC_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_GMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_GMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_GMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_GMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TCC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TCC2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TCC2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TCC2;
+	tmp |= value << MCLK_APBCMASK_TCC2_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TCC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TCC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TCC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TCC3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TCC3) >> MCLK_APBCMASK_TCC3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TCC3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TCC3;
+	tmp |= value << MCLK_APBCMASK_TCC3_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TCC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TCC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TC4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TC4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TC4) >> MCLK_APBCMASK_TC4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TC4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TC4;
+	tmp |= value << MCLK_APBCMASK_TC4_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TC4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TC4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TC5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TC5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TC5) >> MCLK_APBCMASK_TC5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TC5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TC5;
+	tmp |= value << MCLK_APBCMASK_TC5_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TC5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TC5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_PDEC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_PDEC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_PDEC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_PDEC) >> MCLK_APBCMASK_PDEC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_PDEC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_PDEC;
+	tmp |= value << MCLK_APBCMASK_PDEC_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_PDEC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_PDEC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_PDEC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_PDEC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_AC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_AC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_AC) >> MCLK_APBCMASK_AC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_AC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_AC;
+	tmp |= value << MCLK_APBCMASK_AC_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_AC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_AC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_AES_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AES;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_AES_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_AES) >> MCLK_APBCMASK_AES_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_AES_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_AES;
+	tmp |= value << MCLK_APBCMASK_AES_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_AES_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AES;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_AES_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AES;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TRNG_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TRNG;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TRNG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TRNG) >> MCLK_APBCMASK_TRNG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TRNG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TRNG;
+	tmp |= value << MCLK_APBCMASK_TRNG_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TRNG_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TRNG;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TRNG_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TRNG;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_ICM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ICM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_ICM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_ICM) >> MCLK_APBCMASK_ICM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_ICM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_ICM;
+	tmp |= value << MCLK_APBCMASK_ICM_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_ICM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ICM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_ICM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ICM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_QSPI_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_QSPI;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_QSPI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_QSPI) >> MCLK_APBCMASK_QSPI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_QSPI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_QSPI;
+	tmp |= value << MCLK_APBCMASK_QSPI_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_QSPI_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_QSPI;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_QSPI_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_QSPI;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_CCL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_CCL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_CCL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_CCL) >> MCLK_APBCMASK_CCL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_CCL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_CCL;
+	tmp |= value << MCLK_APBCMASK_CCL_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_CCL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_CCL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_CCL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_CCL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->APBCMASK.reg;
+}
+
+static inline void hri_mclk_set_APBDMASK_SERCOM4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_SERCOM4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_SERCOM4) >> MCLK_APBDMASK_SERCOM4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_SERCOM4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_SERCOM4;
+	tmp |= value << MCLK_APBDMASK_SERCOM4_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_SERCOM4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_SERCOM4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_SERCOM5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_SERCOM5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_SERCOM5) >> MCLK_APBDMASK_SERCOM5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_SERCOM5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_SERCOM5;
+	tmp |= value << MCLK_APBDMASK_SERCOM5_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_SERCOM5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_SERCOM5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_SERCOM6_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM6;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_SERCOM6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_SERCOM6) >> MCLK_APBDMASK_SERCOM6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_SERCOM6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_SERCOM6;
+	tmp |= value << MCLK_APBDMASK_SERCOM6_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_SERCOM6_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM6;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_SERCOM6_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM6;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_SERCOM7_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM7;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_SERCOM7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_SERCOM7) >> MCLK_APBDMASK_SERCOM7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_SERCOM7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_SERCOM7;
+	tmp |= value << MCLK_APBDMASK_SERCOM7_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_SERCOM7_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM7;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_SERCOM7_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM7;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_TCC4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TCC4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_TCC4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_TCC4) >> MCLK_APBDMASK_TCC4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_TCC4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_TCC4;
+	tmp |= value << MCLK_APBDMASK_TCC4_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_TCC4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TCC4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_TCC4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TCC4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_TC6_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC6;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_TC6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_TC6) >> MCLK_APBDMASK_TC6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_TC6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_TC6;
+	tmp |= value << MCLK_APBDMASK_TC6_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_TC6_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC6;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_TC6_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC6;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_TC7_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC7;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_TC7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_TC7) >> MCLK_APBDMASK_TC7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_TC7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_TC7;
+	tmp |= value << MCLK_APBDMASK_TC7_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_TC7_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC7;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_TC7_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC7;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_ADC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_ADC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_ADC0) >> MCLK_APBDMASK_ADC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_ADC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_ADC0;
+	tmp |= value << MCLK_APBDMASK_ADC0_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_ADC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_ADC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_ADC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_ADC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_ADC1) >> MCLK_APBDMASK_ADC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_ADC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_ADC1;
+	tmp |= value << MCLK_APBDMASK_ADC1_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_ADC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_ADC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_DAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_DAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_DAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_DAC) >> MCLK_APBDMASK_DAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_DAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_DAC;
+	tmp |= value << MCLK_APBDMASK_DAC_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_DAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_DAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_DAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_DAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_I2S_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_I2S;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_I2S_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_I2S) >> MCLK_APBDMASK_I2S_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_I2S_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_I2S;
+	tmp |= value << MCLK_APBDMASK_I2S_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_I2S_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_I2S;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_I2S_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_I2S;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_PCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_PCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBDMASK_PCC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp = (tmp & MCLK_APBDMASK_PCC) >> MCLK_APBDMASK_PCC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_PCC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= ~MCLK_APBDMASK_PCC;
+	tmp |= value << MCLK_APBDMASK_PCC_Pos;
+	((Mclk *)hw)->APBDMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_PCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_PCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_PCC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_PCC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbdmask_reg_t hri_mclk_get_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBDMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBDMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbdmask_reg_t hri_mclk_read_APBDMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->APBDMASK.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_MCLK_E54_H_INCLUDED */
+#endif /* _SAME54_MCLK_COMPONENT_ */
diff --git a/hri/hri_mpu_e54.h b/hri/hri_mpu_e54.h
new file mode 100644
index 0000000..b195272
--- /dev/null
+++ b/hri/hri_mpu_e54.h
@@ -0,0 +1,518 @@
+/**
+ * \file
+ *
+ * \brief SAM MPU
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_MPU_COMPONENT_
+#ifndef _HRI_MPU_E54_H_INCLUDED_
+#define _HRI_MPU_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_MPU_CRITICAL_SECTIONS)
+#define MPU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define MPU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define MPU_CRITICAL_SECTION_ENTER()
+#define MPU_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_mpu_ctrl_reg_t;
+typedef uint32_t hri_mpu_rasr_a1_reg_t;
+typedef uint32_t hri_mpu_rasr_a2_reg_t;
+typedef uint32_t hri_mpu_rasr_a3_reg_t;
+typedef uint32_t hri_mpu_rasr_reg_t;
+typedef uint32_t hri_mpu_rbar_a1_reg_t;
+typedef uint32_t hri_mpu_rbar_a2_reg_t;
+typedef uint32_t hri_mpu_rbar_a3_reg_t;
+typedef uint32_t hri_mpu_rbar_reg_t;
+typedef uint32_t hri_mpu_rnr_reg_t;
+typedef uint32_t hri_mpu_type_reg_t;
+
+static inline bool hri_mpu_get_TYPE_SEPARATE_bit(const void *const hw)
+{
+	return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_SEPARATE) >> 0;
+}
+
+static inline hri_mpu_type_reg_t hri_mpu_get_TYPE_DREGION_bf(const void *const hw, hri_mpu_type_reg_t mask)
+{
+	return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_DREGION(mask)) >> 8;
+}
+
+static inline hri_mpu_type_reg_t hri_mpu_read_TYPE_DREGION_bf(const void *const hw)
+{
+	return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_DREGION_Msk) >> 8;
+}
+
+static inline hri_mpu_type_reg_t hri_mpu_get_TYPE_IREGION_bf(const void *const hw, hri_mpu_type_reg_t mask)
+{
+	return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_IREGION(mask)) >> 16;
+}
+
+static inline hri_mpu_type_reg_t hri_mpu_read_TYPE_IREGION_bf(const void *const hw)
+{
+	return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_IREGION_Msk) >> 16;
+}
+
+static inline hri_mpu_type_reg_t hri_mpu_get_TYPE_reg(const void *const hw, hri_mpu_type_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mpu *)hw)->TYPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mpu_type_reg_t hri_mpu_read_TYPE_reg(const void *const hw)
+{
+	return ((Mpu *)hw)->TYPE.reg;
+}
+
+static inline void hri_mpu_set_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->CTRL.reg |= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_ctrl_reg_t hri_mpu_get_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mpu *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mpu_write_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t data)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->CTRL.reg = data;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_clear_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->CTRL.reg &= ~mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_toggle_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->CTRL.reg ^= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_ctrl_reg_t hri_mpu_read_CTRL_reg(const void *const hw)
+{
+	return ((Mpu *)hw)->CTRL.reg;
+}
+
+static inline void hri_mpu_set_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RNR.reg |= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_rnr_reg_t hri_mpu_get_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mpu *)hw)->RNR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mpu_write_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t data)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RNR.reg = data;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_clear_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RNR.reg &= ~mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_toggle_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RNR.reg ^= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_rnr_reg_t hri_mpu_read_RNR_reg(const void *const hw)
+{
+	return ((Mpu *)hw)->RNR.reg;
+}
+
+static inline void hri_mpu_set_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RBAR.reg |= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_rbar_reg_t hri_mpu_get_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mpu *)hw)->RBAR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mpu_write_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t data)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RBAR.reg = data;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_clear_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RBAR.reg &= ~mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_toggle_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RBAR.reg ^= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_rbar_reg_t hri_mpu_read_RBAR_reg(const void *const hw)
+{
+	return ((Mpu *)hw)->RBAR.reg;
+}
+
+static inline void hri_mpu_set_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RASR.reg |= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_rasr_reg_t hri_mpu_get_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mpu *)hw)->RASR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mpu_write_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t data)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RASR.reg = data;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_clear_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RASR.reg &= ~mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_toggle_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RASR.reg ^= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_rasr_reg_t hri_mpu_read_RASR_reg(const void *const hw)
+{
+	return ((Mpu *)hw)->RASR.reg;
+}
+
+static inline void hri_mpu_set_RBAR_A1_reg(const void *const hw, hri_mpu_rbar_a1_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RBAR_A1.reg |= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_rbar_a1_reg_t hri_mpu_get_RBAR_A1_reg(const void *const hw, hri_mpu_rbar_a1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mpu *)hw)->RBAR_A1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mpu_write_RBAR_A1_reg(const void *const hw, hri_mpu_rbar_a1_reg_t data)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RBAR_A1.reg = data;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_clear_RBAR_A1_reg(const void *const hw, hri_mpu_rbar_a1_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RBAR_A1.reg &= ~mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_toggle_RBAR_A1_reg(const void *const hw, hri_mpu_rbar_a1_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RBAR_A1.reg ^= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_rbar_a1_reg_t hri_mpu_read_RBAR_A1_reg(const void *const hw)
+{
+	return ((Mpu *)hw)->RBAR_A1.reg;
+}
+
+static inline void hri_mpu_set_RASR_A1_reg(const void *const hw, hri_mpu_rasr_a1_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RASR_A1.reg |= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_rasr_a1_reg_t hri_mpu_get_RASR_A1_reg(const void *const hw, hri_mpu_rasr_a1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mpu *)hw)->RASR_A1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mpu_write_RASR_A1_reg(const void *const hw, hri_mpu_rasr_a1_reg_t data)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RASR_A1.reg = data;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_clear_RASR_A1_reg(const void *const hw, hri_mpu_rasr_a1_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RASR_A1.reg &= ~mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_toggle_RASR_A1_reg(const void *const hw, hri_mpu_rasr_a1_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RASR_A1.reg ^= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_rasr_a1_reg_t hri_mpu_read_RASR_A1_reg(const void *const hw)
+{
+	return ((Mpu *)hw)->RASR_A1.reg;
+}
+
+static inline void hri_mpu_set_RBAR_A2_reg(const void *const hw, hri_mpu_rbar_a2_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RBAR_A2.reg |= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_rbar_a2_reg_t hri_mpu_get_RBAR_A2_reg(const void *const hw, hri_mpu_rbar_a2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mpu *)hw)->RBAR_A2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mpu_write_RBAR_A2_reg(const void *const hw, hri_mpu_rbar_a2_reg_t data)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RBAR_A2.reg = data;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_clear_RBAR_A2_reg(const void *const hw, hri_mpu_rbar_a2_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RBAR_A2.reg &= ~mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_toggle_RBAR_A2_reg(const void *const hw, hri_mpu_rbar_a2_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RBAR_A2.reg ^= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_rbar_a2_reg_t hri_mpu_read_RBAR_A2_reg(const void *const hw)
+{
+	return ((Mpu *)hw)->RBAR_A2.reg;
+}
+
+static inline void hri_mpu_set_RASR_A2_reg(const void *const hw, hri_mpu_rasr_a2_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RASR_A2.reg |= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_rasr_a2_reg_t hri_mpu_get_RASR_A2_reg(const void *const hw, hri_mpu_rasr_a2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mpu *)hw)->RASR_A2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mpu_write_RASR_A2_reg(const void *const hw, hri_mpu_rasr_a2_reg_t data)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RASR_A2.reg = data;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_clear_RASR_A2_reg(const void *const hw, hri_mpu_rasr_a2_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RASR_A2.reg &= ~mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_toggle_RASR_A2_reg(const void *const hw, hri_mpu_rasr_a2_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RASR_A2.reg ^= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_rasr_a2_reg_t hri_mpu_read_RASR_A2_reg(const void *const hw)
+{
+	return ((Mpu *)hw)->RASR_A2.reg;
+}
+
+static inline void hri_mpu_set_RBAR_A3_reg(const void *const hw, hri_mpu_rbar_a3_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RBAR_A3.reg |= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_rbar_a3_reg_t hri_mpu_get_RBAR_A3_reg(const void *const hw, hri_mpu_rbar_a3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mpu *)hw)->RBAR_A3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mpu_write_RBAR_A3_reg(const void *const hw, hri_mpu_rbar_a3_reg_t data)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RBAR_A3.reg = data;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_clear_RBAR_A3_reg(const void *const hw, hri_mpu_rbar_a3_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RBAR_A3.reg &= ~mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_toggle_RBAR_A3_reg(const void *const hw, hri_mpu_rbar_a3_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RBAR_A3.reg ^= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_rbar_a3_reg_t hri_mpu_read_RBAR_A3_reg(const void *const hw)
+{
+	return ((Mpu *)hw)->RBAR_A3.reg;
+}
+
+static inline void hri_mpu_set_RASR_A3_reg(const void *const hw, hri_mpu_rasr_a3_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RASR_A3.reg |= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_rasr_a3_reg_t hri_mpu_get_RASR_A3_reg(const void *const hw, hri_mpu_rasr_a3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mpu *)hw)->RASR_A3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mpu_write_RASR_A3_reg(const void *const hw, hri_mpu_rasr_a3_reg_t data)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RASR_A3.reg = data;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_clear_RASR_A3_reg(const void *const hw, hri_mpu_rasr_a3_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RASR_A3.reg &= ~mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mpu_toggle_RASR_A3_reg(const void *const hw, hri_mpu_rasr_a3_reg_t mask)
+{
+	MPU_CRITICAL_SECTION_ENTER();
+	((Mpu *)hw)->RASR_A3.reg ^= mask;
+	MPU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mpu_rasr_a3_reg_t hri_mpu_read_RASR_A3_reg(const void *const hw)
+{
+	return ((Mpu *)hw)->RASR_A3.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_MPU_E54_H_INCLUDED */
+#endif /* _SAME54_MPU_COMPONENT_ */
diff --git a/hri/hri_nvic_e54.h b/hri/hri_nvic_e54.h
new file mode 100644
index 0000000..ce7d41f
--- /dev/null
+++ b/hri/hri_nvic_e54.h
@@ -0,0 +1,319 @@
+/**
+ * \file
+ *
+ * \brief SAM NVIC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_NVIC_COMPONENT_
+#ifndef _HRI_NVIC_E54_H_INCLUDED_
+#define _HRI_NVIC_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_NVIC_CRITICAL_SECTIONS)
+#define NVIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define NVIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define NVIC_CRITICAL_SECTION_ENTER()
+#define NVIC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_nvic_iabr_reg_t;
+typedef uint32_t hri_nvic_icer_reg_t;
+typedef uint32_t hri_nvic_icpr_reg_t;
+typedef uint32_t hri_nvic_iser_reg_t;
+typedef uint32_t hri_nvic_ispr_reg_t;
+typedef uint32_t hri_nvic_stir_reg_t;
+typedef uint8_t  hri_nvic_ip_reg_t;
+
+static inline void hri_nvic_set_ISER_reg(const void *const hw, uint8_t index, hri_nvic_iser_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISER[index].reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_iser_reg_t hri_nvic_get_ISER_reg(const void *const hw, uint8_t index, hri_nvic_iser_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->ISER[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_ISER_reg(const void *const hw, uint8_t index, hri_nvic_iser_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISER[index].reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_ISER_reg(const void *const hw, uint8_t index, hri_nvic_iser_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISER[index].reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_ISER_reg(const void *const hw, uint8_t index, hri_nvic_iser_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISER[index].reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_iser_reg_t hri_nvic_read_ISER_reg(const void *const hw, uint8_t index)
+{
+	return ((Nvic *)hw)->ISER[index].reg;
+}
+
+static inline void hri_nvic_set_ICER_reg(const void *const hw, uint8_t index, hri_nvic_icer_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICER[index].reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_icer_reg_t hri_nvic_get_ICER_reg(const void *const hw, uint8_t index, hri_nvic_icer_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->ICER[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_ICER_reg(const void *const hw, uint8_t index, hri_nvic_icer_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICER[index].reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_ICER_reg(const void *const hw, uint8_t index, hri_nvic_icer_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICER[index].reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_ICER_reg(const void *const hw, uint8_t index, hri_nvic_icer_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICER[index].reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_icer_reg_t hri_nvic_read_ICER_reg(const void *const hw, uint8_t index)
+{
+	return ((Nvic *)hw)->ICER[index].reg;
+}
+
+static inline void hri_nvic_set_ISPR_reg(const void *const hw, uint8_t index, hri_nvic_ispr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISPR[index].reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_ispr_reg_t hri_nvic_get_ISPR_reg(const void *const hw, uint8_t index, hri_nvic_ispr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->ISPR[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_ISPR_reg(const void *const hw, uint8_t index, hri_nvic_ispr_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISPR[index].reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_ISPR_reg(const void *const hw, uint8_t index, hri_nvic_ispr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISPR[index].reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_ISPR_reg(const void *const hw, uint8_t index, hri_nvic_ispr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISPR[index].reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_ispr_reg_t hri_nvic_read_ISPR_reg(const void *const hw, uint8_t index)
+{
+	return ((Nvic *)hw)->ISPR[index].reg;
+}
+
+static inline void hri_nvic_set_ICPR_reg(const void *const hw, uint8_t index, hri_nvic_icpr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICPR[index].reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_icpr_reg_t hri_nvic_get_ICPR_reg(const void *const hw, uint8_t index, hri_nvic_icpr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->ICPR[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_ICPR_reg(const void *const hw, uint8_t index, hri_nvic_icpr_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICPR[index].reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_ICPR_reg(const void *const hw, uint8_t index, hri_nvic_icpr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICPR[index].reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_ICPR_reg(const void *const hw, uint8_t index, hri_nvic_icpr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICPR[index].reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_icpr_reg_t hri_nvic_read_ICPR_reg(const void *const hw, uint8_t index)
+{
+	return ((Nvic *)hw)->ICPR[index].reg;
+}
+
+static inline void hri_nvic_set_IABR_reg(const void *const hw, uint8_t index, hri_nvic_iabr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->IABR[index].reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_iabr_reg_t hri_nvic_get_IABR_reg(const void *const hw, uint8_t index, hri_nvic_iabr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->IABR[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_IABR_reg(const void *const hw, uint8_t index, hri_nvic_iabr_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->IABR[index].reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_IABR_reg(const void *const hw, uint8_t index, hri_nvic_iabr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->IABR[index].reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_IABR_reg(const void *const hw, uint8_t index, hri_nvic_iabr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->IABR[index].reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_iabr_reg_t hri_nvic_read_IABR_reg(const void *const hw, uint8_t index)
+{
+	return ((Nvic *)hw)->IABR[index].reg;
+}
+
+static inline void hri_nvic_set_IP_reg(const void *const hw, uint8_t index, hri_nvic_ip_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->IP[index].reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_ip_reg_t hri_nvic_get_IP_reg(const void *const hw, uint8_t index, hri_nvic_ip_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Nvic *)hw)->IP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_IP_reg(const void *const hw, uint8_t index, hri_nvic_ip_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->IP[index].reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_IP_reg(const void *const hw, uint8_t index, hri_nvic_ip_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->IP[index].reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_IP_reg(const void *const hw, uint8_t index, hri_nvic_ip_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->IP[index].reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_ip_reg_t hri_nvic_read_IP_reg(const void *const hw, uint8_t index)
+{
+	return ((Nvic *)hw)->IP[index].reg;
+}
+
+static inline void hri_nvic_write_STIR_reg(const void *const hw, hri_nvic_stir_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->STIR.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_NVIC_E54_H_INCLUDED */
+#endif /* _SAME54_NVIC_COMPONENT_ */
diff --git a/hri/hri_nvmctrl_e54.h b/hri/hri_nvmctrl_e54.h
new file mode 100644
index 0000000..12d4022
--- /dev/null
+++ b/hri/hri_nvmctrl_e54.h
@@ -0,0 +1,1618 @@
+/**
+ * \file
+ *
+ * \brief SAM NVMCTRL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_NVMCTRL_COMPONENT_
+#ifndef _HRI_NVMCTRL_E54_H_INCLUDED_
+#define _HRI_NVMCTRL_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS)
+#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define NVMCTRL_CRITICAL_SECTION_ENTER()
+#define NVMCTRL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_nvmctrl_ctrla_reg_t;
+typedef uint16_t hri_nvmctrl_ctrlb_reg_t;
+typedef uint16_t hri_nvmctrl_intenset_reg_t;
+typedef uint16_t hri_nvmctrl_intflag_reg_t;
+typedef uint16_t hri_nvmctrl_status_reg_t;
+typedef uint32_t hri_nvmctrl_addr_reg_t;
+typedef uint32_t hri_nvmctrl_eccerr_reg_t;
+typedef uint32_t hri_nvmctrl_param_reg_t;
+typedef uint32_t hri_nvmctrl_pbldata_reg_t;
+typedef uint32_t hri_nvmctrl_runlock_reg_t;
+typedef uint32_t hri_nvmctrl_seestat_reg_t;
+typedef uint8_t  hri_nvmctrl_dbgctrl_reg_t;
+typedef uint8_t  hri_nvmctrl_seecfg_reg_t;
+
+static inline bool hri_nvmctrl_get_INTFLAG_DONE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_DONE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_ADDRE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_ADDRE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_PROGE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_PROGE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_LOCKE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_LOCKE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_ECCSE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_ECCSE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_ECCDE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_ECCDE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_NVME_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_NVME_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_SUSP_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_SUSP_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_SEESFULL_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_SEESFULL_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_SEESOVF_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_SEESOVF_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_SEEWRC_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_SEEWRC_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_DONE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_DONE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_ADDRE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_ADDRE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_PROGE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_PROGE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_LOCKE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_LOCKE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_ECCSE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_ECCSE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_ECCDE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_ECCDE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_NVME_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_NVME_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_SUSP_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_SUSP_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_SEESFULL_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_SEESFULL_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_SEESOVF_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_SEESOVF_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_SEEWRC_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_SEEWRC_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC;
+}
+
+static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const         hw,
+                                                                    hri_nvmctrl_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_nvmctrl_set_INTEN_DONE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_DONE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_DONE) >> NVMCTRL_INTENSET_DONE_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_DONE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_DONE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE;
+}
+
+static inline void hri_nvmctrl_set_INTEN_ADDRE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_ADDRE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ADDRE) >> NVMCTRL_INTENSET_ADDRE_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_ADDRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_ADDRE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE;
+}
+
+static inline void hri_nvmctrl_set_INTEN_PROGE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_PROGE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_PROGE) >> NVMCTRL_INTENSET_PROGE_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_PROGE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_PROGE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE;
+}
+
+static inline void hri_nvmctrl_set_INTEN_LOCKE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_LOCKE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_LOCKE) >> NVMCTRL_INTENSET_LOCKE_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_LOCKE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_LOCKE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE;
+}
+
+static inline void hri_nvmctrl_set_INTEN_ECCSE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_ECCSE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCSE) >> NVMCTRL_INTENSET_ECCSE_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_ECCSE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_ECCSE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE;
+}
+
+static inline void hri_nvmctrl_set_INTEN_ECCDE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_ECCDE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCDE) >> NVMCTRL_INTENSET_ECCDE_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_ECCDE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_ECCDE_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE;
+}
+
+static inline void hri_nvmctrl_set_INTEN_NVME_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_NVME_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_NVME) >> NVMCTRL_INTENSET_NVME_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_NVME_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_NVME_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME;
+}
+
+static inline void hri_nvmctrl_set_INTEN_SUSP_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_SUSP_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SUSP) >> NVMCTRL_INTENSET_SUSP_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_SUSP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_SUSP_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP;
+}
+
+static inline void hri_nvmctrl_set_INTEN_SEESFULL_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_SEESFULL_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESFULL) >> NVMCTRL_INTENSET_SEESFULL_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_SEESFULL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_SEESFULL_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL;
+}
+
+static inline void hri_nvmctrl_set_INTEN_SEESOVF_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_SEESOVF_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESOVF) >> NVMCTRL_INTENSET_SEESOVF_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_SEESOVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_SEESOVF_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF;
+}
+
+static inline void hri_nvmctrl_set_INTEN_SEEWRC_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_SEEWRC_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEEWRC) >> NVMCTRL_INTENSET_SEEWRC_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_SEEWRC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_SEEWRC_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC;
+}
+
+static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const          hw,
+                                                                   hri_nvmctrl_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->INTENSET.reg;
+}
+
+static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = data;
+	((Nvmctrl *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_nvmctrl_get_PARAM_SEE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_SEE) >> NVMCTRL_PARAM_SEE_Pos;
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos;
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos;
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos;
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos;
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->PARAM.reg;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_READY_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_READY) >> NVMCTRL_STATUS_READY_Pos;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_SUSP_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SUSP) >> NVMCTRL_STATUS_SUSP_Pos;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_AFIRST_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_AFIRST) >> NVMCTRL_STATUS_AFIRST_Pos;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_BPDIS_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BPDIS) >> NVMCTRL_STATUS_BPDIS_Pos;
+}
+
+static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_BOOTPROT_bf(const void *const        hw,
+                                                                          hri_nvmctrl_status_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT(mask)) >> NVMCTRL_STATUS_BOOTPROT_Pos;
+}
+
+static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_BOOTPROT_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT_Msk) >> NVMCTRL_STATUS_BOOTPROT_Pos;
+}
+
+static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->STATUS.reg;
+}
+
+static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_RUNLOCK_bf(const void *const         hw,
+                                                                           hri_nvmctrl_runlock_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK(mask)) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos;
+}
+
+static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_RUNLOCK_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK_Msk) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos;
+}
+
+static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_reg(const void *const         hw,
+                                                                    hri_nvmctrl_runlock_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->RUNLOCK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->RUNLOCK.reg;
+}
+
+static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_DATA_bf(const void *const hw, uint8_t index,
+                                                                        hri_nvmctrl_pbldata_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA(mask)) >> NVMCTRL_PBLDATA_DATA_Pos;
+}
+
+static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_DATA_bf(const void *const hw, uint8_t index)
+{
+	return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA_Msk) >> NVMCTRL_PBLDATA_DATA_Pos;
+}
+
+static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_reg(const void *const hw, uint8_t index,
+                                                                    hri_nvmctrl_pbldata_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PBLDATA[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_reg(const void *const hw, uint8_t index)
+{
+	return ((Nvmctrl *)hw)->PBLDATA[index].reg;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_ADDR_bf(const void *const        hw,
+                                                                      hri_nvmctrl_eccerr_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR(mask)) >> NVMCTRL_ECCERR_ADDR_Pos;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_ADDR_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR_Msk) >> NVMCTRL_ECCERR_ADDR_Pos;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEL_bf(const void *const        hw,
+                                                                       hri_nvmctrl_eccerr_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL(mask)) >> NVMCTRL_ECCERR_TYPEL_Pos;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEL_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL_Msk) >> NVMCTRL_ECCERR_TYPEL_Pos;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEH_bf(const void *const        hw,
+                                                                       hri_nvmctrl_eccerr_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH(mask)) >> NVMCTRL_ECCERR_TYPEH_Pos;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEH_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH_Msk) >> NVMCTRL_ECCERR_TYPEH_Pos;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_reg(const void *const hw, hri_nvmctrl_eccerr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ECCERR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->ECCERR.reg;
+}
+
+static inline bool hri_nvmctrl_get_SEESTAT_ASEES_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_ASEES) >> NVMCTRL_SEESTAT_ASEES_Pos;
+}
+
+static inline bool hri_nvmctrl_get_SEESTAT_LOAD_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOAD) >> NVMCTRL_SEESTAT_LOAD_Pos;
+}
+
+static inline bool hri_nvmctrl_get_SEESTAT_BUSY_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_BUSY) >> NVMCTRL_SEESTAT_BUSY_Pos;
+}
+
+static inline bool hri_nvmctrl_get_SEESTAT_LOCK_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOCK) >> NVMCTRL_SEESTAT_LOCK_Pos;
+}
+
+static inline bool hri_nvmctrl_get_SEESTAT_RLOCK_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_RLOCK) >> NVMCTRL_SEESTAT_RLOCK_Pos;
+}
+
+static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_SBLK_bf(const void *const         hw,
+                                                                        hri_nvmctrl_seestat_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK(mask)) >> NVMCTRL_SEESTAT_SBLK_Pos;
+}
+
+static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_SBLK_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK_Msk) >> NVMCTRL_SEESTAT_SBLK_Pos;
+}
+
+static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_PSZ_bf(const void *const         hw,
+                                                                       hri_nvmctrl_seestat_reg_t mask)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ(mask)) >> NVMCTRL_SEESTAT_PSZ_Pos;
+}
+
+static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_PSZ_bf(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ_Msk) >> NVMCTRL_SEESTAT_PSZ_Pos;
+}
+
+static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_reg(const void *const         hw,
+                                                                    hri_nvmctrl_seestat_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->SEESTAT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->SEESTAT.reg;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_AUTOWS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AUTOWS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLA_AUTOWS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_AUTOWS) >> NVMCTRL_CTRLA_AUTOWS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_AUTOWS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_AUTOWS;
+	tmp |= value << NVMCTRL_CTRLA_AUTOWS_Pos;
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_AUTOWS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AUTOWS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_AUTOWS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AUTOWS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLA_SUSPEN_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_SUSPEN;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLA_SUSPEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_SUSPEN) >> NVMCTRL_CTRLA_SUSPEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_SUSPEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_SUSPEN;
+	tmp |= value << NVMCTRL_CTRLA_SUSPEN_Pos;
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_SUSPEN_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_SUSPEN;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_SUSPEN_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_SUSPEN;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLA_AHBNS0_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS0;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLA_AHBNS0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_AHBNS0) >> NVMCTRL_CTRLA_AHBNS0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_AHBNS0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_AHBNS0;
+	tmp |= value << NVMCTRL_CTRLA_AHBNS0_Pos;
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_AHBNS0_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS0;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_AHBNS0_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS0;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLA_AHBNS1_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS1;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLA_AHBNS1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_AHBNS1) >> NVMCTRL_CTRLA_AHBNS1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_AHBNS1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_AHBNS1;
+	tmp |= value << NVMCTRL_CTRLA_AHBNS1_Pos;
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_AHBNS1_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS1;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_AHBNS1_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS1;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLA_CACHEDIS0_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS0;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS0) >> NVMCTRL_CTRLA_CACHEDIS0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_CACHEDIS0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_CACHEDIS0;
+	tmp |= value << NVMCTRL_CTRLA_CACHEDIS0_Pos;
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS0_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS0;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS0_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS0;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLA_CACHEDIS1_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS1;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS1) >> NVMCTRL_CTRLA_CACHEDIS1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_CACHEDIS1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_CACHEDIS1;
+	tmp |= value << NVMCTRL_CTRLA_CACHEDIS1_Pos;
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS1_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS1;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS1_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS1;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_WMODE(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_WMODE(mask)) >> NVMCTRL_CTRLA_WMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_WMODE_Msk;
+	tmp |= NVMCTRL_CTRLA_WMODE(data);
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_WMODE(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_WMODE(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_WMODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_WMODE_Msk) >> NVMCTRL_CTRLA_WMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_PRM(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_PRM(mask)) >> NVMCTRL_CTRLA_PRM_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_PRM_Msk;
+	tmp |= NVMCTRL_CTRLA_PRM(data);
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_PRM(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_PRM(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_PRM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_PRM_Msk) >> NVMCTRL_CTRLA_PRM_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_RWS(mask)) >> NVMCTRL_CTRLA_RWS_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_RWS_Msk;
+	tmp |= NVMCTRL_CTRLA_RWS(data);
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_RWS(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_RWS(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_RWS_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_RWS_Msk) >> NVMCTRL_CTRLA_RWS_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->CTRLA.reg;
+}
+
+static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp &= ~NVMCTRL_ADDR_ADDR_Msk;
+	tmp |= NVMCTRL_ADDR_ADDR(data);
+	((Nvmctrl *)hw)->ADDR.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->ADDR.reg;
+}
+
+static inline void hri_nvmctrl_set_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->DBGCTRL.reg;
+	tmp = (tmp & NVMCTRL_DBGCTRL_ECCDIS) >> NVMCTRL_DBGCTRL_ECCDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->DBGCTRL.reg;
+	tmp &= ~NVMCTRL_DBGCTRL_ECCDIS;
+	tmp |= value << NVMCTRL_DBGCTRL_ECCDIS_Pos;
+	((Nvmctrl *)hw)->DBGCTRL.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCELOG;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->DBGCTRL.reg;
+	tmp = (tmp & NVMCTRL_DBGCTRL_ECCELOG) >> NVMCTRL_DBGCTRL_ECCELOG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->DBGCTRL.reg;
+	tmp &= ~NVMCTRL_DBGCTRL_ECCELOG;
+	tmp |= value << NVMCTRL_DBGCTRL_ECCELOG_Pos;
+	((Nvmctrl *)hw)->DBGCTRL.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCELOG;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCELOG;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_get_DBGCTRL_reg(const void *const         hw,
+                                                                    hri_nvmctrl_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->DBGCTRL.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_nvmctrl_set_SEECFG_WMODE_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_WMODE;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_SEECFG_WMODE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->SEECFG.reg;
+	tmp = (tmp & NVMCTRL_SEECFG_WMODE) >> NVMCTRL_SEECFG_WMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_SEECFG_WMODE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->SEECFG.reg;
+	tmp &= ~NVMCTRL_SEECFG_WMODE;
+	tmp |= value << NVMCTRL_SEECFG_WMODE_Pos;
+	((Nvmctrl *)hw)->SEECFG.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_SEECFG_WMODE_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_WMODE;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_SEECFG_WMODE_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_WMODE;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_SEECFG_APRDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_APRDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_SEECFG_APRDIS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->SEECFG.reg;
+	tmp = (tmp & NVMCTRL_SEECFG_APRDIS) >> NVMCTRL_SEECFG_APRDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_SEECFG_APRDIS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->SEECFG.reg;
+	tmp &= ~NVMCTRL_SEECFG_APRDIS;
+	tmp |= value << NVMCTRL_SEECFG_APRDIS_Pos;
+	((Nvmctrl *)hw)->SEECFG.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_SEECFG_APRDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_APRDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_SEECFG_APRDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_APRDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_get_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->SEECFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->SEECFG.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_read_SEECFG_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->SEECFG.reg;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_NVMCTRL_E54_H_INCLUDED */
+#endif /* _SAME54_NVMCTRL_COMPONENT_ */
diff --git a/hri/hri_osc32kctrl_e54.h b/hri/hri_osc32kctrl_e54.h
new file mode 100644
index 0000000..2eabbca
--- /dev/null
+++ b/hri/hri_osc32kctrl_e54.h
@@ -0,0 +1,1199 @@
+/**
+ * \file
+ *
+ * \brief SAM OSC32KCTRL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_OSC32KCTRL_COMPONENT_
+#ifndef _HRI_OSC32KCTRL_E54_H_INCLUDED_
+#define _HRI_OSC32KCTRL_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS)
+#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define OSC32KCTRL_CRITICAL_SECTION_ENTER()
+#define OSC32KCTRL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_osc32kctrl_xosc32k_reg_t;
+typedef uint32_t hri_osc32kctrl_intenset_reg_t;
+typedef uint32_t hri_osc32kctrl_intflag_reg_t;
+typedef uint32_t hri_osc32kctrl_osculp32k_reg_t;
+typedef uint32_t hri_osc32kctrl_status_reg_t;
+typedef uint8_t  hri_osc32kctrl_cfdctrl_reg_t;
+typedef uint8_t  hri_osc32kctrl_evctrl_reg_t;
+typedef uint8_t  hri_osc32kctrl_rtcctrl_reg_t;
+
+static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY;
+}
+
+static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL;
+}
+
+static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY;
+}
+
+static inline bool hri_osc32kctrl_get_interrupt_XOSC32KFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_interrupt_XOSC32KFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL;
+}
+
+static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+}
+
+static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos;
+}
+
+static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+	} else {
+		((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+	}
+}
+
+static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+}
+
+static inline void hri_osc32kctrl_set_INTEN_XOSC32KFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL;
+}
+
+static inline bool hri_osc32kctrl_get_INTEN_XOSC32KFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KFAIL) >> OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos;
+}
+
+static inline void hri_osc32kctrl_write_INTEN_XOSC32KFAIL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL;
+	} else {
+		((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL;
+	}
+}
+
+static inline void hri_osc32kctrl_clear_INTEN_XOSC32KFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL;
+}
+
+static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const             hw,
+                                                                         hri_osc32kctrl_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->INTENSET.reg;
+}
+
+static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = data;
+	((Osc32kctrl *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask)
+{
+	((Osc32kctrl *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos;
+}
+
+static inline bool hri_osc32kctrl_get_STATUS_XOSC32KFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KFAIL) >> OSC32KCTRL_STATUS_XOSC32KFAIL_Pos;
+}
+
+static inline bool hri_osc32kctrl_get_STATUS_XOSC32KSW_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KSW) >> OSC32KCTRL_STATUS_XOSC32KSW_Pos;
+}
+
+static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const           hw,
+                                                                        hri_osc32kctrl_status_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->STATUS.reg;
+}
+
+static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const            hw,
+                                                                                hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk;
+	tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data);
+	((Osc32kctrl *)hw)->RTCCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->RTCCTRL.reg;
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_ENABLE;
+	tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_XTALEN;
+	tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_EN32K;
+	tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_EN1K;
+	tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY;
+	tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND;
+	tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK;
+	tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const            hw,
+                                                                                 hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk;
+	tmp |= OSC32KCTRL_XOSC32K_STARTUP(data);
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_CGM(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_CGM_bf(const void *const            hw,
+                                                                             hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_CGM(mask)) >> OSC32KCTRL_XOSC32K_CGM_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_CGM_Msk;
+	tmp |= OSC32KCTRL_XOSC32K_CGM(data);
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_CGM(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_CGM(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_CGM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_CGM_Msk) >> OSC32KCTRL_XOSC32K_CGM_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->XOSC32K.reg;
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDEN) >> OSC32KCTRL_CFDCTRL_CFDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_CFDEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= ~OSC32KCTRL_CFDCTRL_CFDEN;
+	tmp |= value << OSC32KCTRL_CFDCTRL_CFDEN_Pos;
+	((Osc32kctrl *)hw)->CFDCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_SWBACK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_CFDCTRL_SWBACK) >> OSC32KCTRL_CFDCTRL_SWBACK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_SWBACK_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= ~OSC32KCTRL_CFDCTRL_SWBACK;
+	tmp |= value << OSC32KCTRL_CFDCTRL_SWBACK_Pos;
+	((Osc32kctrl *)hw)->CFDCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_SWBACK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_SWBACK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDPRESC;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDPRESC) >> OSC32KCTRL_CFDCTRL_CFDPRESC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_CFDPRESC_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= ~OSC32KCTRL_CFDCTRL_CFDPRESC;
+	tmp |= value << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos;
+	((Osc32kctrl *)hw)->CFDCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDPRESC;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDPRESC;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_get_CFDCTRL_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_read_CFDCTRL_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->CFDCTRL.reg;
+}
+
+static inline void hri_osc32kctrl_set_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg |= OSC32KCTRL_EVCTRL_CFDEO;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->EVCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_EVCTRL_CFDEO) >> OSC32KCTRL_EVCTRL_CFDEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->EVCTRL.reg;
+	tmp &= ~OSC32KCTRL_EVCTRL_CFDEO;
+	tmp |= value << OSC32KCTRL_EVCTRL_CFDEO_Pos;
+	((Osc32kctrl *)hw)->EVCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg &= ~OSC32KCTRL_EVCTRL_CFDEO;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg ^= OSC32KCTRL_EVCTRL_CFDEO;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_get_EVCTRL_reg(const void *const           hw,
+                                                                        hri_osc32kctrl_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_EN32K) >> OSC32KCTRL_OSCULP32K_EN32K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_EN32K_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_EN32K;
+	tmp |= value << OSC32KCTRL_OSCULP32K_EN32K_Pos;
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_EN1K) >> OSC32KCTRL_OSCULP32K_EN1K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_EN1K_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_EN1K;
+	tmp |= value << OSC32KCTRL_OSCULP32K_EN1K_Pos;
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK;
+	tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos;
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const              hw,
+                                                                                   hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk;
+	tmp |= OSC32KCTRL_OSCULP32K_CALIB(data);
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const              hw,
+                                                                              hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->OSCULP32K.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_OSC32KCTRL_E54_H_INCLUDED */
+#endif /* _SAME54_OSC32KCTRL_COMPONENT_ */
diff --git a/hri/hri_oscctrl_e54.h b/hri/hri_oscctrl_e54.h
new file mode 100644
index 0000000..f331410
--- /dev/null
+++ b/hri/hri_oscctrl_e54.h
@@ -0,0 +1,4441 @@
+/**
+ * \file
+ *
+ * \brief SAM OSCCTRL
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_OSCCTRL_COMPONENT_
+#ifndef _HRI_OSCCTRL_E54_H_INCLUDED_
+#define _HRI_OSCCTRL_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS)
+#define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define OSCCTRL_CRITICAL_SECTION_ENTER()
+#define OSCCTRL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_oscctrl_dfllmul_reg_t;
+typedef uint32_t hri_oscctrl_dfllval_reg_t;
+typedef uint32_t hri_oscctrl_dpllctrlb_reg_t;
+typedef uint32_t hri_oscctrl_dpllratio_reg_t;
+typedef uint32_t hri_oscctrl_dpllstatus_reg_t;
+typedef uint32_t hri_oscctrl_dpllsyncbusy_reg_t;
+typedef uint32_t hri_oscctrl_intenset_reg_t;
+typedef uint32_t hri_oscctrl_intflag_reg_t;
+typedef uint32_t hri_oscctrl_status_reg_t;
+typedef uint32_t hri_oscctrl_xoscctrl_reg_t;
+typedef uint32_t hri_oscctrldpll_dpllctrlb_reg_t;
+typedef uint32_t hri_oscctrldpll_dpllratio_reg_t;
+typedef uint32_t hri_oscctrldpll_dpllstatus_reg_t;
+typedef uint32_t hri_oscctrldpll_dpllsyncbusy_reg_t;
+typedef uint8_t  hri_oscctrl_dfllctrla_reg_t;
+typedef uint8_t  hri_oscctrl_dfllctrlb_reg_t;
+typedef uint8_t  hri_oscctrl_dfllsync_reg_t;
+typedef uint8_t  hri_oscctrl_dpllctrla_reg_t;
+typedef uint8_t  hri_oscctrl_evctrl_reg_t;
+typedef uint8_t  hri_oscctrldpll_dpllctrla_reg_t;
+
+static inline void hri_oscctrldpll_wait_for_sync(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg)
+{
+	while (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_oscctrldpll_is_syncing(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg)
+{
+	return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg;
+}
+
+static inline void hri_oscctrl_wait_for_sync(const void *const hw, uint8_t submodule_index,
+                                             hri_oscctrl_dpllsyncbusy_reg_t reg)
+{
+	while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_oscctrl_is_syncing(const void *const hw, uint8_t submodule_index,
+                                          hri_oscctrl_dpllsyncbusy_reg_t reg)
+{
+	return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg;
+}
+
+static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw)
+{
+	return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO)
+	       >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos;
+}
+
+static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_get_DPLLSYNCBUSY_reg(const void *const              hw,
+                                                                                  hri_oscctrl_dpllsyncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_read_DPLLSYNCBUSY_reg(const void *const hw)
+{
+	return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg;
+}
+
+static inline bool hri_oscctrldpll_get_DPLLSTATUS_LOCK_bit(const void *const hw)
+{
+	return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos;
+}
+
+static inline bool hri_oscctrldpll_get_DPLLSTATUS_CLKRDY_bit(const void *const hw)
+{
+	return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos;
+}
+
+static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_get_DPLLSTATUS_reg(const void *const            hw,
+                                                                              hri_oscctrl_dpllstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_read_DPLLSTATUS_reg(const void *const hw)
+{
+	return ((OscctrlDpll *)hw)->DPLLSTATUS.reg;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrldpll_get_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE;
+	tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos;
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrldpll_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos;
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrldpll_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND;
+	tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos;
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg |= mask;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_get_DPLLCTRLA_reg(const void *const           hw,
+                                                                            hri_oscctrl_dpllctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg = data;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~mask;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= mask;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_read_DPLLCTRLA_reg(const void *const hw)
+{
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	return ((OscctrlDpll *)hw)->DPLLCTRLA.reg;
+}
+
+static inline void hri_oscctrldpll_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDR_bf(const void *const           hw,
+                                                                               hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk;
+	tmp |= OSCCTRL_DPLLRATIO_LDR(data);
+	((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDRFRAC_bf(const void *const           hw,
+                                                                                   hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk;
+	tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data);
+	((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDRFRAC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg |= mask;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_reg(const void *const           hw,
+                                                                            hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg = data;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~mask;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLRATIO.reg ^= mask;
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_reg(const void *const hw)
+{
+	hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	return ((OscctrlDpll *)hw)->DPLLRATIO.reg;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrldpll_get_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_WUF;
+	tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos;
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrldpll_get_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS;
+	tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos;
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrldpll_get_DPLLCTRLB_DCOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN;
+	tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos;
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_FILTER_bf(const void *const           hw,
+                                                                                  hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_FILTER(data);
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_FILTER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_REFCLK_bf(const void *const           hw,
+                                                                                  hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data);
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_REFCLK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_LTIME_bf(const void *const           hw,
+                                                                                 hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_LTIME(data);
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_LTIME_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DCOFILTER_bf(const void *const           hw,
+                                                                                     hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data);
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DIV_bf(const void *const           hw,
+                                                                               hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_DIV(data);
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DIV_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_reg(const void *const           hw,
+                                                                            hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrldpll_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrldpll_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_reg(const void *const hw)
+{
+	return ((OscctrlDpll *)hw)->DPLLCTRLB.reg;
+}
+
+static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE)
+	       >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO)
+	       >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos;
+}
+
+static inline hri_oscctrl_dpllsyncbusy_reg_t
+hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllsyncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw,
+                                                                               uint8_t           submodule_index)
+{
+	return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg;
+}
+
+static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK)
+	       >> OSCCTRL_DPLLSTATUS_LOCK_Pos;
+}
+
+static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY)
+	       >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos;
+}
+
+static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                          hri_oscctrl_dpllstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw,
+                                                                           uint8_t           submodule_index)
+{
+	return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE;
+	tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos;
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos;
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND;
+	tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos;
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= mask;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_oscctrl_dpllctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllctrla_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = data;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~mask;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= mask;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index)
+{
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg;
+}
+
+static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t
+hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_oscctrl_dpllratio_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk;
+	tmp |= OSCCTRL_DPLLRATIO_LDR(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t
+hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_oscctrl_dpllratio_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk;
+	tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= mask;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllratio_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = data;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~mask;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= mask;
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index)
+{
+	hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK);
+	return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_WUF;
+	tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos;
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS;
+	tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos;
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN;
+	tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos;
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t
+hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_FILTER(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw,
+                                                                               uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t
+hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw,
+                                                                               uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t
+hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_LTIME(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw,
+                                                                              uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t
+hri_oscctrl_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index,
+                                                             hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw,
+                                                                                  uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t
+hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_DIV(data);
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllctrlb_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL0LTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL0LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL0LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL0LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL1LTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL1LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLL1LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLL1LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO;
+}
+
+static inline bool hri_oscctrl_get_interrupt_XOSCRDY0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_XOSCRDY0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0;
+}
+
+static inline bool hri_oscctrl_get_interrupt_XOSCRDY1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_XOSCRDY1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1;
+}
+
+static inline bool hri_oscctrl_get_interrupt_XOSCFAIL0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_XOSCFAIL0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0;
+}
+
+static inline bool hri_oscctrl_get_interrupt_XOSCFAIL1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_XOSCFAIL1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL0LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL0LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL0LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL0LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL0LTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL0LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL0LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL0LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL1LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL1LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL1LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL1LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL1LTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL1LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLL1LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLL1LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO;
+}
+
+static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const         hw,
+                                                                    hri_oscctrl_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_oscctrl_set_INTEN_XOSCRDY0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0;
+}
+
+static inline bool hri_oscctrl_get_INTEN_XOSCRDY0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY0) >> OSCCTRL_INTENSET_XOSCRDY0_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_XOSCRDY0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_XOSCRDY0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0;
+}
+
+static inline void hri_oscctrl_set_INTEN_XOSCRDY1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1;
+}
+
+static inline bool hri_oscctrl_get_INTEN_XOSCRDY1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY1) >> OSCCTRL_INTENSET_XOSCRDY1_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_XOSCRDY1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_XOSCRDY1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1;
+}
+
+static inline void hri_oscctrl_set_INTEN_XOSCFAIL0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0;
+}
+
+static inline bool hri_oscctrl_get_INTEN_XOSCFAIL0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL0) >> OSCCTRL_INTENSET_XOSCFAIL0_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_XOSCFAIL0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_XOSCFAIL0_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0;
+}
+
+static inline void hri_oscctrl_set_INTEN_XOSCFAIL1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1;
+}
+
+static inline bool hri_oscctrl_get_INTEN_XOSCFAIL1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL1) >> OSCCTRL_INTENSET_XOSCFAIL1_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_XOSCFAIL1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_XOSCFAIL1_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRDY) >> OSCCTRL_INTENSET_DFLLRDY_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLOOB) >> OSCCTRL_INTENSET_DFLLOOB_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKF) >> OSCCTRL_INTENSET_DFLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKC) >> OSCCTRL_INTENSET_DFLLLCKC_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRCS) >> OSCCTRL_INTENSET_DFLLRCS_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL0LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL0LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKR) >> OSCCTRL_INTENSET_DPLL0LCKR_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL0LCKR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL0LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL0LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL0LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKF) >> OSCCTRL_INTENSET_DPLL0LCKF_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL0LCKF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL0LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL0LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL0LTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LTO) >> OSCCTRL_INTENSET_DPLL0LTO_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL0LTO_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL0LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL0LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL0LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LDRTO) >> OSCCTRL_INTENSET_DPLL0LDRTO_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL0LDRTO_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL0LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL1LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL1LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKR) >> OSCCTRL_INTENSET_DPLL1LCKR_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL1LCKR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL1LCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL1LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL1LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKF) >> OSCCTRL_INTENSET_DPLL1LCKF_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL1LCKF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL1LCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL1LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL1LTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LTO) >> OSCCTRL_INTENSET_DPLL1LTO_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL1LTO_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL1LTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLL1LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLL1LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LDRTO) >> OSCCTRL_INTENSET_DPLL1LDRTO_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLL1LDRTO_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLL1LDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO;
+}
+
+static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask)
+{
+	((Oscctrl *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const          hw,
+                                                                   hri_oscctrl_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->INTENSET.reg;
+}
+
+static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data)
+{
+	((Oscctrl *)hw)->INTENSET.reg = data;
+	((Oscctrl *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCRDY0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY0) >> OSCCTRL_STATUS_XOSCRDY0_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCRDY1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY1) >> OSCCTRL_STATUS_XOSCRDY1_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCFAIL0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL0) >> OSCCTRL_STATUS_XOSCFAIL0_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCFAIL1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL1) >> OSCCTRL_STATUS_XOSCFAIL1_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCCKSW0_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW0) >> OSCCTRL_STATUS_XOSCCKSW0_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCCKSW1_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW1) >> OSCCTRL_STATUS_XOSCCKSW1_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLOOB) >> OSCCTRL_STATUS_DFLLOOB_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKF) >> OSCCTRL_STATUS_DFLLLCKF_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKC) >> OSCCTRL_STATUS_DFLLLCKC_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRCS) >> OSCCTRL_STATUS_DFLLRCS_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL0LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKR) >> OSCCTRL_STATUS_DPLL0LCKR_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL0LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKF) >> OSCCTRL_STATUS_DPLL0LCKF_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL0TO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0TO) >> OSCCTRL_STATUS_DPLL0TO_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL0LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LDRTO) >> OSCCTRL_STATUS_DPLL0LDRTO_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL1LCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKR) >> OSCCTRL_STATUS_DPLL1LCKR_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL1LCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKF) >> OSCCTRL_STATUS_DPLL1LCKF_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL1TO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1TO) >> OSCCTRL_STATUS_DPLL1TO_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLL1LDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LDRTO) >> OSCCTRL_STATUS_DPLL1LDRTO_Pos;
+}
+
+static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->STATUS.reg;
+}
+
+static inline void hri_oscctrl_set_EVCTRL_CFDEO0_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO0;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_EVCTRL_CFDEO0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp = (tmp & OSCCTRL_EVCTRL_CFDEO0) >> OSCCTRL_EVCTRL_CFDEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_EVCTRL_CFDEO0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp &= ~OSCCTRL_EVCTRL_CFDEO0;
+	tmp |= value << OSCCTRL_EVCTRL_CFDEO0_Pos;
+	((Oscctrl *)hw)->EVCTRL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_EVCTRL_CFDEO0_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO0;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_EVCTRL_CFDEO0_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO0;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_EVCTRL_CFDEO1_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO1;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_EVCTRL_CFDEO1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp = (tmp & OSCCTRL_EVCTRL_CFDEO1) >> OSCCTRL_EVCTRL_CFDEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_EVCTRL_CFDEO1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp &= ~OSCCTRL_EVCTRL_CFDEO1;
+	tmp |= value << OSCCTRL_EVCTRL_CFDEO1_Pos;
+	((Oscctrl *)hw)->EVCTRL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_EVCTRL_CFDEO1_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO1;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_EVCTRL_CFDEO1_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO1;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_get_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_ENABLE;
+	tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_XTALEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_XTALEN;
+	tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_XTALEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_XTALEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_RUNSTDBY;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY;
+	tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ONDEMAND;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND;
+	tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ONDEMAND;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_LOWBUFGAIN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_LOWBUFGAIN) >> OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN;
+	tmp |= value << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_LOWBUFGAIN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENALC;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_ENALC) >> OSCCTRL_XOSCCTRL_ENALC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_ENALC;
+	tmp |= value << OSCCTRL_XOSCCTRL_ENALC_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENALC;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENALC;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_CFDEN) >> OSCCTRL_XOSCCTRL_CFDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_CFDEN;
+	tmp |= value << OSCCTRL_XOSCCTRL_CFDEN_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_SWBEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_SWBEN) >> OSCCTRL_XOSCCTRL_SWBEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_SWBEN;
+	tmp |= value << OSCCTRL_XOSCCTRL_SWBEN_Pos;
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_SWBEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_SWBEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index,
+                                                     hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IPTAT(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index,
+                                                                           hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT(mask)) >> OSCCTRL_XOSCCTRL_IPTAT_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index,
+                                                       hri_oscctrl_xoscctrl_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_IPTAT_Msk;
+	tmp |= OSCCTRL_XOSCCTRL_IPTAT(data);
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index,
+                                                       hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IPTAT(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index,
+                                                        hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IPTAT(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT_Msk) >> OSCCTRL_XOSCCTRL_IPTAT_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index,
+                                                     hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IMULT(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index,
+                                                                           hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT(mask)) >> OSCCTRL_XOSCCTRL_IMULT_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index,
+                                                       hri_oscctrl_xoscctrl_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_IMULT_Msk;
+	tmp |= OSCCTRL_XOSCCTRL_IMULT(data);
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index,
+                                                       hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IMULT(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index,
+                                                        hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IMULT(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT_Msk) >> OSCCTRL_XOSCCTRL_IMULT_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index,
+                                                       hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_STARTUP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index,
+                                                                             hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index,
+                                                         hri_oscctrl_xoscctrl_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk;
+	tmp |= OSCCTRL_XOSCCTRL_STARTUP(data);
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index,
+                                                         hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index,
+                                                          hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index,
+                                                        hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDPRESC(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index,
+                                                                              hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC(mask)) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index,
+                                                          hri_oscctrl_xoscctrl_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_CFDPRESC_Msk;
+	tmp |= OSCCTRL_XOSCCTRL_CFDPRESC(data);
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index,
+                                                          hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDPRESC(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index,
+                                                           hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDPRESC(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC_Msk) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const hw, uint8_t index,
+                                                                      hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL[index].reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((Oscctrl *)hw)->XOSCCTRL[index].reg;
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLA_ENABLE) >> OSCCTRL_DFLLCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLA_ENABLE;
+	tmp |= value << OSCCTRL_DFLLCTRLA_ENABLE_Pos;
+	((Oscctrl *)hw)->DFLLCTRLA.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_RUNSTDBY;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLA_RUNSTDBY) >> OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY;
+	tmp |= value << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos;
+	((Oscctrl *)hw)->DFLLCTRLA.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_RUNSTDBY;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ONDEMAND;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLA_ONDEMAND) >> OSCCTRL_DFLLCTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLA_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLA_ONDEMAND;
+	tmp |= value << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos;
+	((Oscctrl *)hw)->DFLLCTRLA.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ONDEMAND;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ONDEMAND;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_get_DFLLCTRLA_reg(const void *const           hw,
+                                                                        hri_oscctrl_dfllctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLA.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_read_DFLLCTRLA_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLCTRLA.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_MODE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_MODE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_MODE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_MODE) >> OSCCTRL_DFLLCTRLB_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_MODE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_MODE;
+	tmp |= value << OSCCTRL_DFLLCTRLB_MODE_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_MODE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_MODE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_MODE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_MODE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_STABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_STABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_STABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_STABLE) >> OSCCTRL_DFLLCTRLB_STABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_STABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_STABLE;
+	tmp |= value << OSCCTRL_DFLLCTRLB_STABLE_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_STABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_STABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_STABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_STABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_LLAW_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_LLAW;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_LLAW_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_LLAW) >> OSCCTRL_DFLLCTRLB_LLAW_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_LLAW_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_LLAW;
+	tmp |= value << OSCCTRL_DFLLCTRLB_LLAW_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_LLAW_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_LLAW;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_LLAW_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_LLAW;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_USBCRM_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_USBCRM;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_USBCRM_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_USBCRM) >> OSCCTRL_DFLLCTRLB_USBCRM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_USBCRM_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_USBCRM;
+	tmp |= value << OSCCTRL_DFLLCTRLB_USBCRM_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_USBCRM_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_USBCRM;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_USBCRM_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_USBCRM;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_CCDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_CCDIS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_CCDIS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_CCDIS) >> OSCCTRL_DFLLCTRLB_CCDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_CCDIS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_CCDIS;
+	tmp |= value << OSCCTRL_DFLLCTRLB_CCDIS_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_CCDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_CCDIS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_CCDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_CCDIS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_QLDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_QLDIS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_QLDIS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_QLDIS) >> OSCCTRL_DFLLCTRLB_QLDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_QLDIS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_QLDIS;
+	tmp |= value << OSCCTRL_DFLLCTRLB_QLDIS_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_QLDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_QLDIS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_QLDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_QLDIS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_BPLCKC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_BPLCKC;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_BPLCKC_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_BPLCKC) >> OSCCTRL_DFLLCTRLB_BPLCKC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_BPLCKC_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_BPLCKC;
+	tmp |= value << OSCCTRL_DFLLCTRLB_BPLCKC_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_BPLCKC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_BPLCKC;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_BPLCKC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_BPLCKC;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_WAITLOCK_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_WAITLOCK;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRLB_WAITLOCK_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRLB_WAITLOCK) >> OSCCTRL_DFLLCTRLB_WAITLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_WAITLOCK_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DFLLCTRLB_WAITLOCK;
+	tmp |= value << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos;
+	((Oscctrl *)hw)->DFLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_WAITLOCK_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_WAITLOCK;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_WAITLOCK_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_WAITLOCK;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_get_DFLLCTRLB_reg(const void *const           hw,
+                                                                        hri_oscctrl_dfllctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRLB.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_read_DFLLCTRLB_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLCTRLB.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_FINE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_FINE_bf(const void *const         hw,
+                                                                        hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_FINE(mask)) >> OSCCTRL_DFLLVAL_FINE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= ~OSCCTRL_DFLLVAL_FINE_Msk;
+	tmp |= OSCCTRL_DFLLVAL_FINE(data);
+	((Oscctrl *)hw)->DFLLVAL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_FINE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_FINE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_FINE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_FINE_Msk) >> OSCCTRL_DFLLVAL_FINE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_COARSE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_COARSE_bf(const void *const         hw,
+                                                                          hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_COARSE(mask)) >> OSCCTRL_DFLLVAL_COARSE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= ~OSCCTRL_DFLLVAL_COARSE_Msk;
+	tmp |= OSCCTRL_DFLLVAL_COARSE(data);
+	((Oscctrl *)hw)->DFLLVAL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_COARSE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_COARSE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_COARSE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_COARSE_Msk) >> OSCCTRL_DFLLVAL_COARSE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_DIFF(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_DIFF_bf(const void *const         hw,
+                                                                        hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_DIFF(mask)) >> OSCCTRL_DFLLVAL_DIFF_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= ~OSCCTRL_DFLLVAL_DIFF_Msk;
+	tmp |= OSCCTRL_DFLLVAL_DIFF(data);
+	((Oscctrl *)hw)->DFLLVAL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_DIFF(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_DIFF(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_DIFF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_DIFF_Msk) >> OSCCTRL_DFLLVAL_DIFF_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_reg(const void *const         hw,
+                                                                    hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLVAL.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_MUL(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_MUL_bf(const void *const         hw,
+                                                                       hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_MUL(mask)) >> OSCCTRL_DFLLMUL_MUL_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= ~OSCCTRL_DFLLMUL_MUL_Msk;
+	tmp |= OSCCTRL_DFLLMUL_MUL(data);
+	((Oscctrl *)hw)->DFLLMUL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_MUL(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_MUL(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_MUL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_MUL_Msk) >> OSCCTRL_DFLLMUL_MUL_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_FSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_FSTEP_bf(const void *const         hw,
+                                                                         hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP(mask)) >> OSCCTRL_DFLLMUL_FSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= ~OSCCTRL_DFLLMUL_FSTEP_Msk;
+	tmp |= OSCCTRL_DFLLMUL_FSTEP(data);
+	((Oscctrl *)hw)->DFLLMUL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_FSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_FSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_FSTEP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP_Msk) >> OSCCTRL_DFLLMUL_FSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_CSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_CSTEP_bf(const void *const         hw,
+                                                                         hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP(mask)) >> OSCCTRL_DFLLMUL_CSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= ~OSCCTRL_DFLLMUL_CSTEP_Msk;
+	tmp |= OSCCTRL_DFLLMUL_CSTEP(data);
+	((Oscctrl *)hw)->DFLLMUL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_CSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_CSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_CSTEP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP_Msk) >> OSCCTRL_DFLLMUL_CSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_reg(const void *const         hw,
+                                                                    hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLMUL.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLSYNC_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLSYNC_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp = (tmp & OSCCTRL_DFLLSYNC_ENABLE) >> OSCCTRL_DFLLSYNC_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLSYNC_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp &= ~OSCCTRL_DFLLSYNC_ENABLE;
+	tmp |= value << OSCCTRL_DFLLSYNC_ENABLE_Pos;
+	((Oscctrl *)hw)->DFLLSYNC.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLSYNC_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLSYNC_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_ENABLE;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLSYNC_DFLLCTRLB_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLCTRLB;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLCTRLB) >> OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLSYNC_DFLLCTRLB_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB;
+	tmp |= value << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos;
+	((Oscctrl *)hw)->DFLLSYNC.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLSYNC_DFLLCTRLB_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLCTRLB_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLCTRLB;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLSYNC_DFLLVAL_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLVAL;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLVAL) >> OSCCTRL_DFLLSYNC_DFLLVAL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLSYNC_DFLLVAL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp &= ~OSCCTRL_DFLLSYNC_DFLLVAL;
+	tmp |= value << OSCCTRL_DFLLSYNC_DFLLVAL_Pos;
+	((Oscctrl *)hw)->DFLLSYNC.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLSYNC_DFLLVAL_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLVAL;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLVAL_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLVAL;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLSYNC_DFLLMUL_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLMUL;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLMUL) >> OSCCTRL_DFLLSYNC_DFLLMUL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLSYNC_DFLLMUL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp &= ~OSCCTRL_DFLLSYNC_DFLLMUL;
+	tmp |= value << OSCCTRL_DFLLSYNC_DFLLMUL_Pos;
+	((Oscctrl *)hw)->DFLLSYNC.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLSYNC_DFLLMUL_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLMUL;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLMUL_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLMUL;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_get_DFLLSYNC_reg(const void *const          hw,
+                                                                      hri_oscctrl_dfllsync_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_read_DFLLSYNC_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLSYNC.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_OSCCTRL_E54_H_INCLUDED */
+#endif /* _SAME54_OSCCTRL_COMPONENT_ */
diff --git a/hri/hri_pac_e54.h b/hri/hri_pac_e54.h
new file mode 100644
index 0000000..8963135
--- /dev/null
+++ b/hri/hri_pac_e54.h
@@ -0,0 +1,1514 @@
+/**
+ * \file
+ *
+ * \brief SAM PAC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_PAC_COMPONENT_
+#ifndef _HRI_PAC_E54_H_INCLUDED_
+#define _HRI_PAC_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PAC_CRITICAL_SECTIONS)
+#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PAC_CRITICAL_SECTION_ENTER()
+#define PAC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_pac_intflaga_reg_t;
+typedef uint32_t hri_pac_intflagahb_reg_t;
+typedef uint32_t hri_pac_intflagb_reg_t;
+typedef uint32_t hri_pac_intflagc_reg_t;
+typedef uint32_t hri_pac_intflagd_reg_t;
+typedef uint32_t hri_pac_statusa_reg_t;
+typedef uint32_t hri_pac_statusb_reg_t;
+typedef uint32_t hri_pac_statusc_reg_t;
+typedef uint32_t hri_pac_statusd_reg_t;
+typedef uint32_t hri_pac_wrctrl_reg_t;
+typedef uint8_t  hri_pac_evctrl_reg_t;
+typedef uint8_t  hri_pac_intenset_reg_t;
+
+static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_FLASH_ALT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH_ALT) >> PAC_INTFLAGAHB_FLASH_ALT_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_FLASH_ALT_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH_ALT;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_SEEPROM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SEEPROM) >> PAC_INTFLAGAHB_SEEPROM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_SEEPROM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SEEPROM;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_RAMCM4S_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMCM4S) >> PAC_INTFLAGAHB_RAMCM4S_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_RAMCM4S_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMCM4S;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMPPPDSU) >> PAC_INTFLAGAHB_RAMPPPDSU_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMPPPDSU;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_RAMDMAWR_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMAWR) >> PAC_INTFLAGAHB_RAMDMAWR_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_RAMDMAWR_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMAWR;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_RAMDMACICM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMACICM) >> PAC_INTFLAGAHB_RAMDMACICM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_RAMDMACICM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMACICM;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HPB3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB3) >> PAC_INTFLAGAHB_HPB3_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HPB3_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB3;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_PUKCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_PUKCC) >> PAC_INTFLAGAHB_PUKCC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_PUKCC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_PUKCC;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_SDHC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC0) >> PAC_INTFLAGAHB_SDHC0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_SDHC0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC0;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_SDHC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC1) >> PAC_INTFLAGAHB_SDHC1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_SDHC1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC1;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_QSPI_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_QSPI) >> PAC_INTFLAGAHB_QSPI_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_QSPI_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_QSPI;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_BKUPRAM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_BKUPRAM) >> PAC_INTFLAGAHB_BKUPRAM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_BKUPRAM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_BKUPRAM;
+}
+
+static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGAHB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGAHB.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = mask;
+}
+
+static inline bool hri_pac_get_INTFLAGA_PAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PAC) >> PAC_INTFLAGA_PAC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_PAC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PAC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM;
+}
+
+static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK;
+}
+
+static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL;
+}
+
+static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL;
+}
+
+static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK;
+}
+
+static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT;
+}
+
+static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_FREQM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_FREQM) >> PAC_INTFLAGA_FREQM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_FREQM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_FREQM;
+}
+
+static inline bool hri_pac_get_INTFLAGA_SERCOM0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM0) >> PAC_INTFLAGA_SERCOM0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_SERCOM0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM0;
+}
+
+static inline bool hri_pac_get_INTFLAGA_SERCOM1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM1) >> PAC_INTFLAGA_SERCOM1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_SERCOM1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM1;
+}
+
+static inline bool hri_pac_get_INTFLAGA_TC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC0) >> PAC_INTFLAGA_TC0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_TC0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC0;
+}
+
+static inline bool hri_pac_get_INTFLAGA_TC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC1) >> PAC_INTFLAGA_TC1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_TC1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC1;
+}
+
+static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGA.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGA.reg = mask;
+}
+
+static inline bool hri_pac_get_INTFLAGB_USB_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_USB) >> PAC_INTFLAGB_USB_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_USB_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_USB;
+}
+
+static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU;
+}
+
+static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL;
+}
+
+static inline bool hri_pac_get_INTFLAGB_CMCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_CMCC) >> PAC_INTFLAGB_CMCC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_CMCC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_CMCC;
+}
+
+static inline bool hri_pac_get_INTFLAGB_PORT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_PORT) >> PAC_INTFLAGB_PORT_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_PORT_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_PORT;
+}
+
+static inline bool hri_pac_get_INTFLAGB_DMAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DMAC) >> PAC_INTFLAGB_DMAC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_DMAC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DMAC;
+}
+
+static inline bool hri_pac_get_INTFLAGB_HMATRIX_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_HMATRIX) >> PAC_INTFLAGB_HMATRIX_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_HMATRIX_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_HMATRIX;
+}
+
+static inline bool hri_pac_get_INTFLAGB_EVSYS_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_EVSYS) >> PAC_INTFLAGB_EVSYS_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_EVSYS_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_EVSYS;
+}
+
+static inline bool hri_pac_get_INTFLAGB_SERCOM2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM2) >> PAC_INTFLAGB_SERCOM2_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_SERCOM2_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM2;
+}
+
+static inline bool hri_pac_get_INTFLAGB_SERCOM3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM3) >> PAC_INTFLAGB_SERCOM3_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_SERCOM3_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM3;
+}
+
+static inline bool hri_pac_get_INTFLAGB_TCC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC0) >> PAC_INTFLAGB_TCC0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_TCC0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC0;
+}
+
+static inline bool hri_pac_get_INTFLAGB_TCC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC1) >> PAC_INTFLAGB_TCC1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_TCC1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC1;
+}
+
+static inline bool hri_pac_get_INTFLAGB_TC2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC2) >> PAC_INTFLAGB_TC2_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_TC2_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC2;
+}
+
+static inline bool hri_pac_get_INTFLAGB_TC3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC3) >> PAC_INTFLAGB_TC3_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_TC3_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC3;
+}
+
+static inline bool hri_pac_get_INTFLAGB_RAMECC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_RAMECC) >> PAC_INTFLAGB_RAMECC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_RAMECC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_RAMECC;
+}
+
+static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGB.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGB.reg = mask;
+}
+
+static inline bool hri_pac_get_INTFLAGC_CAN0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN0) >> PAC_INTFLAGC_CAN0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_CAN0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN0;
+}
+
+static inline bool hri_pac_get_INTFLAGC_CAN1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN1) >> PAC_INTFLAGC_CAN1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_CAN1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN1;
+}
+
+static inline bool hri_pac_get_INTFLAGC_GMAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_GMAC) >> PAC_INTFLAGC_GMAC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_GMAC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_GMAC;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TCC2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC2) >> PAC_INTFLAGC_TCC2_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TCC2_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC2;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TCC3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC3) >> PAC_INTFLAGC_TCC3_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TCC3_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC3;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TC4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC4) >> PAC_INTFLAGC_TC4_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TC4_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC4;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TC5_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC5) >> PAC_INTFLAGC_TC5_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TC5_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC5;
+}
+
+static inline bool hri_pac_get_INTFLAGC_PDEC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PDEC) >> PAC_INTFLAGC_PDEC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_PDEC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PDEC;
+}
+
+static inline bool hri_pac_get_INTFLAGC_AC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AC) >> PAC_INTFLAGC_AC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_AC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AC;
+}
+
+static inline bool hri_pac_get_INTFLAGC_AES_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AES) >> PAC_INTFLAGC_AES_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_AES_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AES;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TRNG_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TRNG) >> PAC_INTFLAGC_TRNG_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TRNG_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TRNG;
+}
+
+static inline bool hri_pac_get_INTFLAGC_ICM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ICM) >> PAC_INTFLAGC_ICM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_ICM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ICM;
+}
+
+static inline bool hri_pac_get_INTFLAGC_PUKCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PUKCC) >> PAC_INTFLAGC_PUKCC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_PUKCC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PUKCC;
+}
+
+static inline bool hri_pac_get_INTFLAGC_QSPI_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_QSPI) >> PAC_INTFLAGC_QSPI_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_QSPI_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_QSPI;
+}
+
+static inline bool hri_pac_get_INTFLAGC_CCL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CCL) >> PAC_INTFLAGC_CCL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_CCL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CCL;
+}
+
+static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGC.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGC.reg = mask;
+}
+
+static inline bool hri_pac_get_INTFLAGD_SERCOM4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM4) >> PAC_INTFLAGD_SERCOM4_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_SERCOM4_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM4;
+}
+
+static inline bool hri_pac_get_INTFLAGD_SERCOM5_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM5) >> PAC_INTFLAGD_SERCOM5_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_SERCOM5_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM5;
+}
+
+static inline bool hri_pac_get_INTFLAGD_SERCOM6_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM6) >> PAC_INTFLAGD_SERCOM6_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_SERCOM6_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM6;
+}
+
+static inline bool hri_pac_get_INTFLAGD_SERCOM7_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM7) >> PAC_INTFLAGD_SERCOM7_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_SERCOM7_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM7;
+}
+
+static inline bool hri_pac_get_INTFLAGD_TCC4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TCC4) >> PAC_INTFLAGD_TCC4_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_TCC4_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TCC4;
+}
+
+static inline bool hri_pac_get_INTFLAGD_TC6_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC6) >> PAC_INTFLAGD_TC6_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_TC6_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC6;
+}
+
+static inline bool hri_pac_get_INTFLAGD_TC7_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC7) >> PAC_INTFLAGD_TC7_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_TC7_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC7;
+}
+
+static inline bool hri_pac_get_INTFLAGD_ADC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC0) >> PAC_INTFLAGD_ADC0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_ADC0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC0;
+}
+
+static inline bool hri_pac_get_INTFLAGD_ADC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC1) >> PAC_INTFLAGD_ADC1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_ADC1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC1;
+}
+
+static inline bool hri_pac_get_INTFLAGD_DAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_DAC) >> PAC_INTFLAGD_DAC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_DAC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_DAC;
+}
+
+static inline bool hri_pac_get_INTFLAGD_I2S_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_I2S) >> PAC_INTFLAGD_I2S_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_I2S_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_I2S;
+}
+
+static inline bool hri_pac_get_INTFLAGD_PCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_PCC) >> PAC_INTFLAGD_PCC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGD_PCC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_PCC;
+}
+
+static inline hri_pac_intflagd_reg_t hri_pac_get_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflagd_reg_t hri_pac_read_INTFLAGD_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGD.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGD.reg = mask;
+}
+
+static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR;
+}
+
+static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR;
+	} else {
+		((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR;
+}
+
+static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask)
+{
+	((Pac *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pac *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTENSET.reg;
+}
+
+static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data)
+{
+	((Pac *)hw)->INTENSET.reg = data;
+	((Pac *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask)
+{
+	((Pac *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_pac_get_STATUSA_PAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PAC) >> PAC_STATUSA_PAC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_FREQM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_FREQM) >> PAC_STATUSA_FREQM_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_SERCOM0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM0) >> PAC_STATUSA_SERCOM0_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_SERCOM1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM1) >> PAC_STATUSA_SERCOM1_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_TC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC0) >> PAC_STATUSA_TC0_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_TC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC1) >> PAC_STATUSA_TC1_Pos;
+}
+
+static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->STATUSA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw)
+{
+	return ((Pac *)hw)->STATUSA.reg;
+}
+
+static inline bool hri_pac_get_STATUSB_USB_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_USB) >> PAC_STATUSB_USB_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_CMCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_CMCC) >> PAC_STATUSB_CMCC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_PORT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_PORT) >> PAC_STATUSB_PORT_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_DMAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DMAC) >> PAC_STATUSB_DMAC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_HMATRIX_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_HMATRIX) >> PAC_STATUSB_HMATRIX_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_EVSYS_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_EVSYS) >> PAC_STATUSB_EVSYS_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_SERCOM2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM2) >> PAC_STATUSB_SERCOM2_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_SERCOM3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM3) >> PAC_STATUSB_SERCOM3_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_TCC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC0) >> PAC_STATUSB_TCC0_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_TCC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC1) >> PAC_STATUSB_TCC1_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_TC2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC2) >> PAC_STATUSB_TC2_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_TC3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC3) >> PAC_STATUSB_TC3_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_RAMECC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_RAMECC) >> PAC_STATUSB_RAMECC_Pos;
+}
+
+static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->STATUSB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw)
+{
+	return ((Pac *)hw)->STATUSB.reg;
+}
+
+static inline bool hri_pac_get_STATUSC_CAN0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN0) >> PAC_STATUSC_CAN0_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_CAN1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN1) >> PAC_STATUSC_CAN1_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_GMAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_GMAC) >> PAC_STATUSC_GMAC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TCC2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC2) >> PAC_STATUSC_TCC2_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TCC3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC3) >> PAC_STATUSC_TCC3_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TC4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC4) >> PAC_STATUSC_TC4_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TC5_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC5) >> PAC_STATUSC_TC5_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_PDEC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PDEC) >> PAC_STATUSC_PDEC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_AC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AC) >> PAC_STATUSC_AC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_AES_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AES) >> PAC_STATUSC_AES_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TRNG_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TRNG) >> PAC_STATUSC_TRNG_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_ICM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ICM) >> PAC_STATUSC_ICM_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_PUKCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PUKCC) >> PAC_STATUSC_PUKCC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_QSPI_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_QSPI) >> PAC_STATUSC_QSPI_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_CCL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CCL) >> PAC_STATUSC_CCL_Pos;
+}
+
+static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->STATUSC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw)
+{
+	return ((Pac *)hw)->STATUSC.reg;
+}
+
+static inline bool hri_pac_get_STATUSD_SERCOM4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM4) >> PAC_STATUSD_SERCOM4_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_SERCOM5_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM5) >> PAC_STATUSD_SERCOM5_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_SERCOM6_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM6) >> PAC_STATUSD_SERCOM6_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_SERCOM7_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM7) >> PAC_STATUSD_SERCOM7_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_TCC4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TCC4) >> PAC_STATUSD_TCC4_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_TC6_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC6) >> PAC_STATUSD_TC6_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_TC7_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC7) >> PAC_STATUSD_TC7_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_ADC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC0) >> PAC_STATUSD_ADC0_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_ADC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC1) >> PAC_STATUSD_ADC1_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_DAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_DAC) >> PAC_STATUSD_DAC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_I2S_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_I2S) >> PAC_STATUSD_I2S_Pos;
+}
+
+static inline bool hri_pac_get_STATUSD_PCC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_PCC) >> PAC_STATUSD_PCC_Pos;
+}
+
+static inline hri_pac_statusd_reg_t hri_pac_get_STATUSD_reg(const void *const hw, hri_pac_statusd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->STATUSD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_statusd_reg_t hri_pac_read_STATUSD_reg(const void *const hw)
+{
+	return ((Pac *)hw)->STATUSD.reg;
+}
+
+static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data)
+{
+	uint32_t tmp;
+	PAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp &= ~PAC_WRCTRL_PERID_Msk;
+	tmp |= PAC_WRCTRL_PERID(data);
+	((Pac *)hw)->WRCTRL.reg = tmp;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data)
+{
+	uint32_t tmp;
+	PAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp &= ~PAC_WRCTRL_KEY_Msk;
+	tmp |= PAC_WRCTRL_KEY(data);
+	((Pac *)hw)->WRCTRL.reg = tmp;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg |= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg = data;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg &= ~mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg ^= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw)
+{
+	return ((Pac *)hw)->WRCTRL.reg;
+}
+
+static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pac *)hw)->EVCTRL.reg;
+	tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	PAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pac *)hw)->EVCTRL.reg;
+	tmp &= ~PAC_EVCTRL_ERREO;
+	tmp |= value << PAC_EVCTRL_ERREO_Pos;
+	((Pac *)hw)->EVCTRL.reg = tmp;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg |= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pac *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg = data;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg &= ~mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg ^= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Pac *)hw)->EVCTRL.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PAC_E54_H_INCLUDED */
+#endif /* _SAME54_PAC_COMPONENT_ */
diff --git a/hri/hri_pcc_e54.h b/hri/hri_pcc_e54.h
new file mode 100644
index 0000000..42a5600
--- /dev/null
+++ b/hri/hri_pcc_e54.h
@@ -0,0 +1,298 @@
+/**
+ * \file
+ *
+ * \brief SAM PCC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_PCC_COMPONENT_
+#ifndef _HRI_PCC_E54_H_INCLUDED_
+#define _HRI_PCC_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PCC_CRITICAL_SECTIONS)
+#define PCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PCC_CRITICAL_SECTION_ENTER()
+#define PCC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_pcc_imr_reg_t;
+typedef uint32_t hri_pcc_isr_reg_t;
+typedef uint32_t hri_pcc_mr_reg_t;
+typedef uint32_t hri_pcc_rhr_reg_t;
+typedef uint32_t hri_pcc_wpmr_reg_t;
+typedef uint32_t hri_pcc_wpsr_reg_t;
+
+static inline void hri_pcc_set_IMR_DRDY_bit(const void *const hw)
+{
+	((Pcc *)hw)->IER.reg = PCC_IMR_DRDY;
+}
+
+static inline bool hri_pcc_get_IMR_DRDY_bit(const void *const hw)
+{
+	return (((Pcc *)hw)->IMR.reg & PCC_IMR_DRDY) >> PCC_IMR_DRDY_Pos;
+}
+
+static inline void hri_pcc_write_IMR_DRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY;
+	} else {
+		((Pcc *)hw)->IER.reg = PCC_IMR_DRDY;
+	}
+}
+
+static inline void hri_pcc_clear_IMR_DRDY_bit(const void *const hw)
+{
+	((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY;
+}
+
+static inline void hri_pcc_set_IMR_OVRE_bit(const void *const hw)
+{
+	((Pcc *)hw)->IER.reg = PCC_IMR_OVRE;
+}
+
+static inline bool hri_pcc_get_IMR_OVRE_bit(const void *const hw)
+{
+	return (((Pcc *)hw)->IMR.reg & PCC_IMR_OVRE) >> PCC_IMR_OVRE_Pos;
+}
+
+static inline void hri_pcc_write_IMR_OVRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE;
+	} else {
+		((Pcc *)hw)->IER.reg = PCC_IMR_OVRE;
+	}
+}
+
+static inline void hri_pcc_clear_IMR_OVRE_bit(const void *const hw)
+{
+	((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE;
+}
+
+static inline void hri_pcc_set_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask)
+{
+	((Pcc *)hw)->IER.reg = mask;
+}
+
+static inline hri_pcc_imr_reg_t hri_pcc_get_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pcc *)hw)->IMR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pcc_imr_reg_t hri_pcc_read_IMR_reg(const void *const hw)
+{
+	return ((Pcc *)hw)->IMR.reg;
+}
+
+static inline void hri_pcc_write_IMR_reg(const void *const hw, hri_pcc_imr_reg_t data)
+{
+	((Pcc *)hw)->IER.reg = data;
+	((Pcc *)hw)->IDR.reg = ~data;
+}
+
+static inline void hri_pcc_clear_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask)
+{
+	((Pcc *)hw)->IDR.reg = mask;
+}
+
+static inline bool hri_pcc_get_ISR_DRDY_bit(const void *const hw)
+{
+	return (((Pcc *)hw)->ISR.reg & PCC_ISR_DRDY) >> PCC_ISR_DRDY_Pos;
+}
+
+static inline bool hri_pcc_get_ISR_OVRE_bit(const void *const hw)
+{
+	return (((Pcc *)hw)->ISR.reg & PCC_ISR_OVRE) >> PCC_ISR_OVRE_Pos;
+}
+
+static inline hri_pcc_isr_reg_t hri_pcc_get_ISR_reg(const void *const hw, hri_pcc_isr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pcc *)hw)->ISR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pcc_isr_reg_t hri_pcc_read_ISR_reg(const void *const hw)
+{
+	return ((Pcc *)hw)->ISR.reg;
+}
+
+static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_RDATA_bf(const void *const hw, hri_pcc_rhr_reg_t mask)
+{
+	return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA(mask)) >> PCC_RHR_RDATA_Pos;
+}
+
+static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_RDATA_bf(const void *const hw)
+{
+	return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA_Msk) >> PCC_RHR_RDATA_Pos;
+}
+
+static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_reg(const void *const hw, hri_pcc_rhr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pcc *)hw)->RHR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_reg(const void *const hw)
+{
+	return ((Pcc *)hw)->RHR.reg;
+}
+
+static inline bool hri_pcc_get_WPSR_WPVS_bit(const void *const hw)
+{
+	return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVS) >> PCC_WPSR_WPVS_Pos;
+}
+
+static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_WPVSRC_bf(const void *const hw, hri_pcc_wpsr_reg_t mask)
+{
+	return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC(mask)) >> PCC_WPSR_WPVSRC_Pos;
+}
+
+static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_WPVSRC_bf(const void *const hw)
+{
+	return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC_Msk) >> PCC_WPSR_WPVSRC_Pos;
+}
+
+static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_reg(const void *const hw, hri_pcc_wpsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pcc *)hw)->WPSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_reg(const void *const hw)
+{
+	return ((Pcc *)hw)->WPSR.reg;
+}
+
+static inline void hri_pcc_set_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->MR.reg |= mask;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pcc_mr_reg_t hri_pcc_get_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pcc *)hw)->MR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pcc_write_MR_reg(const void *const hw, hri_pcc_mr_reg_t data)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->MR.reg = data;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pcc_clear_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->MR.reg &= ~mask;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pcc_toggle_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->MR.reg ^= mask;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pcc_mr_reg_t hri_pcc_read_MR_reg(const void *const hw)
+{
+	return ((Pcc *)hw)->MR.reg;
+}
+
+static inline void hri_pcc_set_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->WPMR.reg |= mask;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pcc_wpmr_reg_t hri_pcc_get_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pcc *)hw)->WPMR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pcc_write_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t data)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->WPMR.reg = data;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pcc_clear_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->WPMR.reg &= ~mask;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pcc_toggle_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask)
+{
+	PCC_CRITICAL_SECTION_ENTER();
+	((Pcc *)hw)->WPMR.reg ^= mask;
+	PCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pcc_wpmr_reg_t hri_pcc_read_WPMR_reg(const void *const hw)
+{
+	return ((Pcc *)hw)->WPMR.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PCC_E54_H_INCLUDED */
+#endif /* _SAME54_PCC_COMPONENT_ */
diff --git a/hri/hri_pdec_e54.h b/hri/hri_pdec_e54.h
new file mode 100644
index 0000000..ec7ce30
--- /dev/null
+++ b/hri/hri_pdec_e54.h
@@ -0,0 +1,2684 @@
+/**
+ * \file
+ *
+ * \brief SAM PDEC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_PDEC_COMPONENT_
+#ifndef _HRI_PDEC_E54_H_INCLUDED_
+#define _HRI_PDEC_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PDEC_CRITICAL_SECTIONS)
+#define PDEC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PDEC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PDEC_CRITICAL_SECTION_ENTER()
+#define PDEC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_pdec_evctrl_reg_t;
+typedef uint16_t hri_pdec_status_reg_t;
+typedef uint32_t hri_pdec_cc_reg_t;
+typedef uint32_t hri_pdec_ccbuf_reg_t;
+typedef uint32_t hri_pdec_count_reg_t;
+typedef uint32_t hri_pdec_ctrla_reg_t;
+typedef uint32_t hri_pdec_syncbusy_reg_t;
+typedef uint8_t  hri_pdec_ctrlbset_reg_t;
+typedef uint8_t  hri_pdec_dbgctrl_reg_t;
+typedef uint8_t  hri_pdec_filter_reg_t;
+typedef uint8_t  hri_pdec_filterbuf_reg_t;
+typedef uint8_t  hri_pdec_intenset_reg_t;
+typedef uint8_t  hri_pdec_intflag_reg_t;
+typedef uint8_t  hri_pdec_presc_reg_t;
+typedef uint8_t  hri_pdec_prescbuf_reg_t;
+
+static inline void hri_pdec_wait_for_sync(const void *const hw, hri_pdec_syncbusy_reg_t reg)
+{
+	while (((Pdec *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_pdec_is_syncing(const void *const hw, hri_pdec_syncbusy_reg_t reg)
+{
+	return ((Pdec *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_pdec_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_pdec_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF;
+}
+
+static inline bool hri_pdec_get_INTFLAG_ERR_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_pdec_clear_INTFLAG_ERR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR;
+}
+
+static inline bool hri_pdec_get_INTFLAG_DIR_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos;
+}
+
+static inline void hri_pdec_clear_INTFLAG_DIR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR;
+}
+
+static inline bool hri_pdec_get_INTFLAG_VLC_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos;
+}
+
+static inline void hri_pdec_clear_INTFLAG_VLC_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC;
+}
+
+static inline bool hri_pdec_get_INTFLAG_MC0_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_pdec_clear_INTFLAG_MC0_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0;
+}
+
+static inline bool hri_pdec_get_INTFLAG_MC1_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_pdec_clear_INTFLAG_MC1_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1;
+}
+
+static inline bool hri_pdec_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_pdec_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF;
+}
+
+static inline bool hri_pdec_get_interrupt_ERR_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_pdec_clear_interrupt_ERR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR;
+}
+
+static inline bool hri_pdec_get_interrupt_DIR_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos;
+}
+
+static inline void hri_pdec_clear_interrupt_DIR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR;
+}
+
+static inline bool hri_pdec_get_interrupt_VLC_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos;
+}
+
+static inline void hri_pdec_clear_interrupt_VLC_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC;
+}
+
+static inline bool hri_pdec_get_interrupt_MC0_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_pdec_clear_interrupt_MC0_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0;
+}
+
+static inline bool hri_pdec_get_interrupt_MC1_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_pdec_clear_interrupt_MC1_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1;
+}
+
+static inline hri_pdec_intflag_reg_t hri_pdec_get_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pdec_intflag_reg_t hri_pdec_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Pdec *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_pdec_clear_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask)
+{
+	((Pdec *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_pdec_set_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD;
+}
+
+static inline bool hri_pdec_get_CTRLB_LUPD_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->CTRLBSET.reg & PDEC_CTRLBSET_LUPD) >> PDEC_CTRLBSET_LUPD_Pos;
+}
+
+static inline void hri_pdec_write_CTRLB_LUPD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD;
+	} else {
+		((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD;
+	}
+}
+
+static inline void hri_pdec_clear_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD;
+}
+
+static inline void hri_pdec_set_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask)
+{
+	((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(mask);
+}
+
+static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->CTRLBSET.reg;
+	tmp = (tmp & PDEC_CTRLBSET_CMD(mask)) >> PDEC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->CTRLBSET.reg;
+	tmp = (tmp & PDEC_CTRLBSET_CMD_Msk) >> PDEC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t data)
+{
+	((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(data);
+	((Pdec *)hw)->CTRLBCLR.reg = ~PDEC_CTRLBSET_CMD(data);
+}
+
+static inline void hri_pdec_clear_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask)
+{
+	((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_CMD(mask);
+}
+
+static inline void hri_pdec_set_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask)
+{
+	((Pdec *)hw)->CTRLBSET.reg = mask;
+}
+
+static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->CTRLBSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_reg(const void *const hw)
+{
+	return ((Pdec *)hw)->CTRLBSET.reg;
+}
+
+static inline void hri_pdec_write_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t data)
+{
+	((Pdec *)hw)->CTRLBSET.reg = data;
+	((Pdec *)hw)->CTRLBCLR.reg = ~data;
+}
+
+static inline void hri_pdec_clear_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask)
+{
+	((Pdec *)hw)->CTRLBCLR.reg = mask;
+}
+
+static inline void hri_pdec_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF;
+}
+
+static inline bool hri_pdec_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_OVF) >> PDEC_INTENSET_OVF_Pos;
+}
+
+static inline void hri_pdec_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF;
+	} else {
+		((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF;
+	}
+}
+
+static inline void hri_pdec_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF;
+}
+
+static inline void hri_pdec_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR;
+}
+
+static inline bool hri_pdec_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_ERR) >> PDEC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_pdec_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR;
+	} else {
+		((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_pdec_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR;
+}
+
+static inline void hri_pdec_set_INTEN_DIR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR;
+}
+
+static inline bool hri_pdec_get_INTEN_DIR_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_DIR) >> PDEC_INTENSET_DIR_Pos;
+}
+
+static inline void hri_pdec_write_INTEN_DIR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR;
+	} else {
+		((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR;
+	}
+}
+
+static inline void hri_pdec_clear_INTEN_DIR_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR;
+}
+
+static inline void hri_pdec_set_INTEN_VLC_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC;
+}
+
+static inline bool hri_pdec_get_INTEN_VLC_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_VLC) >> PDEC_INTENSET_VLC_Pos;
+}
+
+static inline void hri_pdec_write_INTEN_VLC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC;
+	} else {
+		((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC;
+	}
+}
+
+static inline void hri_pdec_clear_INTEN_VLC_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC;
+}
+
+static inline void hri_pdec_set_INTEN_MC0_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0;
+}
+
+static inline bool hri_pdec_get_INTEN_MC0_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC0) >> PDEC_INTENSET_MC0_Pos;
+}
+
+static inline void hri_pdec_write_INTEN_MC0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0;
+	} else {
+		((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0;
+	}
+}
+
+static inline void hri_pdec_clear_INTEN_MC0_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0;
+}
+
+static inline void hri_pdec_set_INTEN_MC1_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1;
+}
+
+static inline bool hri_pdec_get_INTEN_MC1_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC1) >> PDEC_INTENSET_MC1_Pos;
+}
+
+static inline void hri_pdec_write_INTEN_MC1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1;
+	} else {
+		((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1;
+	}
+}
+
+static inline void hri_pdec_clear_INTEN_MC1_bit(const void *const hw)
+{
+	((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1;
+}
+
+static inline void hri_pdec_set_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask)
+{
+	((Pdec *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_pdec_intenset_reg_t hri_pdec_get_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pdec_intenset_reg_t hri_pdec_read_INTEN_reg(const void *const hw)
+{
+	return ((Pdec *)hw)->INTENSET.reg;
+}
+
+static inline void hri_pdec_write_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t data)
+{
+	((Pdec *)hw)->INTENSET.reg = data;
+	((Pdec *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_pdec_clear_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask)
+{
+	((Pdec *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_SWRST) >> PDEC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_ENABLE) >> PDEC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CTRLB) >> PDEC_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_STATUS_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_STATUS) >> PDEC_SYNCBUSY_STATUS_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_PRESC_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_PRESC) >> PDEC_SYNCBUSY_PRESC_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_FILTER_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_FILTER) >> PDEC_SYNCBUSY_FILTER_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_COUNT) >> PDEC_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_CC0_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC0) >> PDEC_SYNCBUSY_CC0_Pos;
+}
+
+static inline bool hri_pdec_get_SYNCBUSY_CC1_bit(const void *const hw)
+{
+	return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC1) >> PDEC_SYNCBUSY_CC1_Pos;
+}
+
+static inline hri_pdec_syncbusy_reg_t hri_pdec_get_SYNCBUSY_reg(const void *const hw, hri_pdec_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pdec_syncbusy_reg_t hri_pdec_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Pdec *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_pdec_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWRST;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST);
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_SWRST) >> PDEC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ENABLE;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_ENABLE) >> PDEC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_ENABLE;
+	tmp |= value << PDEC_CTRLA_ENABLE_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ENABLE;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ENABLE;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_RUNSTDBY;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_RUNSTDBY) >> PDEC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_RUNSTDBY;
+	tmp |= value << PDEC_CTRLA_RUNSTDBY_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_RUNSTDBY;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_RUNSTDBY;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_ALOCK_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ALOCK;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_ALOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_ALOCK) >> PDEC_CTRLA_ALOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_ALOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_ALOCK;
+	tmp |= value << PDEC_CTRLA_ALOCK_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_ALOCK_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ALOCK;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_ALOCK_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ALOCK;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_SWAP_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWAP;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_SWAP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_SWAP) >> PDEC_CTRLA_SWAP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_SWAP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_SWAP;
+	tmp |= value << PDEC_CTRLA_SWAP_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_SWAP_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_SWAP;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_SWAP_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_SWAP;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PEREN_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PEREN;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PEREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PEREN) >> PDEC_CTRLA_PEREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PEREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PEREN;
+	tmp |= value << PDEC_CTRLA_PEREN_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PEREN_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PEREN;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PEREN_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PEREN;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PINEN0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PINEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PINEN0) >> PDEC_CTRLA_PINEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PINEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PINEN0;
+	tmp |= value << PDEC_CTRLA_PINEN0_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PINEN0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PINEN0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PINEN1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PINEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PINEN1) >> PDEC_CTRLA_PINEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PINEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PINEN1;
+	tmp |= value << PDEC_CTRLA_PINEN1_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PINEN1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PINEN1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PINEN2_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN2;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PINEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PINEN2) >> PDEC_CTRLA_PINEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PINEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PINEN2;
+	tmp |= value << PDEC_CTRLA_PINEN2_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PINEN2_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN2;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PINEN2_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN2;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PINVEN0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PINVEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PINVEN0) >> PDEC_CTRLA_PINVEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PINVEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PINVEN0;
+	tmp |= value << PDEC_CTRLA_PINVEN0_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PINVEN0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PINVEN0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PINVEN1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PINVEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PINVEN1) >> PDEC_CTRLA_PINVEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PINVEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PINVEN1;
+	tmp |= value << PDEC_CTRLA_PINVEN1_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PINVEN1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PINVEN1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_PINVEN2_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN2;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_CTRLA_PINVEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_PINVEN2) >> PDEC_CTRLA_PINVEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_PINVEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_PINVEN2;
+	tmp |= value << PDEC_CTRLA_PINVEN2_Pos;
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_PINVEN2_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN2;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_PINVEN2_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN2;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MODE(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_MODE(mask)) >> PDEC_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_MODE_Msk;
+	tmp |= PDEC_CTRLA_MODE(data);
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MODE(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MODE(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_MODE_Msk) >> PDEC_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_CONF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_CONF(mask)) >> PDEC_CTRLA_CONF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_CONF_Msk;
+	tmp |= PDEC_CTRLA_CONF(data);
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_CONF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_CONF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_CONF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_CONF_Msk) >> PDEC_CTRLA_CONF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ANGULAR(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_ANGULAR(mask)) >> PDEC_CTRLA_ANGULAR_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_ANGULAR_Msk;
+	tmp |= PDEC_CTRLA_ANGULAR(data);
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ANGULAR(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ANGULAR(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_ANGULAR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_ANGULAR_Msk) >> PDEC_CTRLA_ANGULAR_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MAXCMP(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_MAXCMP(mask)) >> PDEC_CTRLA_MAXCMP_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= ~PDEC_CTRLA_MAXCMP_Msk;
+	tmp |= PDEC_CTRLA_MAXCMP(data);
+	((Pdec *)hw)->CTRLA.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MAXCMP(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MAXCMP(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MAXCMP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp = (tmp & PDEC_CTRLA_MAXCMP_Msk) >> PDEC_CTRLA_MAXCMP_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	tmp = ((Pdec *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CTRLA.reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE);
+	return ((Pdec *)hw)->CTRLA.reg;
+}
+
+static inline void hri_pdec_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_OVFEO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_OVFEO) >> PDEC_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_OVFEO;
+	tmp |= value << PDEC_EVCTRL_OVFEO_Pos;
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_OVFEO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_OVFEO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_ERREO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_EVCTRL_ERREO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_ERREO) >> PDEC_EVCTRL_ERREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_ERREO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_ERREO;
+	tmp |= value << PDEC_EVCTRL_ERREO_Pos;
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_ERREO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_ERREO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_EVCTRL_DIREO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_DIREO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_EVCTRL_DIREO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_DIREO) >> PDEC_EVCTRL_DIREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_DIREO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_DIREO;
+	tmp |= value << PDEC_EVCTRL_DIREO_Pos;
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_DIREO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_DIREO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_DIREO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_DIREO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_EVCTRL_VLCEO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_VLCEO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_EVCTRL_VLCEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_VLCEO) >> PDEC_EVCTRL_VLCEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_VLCEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_VLCEO;
+	tmp |= value << PDEC_EVCTRL_VLCEO_Pos;
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_VLCEO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_VLCEO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_VLCEO_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_VLCEO;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO0;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_MCEO0) >> PDEC_EVCTRL_MCEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_MCEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_MCEO0;
+	tmp |= value << PDEC_EVCTRL_MCEO0_Pos;
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO0;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO0;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO1;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_MCEO1) >> PDEC_EVCTRL_MCEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_MCEO1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_MCEO1;
+	tmp |= value << PDEC_EVCTRL_MCEO1_Pos;
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO1;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO1;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVACT(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_EVACT(mask)) >> PDEC_EVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t data)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_EVACT_Msk;
+	tmp |= PDEC_EVCTRL_EVACT(data);
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVACT(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVACT(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVACT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_EVACT_Msk) >> PDEC_EVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVINV(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_EVINV(mask)) >> PDEC_EVCTRL_EVINV_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t data)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_EVINV_Msk;
+	tmp |= PDEC_EVCTRL_EVINV(data);
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVINV(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVINV(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVINV_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_EVINV_Msk) >> PDEC_EVCTRL_EVINV_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVEI(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_EVEI(mask)) >> PDEC_EVCTRL_EVEI_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t data)
+{
+	uint16_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= ~PDEC_EVCTRL_EVEI_Msk;
+	tmp |= PDEC_EVCTRL_EVEI(data);
+	((Pdec *)hw)->EVCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVEI(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVEI(mask);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVEI_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp = (tmp & PDEC_EVCTRL_EVEI_Msk) >> PDEC_EVCTRL_EVEI_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg |= mask;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Pdec *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg = data;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg &= ~mask;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->EVCTRL.reg ^= mask;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Pdec *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_pdec_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg |= PDEC_DBGCTRL_DBGRUN;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->DBGCTRL.reg;
+	tmp = (tmp & PDEC_DBGCTRL_DBGRUN) >> PDEC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pdec_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->DBGCTRL.reg;
+	tmp &= ~PDEC_DBGCTRL_DBGRUN;
+	tmp |= value << PDEC_DBGCTRL_DBGRUN_Pos;
+	((Pdec *)hw)->DBGCTRL.reg = tmp;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg &= ~PDEC_DBGCTRL_DBGRUN;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg ^= PDEC_DBGCTRL_DBGRUN;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_set_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg |= mask;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_dbgctrl_reg_t hri_pdec_get_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg = data;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg &= ~mask;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->DBGCTRL.reg ^= mask;
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_dbgctrl_reg_t hri_pdec_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Pdec *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_pdec_set_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg |= PDEC_PRESC_PRESC(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	tmp = ((Pdec *)hw)->PRESC.reg;
+	tmp = (tmp & PDEC_PRESC_PRESC(mask)) >> PDEC_PRESC_PRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t data)
+{
+	uint8_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->PRESC.reg;
+	tmp &= ~PDEC_PRESC_PRESC_Msk;
+	tmp |= PDEC_PRESC_PRESC(data);
+	((Pdec *)hw)->PRESC.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg &= ~PDEC_PRESC_PRESC(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg ^= PDEC_PRESC_PRESC(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_PRESC_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	tmp = ((Pdec *)hw)->PRESC.reg;
+	tmp = (tmp & PDEC_PRESC_PRESC_Msk) >> PDEC_PRESC_PRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	tmp = ((Pdec *)hw)->PRESC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESC.reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC);
+	return ((Pdec *)hw)->PRESC.reg;
+}
+
+static inline void hri_pdec_set_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg |= PDEC_FILTER_FILTER(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	tmp = ((Pdec *)hw)->FILTER.reg;
+	tmp = (tmp & PDEC_FILTER_FILTER(mask)) >> PDEC_FILTER_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t data)
+{
+	uint8_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->FILTER.reg;
+	tmp &= ~PDEC_FILTER_FILTER_Msk;
+	tmp |= PDEC_FILTER_FILTER(data);
+	((Pdec *)hw)->FILTER.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg &= ~PDEC_FILTER_FILTER(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg ^= PDEC_FILTER_FILTER(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_FILTER_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	tmp = ((Pdec *)hw)->FILTER.reg;
+	tmp = (tmp & PDEC_FILTER_FILTER_Msk) >> PDEC_FILTER_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	tmp = ((Pdec *)hw)->FILTER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTER.reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER);
+	return ((Pdec *)hw)->FILTER.reg;
+}
+
+static inline void hri_pdec_set_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg |= PDEC_PRESCBUF_PRESCBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_PRESCBUF_bf(const void *const       hw,
+                                                                        hri_pdec_prescbuf_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->PRESCBUF.reg;
+	tmp = (tmp & PDEC_PRESCBUF_PRESCBUF(mask)) >> PDEC_PRESCBUF_PRESCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t data)
+{
+	uint8_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->PRESCBUF.reg;
+	tmp &= ~PDEC_PRESCBUF_PRESCBUF_Msk;
+	tmp |= PDEC_PRESCBUF_PRESCBUF(data);
+	((Pdec *)hw)->PRESCBUF.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg &= ~PDEC_PRESCBUF_PRESCBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg ^= PDEC_PRESCBUF_PRESCBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_PRESCBUF_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->PRESCBUF.reg;
+	tmp = (tmp & PDEC_PRESCBUF_PRESCBUF_Msk) >> PDEC_PRESCBUF_PRESCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	tmp = ((Pdec *)hw)->PRESCBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->PRESCBUF.reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return ((Pdec *)hw)->PRESCBUF.reg;
+}
+
+static inline void hri_pdec_set_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg |= PDEC_FILTERBUF_FILTERBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_FILTERBUF_bf(const void *const        hw,
+                                                                           hri_pdec_filterbuf_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->FILTERBUF.reg;
+	tmp = (tmp & PDEC_FILTERBUF_FILTERBUF(mask)) >> PDEC_FILTERBUF_FILTERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t data)
+{
+	uint8_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->FILTERBUF.reg;
+	tmp &= ~PDEC_FILTERBUF_FILTERBUF_Msk;
+	tmp |= PDEC_FILTERBUF_FILTERBUF(data);
+	((Pdec *)hw)->FILTERBUF.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg &= ~PDEC_FILTERBUF_FILTERBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg ^= PDEC_FILTERBUF_FILTERBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_FILTERBUF_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pdec *)hw)->FILTERBUF.reg;
+	tmp = (tmp & PDEC_FILTERBUF_FILTERBUF_Msk) >> PDEC_FILTERBUF_FILTERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	uint8_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	tmp = ((Pdec *)hw)->FILTERBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->FILTERBUF.reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return ((Pdec *)hw)->FILTERBUF.reg;
+}
+
+static inline void hri_pdec_set_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg |= PDEC_COUNT_COUNT(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	tmp = ((Pdec *)hw)->COUNT.reg;
+	tmp = (tmp & PDEC_COUNT_COUNT(mask)) >> PDEC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->COUNT.reg;
+	tmp &= ~PDEC_COUNT_COUNT_Msk;
+	tmp |= PDEC_COUNT_COUNT(data);
+	((Pdec *)hw)->COUNT.reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg &= ~PDEC_COUNT_COUNT(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg ^= PDEC_COUNT_COUNT(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	tmp = ((Pdec *)hw)->COUNT.reg;
+	tmp = (tmp & PDEC_COUNT_COUNT_Msk) >> PDEC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	tmp = ((Pdec *)hw)->COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_COUNT_reg(const void *const hw, hri_pdec_count_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->COUNT.reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT);
+	return ((Pdec *)hw)->COUNT.reg;
+}
+
+static inline void hri_pdec_set_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg |= PDEC_CC_CC(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_cc_reg_t hri_pdec_get_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	tmp = ((Pdec *)hw)->CC[index].reg;
+	tmp = (tmp & PDEC_CC_CC(mask)) >> PDEC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CC[index].reg;
+	tmp &= ~PDEC_CC_CC_Msk;
+	tmp |= PDEC_CC_CC(data);
+	((Pdec *)hw)->CC[index].reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg &= ~PDEC_CC_CC(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg ^= PDEC_CC_CC(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_cc_reg_t hri_pdec_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	tmp = ((Pdec *)hw)->CC[index].reg;
+	tmp = (tmp & PDEC_CC_CC_Msk) >> PDEC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_cc_reg_t hri_pdec_get_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	tmp = ((Pdec *)hw)->CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CC[index].reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_cc_reg_t hri_pdec_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1);
+	return ((Pdec *)hw)->CC[index].reg;
+}
+
+static inline void hri_pdec_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg |= PDEC_CCBUF_CCBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                               hri_pdec_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CCBUF[index].reg;
+	tmp = (tmp & PDEC_CCBUF_CCBUF(mask)) >> PDEC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	PDEC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pdec *)hw)->CCBUF[index].reg;
+	tmp &= ~PDEC_CCBUF_CCBUF_Msk;
+	tmp |= PDEC_CCBUF_CCBUF(data);
+	((Pdec *)hw)->CCBUF[index].reg = tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg &= ~PDEC_CCBUF_CCBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg ^= PDEC_CCBUF_CCBUF(mask);
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Pdec *)hw)->CCBUF[index].reg;
+	tmp = (tmp & PDEC_CCBUF_CCBUF_Msk) >> PDEC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_pdec_set_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg |= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_reg(const void *const hw, uint8_t index,
+                                                          hri_pdec_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	tmp = ((Pdec *)hw)->CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_write_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg = data;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg &= ~mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pdec_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->CCBUF[index].reg ^= mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return ((Pdec *)hw)->CCBUF[index].reg;
+}
+
+static inline bool hri_pdec_get_STATUS_QERR_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_QERR) >> PDEC_STATUS_QERR_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_QERR_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_QERR;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_IDXERR_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_IDXERR) >> PDEC_STATUS_IDXERR_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_IDXERR_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_IDXERR;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_MPERR_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_MPERR) >> PDEC_STATUS_MPERR_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_MPERR_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_MPERR;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_WINERR_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_WINERR) >> PDEC_STATUS_WINERR_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_WINERR_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_WINERR;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_HERR_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_HERR) >> PDEC_STATUS_HERR_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_HERR_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_HERR;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_STOP_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_STOP) >> PDEC_STATUS_STOP_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_STOP_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_STOP;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_DIR_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_DIR) >> PDEC_STATUS_DIR_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_DIR_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_DIR;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_PRESCBUFV_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_PRESCBUFV) >> PDEC_STATUS_PRESCBUFV_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_PRESCBUFV_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_PRESCBUFV;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_FILTERBUFV_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_FILTERBUFV) >> PDEC_STATUS_FILTERBUFV_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_FILTERBUFV_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_FILTERBUFV;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV0) >> PDEC_STATUS_CCBUFV0_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV0;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pdec_get_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV1) >> PDEC_STATUS_CCBUFV1_Pos;
+}
+
+static inline void hri_pdec_clear_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV1;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_status_reg_t hri_pdec_get_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask)
+{
+	uint16_t tmp;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	tmp = ((Pdec *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pdec_clear_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask)
+{
+	PDEC_CRITICAL_SECTION_ENTER();
+	((Pdec *)hw)->STATUS.reg = mask;
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	PDEC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pdec_status_reg_t hri_pdec_read_STATUS_reg(const void *const hw)
+{
+	hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK);
+	return ((Pdec *)hw)->STATUS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PDEC_E54_H_INCLUDED */
+#endif /* _SAME54_PDEC_COMPONENT_ */
diff --git a/hri/hri_pm_e54.h b/hri/hri_pm_e54.h
new file mode 100644
index 0000000..0b91bee
--- /dev/null
+++ b/hri/hri_pm_e54.h
@@ -0,0 +1,820 @@
+/**
+ * \file
+ *
+ * \brief SAM PM
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_PM_COMPONENT_
+#ifndef _HRI_PM_E54_H_INCLUDED_
+#define _HRI_PM_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PM_CRITICAL_SECTIONS)
+#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PM_CRITICAL_SECTION_ENTER()
+#define PM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint8_t hri_pm_bkupcfg_reg_t;
+typedef uint8_t hri_pm_ctrla_reg_t;
+typedef uint8_t hri_pm_hibcfg_reg_t;
+typedef uint8_t hri_pm_intenset_reg_t;
+typedef uint8_t hri_pm_intflag_reg_t;
+typedef uint8_t hri_pm_pwsakdly_reg_t;
+typedef uint8_t hri_pm_sleepcfg_reg_t;
+typedef uint8_t hri_pm_stdbycfg_reg_t;
+
+static inline bool hri_pm_get_INTFLAG_SLEEPRDY_bit(const void *const hw)
+{
+	return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos;
+}
+
+static inline void hri_pm_clear_INTFLAG_SLEEPRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY;
+}
+
+static inline bool hri_pm_get_interrupt_SLEEPRDY_bit(const void *const hw)
+{
+	return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos;
+}
+
+static inline void hri_pm_clear_interrupt_SLEEPRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY;
+}
+
+static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask)
+{
+	((Pm *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_pm_set_INTEN_SLEEPRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY;
+}
+
+static inline bool hri_pm_get_INTEN_SLEEPRDY_bit(const void *const hw)
+{
+	return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_SLEEPRDY) >> PM_INTENSET_SLEEPRDY_Pos;
+}
+
+static inline void hri_pm_write_INTEN_SLEEPRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY;
+	} else {
+		((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY;
+	}
+}
+
+static inline void hri_pm_clear_INTEN_SLEEPRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY;
+}
+
+static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
+{
+	((Pm *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw)
+{
+	return ((Pm *)hw)->INTENSET.reg;
+}
+
+static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data)
+{
+	((Pm *)hw)->INTENSET.reg = data;
+	((Pm *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
+{
+	((Pm *)hw)->INTENCLR.reg = mask;
+}
+
+static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->CTRLA.reg;
+	tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->CTRLA.reg;
+	tmp &= ~PM_CTRLA_IORET;
+	tmp |= value << PM_CTRLA_IORET_Pos;
+	((Pm *)hw)->CTRLA.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw)
+{
+	return ((Pm *)hw)->CTRLA.reg;
+}
+
+static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk;
+	tmp |= PM_SLEEPCFG_SLEEPMODE(data);
+	((Pm *)hw)->SLEEPCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->SLEEPCFG.reg;
+}
+
+static inline void hri_pm_set_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_RAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_RAMCFG(mask)) >> PM_STDBYCFG_RAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp &= ~PM_STDBYCFG_RAMCFG_Msk;
+	tmp |= PM_STDBYCFG_RAMCFG(data);
+	((Pm *)hw)->STDBYCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_RAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_RAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_RAMCFG_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_RAMCFG_Msk) >> PM_STDBYCFG_RAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_FASTWKUP(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_FASTWKUP(mask)) >> PM_STDBYCFG_FASTWKUP_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp &= ~PM_STDBYCFG_FASTWKUP_Msk;
+	tmp |= PM_STDBYCFG_FASTWKUP(data);
+	((Pm *)hw)->STDBYCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_FASTWKUP(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_FASTWKUP(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_FASTWKUP_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_FASTWKUP_Msk) >> PM_STDBYCFG_FASTWKUP_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->STDBYCFG.reg;
+}
+
+static inline void hri_pm_set_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_RAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp = (tmp & PM_HIBCFG_RAMCFG(mask)) >> PM_HIBCFG_RAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp &= ~PM_HIBCFG_RAMCFG_Msk;
+	tmp |= PM_HIBCFG_RAMCFG(data);
+	((Pm *)hw)->HIBCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_RAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_RAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_RAMCFG_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp = (tmp & PM_HIBCFG_RAMCFG_Msk) >> PM_HIBCFG_RAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_BRAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp = (tmp & PM_HIBCFG_BRAMCFG(mask)) >> PM_HIBCFG_BRAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp &= ~PM_HIBCFG_BRAMCFG_Msk;
+	tmp |= PM_HIBCFG_BRAMCFG(data);
+	((Pm *)hw)->HIBCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_BRAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_BRAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_BRAMCFG_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp = (tmp & PM_HIBCFG_BRAMCFG_Msk) >> PM_HIBCFG_BRAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->HIBCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->HIBCFG.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->HIBCFG.reg;
+}
+
+static inline void hri_pm_set_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg |= PM_BKUPCFG_BRAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->BKUPCFG.reg;
+	tmp = (tmp & PM_BKUPCFG_BRAMCFG(mask)) >> PM_BKUPCFG_BRAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->BKUPCFG.reg;
+	tmp &= ~PM_BKUPCFG_BRAMCFG_Msk;
+	tmp |= PM_BKUPCFG_BRAMCFG(data);
+	((Pm *)hw)->BKUPCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg &= ~PM_BKUPCFG_BRAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg ^= PM_BKUPCFG_BRAMCFG(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_BRAMCFG_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->BKUPCFG.reg;
+	tmp = (tmp & PM_BKUPCFG_BRAMCFG_Msk) >> PM_BKUPCFG_BRAMCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->BKUPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->BKUPCFG.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->BKUPCFG.reg;
+}
+
+static inline void hri_pm_set_PWSAKDLY_IGNACK_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_IGNACK;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_PWSAKDLY_IGNACK_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PWSAKDLY.reg;
+	tmp = (tmp & PM_PWSAKDLY_IGNACK) >> PM_PWSAKDLY_IGNACK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_PWSAKDLY_IGNACK_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->PWSAKDLY.reg;
+	tmp &= ~PM_PWSAKDLY_IGNACK;
+	tmp |= value << PM_PWSAKDLY_IGNACK_Pos;
+	((Pm *)hw)->PWSAKDLY.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_PWSAKDLY_IGNACK_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_IGNACK;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_PWSAKDLY_IGNACK_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_IGNACK;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_DLYVAL(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PWSAKDLY.reg;
+	tmp = (tmp & PM_PWSAKDLY_DLYVAL(mask)) >> PM_PWSAKDLY_DLYVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->PWSAKDLY.reg;
+	tmp &= ~PM_PWSAKDLY_DLYVAL_Msk;
+	tmp |= PM_PWSAKDLY_DLYVAL(data);
+	((Pm *)hw)->PWSAKDLY.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_DLYVAL(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_DLYVAL(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_DLYVAL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PWSAKDLY.reg;
+	tmp = (tmp & PM_PWSAKDLY_DLYVAL_Msk) >> PM_PWSAKDLY_DLYVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PWSAKDLY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PWSAKDLY.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_reg(const void *const hw)
+{
+	return ((Pm *)hw)->PWSAKDLY.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PM_E54_H_INCLUDED */
+#endif /* _SAME54_PM_COMPONENT_ */
diff --git a/hri/hri_port_e54.h b/hri/hri_port_e54.h
new file mode 100644
index 0000000..261fcf5
--- /dev/null
+++ b/hri/hri_port_e54.h
@@ -0,0 +1,2528 @@
+/**
+ * \file
+ *
+ * \brief SAM PORT
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_PORT_COMPONENT_
+#ifndef _HRI_PORT_E54_H_INCLUDED_
+#define _HRI_PORT_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PORT_CRITICAL_SECTIONS)
+#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PORT_CRITICAL_SECTION_ENTER()
+#define PORT_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_port_ctrl_reg_t;
+typedef uint32_t hri_port_dir_reg_t;
+typedef uint32_t hri_port_evctrl_reg_t;
+typedef uint32_t hri_port_in_reg_t;
+typedef uint32_t hri_port_out_reg_t;
+typedef uint32_t hri_port_wrconfig_reg_t;
+typedef uint32_t hri_portgroup_ctrl_reg_t;
+typedef uint32_t hri_portgroup_dir_reg_t;
+typedef uint32_t hri_portgroup_evctrl_reg_t;
+typedef uint32_t hri_portgroup_in_reg_t;
+typedef uint32_t hri_portgroup_out_reg_t;
+typedef uint32_t hri_portgroup_wrconfig_reg_t;
+typedef uint8_t  hri_port_pincfg_reg_t;
+typedef uint8_t  hri_port_pmux_reg_t;
+typedef uint8_t  hri_portgroup_pincfg_reg_t;
+typedef uint8_t  hri_portgroup_pmux_reg_t;
+
+static inline void hri_portgroup_set_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(mask);
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_get_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->DIR.reg;
+	tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_read_DIR_DIR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->DIR.reg;
+	tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t data)
+{
+	((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(data);
+	((PortGroup *)hw)->DIRCLR.reg = ~PORT_DIR_DIR(data);
+}
+
+static inline void hri_portgroup_clear_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRCLR.reg = PORT_DIR_DIR(mask);
+}
+
+static inline void hri_portgroup_toggle_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRTGL.reg = PORT_DIR_DIR(mask);
+}
+
+static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRSET.reg = mask;
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->DIR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->DIR.reg;
+}
+
+static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data)
+{
+	((PortGroup *)hw)->DIRSET.reg = data;
+	((PortGroup *)hw)->DIRCLR.reg = ~data;
+}
+
+static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRCLR.reg = mask;
+}
+
+static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRTGL.reg = mask;
+}
+
+static inline void hri_portgroup_set_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(mask);
+}
+
+static inline hri_port_out_reg_t hri_portgroup_get_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->OUT.reg;
+	tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_portgroup_read_OUT_OUT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->OUT.reg;
+	tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t data)
+{
+	((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(data);
+	((PortGroup *)hw)->OUTCLR.reg = ~PORT_OUT_OUT(data);
+}
+
+static inline void hri_portgroup_clear_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTCLR.reg = PORT_OUT_OUT(mask);
+}
+
+static inline void hri_portgroup_toggle_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTTGL.reg = PORT_OUT_OUT(mask);
+}
+
+static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTSET.reg = mask;
+}
+
+static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->OUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->OUT.reg;
+}
+
+static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data)
+{
+	((PortGroup *)hw)->OUTSET.reg = data;
+	((PortGroup *)hw)->OUTCLR.reg = ~data;
+}
+
+static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTCLR.reg = mask;
+}
+
+static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTTGL.reg = mask;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_get_IN_IN_bf(const void *const hw, hri_port_in_reg_t mask)
+{
+	return (((PortGroup *)hw)->IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_read_IN_IN_bf(const void *const hw)
+{
+	return (((PortGroup *)hw)->IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->IN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->IN.reg;
+}
+
+static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp &= ~PORT_CTRL_SAMPLING_Msk;
+	tmp |= PORT_CTRL_SAMPLING(data);
+	((PortGroup *)hw)->CTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->CTRL.reg;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI0;
+	tmp |= value << PORT_EVCTRL_PORTEI0_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI1;
+	tmp |= value << PORT_EVCTRL_PORTEI1_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI2;
+	tmp |= value << PORT_EVCTRL_PORTEI2_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI3;
+	tmp |= value << PORT_EVCTRL_PORTEI3_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID0_Msk;
+	tmp |= PORT_EVCTRL_PID0(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT0_Msk;
+	tmp |= PORT_EVCTRL_EVACT0(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID1_Msk;
+	tmp |= PORT_EVCTRL_PID1(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT1_Msk;
+	tmp |= PORT_EVCTRL_EVACT1(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID2_Msk;
+	tmp |= PORT_EVCTRL_PID2(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT2_Msk;
+	tmp |= PORT_EVCTRL_EVACT2(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID3_Msk;
+	tmp |= PORT_EVCTRL_PID3(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT3_Msk;
+	tmp |= PORT_EVCTRL_EVACT3(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index,
+                                                                  hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXE_Msk;
+	tmp |= PORT_PMUX_PMUXE(data);
+	((PortGroup *)hw)->PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index,
+                                                                  hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXO_Msk;
+	tmp |= PORT_PMUX_PMUXO(data);
+	((PortGroup *)hw)->PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index,
+                                                             hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index)
+{
+	return ((PortGroup *)hw)->PMUX[index].reg;
+}
+
+static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PMUXEN;
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_INEN;
+	tmp |= value << PORT_PINCFG_INEN_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PULLEN;
+	tmp |= value << PORT_PINCFG_PULLEN_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_DRVSTR;
+	tmp |= value << PORT_PINCFG_DRVSTR_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index,
+                                                                 hri_port_pincfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index)
+{
+	return ((PortGroup *)hw)->PINCFG[index].reg;
+}
+
+static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->WRCONFIG.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(mask);
+}
+
+static inline hri_port_dir_reg_t hri_port_get_DIR_DIR_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
+	tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_port_read_DIR_DIR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
+	tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(data);
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~PORT_DIR_DIR(data);
+}
+
+static inline void hri_port_clear_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = PORT_DIR_DIR(mask);
+}
+
+static inline void hri_port_toggle_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRTGL.reg = PORT_DIR_DIR(mask);
+}
+
+static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
+}
+
+static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].DIR.reg;
+}
+
+static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = data;
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data;
+}
+
+static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
+}
+
+static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask;
+}
+
+static inline void hri_port_set_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(mask);
+}
+
+static inline hri_port_out_reg_t hri_port_get_OUT_OUT_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
+	tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_port_read_OUT_OUT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
+	tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(data);
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~PORT_OUT_OUT(data);
+}
+
+static inline void hri_port_clear_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = PORT_OUT_OUT(mask);
+}
+
+static inline void hri_port_toggle_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTTGL.reg = PORT_OUT_OUT(mask);
+}
+
+static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = mask;
+}
+
+static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].OUT.reg;
+}
+
+static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = data;
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data;
+}
+
+static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
+}
+
+static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask;
+}
+
+static inline hri_port_in_reg_t hri_port_get_IN_IN_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_port_in_reg_t mask)
+{
+	return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos;
+}
+
+static inline hri_port_in_reg_t hri_port_read_IN_IN_bf(const void *const hw, uint8_t submodule_index)
+{
+	return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos;
+}
+
+static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_in_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].IN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].IN.reg;
+}
+
+static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_ctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp &= ~PORT_CTRL_SAMPLING_Msk;
+	tmp |= PORT_CTRL_SAMPLING(data);
+	((Port *)hw)->Group[submodule_index].CTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].CTRL.reg;
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI0;
+	tmp |= value << PORT_EVCTRL_PORTEI0_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI1;
+	tmp |= value << PORT_EVCTRL_PORTEI1_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI2;
+	tmp |= value << PORT_EVCTRL_PORTEI2_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI3;
+	tmp |= value << PORT_EVCTRL_PORTEI3_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID0_Msk;
+	tmp |= PORT_EVCTRL_PID0(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT0_Msk;
+	tmp |= PORT_EVCTRL_EVACT0(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID1_Msk;
+	tmp |= PORT_EVCTRL_PID1(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT1_Msk;
+	tmp |= PORT_EVCTRL_EVACT1(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID2_Msk;
+	tmp |= PORT_EVCTRL_PID2(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT2_Msk;
+	tmp |= PORT_EVCTRL_EVACT2(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID3_Msk;
+	tmp |= PORT_EVCTRL_PID3(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT3_Msk;
+	tmp |= PORT_EVCTRL_EVACT3(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+}
+
+static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                              hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index,
+                                                             uint8_t index, hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXE_Msk;
+	tmp |= PORT_PMUX_PMUXE(data);
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                 hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index,
+                                                              uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                              hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index,
+                                                             uint8_t index, hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXO_Msk;
+	tmp |= PORT_PMUX_PMUXO(data);
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                 hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index,
+                                                              uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                         hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                        hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                           hri_port_pmux_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                           hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                            hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	return ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+}
+
+static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                    bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PMUXEN;
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                  bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_INEN;
+	tmp |= value << PORT_PINCFG_INEN_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                    bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PULLEN;
+	tmp |= value << PORT_PINCFG_PULLEN_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                    bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_DRVSTR;
+	tmp |= value << PORT_PINCFG_DRVSTR_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                           hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                            uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                             hri_port_pincfg_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                             hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                              hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                             uint8_t index)
+{
+	return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+}
+
+static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_port_wrconfig_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PORT_E54_H_INCLUDED */
+#endif /* _SAME54_PORT_COMPONENT_ */
diff --git a/hri/hri_qspi_e54.h b/hri/hri_qspi_e54.h
new file mode 100644
index 0000000..23742bc
--- /dev/null
+++ b/hri/hri_qspi_e54.h
@@ -0,0 +1,2058 @@
+/**
+ * \file
+ *
+ * \brief SAM QSPI
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_QSPI_COMPONENT_
+#ifndef _HRI_QSPI_E54_H_INCLUDED_
+#define _HRI_QSPI_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_QSPI_CRITICAL_SECTIONS)
+#define QSPI_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define QSPI_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define QSPI_CRITICAL_SECTION_ENTER()
+#define QSPI_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_qspi_baud_reg_t;
+typedef uint32_t hri_qspi_ctrla_reg_t;
+typedef uint32_t hri_qspi_ctrlb_reg_t;
+typedef uint32_t hri_qspi_instraddr_reg_t;
+typedef uint32_t hri_qspi_instrctrl_reg_t;
+typedef uint32_t hri_qspi_instrframe_reg_t;
+typedef uint32_t hri_qspi_intenset_reg_t;
+typedef uint32_t hri_qspi_intflag_reg_t;
+typedef uint32_t hri_qspi_rxdata_reg_t;
+typedef uint32_t hri_qspi_scrambctrl_reg_t;
+typedef uint32_t hri_qspi_scrambkey_reg_t;
+typedef uint32_t hri_qspi_status_reg_t;
+typedef uint32_t hri_qspi_txdata_reg_t;
+
+static inline bool hri_qspi_get_INTFLAG_RXC_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_qspi_clear_INTFLAG_RXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC;
+}
+
+static inline bool hri_qspi_get_INTFLAG_DRE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_qspi_clear_INTFLAG_DRE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE;
+}
+
+static inline bool hri_qspi_get_INTFLAG_TXC_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_qspi_clear_INTFLAG_TXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC;
+}
+
+static inline bool hri_qspi_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_qspi_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR;
+}
+
+static inline bool hri_qspi_get_INTFLAG_CSRISE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos;
+}
+
+static inline void hri_qspi_clear_INTFLAG_CSRISE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE;
+}
+
+static inline bool hri_qspi_get_INTFLAG_INSTREND_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos;
+}
+
+static inline void hri_qspi_clear_INTFLAG_INSTREND_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND;
+}
+
+static inline bool hri_qspi_get_interrupt_RXC_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_qspi_clear_interrupt_RXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC;
+}
+
+static inline bool hri_qspi_get_interrupt_DRE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_qspi_clear_interrupt_DRE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE;
+}
+
+static inline bool hri_qspi_get_interrupt_TXC_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_qspi_clear_interrupt_TXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC;
+}
+
+static inline bool hri_qspi_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_qspi_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR;
+}
+
+static inline bool hri_qspi_get_interrupt_CSRISE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos;
+}
+
+static inline void hri_qspi_clear_interrupt_CSRISE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE;
+}
+
+static inline bool hri_qspi_get_interrupt_INSTREND_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos;
+}
+
+static inline void hri_qspi_clear_interrupt_INSTREND_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND;
+}
+
+static inline hri_qspi_intflag_reg_t hri_qspi_get_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_qspi_intflag_reg_t hri_qspi_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_qspi_clear_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask)
+{
+	((Qspi *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_qspi_set_INTEN_RXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC;
+}
+
+static inline bool hri_qspi_get_INTEN_RXC_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_RXC) >> QSPI_INTENSET_RXC_Pos;
+}
+
+static inline void hri_qspi_write_INTEN_RXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC;
+	} else {
+		((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC;
+	}
+}
+
+static inline void hri_qspi_clear_INTEN_RXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC;
+}
+
+static inline void hri_qspi_set_INTEN_DRE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE;
+}
+
+static inline bool hri_qspi_get_INTEN_DRE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_DRE) >> QSPI_INTENSET_DRE_Pos;
+}
+
+static inline void hri_qspi_write_INTEN_DRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE;
+	} else {
+		((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE;
+	}
+}
+
+static inline void hri_qspi_clear_INTEN_DRE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE;
+}
+
+static inline void hri_qspi_set_INTEN_TXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC;
+}
+
+static inline bool hri_qspi_get_INTEN_TXC_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_TXC) >> QSPI_INTENSET_TXC_Pos;
+}
+
+static inline void hri_qspi_write_INTEN_TXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC;
+	} else {
+		((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC;
+	}
+}
+
+static inline void hri_qspi_clear_INTEN_TXC_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC;
+}
+
+static inline void hri_qspi_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR;
+}
+
+static inline bool hri_qspi_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_ERROR) >> QSPI_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_qspi_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR;
+	} else {
+		((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_qspi_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR;
+}
+
+static inline void hri_qspi_set_INTEN_CSRISE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE;
+}
+
+static inline bool hri_qspi_get_INTEN_CSRISE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_CSRISE) >> QSPI_INTENSET_CSRISE_Pos;
+}
+
+static inline void hri_qspi_write_INTEN_CSRISE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE;
+	} else {
+		((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE;
+	}
+}
+
+static inline void hri_qspi_clear_INTEN_CSRISE_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE;
+}
+
+static inline void hri_qspi_set_INTEN_INSTREND_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND;
+}
+
+static inline bool hri_qspi_get_INTEN_INSTREND_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_INSTREND) >> QSPI_INTENSET_INSTREND_Pos;
+}
+
+static inline void hri_qspi_write_INTEN_INSTREND_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND;
+	} else {
+		((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND;
+	}
+}
+
+static inline void hri_qspi_clear_INTEN_INSTREND_bit(const void *const hw)
+{
+	((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND;
+}
+
+static inline void hri_qspi_set_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask)
+{
+	((Qspi *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_qspi_intenset_reg_t hri_qspi_get_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_qspi_intenset_reg_t hri_qspi_read_INTEN_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->INTENSET.reg;
+}
+
+static inline void hri_qspi_write_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t data)
+{
+	((Qspi *)hw)->INTENSET.reg = data;
+	((Qspi *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_qspi_clear_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask)
+{
+	((Qspi *)hw)->INTENCLR.reg = mask;
+}
+
+static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_DATA_bf(const void *const hw, hri_qspi_rxdata_reg_t mask)
+{
+	return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA(mask)) >> QSPI_RXDATA_DATA_Pos;
+}
+
+static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_DATA_bf(const void *const hw)
+{
+	return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA_Msk) >> QSPI_RXDATA_DATA_Pos;
+}
+
+static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_reg(const void *const hw, hri_qspi_rxdata_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->RXDATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->RXDATA.reg;
+}
+
+static inline bool hri_qspi_get_STATUS_ENABLE_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_ENABLE) >> QSPI_STATUS_ENABLE_Pos;
+}
+
+static inline bool hri_qspi_get_STATUS_CSSTATUS_bit(const void *const hw)
+{
+	return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_CSSTATUS) >> QSPI_STATUS_CSSTATUS_Pos;
+}
+
+static inline hri_qspi_status_reg_t hri_qspi_get_STATUS_reg(const void *const hw, hri_qspi_status_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_qspi_status_reg_t hri_qspi_read_STATUS_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->STATUS.reg;
+}
+
+static inline void hri_qspi_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_SWRST;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLA.reg;
+	tmp = (tmp & QSPI_CTRLA_SWRST) >> QSPI_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_ENABLE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLA.reg;
+	tmp = (tmp & QSPI_CTRLA_ENABLE) >> QSPI_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLA.reg;
+	tmp &= ~QSPI_CTRLA_ENABLE;
+	tmp |= value << QSPI_CTRLA_ENABLE_Pos;
+	((Qspi *)hw)->CTRLA.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_ENABLE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_ENABLE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_CTRLA_LASTXFER_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_LASTXFER;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLA_LASTXFER_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLA.reg;
+	tmp = (tmp & QSPI_CTRLA_LASTXFER) >> QSPI_CTRLA_LASTXFER_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_CTRLA_LASTXFER_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLA.reg;
+	tmp &= ~QSPI_CTRLA_LASTXFER;
+	tmp |= value << QSPI_CTRLA_LASTXFER_Pos;
+	((Qspi *)hw)->CTRLA.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLA_LASTXFER_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_LASTXFER;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLA_LASTXFER_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_LASTXFER;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrla_reg_t hri_qspi_get_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLA.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrla_reg_t hri_qspi_read_CTRLA_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->CTRLA.reg;
+}
+
+static inline void hri_qspi_set_CTRLB_MODE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_MODE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLB_MODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_MODE) >> QSPI_CTRLB_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_MODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_MODE;
+	tmp |= value << QSPI_CTRLB_MODE_Pos;
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_MODE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_MODE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_MODE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_MODE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_CTRLB_LOOPEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_LOOPEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLB_LOOPEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_LOOPEN) >> QSPI_CTRLB_LOOPEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_LOOPEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_LOOPEN;
+	tmp |= value << QSPI_CTRLB_LOOPEN_Pos;
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_LOOPEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_LOOPEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_LOOPEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_LOOPEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_CTRLB_WDRBT_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_WDRBT;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLB_WDRBT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_WDRBT) >> QSPI_CTRLB_WDRBT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_WDRBT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_WDRBT;
+	tmp |= value << QSPI_CTRLB_WDRBT_Pos;
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_WDRBT_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_WDRBT;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_WDRBT_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_WDRBT;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_CTRLB_SMEMREG_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_SMEMREG;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_CTRLB_SMEMREG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_SMEMREG) >> QSPI_CTRLB_SMEMREG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_SMEMREG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_SMEMREG;
+	tmp |= value << QSPI_CTRLB_SMEMREG_Pos;
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_SMEMREG_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_SMEMREG;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_SMEMREG_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_SMEMREG;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_CSMODE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_CSMODE(mask)) >> QSPI_CTRLB_CSMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_CSMODE_Msk;
+	tmp |= QSPI_CTRLB_CSMODE(data);
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_CSMODE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_CSMODE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_CSMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_CSMODE_Msk) >> QSPI_CTRLB_CSMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DATALEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_DATALEN(mask)) >> QSPI_CTRLB_DATALEN_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_DATALEN_Msk;
+	tmp |= QSPI_CTRLB_DATALEN(data);
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DATALEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DATALEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DATALEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_DATALEN_Msk) >> QSPI_CTRLB_DATALEN_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYBCT(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_DLYBCT(mask)) >> QSPI_CTRLB_DLYBCT_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_DLYBCT_Msk;
+	tmp |= QSPI_CTRLB_DLYBCT(data);
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYBCT(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYBCT(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYBCT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_DLYBCT_Msk) >> QSPI_CTRLB_DLYBCT_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYCS(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_DLYCS(mask)) >> QSPI_CTRLB_DLYCS_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= ~QSPI_CTRLB_DLYCS_Msk;
+	tmp |= QSPI_CTRLB_DLYCS(data);
+	((Qspi *)hw)->CTRLB.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYCS(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYCS(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYCS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp = (tmp & QSPI_CTRLB_DLYCS_Msk) >> QSPI_CTRLB_DLYCS_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->CTRLB.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->CTRLB.reg;
+}
+
+static inline void hri_qspi_set_BAUD_CPOL_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPOL;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_BAUD_CPOL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp = (tmp & QSPI_BAUD_CPOL) >> QSPI_BAUD_CPOL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_BAUD_CPOL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp &= ~QSPI_BAUD_CPOL;
+	tmp |= value << QSPI_BAUD_CPOL_Pos;
+	((Qspi *)hw)->BAUD.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_BAUD_CPOL_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPOL;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_BAUD_CPOL_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPOL;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_BAUD_CPHA_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPHA;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_BAUD_CPHA_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp = (tmp & QSPI_BAUD_CPHA) >> QSPI_BAUD_CPHA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_BAUD_CPHA_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp &= ~QSPI_BAUD_CPHA;
+	tmp |= value << QSPI_BAUD_CPHA_Pos;
+	((Qspi *)hw)->BAUD.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_BAUD_CPHA_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPHA;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_BAUD_CPHA_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPHA;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_BAUD(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp = (tmp & QSPI_BAUD_BAUD(mask)) >> QSPI_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp &= ~QSPI_BAUD_BAUD_Msk;
+	tmp |= QSPI_BAUD_BAUD(data);
+	((Qspi *)hw)->BAUD.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_BAUD(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_BAUD(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp = (tmp & QSPI_BAUD_BAUD_Msk) >> QSPI_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_DLYBS(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp = (tmp & QSPI_BAUD_DLYBS(mask)) >> QSPI_BAUD_DLYBS_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp &= ~QSPI_BAUD_DLYBS_Msk;
+	tmp |= QSPI_BAUD_DLYBS(data);
+	((Qspi *)hw)->BAUD.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_DLYBS(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_DLYBS(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_DLYBS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp = (tmp & QSPI_BAUD_DLYBS_Msk) >> QSPI_BAUD_DLYBS_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->BAUD.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->BAUD.reg;
+}
+
+static inline void hri_qspi_set_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg |= QSPI_INSTRADDR_ADDR(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_ADDR_bf(const void *const        hw,
+                                                                      hri_qspi_instraddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRADDR.reg;
+	tmp = (tmp & QSPI_INSTRADDR_ADDR(mask)) >> QSPI_INSTRADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRADDR.reg;
+	tmp &= ~QSPI_INSTRADDR_ADDR_Msk;
+	tmp |= QSPI_INSTRADDR_ADDR(data);
+	((Qspi *)hw)->INSTRADDR.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg &= ~QSPI_INSTRADDR_ADDR(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg ^= QSPI_INSTRADDR_ADDR(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRADDR.reg;
+	tmp = (tmp & QSPI_INSTRADDR_ADDR_Msk) >> QSPI_INSTRADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRADDR.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->INSTRADDR.reg;
+}
+
+static inline void hri_qspi_set_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_INSTR(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_INSTR_bf(const void *const        hw,
+                                                                       hri_qspi_instrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp = (tmp & QSPI_INSTRCTRL_INSTR(mask)) >> QSPI_INSTRCTRL_INSTR_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp &= ~QSPI_INSTRCTRL_INSTR_Msk;
+	tmp |= QSPI_INSTRCTRL_INSTR(data);
+	((Qspi *)hw)->INSTRCTRL.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_INSTR(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_INSTR(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_INSTR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp = (tmp & QSPI_INSTRCTRL_INSTR_Msk) >> QSPI_INSTRCTRL_INSTR_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_OPTCODE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_OPTCODE_bf(const void *const        hw,
+                                                                         hri_qspi_instrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp = (tmp & QSPI_INSTRCTRL_OPTCODE(mask)) >> QSPI_INSTRCTRL_OPTCODE_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp &= ~QSPI_INSTRCTRL_OPTCODE_Msk;
+	tmp |= QSPI_INSTRCTRL_OPTCODE(data);
+	((Qspi *)hw)->INSTRCTRL.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_OPTCODE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_OPTCODE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_OPTCODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp = (tmp & QSPI_INSTRCTRL_OPTCODE_Msk) >> QSPI_INSTRCTRL_OPTCODE_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRCTRL.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->INSTRCTRL.reg;
+}
+
+static inline void hri_qspi_set_INSTRFRAME_INSTREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_INSTREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_INSTREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_INSTREN) >> QSPI_INSTRFRAME_INSTREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_INSTREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_INSTREN;
+	tmp |= value << QSPI_INSTRFRAME_INSTREN_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_INSTREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_INSTREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_INSTREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_INSTREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_ADDREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_ADDREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_ADDREN) >> QSPI_INSTRFRAME_ADDREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_ADDREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_ADDREN;
+	tmp |= value << QSPI_INSTRFRAME_ADDREN_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_ADDREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_ADDREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_OPTCODEEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODEEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_OPTCODEEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_OPTCODEEN) >> QSPI_INSTRFRAME_OPTCODEEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_OPTCODEEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_OPTCODEEN;
+	tmp |= value << QSPI_INSTRFRAME_OPTCODEEN_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_OPTCODEEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODEEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_OPTCODEEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODEEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_DATAEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DATAEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_DATAEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_DATAEN) >> QSPI_INSTRFRAME_DATAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_DATAEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_DATAEN;
+	tmp |= value << QSPI_INSTRFRAME_DATAEN_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_DATAEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DATAEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_DATAEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DATAEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_ADDRLEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDRLEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_ADDRLEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_ADDRLEN) >> QSPI_INSTRFRAME_ADDRLEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_ADDRLEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_ADDRLEN;
+	tmp |= value << QSPI_INSTRFRAME_ADDRLEN_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_ADDRLEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDRLEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_ADDRLEN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDRLEN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_CRMODE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_CRMODE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_CRMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_CRMODE) >> QSPI_INSTRFRAME_CRMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_CRMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_CRMODE;
+	tmp |= value << QSPI_INSTRFRAME_CRMODE_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_CRMODE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_CRMODE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_CRMODE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_CRMODE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_DDREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DDREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_INSTRFRAME_DDREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_DDREN) >> QSPI_INSTRFRAME_DDREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_DDREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_DDREN;
+	tmp |= value << QSPI_INSTRFRAME_DDREN_Pos;
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_DDREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DDREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_DDREN_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DDREN;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_WIDTH(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_WIDTH_bf(const void *const         hw,
+                                                                         hri_qspi_instrframe_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_WIDTH(mask)) >> QSPI_INSTRFRAME_WIDTH_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_WIDTH_Msk;
+	tmp |= QSPI_INSTRFRAME_WIDTH(data);
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_WIDTH(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_WIDTH(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_WIDTH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_WIDTH_Msk) >> QSPI_INSTRFRAME_WIDTH_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODELEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_OPTCODELEN_bf(const void *const         hw,
+                                                                              hri_qspi_instrframe_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN(mask)) >> QSPI_INSTRFRAME_OPTCODELEN_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_OPTCODELEN_Msk;
+	tmp |= QSPI_INSTRFRAME_OPTCODELEN(data);
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODELEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODELEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_OPTCODELEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN_Msk) >> QSPI_INSTRFRAME_OPTCODELEN_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_TFRTYPE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_TFRTYPE_bf(const void *const         hw,
+                                                                           hri_qspi_instrframe_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE(mask)) >> QSPI_INSTRFRAME_TFRTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_TFRTYPE_Msk;
+	tmp |= QSPI_INSTRFRAME_TFRTYPE(data);
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_TFRTYPE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_TFRTYPE(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_TFRTYPE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE_Msk) >> QSPI_INSTRFRAME_TFRTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DUMMYLEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_DUMMYLEN_bf(const void *const         hw,
+                                                                            hri_qspi_instrframe_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN(mask)) >> QSPI_INSTRFRAME_DUMMYLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= ~QSPI_INSTRFRAME_DUMMYLEN_Msk;
+	tmp |= QSPI_INSTRFRAME_DUMMYLEN(data);
+	((Qspi *)hw)->INSTRFRAME.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DUMMYLEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DUMMYLEN(mask);
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_DUMMYLEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN_Msk) >> QSPI_INSTRFRAME_DUMMYLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_qspi_set_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_reg(const void *const         hw,
+                                                                    hri_qspi_instrframe_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->INSTRFRAME.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->INSTRFRAME.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->INSTRFRAME.reg;
+}
+
+static inline void hri_qspi_set_SCRAMBCTRL_ENABLE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_ENABLE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_SCRAMBCTRL_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->SCRAMBCTRL.reg;
+	tmp = (tmp & QSPI_SCRAMBCTRL_ENABLE) >> QSPI_SCRAMBCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_SCRAMBCTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->SCRAMBCTRL.reg;
+	tmp &= ~QSPI_SCRAMBCTRL_ENABLE;
+	tmp |= value << QSPI_SCRAMBCTRL_ENABLE_Pos;
+	((Qspi *)hw)->SCRAMBCTRL.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_SCRAMBCTRL_ENABLE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_ENABLE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_SCRAMBCTRL_ENABLE_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_ENABLE;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_RANDOMDIS;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_qspi_get_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->SCRAMBCTRL.reg;
+	tmp = (tmp & QSPI_SCRAMBCTRL_RANDOMDIS) >> QSPI_SCRAMBCTRL_RANDOMDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_qspi_write_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	QSPI_CRITICAL_SECTION_ENTER();
+	tmp = ((Qspi *)hw)->SCRAMBCTRL.reg;
+	tmp &= ~QSPI_SCRAMBCTRL_RANDOMDIS;
+	tmp |= value << QSPI_SCRAMBCTRL_RANDOMDIS_Pos;
+	((Qspi *)hw)->SCRAMBCTRL.reg = tmp;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_RANDOMDIS;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_RANDOMDIS;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_set_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg |= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_scrambctrl_reg_t hri_qspi_get_SCRAMBCTRL_reg(const void *const         hw,
+                                                                    hri_qspi_scrambctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Qspi *)hw)->SCRAMBCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_qspi_write_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_clear_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg &= ~mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_toggle_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBCTRL.reg ^= mask;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_qspi_scrambctrl_reg_t hri_qspi_read_SCRAMBCTRL_reg(const void *const hw)
+{
+	return ((Qspi *)hw)->SCRAMBCTRL.reg;
+}
+
+static inline void hri_qspi_write_TXDATA_reg(const void *const hw, hri_qspi_txdata_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->TXDATA.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_qspi_write_SCRAMBKEY_reg(const void *const hw, hri_qspi_scrambkey_reg_t data)
+{
+	QSPI_CRITICAL_SECTION_ENTER();
+	((Qspi *)hw)->SCRAMBKEY.reg = data;
+	QSPI_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_QSPI_E54_H_INCLUDED */
+#endif /* _SAME54_QSPI_COMPONENT_ */
diff --git a/hri/hri_ramecc_e54.h b/hri/hri_ramecc_e54.h
new file mode 100644
index 0000000..6031cce
--- /dev/null
+++ b/hri/hri_ramecc_e54.h
@@ -0,0 +1,362 @@
+/**
+ * \file
+ *
+ * \brief SAM RAMECC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_RAMECC_COMPONENT_
+#ifndef _HRI_RAMECC_E54_H_INCLUDED_
+#define _HRI_RAMECC_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_RAMECC_CRITICAL_SECTIONS)
+#define RAMECC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define RAMECC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define RAMECC_CRITICAL_SECTION_ENTER()
+#define RAMECC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_ramecc_erraddr_reg_t;
+typedef uint8_t  hri_ramecc_dbgctrl_reg_t;
+typedef uint8_t  hri_ramecc_intenset_reg_t;
+typedef uint8_t  hri_ramecc_intflag_reg_t;
+typedef uint8_t  hri_ramecc_status_reg_t;
+
+static inline bool hri_ramecc_get_INTFLAG_SINGLEE_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos;
+}
+
+static inline void hri_ramecc_clear_INTFLAG_SINGLEE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE;
+}
+
+static inline bool hri_ramecc_get_INTFLAG_DUALE_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos;
+}
+
+static inline void hri_ramecc_clear_INTFLAG_DUALE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE;
+}
+
+static inline bool hri_ramecc_get_interrupt_SINGLEE_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos;
+}
+
+static inline void hri_ramecc_clear_interrupt_SINGLEE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE;
+}
+
+static inline bool hri_ramecc_get_interrupt_DUALE_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos;
+}
+
+static inline void hri_ramecc_clear_interrupt_DUALE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE;
+}
+
+static inline hri_ramecc_intflag_reg_t hri_ramecc_get_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ramecc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Ramecc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_ramecc_clear_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask)
+{
+	((Ramecc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_ramecc_set_INTEN_SINGLEE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE;
+}
+
+static inline bool hri_ramecc_get_INTEN_SINGLEE_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_SINGLEE) >> RAMECC_INTENSET_SINGLEE_Pos;
+}
+
+static inline void hri_ramecc_write_INTEN_SINGLEE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE;
+	} else {
+		((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE;
+	}
+}
+
+static inline void hri_ramecc_clear_INTEN_SINGLEE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE;
+}
+
+static inline void hri_ramecc_set_INTEN_DUALE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE;
+}
+
+static inline bool hri_ramecc_get_INTEN_DUALE_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_DUALE) >> RAMECC_INTENSET_DUALE_Pos;
+}
+
+static inline void hri_ramecc_write_INTEN_DUALE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE;
+	} else {
+		((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE;
+	}
+}
+
+static inline void hri_ramecc_clear_INTEN_DUALE_bit(const void *const hw)
+{
+	((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE;
+}
+
+static inline void hri_ramecc_set_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask)
+{
+	((Ramecc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_ramecc_intenset_reg_t hri_ramecc_get_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ramecc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ramecc_intenset_reg_t hri_ramecc_read_INTEN_reg(const void *const hw)
+{
+	return ((Ramecc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_ramecc_write_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t data)
+{
+	((Ramecc *)hw)->INTENSET.reg = data;
+	((Ramecc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_ramecc_clear_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask)
+{
+	((Ramecc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_ramecc_get_STATUS_ECCDIS_bit(const void *const hw)
+{
+	return (((Ramecc *)hw)->STATUS.reg & RAMECC_STATUS_ECCDIS) >> RAMECC_STATUS_ECCDIS_Pos;
+}
+
+static inline hri_ramecc_status_reg_t hri_ramecc_get_STATUS_reg(const void *const hw, hri_ramecc_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ramecc *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ramecc_status_reg_t hri_ramecc_read_STATUS_reg(const void *const hw)
+{
+	return ((Ramecc *)hw)->STATUS.reg;
+}
+
+static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_ERRADDR_bf(const void *const        hw,
+                                                                         hri_ramecc_erraddr_reg_t mask)
+{
+	return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR(mask)) >> RAMECC_ERRADDR_ERRADDR_Pos;
+}
+
+static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_ERRADDR_bf(const void *const hw)
+{
+	return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR_Msk) >> RAMECC_ERRADDR_ERRADDR_Pos;
+}
+
+static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_reg(const void *const hw, hri_ramecc_erraddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ramecc *)hw)->ERRADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw)
+{
+	return ((Ramecc *)hw)->ERRADDR.reg;
+}
+
+static inline void hri_ramecc_set_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCDIS;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ramecc_get_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ramecc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & RAMECC_DBGCTRL_ECCDIS) >> RAMECC_DBGCTRL_ECCDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ramecc_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RAMECC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ramecc *)hw)->DBGCTRL.reg;
+	tmp &= ~RAMECC_DBGCTRL_ECCDIS;
+	tmp |= value << RAMECC_DBGCTRL_ECCDIS_Pos;
+	((Ramecc *)hw)->DBGCTRL.reg = tmp;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_clear_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCDIS;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_toggle_DBGCTRL_ECCDIS_bit(const void *const hw)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCDIS;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_set_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCELOG;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ramecc_get_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ramecc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & RAMECC_DBGCTRL_ECCELOG) >> RAMECC_DBGCTRL_ECCELOG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ramecc_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RAMECC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ramecc *)hw)->DBGCTRL.reg;
+	tmp &= ~RAMECC_DBGCTRL_ECCELOG;
+	tmp |= value << RAMECC_DBGCTRL_ECCELOG_Pos;
+	((Ramecc *)hw)->DBGCTRL.reg = tmp;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_clear_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCELOG;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_toggle_DBGCTRL_ECCELOG_bit(const void *const hw)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCELOG;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_set_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg |= mask;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_get_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ramecc *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ramecc_write_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t data)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg = data;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_clear_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg &= ~mask;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ramecc_toggle_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask)
+{
+	RAMECC_CRITICAL_SECTION_ENTER();
+	((Ramecc *)hw)->DBGCTRL.reg ^= mask;
+	RAMECC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Ramecc *)hw)->DBGCTRL.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_RAMECC_E54_H_INCLUDED */
+#endif /* _SAME54_RAMECC_COMPONENT_ */
diff --git a/hri/hri_rstc_e54.h b/hri/hri_rstc_e54.h
new file mode 100644
index 0000000..bf5592a
--- /dev/null
+++ b/hri/hri_rstc_e54.h
@@ -0,0 +1,142 @@
+/**
+ * \file
+ *
+ * \brief SAM RSTC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_RSTC_COMPONENT_
+#ifndef _HRI_RSTC_E54_H_INCLUDED_
+#define _HRI_RSTC_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_RSTC_CRITICAL_SECTIONS)
+#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define RSTC_CRITICAL_SECTION_ENTER()
+#define RSTC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint8_t hri_rstc_bkupexit_reg_t;
+typedef uint8_t hri_rstc_rcause_reg_t;
+
+static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_BODCORE_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODCORE) >> RSTC_RCAUSE_BODCORE_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_BODVDD_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODVDD) >> RSTC_RCAUSE_BODVDD_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_NVM_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_NVM) >> RSTC_RCAUSE_NVM_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_BACKUP_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BACKUP) >> RSTC_RCAUSE_BACKUP_Pos;
+}
+
+static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rstc *)hw)->RCAUSE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw)
+{
+	return ((Rstc *)hw)->RCAUSE.reg;
+}
+
+static inline bool hri_rstc_get_BKUPEXIT_RTC_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_RTC) >> RSTC_BKUPEXIT_RTC_Pos;
+}
+
+static inline bool hri_rstc_get_BKUPEXIT_BBPS_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_BBPS) >> RSTC_BKUPEXIT_BBPS_Pos;
+}
+
+static inline bool hri_rstc_get_BKUPEXIT_HIB_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_HIB) >> RSTC_BKUPEXIT_HIB_Pos;
+}
+
+static inline hri_rstc_bkupexit_reg_t hri_rstc_get_BKUPEXIT_reg(const void *const hw, hri_rstc_bkupexit_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rstc *)hw)->BKUPEXIT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rstc_bkupexit_reg_t hri_rstc_read_BKUPEXIT_reg(const void *const hw)
+{
+	return ((Rstc *)hw)->BKUPEXIT.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_RSTC_E54_H_INCLUDED */
+#endif /* _SAME54_RSTC_COMPONENT_ */
diff --git a/hri/hri_rtc_e54.h b/hri/hri_rtc_e54.h
new file mode 100644
index 0000000..2f2fa3b
--- /dev/null
+++ b/hri/hri_rtc_e54.h
@@ -0,0 +1,10139 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_RTC_COMPONENT_
+#ifndef _HRI_RTC_E54_H_INCLUDED_
+#define _HRI_RTC_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_RTC_CRITICAL_SECTIONS)
+#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define RTC_CRITICAL_SECTION_ENTER()
+#define RTC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_rtcmode0_ctrla_reg_t;
+typedef uint16_t hri_rtcmode0_ctrlb_reg_t;
+typedef uint16_t hri_rtcmode0_intenset_reg_t;
+typedef uint16_t hri_rtcmode0_intflag_reg_t;
+typedef uint16_t hri_rtcmode1_comp_reg_t;
+typedef uint16_t hri_rtcmode1_count_reg_t;
+typedef uint16_t hri_rtcmode1_ctrla_reg_t;
+typedef uint16_t hri_rtcmode1_ctrlb_reg_t;
+typedef uint16_t hri_rtcmode1_intenset_reg_t;
+typedef uint16_t hri_rtcmode1_intflag_reg_t;
+typedef uint16_t hri_rtcmode1_per_reg_t;
+typedef uint16_t hri_rtcmode2_ctrla_reg_t;
+typedef uint16_t hri_rtcmode2_ctrlb_reg_t;
+typedef uint16_t hri_rtcmode2_intenset_reg_t;
+typedef uint16_t hri_rtcmode2_intflag_reg_t;
+typedef uint32_t hri_rtc_bkup_reg_t;
+typedef uint32_t hri_rtc_gp_reg_t;
+typedef uint32_t hri_rtc_tampctrl_reg_t;
+typedef uint32_t hri_rtc_tampid_reg_t;
+typedef uint32_t hri_rtcalarm_alarm_reg_t;
+typedef uint32_t hri_rtcmode0_comp_reg_t;
+typedef uint32_t hri_rtcmode0_count_reg_t;
+typedef uint32_t hri_rtcmode0_evctrl_reg_t;
+typedef uint32_t hri_rtcmode0_syncbusy_reg_t;
+typedef uint32_t hri_rtcmode0_timestamp_reg_t;
+typedef uint32_t hri_rtcmode1_evctrl_reg_t;
+typedef uint32_t hri_rtcmode1_syncbusy_reg_t;
+typedef uint32_t hri_rtcmode1_timestamp_reg_t;
+typedef uint32_t hri_rtcmode2_alarm_reg_t;
+typedef uint32_t hri_rtcmode2_clock_reg_t;
+typedef uint32_t hri_rtcmode2_evctrl_reg_t;
+typedef uint32_t hri_rtcmode2_syncbusy_reg_t;
+typedef uint32_t hri_rtcmode2_timestamp_reg_t;
+typedef uint8_t  hri_rtc_dbgctrl_reg_t;
+typedef uint8_t  hri_rtc_freqcorr_reg_t;
+typedef uint8_t  hri_rtcalarm_mask_reg_t;
+typedef uint8_t  hri_rtcmode2_mask_reg_t;
+
+static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg)
+{
+	while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg)
+{
+	return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg)
+{
+	while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg)
+{
+	return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg)
+{
+	while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg)
+{
+	return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_SECOND_Msk;
+	tmp |= RTC_MODE2_ALARM_SECOND(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk;
+	tmp |= RTC_MODE2_ALARM_MINUTE(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_HOUR_Msk;
+	tmp |= RTC_MODE2_ALARM_HOUR(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_DAY_Msk;
+	tmp |= RTC_MODE2_ALARM_DAY(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MONTH_Msk;
+	tmp |= RTC_MODE2_ALARM_MONTH(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_YEAR_Msk;
+	tmp |= RTC_MODE2_ALARM_YEAR(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_alarm_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+}
+
+static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_rtcmode2_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_mask_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= ~RTC_MODE2_MASK_SEL_Msk;
+	tmp |= RTC_MODE2_MASK_SEL(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_rtcmode2_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcmode2_mask_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+}
+
+static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_SECOND_Msk;
+	tmp |= RTC_MODE2_ALARM_SECOND(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk;
+	tmp |= RTC_MODE2_ALARM_MINUTE(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_HOUR_Msk;
+	tmp |= RTC_MODE2_ALARM_HOUR(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_DAY_Msk;
+	tmp |= RTC_MODE2_ALARM_DAY(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MONTH_Msk;
+	tmp |= RTC_MODE2_ALARM_MONTH(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_YEAR_Msk;
+	tmp |= RTC_MODE2_ALARM_YEAR(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_alarm_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+}
+
+static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_rtcmode2_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_mask_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= ~RTC_MODE2_MASK_SEL_Msk;
+	tmp |= RTC_MODE2_MASK_SEL(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_rtcmode2_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcmode2_mask_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+}
+
+static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const          hw,
+                                                                      hri_rtcmode0_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.INTFLAG.reg;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = mask;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_CMP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_CMP2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_CMP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_CMP3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_CMP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_CMP2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_CMP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_CMP3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF;
+}
+
+static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const          hw,
+                                                                      hri_rtcmode1_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.INTFLAG.reg;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = mask;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_ALARM1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_ALARM1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_ALARM1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_ALARM1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
+}
+
+static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const          hw,
+                                                                      hri_rtcmode2_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.INTFLAG.reg;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = mask;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7;
+}
+
+static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0;
+}
+
+static inline void hri_rtcmode0_set_INTEN_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP1) >> RTC_MODE0_INTENSET_CMP1_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_CMP1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1;
+}
+
+static inline void hri_rtcmode0_set_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_TAMPER) >> RTC_MODE0_INTENSET_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_TAMPER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER;
+}
+
+static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF;
+}
+
+static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = mask;
+}
+
+static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const           hw,
+                                                                     hri_rtcmode0_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.INTENSET.reg;
+}
+
+static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = data;
+	((Rtc *)hw)->MODE0.INTENCLR.reg = ~data;
+}
+
+static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = mask;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7;
+}
+
+static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0;
+}
+
+static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1;
+}
+
+static inline void hri_rtcmode1_set_INTEN_CMP2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_CMP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP2) >> RTC_MODE1_INTENSET_CMP2_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_CMP2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_CMP2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2;
+}
+
+static inline void hri_rtcmode1_set_INTEN_CMP3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_CMP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP3) >> RTC_MODE1_INTENSET_CMP3_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_CMP3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_CMP3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3;
+}
+
+static inline void hri_rtcmode1_set_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_TAMPER) >> RTC_MODE1_INTENSET_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_TAMPER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER;
+}
+
+static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF;
+}
+
+static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = mask;
+}
+
+static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const           hw,
+                                                                     hri_rtcmode1_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.INTENSET.reg;
+}
+
+static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = data;
+	((Rtc *)hw)->MODE1.INTENCLR.reg = ~data;
+}
+
+static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = mask;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7;
+}
+
+static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0;
+}
+
+static inline void hri_rtcmode2_set_INTEN_ALARM1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_ALARM1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM1) >> RTC_MODE2_INTENSET_ALARM1_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_ALARM1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_ALARM1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1;
+}
+
+static inline void hri_rtcmode2_set_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_TAMPER) >> RTC_MODE2_INTENSET_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_TAMPER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER;
+}
+
+static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF;
+}
+
+static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = mask;
+}
+
+static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const           hw,
+                                                                     hri_rtcmode2_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.INTENSET.reg;
+}
+
+static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = data;
+	((Rtc *)hw)->MODE2.INTENCLR.reg = ~data;
+}
+
+static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = mask;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_COMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP1) >> RTC_MODE0_SYNCBUSY_COMP1_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_GP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP0) >> RTC_MODE0_SYNCBUSY_GP0_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_GP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP1) >> RTC_MODE0_SYNCBUSY_GP1_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_GP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP2) >> RTC_MODE0_SYNCBUSY_GP2_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_GP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP3) >> RTC_MODE0_SYNCBUSY_GP3_Pos;
+}
+
+static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const           hw,
+                                                                        hri_rtcmode0_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.SYNCBUSY.reg;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COMP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP2) >> RTC_MODE1_SYNCBUSY_COMP2_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COMP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP3) >> RTC_MODE1_SYNCBUSY_COMP3_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_GP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP0) >> RTC_MODE1_SYNCBUSY_GP0_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_GP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP1) >> RTC_MODE1_SYNCBUSY_GP1_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_GP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP2) >> RTC_MODE1_SYNCBUSY_GP2_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_GP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP3) >> RTC_MODE1_SYNCBUSY_GP3_Pos;
+}
+
+static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const           hw,
+                                                                        hri_rtcmode1_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.SYNCBUSY.reg;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM1) >> RTC_MODE2_SYNCBUSY_ALARM1_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_MASK1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK1) >> RTC_MODE2_SYNCBUSY_MASK1_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_GP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP0) >> RTC_MODE2_SYNCBUSY_GP0_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_GP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP1) >> RTC_MODE2_SYNCBUSY_GP1_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_GP2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP2) >> RTC_MODE2_SYNCBUSY_GP2_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_GP3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP3) >> RTC_MODE2_SYNCBUSY_GP3_Pos;
+}
+
+static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const           hw,
+                                                                        hri_rtcmode2_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.SYNCBUSY.reg;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_COUNT_bf(const void *const            hw,
+                                                                               hri_rtcmode0_timestamp_reg_t mask)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT(mask)) >> RTC_MODE0_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_COUNT_bf(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT_Msk) >> RTC_MODE0_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_reg(const void *const            hw,
+                                                                          hri_rtcmode0_timestamp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.TIMESTAMP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE0.TIMESTAMP.reg;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_COUNT_bf(const void *const            hw,
+                                                                               hri_rtcmode1_timestamp_reg_t mask)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT(mask)) >> RTC_MODE1_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_COUNT_bf(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT_Msk) >> RTC_MODE1_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_reg(const void *const            hw,
+                                                                          hri_rtcmode1_timestamp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.TIMESTAMP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE1.TIMESTAMP.reg;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_SECOND_bf(const void *const            hw,
+                                                                                hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND(mask)) >> RTC_MODE2_TIMESTAMP_SECOND_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_SECOND_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND_Msk) >> RTC_MODE2_TIMESTAMP_SECOND_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MINUTE_bf(const void *const            hw,
+                                                                                hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE(mask)) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MINUTE_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE_Msk) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_HOUR_bf(const void *const            hw,
+                                                                              hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR(mask)) >> RTC_MODE2_TIMESTAMP_HOUR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_HOUR_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR_Msk) >> RTC_MODE2_TIMESTAMP_HOUR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_DAY_bf(const void *const            hw,
+                                                                             hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY(mask)) >> RTC_MODE2_TIMESTAMP_DAY_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_DAY_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY_Msk) >> RTC_MODE2_TIMESTAMP_DAY_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MONTH_bf(const void *const            hw,
+                                                                               hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH(mask)) >> RTC_MODE2_TIMESTAMP_MONTH_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MONTH_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH_Msk) >> RTC_MODE2_TIMESTAMP_MONTH_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_YEAR_bf(const void *const            hw,
+                                                                              hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR(mask)) >> RTC_MODE2_TIMESTAMP_YEAR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_YEAR_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR_Msk) >> RTC_MODE2_TIMESTAMP_YEAR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_reg(const void *const            hw,
+                                                                          hri_rtcmode2_timestamp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.TIMESTAMP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_reg(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return ((Rtc *)hw)->MODE2.TIMESTAMP.reg;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_ENABLE;
+	tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_MATCHCLR;
+	tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_BKTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_BKTRST) >> RTC_MODE0_CTRLA_BKTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_BKTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_BKTRST;
+	tmp |= value << RTC_MODE0_CTRLA_BKTRST_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_BKTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_GPTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_GPTRST) >> RTC_MODE0_CTRLA_GPTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_GPTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_GPTRST;
+	tmp |= value << RTC_MODE0_CTRLA_GPTRST_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_GPTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC;
+	tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const        hw,
+                                                                      hri_rtcmode0_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_MODE_Msk;
+	tmp |= RTC_MODE0_CTRLA_MODE(data);
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const        hw,
+                                                                           hri_rtcmode0_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk;
+	tmp |= RTC_MODE0_CTRLA_PRESCALER(data);
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	return ((Rtc *)hw)->MODE0.CTRLA.reg;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_ENABLE;
+	tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_BKTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_BKTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_BKTRST) >> RTC_MODE1_CTRLA_BKTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_BKTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_BKTRST;
+	tmp |= value << RTC_MODE1_CTRLA_BKTRST_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_BKTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_BKTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_GPTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_GPTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_GPTRST) >> RTC_MODE1_CTRLA_GPTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_GPTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_GPTRST;
+	tmp |= value << RTC_MODE1_CTRLA_GPTRST_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_GPTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_GPTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC;
+	tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const        hw,
+                                                                      hri_rtcmode1_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_MODE_Msk;
+	tmp |= RTC_MODE1_CTRLA_MODE(data);
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const        hw,
+                                                                           hri_rtcmode1_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk;
+	tmp |= RTC_MODE1_CTRLA_PRESCALER(data);
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg = data;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	return ((Rtc *)hw)->MODE1.CTRLA.reg;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_ENABLE;
+	tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_CLKREP;
+	tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_MATCHCLR;
+	tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_BKTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_BKTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_BKTRST) >> RTC_MODE2_CTRLA_BKTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_BKTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_BKTRST;
+	tmp |= value << RTC_MODE2_CTRLA_BKTRST_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_BKTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_BKTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_GPTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_GPTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_GPTRST) >> RTC_MODE2_CTRLA_GPTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_GPTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_GPTRST;
+	tmp |= value << RTC_MODE2_CTRLA_GPTRST_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_GPTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_GPTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC;
+	tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const        hw,
+                                                                      hri_rtcmode2_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_MODE_Msk;
+	tmp |= RTC_MODE2_CTRLA_MODE(data);
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const        hw,
+                                                                           hri_rtcmode2_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk;
+	tmp |= RTC_MODE2_CTRLA_PRESCALER(data);
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg = data;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	return ((Rtc *)hw)->MODE2.CTRLA.reg;
+}
+
+static inline void hri_rtcmode0_set_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_GP0EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_GP0EN) >> RTC_MODE0_CTRLB_GP0EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_GP0EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_GP0EN;
+	tmp |= value << RTC_MODE0_CTRLB_GP0EN_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_GP2EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_GP2EN) >> RTC_MODE0_CTRLB_GP2EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_GP2EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_GP2EN;
+	tmp |= value << RTC_MODE0_CTRLB_GP2EN_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBMAJ) >> RTC_MODE0_CTRLB_DEBMAJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DEBMAJ;
+	tmp |= value << RTC_MODE0_CTRLB_DEBMAJ_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBASYNC) >> RTC_MODE0_CTRLB_DEBASYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DEBASYNC;
+	tmp |= value << RTC_MODE0_CTRLB_DEBASYNC_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_RTCOUT) >> RTC_MODE0_CTRLB_RTCOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_RTCOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_RTCOUT;
+	tmp |= value << RTC_MODE0_CTRLB_RTCOUT_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_DMAEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DMAEN) >> RTC_MODE0_CTRLB_DMAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DMAEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DMAEN;
+	tmp |= value << RTC_MODE0_CTRLB_DMAEN_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_DEBF_bf(const void *const        hw,
+                                                                      hri_rtcmode0_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBF(mask)) >> RTC_MODE0_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DEBF_Msk;
+	tmp |= RTC_MODE0_CTRLB_DEBF(data);
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_DEBF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBF_Msk) >> RTC_MODE0_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_ACTF_bf(const void *const        hw,
+                                                                      hri_rtcmode0_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_ACTF(mask)) >> RTC_MODE0_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_ACTF_Msk;
+	tmp |= RTC_MODE0_CTRLB_ACTF(data);
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_ACTF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_ACTF_Msk) >> RTC_MODE0_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.CTRLB.reg;
+}
+
+static inline void hri_rtcmode1_set_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_GP0EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_GP0EN) >> RTC_MODE1_CTRLB_GP0EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_GP0EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_GP0EN;
+	tmp |= value << RTC_MODE1_CTRLB_GP0EN_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_GP2EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_GP2EN) >> RTC_MODE1_CTRLB_GP2EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_GP2EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_GP2EN;
+	tmp |= value << RTC_MODE1_CTRLB_GP2EN_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBMAJ) >> RTC_MODE1_CTRLB_DEBMAJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DEBMAJ;
+	tmp |= value << RTC_MODE1_CTRLB_DEBMAJ_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBASYNC) >> RTC_MODE1_CTRLB_DEBASYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DEBASYNC;
+	tmp |= value << RTC_MODE1_CTRLB_DEBASYNC_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_RTCOUT) >> RTC_MODE1_CTRLB_RTCOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_RTCOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_RTCOUT;
+	tmp |= value << RTC_MODE1_CTRLB_RTCOUT_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_DMAEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DMAEN) >> RTC_MODE1_CTRLB_DMAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DMAEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DMAEN;
+	tmp |= value << RTC_MODE1_CTRLB_DMAEN_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_DEBF_bf(const void *const        hw,
+                                                                      hri_rtcmode1_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBF(mask)) >> RTC_MODE1_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DEBF_Msk;
+	tmp |= RTC_MODE1_CTRLB_DEBF(data);
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_DEBF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBF_Msk) >> RTC_MODE1_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_ACTF_bf(const void *const        hw,
+                                                                      hri_rtcmode1_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_ACTF(mask)) >> RTC_MODE1_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_ACTF_Msk;
+	tmp |= RTC_MODE1_CTRLB_ACTF(data);
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_ACTF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_ACTF_Msk) >> RTC_MODE1_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.CTRLB.reg;
+}
+
+static inline void hri_rtcmode2_set_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_GP0EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_GP0EN) >> RTC_MODE2_CTRLB_GP0EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_GP0EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_GP0EN;
+	tmp |= value << RTC_MODE2_CTRLB_GP0EN_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_GP2EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_GP2EN) >> RTC_MODE2_CTRLB_GP2EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_GP2EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_GP2EN;
+	tmp |= value << RTC_MODE2_CTRLB_GP2EN_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_GP2EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP2EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBMAJ) >> RTC_MODE2_CTRLB_DEBMAJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DEBMAJ;
+	tmp |= value << RTC_MODE2_CTRLB_DEBMAJ_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBASYNC) >> RTC_MODE2_CTRLB_DEBASYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DEBASYNC;
+	tmp |= value << RTC_MODE2_CTRLB_DEBASYNC_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_RTCOUT) >> RTC_MODE2_CTRLB_RTCOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_RTCOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_RTCOUT;
+	tmp |= value << RTC_MODE2_CTRLB_RTCOUT_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_DMAEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DMAEN) >> RTC_MODE2_CTRLB_DMAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DMAEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DMAEN;
+	tmp |= value << RTC_MODE2_CTRLB_DMAEN_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_DEBF_bf(const void *const        hw,
+                                                                      hri_rtcmode2_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBF(mask)) >> RTC_MODE2_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DEBF_Msk;
+	tmp |= RTC_MODE2_CTRLB_DEBF(data);
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_DEBF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBF_Msk) >> RTC_MODE2_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_ACTF_bf(const void *const        hw,
+                                                                      hri_rtcmode2_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_ACTF(mask)) >> RTC_MODE2_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_ACTF_Msk;
+	tmp |= RTC_MODE2_CTRLB_ACTF(data);
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_ACTF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_ACTF_Msk) >> RTC_MODE2_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.CTRLB.reg;
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO0;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO1;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO2;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO3;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO4;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO5;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO6;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO7;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_CMPEO0;
+	tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO1) >> RTC_MODE0_EVCTRL_CMPEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_CMPEO1;
+	tmp |= value << RTC_MODE0_EVCTRL_CMPEO1_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEREO) >> RTC_MODE0_EVCTRL_TAMPEREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_TAMPEREO;
+	tmp |= value << RTC_MODE0_EVCTRL_TAMPEREO_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_OVFEO;
+	tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEVEI) >> RTC_MODE0_EVCTRL_TAMPEVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_TAMPEVEI;
+	tmp |= value << RTC_MODE0_EVCTRL_TAMPEVEI_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const         hw,
+                                                                    hri_rtcmode0_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.EVCTRL.reg;
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO0;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO1;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO2;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO3;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO4;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO5;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO6;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO7;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_CMPEO0;
+	tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_CMPEO1;
+	tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_CMPEO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_CMPEO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO2) >> RTC_MODE1_EVCTRL_CMPEO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_CMPEO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_CMPEO2;
+	tmp |= value << RTC_MODE1_EVCTRL_CMPEO2_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_CMPEO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_CMPEO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_CMPEO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO3) >> RTC_MODE1_EVCTRL_CMPEO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_CMPEO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_CMPEO3;
+	tmp |= value << RTC_MODE1_EVCTRL_CMPEO3_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_CMPEO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEREO) >> RTC_MODE1_EVCTRL_TAMPEREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_TAMPEREO;
+	tmp |= value << RTC_MODE1_EVCTRL_TAMPEREO_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_OVFEO;
+	tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEVEI) >> RTC_MODE1_EVCTRL_TAMPEVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_TAMPEVEI;
+	tmp |= value << RTC_MODE1_EVCTRL_TAMPEVEI_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const         hw,
+                                                                    hri_rtcmode1_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.EVCTRL.reg;
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO0;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO1;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO2;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO3;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO4;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO5;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO6;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO7;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0;
+	tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_ALARMEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO1) >> RTC_MODE2_EVCTRL_ALARMEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_ALARMEO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_ALARMEO1;
+	tmp |= value << RTC_MODE2_EVCTRL_ALARMEO1_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEREO) >> RTC_MODE2_EVCTRL_TAMPEREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_TAMPEREO;
+	tmp |= value << RTC_MODE2_EVCTRL_TAMPEREO_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_OVFEO;
+	tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEVEI) >> RTC_MODE2_EVCTRL_TAMPEVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_TAMPEVEI;
+	tmp |= value << RTC_MODE2_EVCTRL_TAMPEVEI_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const         hw,
+                                                                    hri_rtcmode2_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.EVCTRL.reg;
+}
+
+static inline void hri_rtc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+	tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+	tmp &= ~RTC_DBGCTRL_DBGRUN;
+	tmp |= value << RTC_DBGCTRL_DBGRUN_Pos;
+	((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_dbgctrl_reg_t hri_rtc_get_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_dbgctrl_reg_t hri_rtc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+}
+
+static inline void hri_rtc_set_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_FREQCORR_SIGN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_FREQCORR_SIGN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp &= ~RTC_FREQCORR_SIGN;
+	tmp |= value << RTC_FREQCORR_SIGN_Pos;
+	((Rtc *)hw)->MODE0.FREQCORR.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp &= ~RTC_FREQCORR_VALUE_Msk;
+	tmp |= RTC_FREQCORR_VALUE(data);
+	((Rtc *)hw)->MODE0.FREQCORR.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_VALUE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	uint8_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	return ((Rtc *)hw)->MODE0.FREQCORR.reg;
+}
+
+static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const        hw,
+                                                                       hri_rtcmode0_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp &= ~RTC_MODE0_COUNT_COUNT_Msk;
+	tmp |= RTC_MODE0_COUNT_COUNT(data);
+	((Rtc *)hw)->MODE0.COUNT.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE0.COUNT.reg;
+}
+
+static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const        hw,
+                                                                       hri_rtcmode1_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp &= ~RTC_MODE1_COUNT_COUNT_Msk;
+	tmp |= RTC_MODE1_COUNT_COUNT(data);
+	((Rtc *)hw)->MODE1.COUNT.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg |= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg = data;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg ^= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE1.COUNT.reg;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const        hw,
+                                                                        hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk;
+	tmp |= RTC_MODE2_CLOCK_SECOND(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const        hw,
+                                                                        hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk;
+	tmp |= RTC_MODE2_CLOCK_MINUTE(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const        hw,
+                                                                      hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk;
+	tmp |= RTC_MODE2_CLOCK_HOUR(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const        hw,
+                                                                     hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_DAY_Msk;
+	tmp |= RTC_MODE2_CLOCK_DAY(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const        hw,
+                                                                       hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk;
+	tmp |= RTC_MODE2_CLOCK_MONTH(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const        hw,
+                                                                      hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk;
+	tmp |= RTC_MODE2_CLOCK_YEAR(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg = data;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return ((Rtc *)hw)->MODE2.CLOCK.reg;
+}
+
+static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp &= ~RTC_MODE1_PER_PER_Msk;
+	tmp |= RTC_MODE1_PER_PER(data);
+	((Rtc *)hw)->MODE1.PER.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg |= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg = data;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg ^= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	return ((Rtc *)hw)->MODE1.PER.reg;
+}
+
+static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index,
+                                                                    hri_rtcmode0_comp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp &= ~RTC_MODE0_COMP_COMP_Msk;
+	tmp |= RTC_MODE0_COMP_COMP(data);
+	((Rtc *)hw)->MODE0.COMP[index].reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index,
+                                                                hri_rtcmode0_comp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1);
+	return ((Rtc *)hw)->MODE0.COMP[index].reg;
+}
+
+static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask);
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index,
+                                                                    hri_rtcmode1_comp_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp &= ~RTC_MODE1_COMP_COMP_Msk;
+	tmp |= RTC_MODE1_COMP_COMP(data);
+	((Rtc *)hw)->MODE1.COMP[index].reg = tmp;
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask);
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask);
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg |= mask;
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index,
+                                                                hri_rtcmode1_comp_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg = data;
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg ^= mask;
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index)
+{
+	hri_rtcmode1_wait_for_sync(
+	    hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3);
+	return ((Rtc *)hw)->MODE1.COMP[index].reg;
+}
+
+static inline void hri_rtc_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg |= RTC_GP_GP(mask);
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_get_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp &= ~RTC_GP_GP_Msk;
+	tmp |= RTC_GP_GP(data);
+	((Rtc *)hw)->MODE0.GP[index].reg = tmp;
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg &= ~RTC_GP_GP(mask);
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg ^= RTC_GP_GP(mask);
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_read_GP_GP_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg |= mask;
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_get_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg = data;
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg ^= mask;
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_read_GP_reg(const void *const hw, uint8_t index)
+{
+	hri_rtcmode0_wait_for_sync(
+	    hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3);
+	return ((Rtc *)hw)->MODE0.GP[index].reg;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL0;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL1;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL2;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL3;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL4;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC0;
+	tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC1;
+	tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC2;
+	tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC3;
+	tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC4;
+	tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN0ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN0ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN1ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN1ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN2ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN2ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN3ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN3ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN4ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN4ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID0;
+	tmp |= value << RTC_TAMPID_TAMPID0_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID1;
+	tmp |= value << RTC_TAMPID_TAMPID1_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID2;
+	tmp |= value << RTC_TAMPID_TAMPID2_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID3;
+	tmp |= value << RTC_TAMPID_TAMPID3_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID4;
+	tmp |= value << RTC_TAMPID_TAMPID4_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPEVT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPEVT;
+	tmp |= value << RTC_TAMPID_TAMPEVT_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPEVT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampid_reg_t hri_rtc_get_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampid_reg_t hri_rtc_read_TAMPID_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.TAMPID.reg;
+}
+
+static inline void hri_rtc_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg |= RTC_BKUP_BKUP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp &= ~RTC_BKUP_BKUP_Msk;
+	tmp |= RTC_BKUP_BKUP(data);
+	((Rtc *)hw)->MODE0.BKUP[index].reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg ^= RTC_BKUP_BKUP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_BKUP_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_reg(const void *const hw, uint8_t index)
+{
+	return ((Rtc *)hw)->MODE0.BKUP[index].reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b)
+#define hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode2_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b)
+#define hri_rtcmode2_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b)
+#define hri_rtcmode2_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b)
+#define hri_rtcmode2_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b)
+#define hri_rtcmode2_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b)
+#define hri_rtcmode2_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a)
+#define hri_rtcmode2_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode2_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode2_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b)
+#define hri_rtcmode2_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode2_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode2_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode2_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode2_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode2_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode2_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode2_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a)
+#define hri_rtcmode2_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b)
+#define hri_rtcmode2_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b)
+#define hri_rtcmode2_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b)
+#define hri_rtcmode2_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b)
+#define hri_rtcmode2_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b)
+#define hri_rtcmode2_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a)
+#define hri_rtcmode2_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c)
+#define hri_rtcmode2_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c)
+#define hri_rtcmode2_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c)
+#define hri_rtcmode2_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c)
+#define hri_rtcmode2_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c)
+#define hri_rtcmode2_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b)
+#define hri_rtcmode2_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c)
+#define hri_rtcmode2_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c)
+#define hri_rtcmode2_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c)
+#define hri_rtcmode2_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c)
+#define hri_rtcmode2_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c)
+#define hri_rtcmode2_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b)
+#define hri_rtcmode2_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode2_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode2_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode2_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode2_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode2_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode2_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode2_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a)
+#define hri_rtcmode2_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode2_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode2_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode2_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode2_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a)
+#define hri_rtcmode2_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode2_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode2_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode2_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode2_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a)
+#define hri_rtcmode2_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode2_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode2_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode2_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode2_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a)
+#define hri_rtcmode2_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode2_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode2_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode2_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode2_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a)
+#define hri_rtcmode2_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b)
+#define hri_rtcmode2_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b)
+#define hri_rtcmode2_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b)
+#define hri_rtcmode2_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b)
+#define hri_rtcmode2_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b)
+#define hri_rtcmode2_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a)
+#define hri_rtcmode2_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode2_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode2_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b)
+#define hri_rtcmode2_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode2_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode2_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode2_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode2_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b)
+#define hri_rtcmode2_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode2_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode2_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode2_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode2_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b)
+#define hri_rtcmode2_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode2_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode2_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode2_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode2_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b)
+#define hri_rtcmode2_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode2_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode2_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode2_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode2_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b)
+#define hri_rtcmode2_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode2_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode2_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode2_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode2_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b)
+#define hri_rtcmode2_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode2_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode2_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b)
+#define hri_rtcmode2_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b)
+#define hri_rtcmode2_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b)
+#define hri_rtcmode2_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b)
+#define hri_rtcmode2_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b)
+#define hri_rtcmode2_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a)
+#define hri_rtcmode2_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode2_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode2_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode2_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode2_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode2_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b)
+#define hri_rtcmode2_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c)
+#define hri_rtcmode2_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c)
+#define hri_rtcmode2_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c)
+#define hri_rtcmode2_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c)
+#define hri_rtcmode2_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c)
+#define hri_rtcmode2_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b)
+#define hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b)
+#define hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode0_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b)
+#define hri_rtcmode0_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b)
+#define hri_rtcmode0_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b)
+#define hri_rtcmode0_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b)
+#define hri_rtcmode0_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b)
+#define hri_rtcmode0_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a)
+#define hri_rtcmode0_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode0_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode0_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b)
+#define hri_rtcmode0_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode0_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode0_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode0_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode0_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode0_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode0_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode0_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a)
+#define hri_rtcmode0_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b)
+#define hri_rtcmode0_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b)
+#define hri_rtcmode0_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b)
+#define hri_rtcmode0_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b)
+#define hri_rtcmode0_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b)
+#define hri_rtcmode0_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a)
+#define hri_rtcmode0_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c)
+#define hri_rtcmode0_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c)
+#define hri_rtcmode0_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c)
+#define hri_rtcmode0_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c)
+#define hri_rtcmode0_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c)
+#define hri_rtcmode0_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b)
+#define hri_rtcmode0_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c)
+#define hri_rtcmode0_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c)
+#define hri_rtcmode0_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c)
+#define hri_rtcmode0_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c)
+#define hri_rtcmode0_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c)
+#define hri_rtcmode0_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b)
+#define hri_rtcmode0_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode0_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode0_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode0_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode0_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode0_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode0_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode0_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a)
+#define hri_rtcmode0_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode0_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode0_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode0_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode0_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a)
+#define hri_rtcmode0_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode0_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode0_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode0_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode0_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a)
+#define hri_rtcmode0_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode0_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode0_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode0_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode0_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a)
+#define hri_rtcmode0_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode0_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode0_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode0_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode0_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a)
+#define hri_rtcmode0_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b)
+#define hri_rtcmode0_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b)
+#define hri_rtcmode0_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b)
+#define hri_rtcmode0_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b)
+#define hri_rtcmode0_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b)
+#define hri_rtcmode0_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a)
+#define hri_rtcmode0_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode0_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode0_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b)
+#define hri_rtcmode0_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode0_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode0_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode0_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode0_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b)
+#define hri_rtcmode0_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode0_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode0_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode0_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode0_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b)
+#define hri_rtcmode0_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode0_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode0_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode0_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode0_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b)
+#define hri_rtcmode0_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode0_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode0_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode0_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode0_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b)
+#define hri_rtcmode0_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode0_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode0_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode0_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode0_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b)
+#define hri_rtcmode0_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode0_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode0_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b)
+#define hri_rtcmode0_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b)
+#define hri_rtcmode0_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b)
+#define hri_rtcmode0_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b)
+#define hri_rtcmode0_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b)
+#define hri_rtcmode0_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a)
+#define hri_rtcmode0_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode0_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode0_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode0_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode0_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode0_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b)
+#define hri_rtcmode0_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c)
+#define hri_rtcmode0_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c)
+#define hri_rtcmode0_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c)
+#define hri_rtcmode0_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c)
+#define hri_rtcmode0_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c)
+#define hri_rtcmode0_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b)
+#define hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b)
+#define hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a)
+#define hri_rtcmode1_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b)
+#define hri_rtcmode1_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b)
+#define hri_rtcmode1_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b)
+#define hri_rtcmode1_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b)
+#define hri_rtcmode1_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b)
+#define hri_rtcmode1_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a)
+#define hri_rtcmode1_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode1_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode1_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b)
+#define hri_rtcmode1_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode1_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a)
+#define hri_rtcmode1_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode1_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode1_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode1_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode1_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b)
+#define hri_rtcmode1_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a)
+#define hri_rtcmode1_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b)
+#define hri_rtcmode1_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b)
+#define hri_rtcmode1_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b)
+#define hri_rtcmode1_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b)
+#define hri_rtcmode1_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b)
+#define hri_rtcmode1_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a)
+#define hri_rtcmode1_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c)
+#define hri_rtcmode1_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c)
+#define hri_rtcmode1_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c)
+#define hri_rtcmode1_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c)
+#define hri_rtcmode1_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c)
+#define hri_rtcmode1_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b)
+#define hri_rtcmode1_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c)
+#define hri_rtcmode1_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c)
+#define hri_rtcmode1_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c)
+#define hri_rtcmode1_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c)
+#define hri_rtcmode1_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c)
+#define hri_rtcmode1_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b)
+#define hri_rtcmode1_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode1_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode1_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a)
+#define hri_rtcmode1_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode1_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode1_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode1_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b)
+#define hri_rtcmode1_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a)
+#define hri_rtcmode1_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode1_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode1_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode1_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b)
+#define hri_rtcmode1_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a)
+#define hri_rtcmode1_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode1_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode1_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode1_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b)
+#define hri_rtcmode1_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a)
+#define hri_rtcmode1_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode1_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode1_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode1_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b)
+#define hri_rtcmode1_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a)
+#define hri_rtcmode1_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode1_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode1_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode1_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b)
+#define hri_rtcmode1_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a)
+#define hri_rtcmode1_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b)
+#define hri_rtcmode1_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b)
+#define hri_rtcmode1_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b)
+#define hri_rtcmode1_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b)
+#define hri_rtcmode1_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b)
+#define hri_rtcmode1_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a)
+#define hri_rtcmode1_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode1_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode1_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b)
+#define hri_rtcmode1_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode1_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a)
+#define hri_rtcmode1_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode1_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode1_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b)
+#define hri_rtcmode1_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode1_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a)
+#define hri_rtcmode1_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode1_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode1_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b)
+#define hri_rtcmode1_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode1_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a)
+#define hri_rtcmode1_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode1_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode1_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b)
+#define hri_rtcmode1_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode1_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a)
+#define hri_rtcmode1_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode1_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode1_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b)
+#define hri_rtcmode1_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode1_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a)
+#define hri_rtcmode1_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode1_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode1_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b)
+#define hri_rtcmode1_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode1_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a)
+#define hri_rtcmode1_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b)
+#define hri_rtcmode1_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b)
+#define hri_rtcmode1_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b)
+#define hri_rtcmode1_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b)
+#define hri_rtcmode1_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b)
+#define hri_rtcmode1_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a)
+#define hri_rtcmode1_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode1_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode1_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode1_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode1_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c)
+#define hri_rtcmode1_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b)
+#define hri_rtcmode1_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c)
+#define hri_rtcmode1_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c)
+#define hri_rtcmode1_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c)
+#define hri_rtcmode1_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c)
+#define hri_rtcmode1_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c)
+#define hri_rtcmode1_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_RTC_E54_H_INCLUDED */
+#endif /* _SAME54_RTC_COMPONENT_ */
diff --git a/hri/hri_sdhc_e54.h b/hri/hri_sdhc_e54.h
new file mode 100644
index 0000000..0b7f609
--- /dev/null
+++ b/hri/hri_sdhc_e54.h
@@ -0,0 +1,7477 @@
+/**
+ * \file
+ *
+ * \brief SAM SDHC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_SDHC_COMPONENT_
+#ifndef _HRI_SDHC_E54_H_INCLUDED_
+#define _HRI_SDHC_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SDHC_CRITICAL_SECTIONS)
+#define SDHC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SDHC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SDHC_CRITICAL_SECTION_ENTER()
+#define SDHC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_sdhc_acesr_reg_t;
+typedef uint16_t hri_sdhc_bcr_reg_t;
+typedef uint16_t hri_sdhc_bsr_reg_t;
+typedef uint16_t hri_sdhc_ccr_reg_t;
+typedef uint16_t hri_sdhc_cr_reg_t;
+typedef uint16_t hri_sdhc_eisier_reg_t;
+typedef uint16_t hri_sdhc_eister_reg_t;
+typedef uint16_t hri_sdhc_eistr_reg_t;
+typedef uint16_t hri_sdhc_feraces_reg_t;
+typedef uint16_t hri_sdhc_fereis_reg_t;
+typedef uint16_t hri_sdhc_hc2r_reg_t;
+typedef uint16_t hri_sdhc_hcvr_reg_t;
+typedef uint16_t hri_sdhc_nisier_reg_t;
+typedef uint16_t hri_sdhc_nister_reg_t;
+typedef uint16_t hri_sdhc_nistr_reg_t;
+typedef uint16_t hri_sdhc_pvr_reg_t;
+typedef uint16_t hri_sdhc_sisr_reg_t;
+typedef uint16_t hri_sdhc_tmr_reg_t;
+typedef uint32_t hri_sdhc_acr_reg_t;
+typedef uint32_t hri_sdhc_arg1r_reg_t;
+typedef uint32_t hri_sdhc_asar_reg_t;
+typedef uint32_t hri_sdhc_bdpr_reg_t;
+typedef uint32_t hri_sdhc_ca0r_reg_t;
+typedef uint32_t hri_sdhc_ca1r_reg_t;
+typedef uint32_t hri_sdhc_cacr_reg_t;
+typedef uint32_t hri_sdhc_cc2r_reg_t;
+typedef uint32_t hri_sdhc_mccar_reg_t;
+typedef uint32_t hri_sdhc_psr_reg_t;
+typedef uint32_t hri_sdhc_rr_reg_t;
+typedef uint32_t hri_sdhc_ssar_reg_t;
+typedef uint8_t  hri_sdhc_aesr_reg_t;
+typedef uint8_t  hri_sdhc_bgcr_reg_t;
+typedef uint8_t  hri_sdhc_dbgr_reg_t;
+typedef uint8_t  hri_sdhc_hc1r_reg_t;
+typedef uint8_t  hri_sdhc_mc1r_reg_t;
+typedef uint8_t  hri_sdhc_mc2r_reg_t;
+typedef uint8_t  hri_sdhc_pcr_reg_t;
+typedef uint8_t  hri_sdhc_srr_reg_t;
+typedef uint8_t  hri_sdhc_tcr_reg_t;
+typedef uint8_t  hri_sdhc_wcr_reg_t;
+
+static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_CMDRESP_bf(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask)
+{
+	return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP(mask)) >> SDHC_RR_CMDRESP_Pos;
+}
+
+static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_CMDRESP_bf(const void *const hw, uint8_t index)
+{
+	return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP_Msk) >> SDHC_RR_CMDRESP_Pos;
+}
+
+static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_reg(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->RR[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_reg(const void *const hw, uint8_t index)
+{
+	return ((Sdhc *)hw)->RR[index].reg;
+}
+
+static inline bool hri_sdhc_get_PSR_CMDINHC_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHC) >> SDHC_PSR_CMDINHC_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_CMDINHD_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHD) >> SDHC_PSR_CMDINHD_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_DLACT_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DLACT) >> SDHC_PSR_DLACT_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_RTREQ_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTREQ) >> SDHC_PSR_RTREQ_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_WTACT_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WTACT) >> SDHC_PSR_WTACT_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_RTACT_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTACT) >> SDHC_PSR_RTACT_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_BUFWREN_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFWREN) >> SDHC_PSR_BUFWREN_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_BUFRDEN_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFRDEN) >> SDHC_PSR_BUFRDEN_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_CARDINS_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDINS) >> SDHC_PSR_CARDINS_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_CARDSS_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDSS) >> SDHC_PSR_CARDSS_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_CARDDPL_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDDPL) >> SDHC_PSR_CARDDPL_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_WRPPL_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WRPPL) >> SDHC_PSR_WRPPL_Pos;
+}
+
+static inline bool hri_sdhc_get_PSR_CMDLL_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDLL) >> SDHC_PSR_CMDLL_Pos;
+}
+
+static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_DATLL_bf(const void *const hw, hri_sdhc_psr_reg_t mask)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL(mask)) >> SDHC_PSR_DATLL_Pos;
+}
+
+static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_DATLL_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL_Msk) >> SDHC_PSR_DATLL_Pos;
+}
+
+static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_reg(const void *const hw, hri_sdhc_psr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->PSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->PSR.reg;
+}
+
+static inline bool hri_sdhc_get_ACESR_ACMD12NE_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMD12NE) >> SDHC_ACESR_ACMD12NE_Pos;
+}
+
+static inline bool hri_sdhc_get_ACESR_ACMDTEO_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDTEO) >> SDHC_ACESR_ACMDTEO_Pos;
+}
+
+static inline bool hri_sdhc_get_ACESR_ACMDCRC_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDCRC) >> SDHC_ACESR_ACMDCRC_Pos;
+}
+
+static inline bool hri_sdhc_get_ACESR_ACMDEND_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDEND) >> SDHC_ACESR_ACMDEND_Pos;
+}
+
+static inline bool hri_sdhc_get_ACESR_ACMDIDX_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDIDX) >> SDHC_ACESR_ACMDIDX_Pos;
+}
+
+static inline bool hri_sdhc_get_ACESR_CMDNI_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_CMDNI) >> SDHC_ACESR_CMDNI_Pos;
+}
+
+static inline hri_sdhc_acesr_reg_t hri_sdhc_get_ACESR_reg(const void *const hw, hri_sdhc_acesr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->ACESR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_acesr_reg_t hri_sdhc_read_ACESR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->ACESR.reg;
+}
+
+static inline bool hri_sdhc_get_CA0R_TEOCLKU_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKU) >> SDHC_CA0R_TEOCLKU_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_ED8SUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ED8SUP) >> SDHC_CA0R_ED8SUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_ADMA2SUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ADMA2SUP) >> SDHC_CA0R_ADMA2SUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_HSSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_HSSUP) >> SDHC_CA0R_HSSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_SDMASUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SDMASUP) >> SDHC_CA0R_SDMASUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_SRSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SRSUP) >> SDHC_CA0R_SRSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_V33VSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V33VSUP) >> SDHC_CA0R_V33VSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_V30VSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V30VSUP) >> SDHC_CA0R_V30VSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_V18VSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V18VSUP) >> SDHC_CA0R_V18VSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_SB64SUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SB64SUP) >> SDHC_CA0R_SB64SUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA0R_ASINTSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ASINTSUP) >> SDHC_CA0R_ASINTSUP_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_TEOCLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF(mask)) >> SDHC_CA0R_TEOCLKF_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_TEOCLKF_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF_Msk) >> SDHC_CA0R_TEOCLKF_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_BASECLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF(mask)) >> SDHC_CA0R_BASECLKF_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_BASECLKF_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF_Msk) >> SDHC_CA0R_BASECLKF_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_MAXBLKL_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL(mask)) >> SDHC_CA0R_MAXBLKL_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_MAXBLKL_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL_Msk) >> SDHC_CA0R_MAXBLKL_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_SLTYPE_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE(mask)) >> SDHC_CA0R_SLTYPE_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_SLTYPE_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE_Msk) >> SDHC_CA0R_SLTYPE_Pos;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_reg(const void *const hw, hri_sdhc_ca0r_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CA0R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->CA0R.reg;
+}
+
+static inline bool hri_sdhc_get_CA1R_SDR50SUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR50SUP) >> SDHC_CA1R_SDR50SUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA1R_SDR104SUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR104SUP) >> SDHC_CA1R_SDR104SUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA1R_DDR50SUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DDR50SUP) >> SDHC_CA1R_DDR50SUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA1R_DRVASUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVASUP) >> SDHC_CA1R_DRVASUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA1R_DRVCSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVCSUP) >> SDHC_CA1R_DRVCSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA1R_DRVDSUP_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVDSUP) >> SDHC_CA1R_DRVDSUP_Pos;
+}
+
+static inline bool hri_sdhc_get_CA1R_TSDR50_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TSDR50) >> SDHC_CA1R_TSDR50_Pos;
+}
+
+static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_TCNTRT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT(mask)) >> SDHC_CA1R_TCNTRT_Pos;
+}
+
+static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_TCNTRT_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT_Msk) >> SDHC_CA1R_TCNTRT_Pos;
+}
+
+static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_CLKMULT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT(mask)) >> SDHC_CA1R_CLKMULT_Pos;
+}
+
+static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_CLKMULT_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT_Msk) >> SDHC_CA1R_CLKMULT_Pos;
+}
+
+static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_reg(const void *const hw, hri_sdhc_ca1r_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CA1R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->CA1R.reg;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR33V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask)
+{
+	return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V(mask)) >> SDHC_MCCAR_MAXCUR33V_Pos;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR33V_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V_Msk) >> SDHC_MCCAR_MAXCUR33V_Pos;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR30V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask)
+{
+	return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V(mask)) >> SDHC_MCCAR_MAXCUR30V_Pos;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR30V_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V_Msk) >> SDHC_MCCAR_MAXCUR30V_Pos;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR18V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask)
+{
+	return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V(mask)) >> SDHC_MCCAR_MAXCUR18V_Pos;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR18V_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V_Msk) >> SDHC_MCCAR_MAXCUR18V_Pos;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_reg(const void *const hw, hri_sdhc_mccar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->MCCAR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->MCCAR.reg;
+}
+
+static inline bool hri_sdhc_get_AESR_LMIS_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_LMIS) >> SDHC_AESR_LMIS_Pos;
+}
+
+static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_ERRST_bf(const void *const hw, hri_sdhc_aesr_reg_t mask)
+{
+	return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST(mask)) >> SDHC_AESR_ERRST_Pos;
+}
+
+static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_ERRST_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST_Msk) >> SDHC_AESR_ERRST_Pos;
+}
+
+static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_reg(const void *const hw, hri_sdhc_aesr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->AESR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->AESR.reg;
+}
+
+static inline bool hri_sdhc_get_SISR_INTSSL_bit(const void *const hw)
+{
+	return (((Sdhc *)hw)->SISR.reg & SDHC_SISR_INTSSL_Msk) >> SDHC_SISR_INTSSL_Pos;
+}
+
+static inline hri_sdhc_sisr_reg_t hri_sdhc_get_SISR_reg(const void *const hw, hri_sdhc_sisr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->SISR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_sisr_reg_t hri_sdhc_read_SISR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->SISR.reg;
+}
+
+static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_SVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask)
+{
+	return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER(mask)) >> SDHC_HCVR_SVER_Pos;
+}
+
+static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_SVER_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER_Msk) >> SDHC_HCVR_SVER_Pos;
+}
+
+static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_VVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask)
+{
+	return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER(mask)) >> SDHC_HCVR_VVER_Pos;
+}
+
+static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_VVER_bf(const void *const hw)
+{
+	return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER_Msk) >> SDHC_HCVR_VVER_Pos;
+}
+
+static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_reg(const void *const hw, hri_sdhc_hcvr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HCVR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->HCVR.reg;
+}
+
+static inline void hri_sdhc_set_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_ADDR(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp = (tmp & SDHC_SSAR_ADDR(mask)) >> SDHC_SSAR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp &= ~SDHC_SSAR_ADDR_Msk;
+	tmp |= SDHC_SSAR_ADDR(data);
+	((Sdhc *)hw)->SSAR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_ADDR(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_ADDR(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp = (tmp & SDHC_SSAR_ADDR_Msk) >> SDHC_SSAR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_CMD23_ARG2(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp = (tmp & SDHC_SSAR_CMD23_ARG2(mask)) >> SDHC_SSAR_CMD23_ARG2_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp &= ~SDHC_SSAR_CMD23_ARG2_Msk;
+	tmp |= SDHC_SSAR_CMD23_ARG2(data);
+	((Sdhc *)hw)->SSAR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_CMD23_ARG2(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_CMD23_ARG2(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_CMD23_ARG2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp = (tmp & SDHC_SSAR_CMD23_ARG2_Msk) >> SDHC_SSAR_CMD23_ARG2_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->SSAR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SSAR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->SSAR.reg;
+}
+
+static inline void hri_sdhc_set_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BLOCKSIZE(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp = (tmp & SDHC_BSR_BLOCKSIZE(mask)) >> SDHC_BSR_BLOCKSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp &= ~SDHC_BSR_BLOCKSIZE_Msk;
+	tmp |= SDHC_BSR_BLOCKSIZE(data);
+	((Sdhc *)hw)->BSR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BLOCKSIZE(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BLOCKSIZE(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BLOCKSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp = (tmp & SDHC_BSR_BLOCKSIZE_Msk) >> SDHC_BSR_BLOCKSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BOUNDARY(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp = (tmp & SDHC_BSR_BOUNDARY(mask)) >> SDHC_BSR_BOUNDARY_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp &= ~SDHC_BSR_BOUNDARY_Msk;
+	tmp |= SDHC_BSR_BOUNDARY(data);
+	((Sdhc *)hw)->BSR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BOUNDARY(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BOUNDARY(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BOUNDARY_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp = (tmp & SDHC_BSR_BOUNDARY_Msk) >> SDHC_BSR_BOUNDARY_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BSR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->BSR.reg;
+}
+
+static inline void hri_sdhc_set_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg |= SDHC_BCR_BCNT(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BCR.reg;
+	tmp = (tmp & SDHC_BCR_BCNT(mask)) >> SDHC_BCR_BCNT_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BCR.reg;
+	tmp &= ~SDHC_BCR_BCNT_Msk;
+	tmp |= SDHC_BCR_BCNT(data);
+	((Sdhc *)hw)->BCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg &= ~SDHC_BCR_BCNT(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg ^= SDHC_BCR_BCNT(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_BCNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BCR.reg;
+	tmp = (tmp & SDHC_BCR_BCNT_Msk) >> SDHC_BCR_BCNT_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->BCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BCR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->BCR.reg;
+}
+
+static inline void hri_sdhc_set_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg |= SDHC_ARG1R_ARG(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ARG1R.reg;
+	tmp = (tmp & SDHC_ARG1R_ARG(mask)) >> SDHC_ARG1R_ARG_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->ARG1R.reg;
+	tmp &= ~SDHC_ARG1R_ARG_Msk;
+	tmp |= SDHC_ARG1R_ARG(data);
+	((Sdhc *)hw)->ARG1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg &= ~SDHC_ARG1R_ARG(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg ^= SDHC_ARG1R_ARG(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_ARG_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ARG1R.reg;
+	tmp = (tmp & SDHC_ARG1R_ARG_Msk) >> SDHC_ARG1R_ARG_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ARG1R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ARG1R.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->ARG1R.reg;
+}
+
+static inline void hri_sdhc_set_TMR_DMAEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DMAEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_TMR_DMAEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp = (tmp & SDHC_TMR_DMAEN) >> SDHC_TMR_DMAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_TMR_DMAEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp &= ~SDHC_TMR_DMAEN;
+	tmp |= value << SDHC_TMR_DMAEN_Pos;
+	((Sdhc *)hw)->TMR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TMR_DMAEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DMAEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TMR_DMAEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DMAEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_TMR_BCEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg |= SDHC_TMR_BCEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_TMR_BCEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp = (tmp & SDHC_TMR_BCEN) >> SDHC_TMR_BCEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_TMR_BCEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp &= ~SDHC_TMR_BCEN;
+	tmp |= value << SDHC_TMR_BCEN_Pos;
+	((Sdhc *)hw)->TMR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TMR_BCEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_BCEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TMR_BCEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_BCEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_TMR_DTDSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DTDSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_TMR_DTDSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp = (tmp & SDHC_TMR_DTDSEL) >> SDHC_TMR_DTDSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_TMR_DTDSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp &= ~SDHC_TMR_DTDSEL;
+	tmp |= value << SDHC_TMR_DTDSEL_Pos;
+	((Sdhc *)hw)->TMR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TMR_DTDSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DTDSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TMR_DTDSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DTDSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_TMR_MSBSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg |= SDHC_TMR_MSBSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_TMR_MSBSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp = (tmp & SDHC_TMR_MSBSEL) >> SDHC_TMR_MSBSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_TMR_MSBSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp &= ~SDHC_TMR_MSBSEL;
+	tmp |= value << SDHC_TMR_MSBSEL_Pos;
+	((Sdhc *)hw)->TMR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TMR_MSBSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_MSBSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TMR_MSBSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_MSBSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg |= SDHC_TMR_ACMDEN(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp = (tmp & SDHC_TMR_ACMDEN(mask)) >> SDHC_TMR_ACMDEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp &= ~SDHC_TMR_ACMDEN_Msk;
+	tmp |= SDHC_TMR_ACMDEN(data);
+	((Sdhc *)hw)->TMR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_ACMDEN(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_ACMDEN(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_ACMDEN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp = (tmp & SDHC_TMR_ACMDEN_Msk) >> SDHC_TMR_ACMDEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->TMR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TMR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->TMR.reg;
+}
+
+static inline void hri_sdhc_set_CR_CMDCCEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDCCEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CR_CMDCCEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_CMDCCEN) >> SDHC_CR_CMDCCEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CR_CMDCCEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= ~SDHC_CR_CMDCCEN;
+	tmp |= value << SDHC_CR_CMDCCEN_Pos;
+	((Sdhc *)hw)->CR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_CMDCCEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDCCEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_CMDCCEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDCCEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CR_CMDICEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDICEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CR_CMDICEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_CMDICEN) >> SDHC_CR_CMDICEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CR_CMDICEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= ~SDHC_CR_CMDICEN;
+	tmp |= value << SDHC_CR_CMDICEN_Pos;
+	((Sdhc *)hw)->CR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_CMDICEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDICEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_CMDICEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDICEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CR_DPSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= SDHC_CR_DPSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CR_DPSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_DPSEL) >> SDHC_CR_DPSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CR_DPSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= ~SDHC_CR_DPSEL;
+	tmp |= value << SDHC_CR_DPSEL_Pos;
+	((Sdhc *)hw)->CR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_DPSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~SDHC_CR_DPSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_DPSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= SDHC_CR_DPSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= SDHC_CR_RESPTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_RESPTYP(mask)) >> SDHC_CR_RESPTYP_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= ~SDHC_CR_RESPTYP_Msk;
+	tmp |= SDHC_CR_RESPTYP(data);
+	((Sdhc *)hw)->CR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~SDHC_CR_RESPTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= SDHC_CR_RESPTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_RESPTYP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_RESPTYP_Msk) >> SDHC_CR_RESPTYP_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_CMDTYP(mask)) >> SDHC_CR_CMDTYP_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= ~SDHC_CR_CMDTYP_Msk;
+	tmp |= SDHC_CR_CMDTYP(data);
+	((Sdhc *)hw)->CR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDTYP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_CMDTYP_Msk) >> SDHC_CR_CMDTYP_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDIDX(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_CMDIDX(mask)) >> SDHC_CR_CMDIDX_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= ~SDHC_CR_CMDIDX_Msk;
+	tmp |= SDHC_CR_CMDIDX(data);
+	((Sdhc *)hw)->CR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDIDX(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDIDX(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDIDX_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp = (tmp & SDHC_CR_CMDIDX_Msk) >> SDHC_CR_CMDIDX_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CR_reg(const void *const hw, hri_sdhc_cr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->CR.reg;
+}
+
+static inline void hri_sdhc_set_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg |= SDHC_BDPR_BUFDATA(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->BDPR.reg;
+	tmp = (tmp & SDHC_BDPR_BUFDATA(mask)) >> SDHC_BDPR_BUFDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BDPR.reg;
+	tmp &= ~SDHC_BDPR_BUFDATA_Msk;
+	tmp |= SDHC_BDPR_BUFDATA(data);
+	((Sdhc *)hw)->BDPR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg &= ~SDHC_BDPR_BUFDATA(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg ^= SDHC_BDPR_BUFDATA(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_BUFDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->BDPR.reg;
+	tmp = (tmp & SDHC_BDPR_BUFDATA_Msk) >> SDHC_BDPR_BUFDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->BDPR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BDPR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->BDPR.reg;
+}
+
+static inline void hri_sdhc_set_HC1R_LEDCTRL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_LEDCTRL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC1R_LEDCTRL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_LEDCTRL) >> SDHC_HC1R_LEDCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_LEDCTRL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= ~SDHC_HC1R_LEDCTRL;
+	tmp |= value << SDHC_HC1R_LEDCTRL_Pos;
+	((Sdhc *)hw)->HC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_LEDCTRL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_LEDCTRL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_LEDCTRL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_LEDCTRL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC1R_DW_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DW;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC1R_DW_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_DW) >> SDHC_HC1R_DW_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_DW_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= ~SDHC_HC1R_DW;
+	tmp |= value << SDHC_HC1R_DW_Pos;
+	((Sdhc *)hw)->HC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_DW_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DW;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_DW_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DW;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC1R_HSEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_HSEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC1R_HSEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_HSEN) >> SDHC_HC1R_HSEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_HSEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= ~SDHC_HC1R_HSEN;
+	tmp |= value << SDHC_HC1R_HSEN_Pos;
+	((Sdhc *)hw)->HC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_HSEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_HSEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_HSEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_HSEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC1R_CARDDTL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDTL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC1R_CARDDTL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_CARDDTL) >> SDHC_HC1R_CARDDTL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_CARDDTL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= ~SDHC_HC1R_CARDDTL;
+	tmp |= value << SDHC_HC1R_CARDDTL_Pos;
+	((Sdhc *)hw)->HC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_CARDDTL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDTL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_CARDDTL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDTL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC1R_CARDDSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC1R_CARDDSEL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_CARDDSEL) >> SDHC_HC1R_CARDDSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_CARDDSEL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= ~SDHC_HC1R_CARDDSEL;
+	tmp |= value << SDHC_HC1R_CARDDSEL_Pos;
+	((Sdhc *)hw)->HC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_CARDDSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_CARDDSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DMASEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_DMASEL(mask)) >> SDHC_HC1R_DMASEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t data)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= ~SDHC_HC1R_DMASEL_Msk;
+	tmp |= SDHC_HC1R_DMASEL(data);
+	((Sdhc *)hw)->HC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DMASEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DMASEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_DMASEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp = (tmp & SDHC_HC1R_DMASEL_Msk) >> SDHC_HC1R_DMASEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->HC1R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC1R.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->HC1R.reg;
+}
+
+static inline void hri_sdhc_set_PCR_SDBPWR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBPWR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_PCR_SDBPWR_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->PCR.reg;
+	tmp = (tmp & SDHC_PCR_SDBPWR) >> SDHC_PCR_SDBPWR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_PCR_SDBPWR_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->PCR.reg;
+	tmp &= ~SDHC_PCR_SDBPWR;
+	tmp |= value << SDHC_PCR_SDBPWR_Pos;
+	((Sdhc *)hw)->PCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PCR_SDBPWR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBPWR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PCR_SDBPWR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBPWR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->PCR.reg;
+	tmp = (tmp & SDHC_PCR_SDBVSEL(mask)) >> SDHC_PCR_SDBVSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t data)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->PCR.reg;
+	tmp &= ~SDHC_PCR_SDBVSEL_Msk;
+	tmp |= SDHC_PCR_SDBVSEL(data);
+	((Sdhc *)hw)->PCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_SDBVSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->PCR.reg;
+	tmp = (tmp & SDHC_PCR_SDBVSEL_Msk) >> SDHC_PCR_SDBVSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->PCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PCR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->PCR.reg;
+}
+
+static inline void hri_sdhc_set_BGCR_STPBGR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_STPBGR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_BGCR_STPBGR_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp = (tmp & SDHC_BGCR_STPBGR) >> SDHC_BGCR_STPBGR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_BGCR_STPBGR_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp &= ~SDHC_BGCR_STPBGR;
+	tmp |= value << SDHC_BGCR_STPBGR_Pos;
+	((Sdhc *)hw)->BGCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BGCR_STPBGR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_STPBGR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BGCR_STPBGR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_STPBGR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_BGCR_CONTR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_CONTR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_BGCR_CONTR_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp = (tmp & SDHC_BGCR_CONTR) >> SDHC_BGCR_CONTR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_BGCR_CONTR_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp &= ~SDHC_BGCR_CONTR;
+	tmp |= value << SDHC_BGCR_CONTR_Pos;
+	((Sdhc *)hw)->BGCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BGCR_CONTR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_CONTR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BGCR_CONTR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_CONTR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_BGCR_RWCTRL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_RWCTRL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_BGCR_RWCTRL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp = (tmp & SDHC_BGCR_RWCTRL) >> SDHC_BGCR_RWCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_BGCR_RWCTRL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp &= ~SDHC_BGCR_RWCTRL;
+	tmp |= value << SDHC_BGCR_RWCTRL_Pos;
+	((Sdhc *)hw)->BGCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BGCR_RWCTRL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_RWCTRL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BGCR_RWCTRL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_RWCTRL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_BGCR_INTBG_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_INTBG;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_BGCR_INTBG_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp = (tmp & SDHC_BGCR_INTBG) >> SDHC_BGCR_INTBG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_BGCR_INTBG_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp &= ~SDHC_BGCR_INTBG;
+	tmp |= value << SDHC_BGCR_INTBG_Pos;
+	((Sdhc *)hw)->BGCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BGCR_INTBG_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_INTBG;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BGCR_INTBG_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_INTBG;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bgcr_reg_t hri_sdhc_get_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->BGCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->BGCR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_bgcr_reg_t hri_sdhc_read_BGCR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->BGCR.reg;
+}
+
+static inline void hri_sdhc_set_WCR_WKENCINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_WCR_WKENCINT_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp = (tmp & SDHC_WCR_WKENCINT) >> SDHC_WCR_WKENCINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_WCR_WKENCINT_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp &= ~SDHC_WCR_WKENCINT;
+	tmp |= value << SDHC_WCR_WKENCINT_Pos;
+	((Sdhc *)hw)->WCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_WCR_WKENCINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_WCR_WKENCINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_WCR_WKENCINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_WCR_WKENCINS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp = (tmp & SDHC_WCR_WKENCINS) >> SDHC_WCR_WKENCINS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_WCR_WKENCINS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp &= ~SDHC_WCR_WKENCINS;
+	tmp |= value << SDHC_WCR_WKENCINS_Pos;
+	((Sdhc *)hw)->WCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_WCR_WKENCINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_WCR_WKENCINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_WCR_WKENCREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_WCR_WKENCREM_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp = (tmp & SDHC_WCR_WKENCREM) >> SDHC_WCR_WKENCREM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_WCR_WKENCREM_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp &= ~SDHC_WCR_WKENCREM;
+	tmp |= value << SDHC_WCR_WKENCREM_Pos;
+	((Sdhc *)hw)->WCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_WCR_WKENCREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_WCR_WKENCREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_wcr_reg_t hri_sdhc_get_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->WCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->WCR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_wcr_reg_t hri_sdhc_read_WCR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->WCR.reg;
+}
+
+static inline void hri_sdhc_set_CCR_INTCLKEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CCR_INTCLKEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_INTCLKEN) >> SDHC_CCR_INTCLKEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CCR_INTCLKEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= ~SDHC_CCR_INTCLKEN;
+	tmp |= value << SDHC_CCR_INTCLKEN_Pos;
+	((Sdhc *)hw)->CCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_INTCLKEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_INTCLKEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CCR_INTCLKS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CCR_INTCLKS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_INTCLKS) >> SDHC_CCR_INTCLKS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CCR_INTCLKS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= ~SDHC_CCR_INTCLKS;
+	tmp |= value << SDHC_CCR_INTCLKS_Pos;
+	((Sdhc *)hw)->CCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_INTCLKS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_INTCLKS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CCR_SDCLKEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CCR_SDCLKEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_SDCLKEN) >> SDHC_CCR_SDCLKEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CCR_SDCLKEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= ~SDHC_CCR_SDCLKEN;
+	tmp |= value << SDHC_CCR_SDCLKEN_Pos;
+	((Sdhc *)hw)->CCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_SDCLKEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_SDCLKEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CCR_CLKGSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= SDHC_CCR_CLKGSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CCR_CLKGSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_CLKGSEL) >> SDHC_CCR_CLKGSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CCR_CLKGSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= ~SDHC_CCR_CLKGSEL;
+	tmp |= value << SDHC_CCR_CLKGSEL_Pos;
+	((Sdhc *)hw)->CCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_CLKGSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_CLKGSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_CLKGSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_CLKGSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= SDHC_CCR_USDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_USDCLKFSEL(mask)) >> SDHC_CCR_USDCLKFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= ~SDHC_CCR_USDCLKFSEL_Msk;
+	tmp |= SDHC_CCR_USDCLKFSEL(data);
+	((Sdhc *)hw)->CCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_USDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_USDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_USDCLKFSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_USDCLKFSEL_Msk) >> SDHC_CCR_USDCLKFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_SDCLKFSEL(mask)) >> SDHC_CCR_SDCLKFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= ~SDHC_CCR_SDCLKFSEL_Msk;
+	tmp |= SDHC_CCR_SDCLKFSEL(data);
+	((Sdhc *)hw)->CCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_SDCLKFSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp = (tmp & SDHC_CCR_SDCLKFSEL_Msk) >> SDHC_CCR_SDCLKFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->CCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CCR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->CCR.reg;
+}
+
+static inline void hri_sdhc_set_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg |= SDHC_TCR_DTCVAL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->TCR.reg;
+	tmp = (tmp & SDHC_TCR_DTCVAL(mask)) >> SDHC_TCR_DTCVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t data)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->TCR.reg;
+	tmp &= ~SDHC_TCR_DTCVAL_Msk;
+	tmp |= SDHC_TCR_DTCVAL(data);
+	((Sdhc *)hw)->TCR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg &= ~SDHC_TCR_DTCVAL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg ^= SDHC_TCR_DTCVAL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_DTCVAL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->TCR.reg;
+	tmp = (tmp & SDHC_TCR_DTCVAL_Msk) >> SDHC_TCR_DTCVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->TCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->TCR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->TCR.reg;
+}
+
+static inline void hri_sdhc_set_SRR_SWRSTALL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTALL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_SRR_SWRSTALL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp = (tmp & SDHC_SRR_SWRSTALL) >> SDHC_SRR_SWRSTALL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_SRR_SWRSTALL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp &= ~SDHC_SRR_SWRSTALL;
+	tmp |= value << SDHC_SRR_SWRSTALL_Pos;
+	((Sdhc *)hw)->SRR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SRR_SWRSTALL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTALL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SRR_SWRSTALL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTALL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_SRR_SWRSTCMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTCMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_SRR_SWRSTCMD_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp = (tmp & SDHC_SRR_SWRSTCMD) >> SDHC_SRR_SWRSTCMD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_SRR_SWRSTCMD_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp &= ~SDHC_SRR_SWRSTCMD;
+	tmp |= value << SDHC_SRR_SWRSTCMD_Pos;
+	((Sdhc *)hw)->SRR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SRR_SWRSTCMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTCMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SRR_SWRSTCMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTCMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_SRR_SWRSTDAT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTDAT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_SRR_SWRSTDAT_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp = (tmp & SDHC_SRR_SWRSTDAT) >> SDHC_SRR_SWRSTDAT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_SRR_SWRSTDAT_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp &= ~SDHC_SRR_SWRSTDAT;
+	tmp |= value << SDHC_SRR_SWRSTDAT_Pos;
+	((Sdhc *)hw)->SRR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SRR_SWRSTDAT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTDAT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SRR_SWRSTDAT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTDAT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_srr_reg_t hri_sdhc_get_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->SRR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->SRR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_srr_reg_t hri_sdhc_read_SRR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->SRR.reg;
+}
+
+static inline void hri_sdhc_set_NISTR_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_CMDC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_CMDC) >> SDHC_NISTR_CMDC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_CMDC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_CMDC;
+	tmp |= value << SDHC_NISTR_CMDC_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_TRFC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_TRFC) >> SDHC_NISTR_TRFC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_TRFC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_TRFC;
+	tmp |= value << SDHC_NISTR_TRFC_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_BLKGE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_BLKGE) >> SDHC_NISTR_BLKGE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_BLKGE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_BLKGE;
+	tmp |= value << SDHC_NISTR_BLKGE_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_DMAINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_DMAINT) >> SDHC_NISTR_DMAINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_DMAINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_DMAINT;
+	tmp |= value << SDHC_NISTR_DMAINT_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_BWRRDY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_BWRRDY) >> SDHC_NISTR_BWRRDY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_BWRRDY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_BWRRDY;
+	tmp |= value << SDHC_NISTR_BWRRDY_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_BRDRDY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_BRDRDY) >> SDHC_NISTR_BRDRDY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_BRDRDY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_BRDRDY;
+	tmp |= value << SDHC_NISTR_BRDRDY_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_CINS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_CINS) >> SDHC_NISTR_CINS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_CINS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_CINS;
+	tmp |= value << SDHC_NISTR_CINS_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_CREM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_CREM) >> SDHC_NISTR_CREM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_CREM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_CREM;
+	tmp |= value << SDHC_NISTR_CREM_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_CINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_CINT) >> SDHC_NISTR_CINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_CINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_CINT;
+	tmp |= value << SDHC_NISTR_CINT_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_EMMC_BOOTAR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_EMMC_BOOTAR) >> SDHC_NISTR_EMMC_BOOTAR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_EMMC_BOOTAR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_EMMC_BOOTAR;
+	tmp |= value << SDHC_NISTR_EMMC_BOOTAR_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_ERRINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_ERRINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTR_ERRINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp = (tmp & SDHC_NISTR_ERRINT) >> SDHC_NISTR_ERRINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_ERRINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= ~SDHC_NISTR_ERRINT;
+	tmp |= value << SDHC_NISTR_ERRINT_Pos;
+	((Sdhc *)hw)->NISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_ERRINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_ERRINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_ERRINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_ERRINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_nistr_reg_t hri_sdhc_get_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_nistr_reg_t hri_sdhc_read_NISTR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->NISTR.reg;
+}
+
+static inline void hri_sdhc_set_EISTR_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_CMDTEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_CMDTEO) >> SDHC_EISTR_CMDTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_CMDTEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_CMDTEO;
+	tmp |= value << SDHC_EISTR_CMDTEO_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_CMDCRC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_CMDCRC) >> SDHC_EISTR_CMDCRC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_CMDCRC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_CMDCRC;
+	tmp |= value << SDHC_EISTR_CMDCRC_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_CMDEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_CMDEND) >> SDHC_EISTR_CMDEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_CMDEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_CMDEND;
+	tmp |= value << SDHC_EISTR_CMDEND_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_CMDIDX_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_CMDIDX) >> SDHC_EISTR_CMDIDX_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_CMDIDX_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_CMDIDX;
+	tmp |= value << SDHC_EISTR_CMDIDX_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_DATTEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_DATTEO) >> SDHC_EISTR_DATTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_DATTEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_DATTEO;
+	tmp |= value << SDHC_EISTR_DATTEO_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_DATCRC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_DATCRC) >> SDHC_EISTR_DATCRC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_DATCRC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_DATCRC;
+	tmp |= value << SDHC_EISTR_DATCRC_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_DATEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_DATEND) >> SDHC_EISTR_DATEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_DATEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_DATEND;
+	tmp |= value << SDHC_EISTR_DATEND_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_CURLIM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_CURLIM) >> SDHC_EISTR_CURLIM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_CURLIM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_CURLIM;
+	tmp |= value << SDHC_EISTR_CURLIM_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_ACMD_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_ACMD) >> SDHC_EISTR_ACMD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_ACMD_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_ACMD;
+	tmp |= value << SDHC_EISTR_ACMD_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_ADMA_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_ADMA) >> SDHC_EISTR_ADMA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_ADMA_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_ADMA;
+	tmp |= value << SDHC_EISTR_ADMA_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTR_EMMC_BOOTAE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp = (tmp & SDHC_EISTR_EMMC_BOOTAE) >> SDHC_EISTR_EMMC_BOOTAE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_EMMC_BOOTAE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= ~SDHC_EISTR_EMMC_BOOTAE;
+	tmp |= value << SDHC_EISTR_EMMC_BOOTAE_Pos;
+	((Sdhc *)hw)->EISTR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_eistr_reg_t hri_sdhc_get_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_eistr_reg_t hri_sdhc_read_EISTR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->EISTR.reg;
+}
+
+static inline void hri_sdhc_set_NISTER_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_CMDC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_CMDC) >> SDHC_NISTER_CMDC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_CMDC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_CMDC;
+	tmp |= value << SDHC_NISTER_CMDC_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_TRFC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_TRFC) >> SDHC_NISTER_TRFC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_TRFC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_TRFC;
+	tmp |= value << SDHC_NISTER_TRFC_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_BLKGE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_BLKGE) >> SDHC_NISTER_BLKGE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_BLKGE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_BLKGE;
+	tmp |= value << SDHC_NISTER_BLKGE_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_DMAINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_DMAINT) >> SDHC_NISTER_DMAINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_DMAINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_DMAINT;
+	tmp |= value << SDHC_NISTER_DMAINT_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_BWRRDY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_BWRRDY) >> SDHC_NISTER_BWRRDY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_BWRRDY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_BWRRDY;
+	tmp |= value << SDHC_NISTER_BWRRDY_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_BRDRDY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_BRDRDY) >> SDHC_NISTER_BRDRDY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_BRDRDY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_BRDRDY;
+	tmp |= value << SDHC_NISTER_BRDRDY_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_CINS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_CINS) >> SDHC_NISTER_CINS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_CINS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_CINS;
+	tmp |= value << SDHC_NISTER_CINS_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_CREM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_CREM) >> SDHC_NISTER_CREM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_CREM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_CREM;
+	tmp |= value << SDHC_NISTER_CREM_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_CINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_CINT) >> SDHC_NISTER_CINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_CINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_CINT;
+	tmp |= value << SDHC_NISTER_CINT_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISTER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp = (tmp & SDHC_NISTER_EMMC_BOOTAR) >> SDHC_NISTER_EMMC_BOOTAR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_EMMC_BOOTAR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= ~SDHC_NISTER_EMMC_BOOTAR;
+	tmp |= value << SDHC_NISTER_EMMC_BOOTAR_Pos;
+	((Sdhc *)hw)->NISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_nister_reg_t hri_sdhc_get_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISTER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISTER.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_nister_reg_t hri_sdhc_read_NISTER_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->NISTER.reg;
+}
+
+static inline void hri_sdhc_set_EISTER_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_CMDTEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_CMDTEO) >> SDHC_EISTER_CMDTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_CMDTEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_CMDTEO;
+	tmp |= value << SDHC_EISTER_CMDTEO_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_CMDCRC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_CMDCRC) >> SDHC_EISTER_CMDCRC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_CMDCRC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_CMDCRC;
+	tmp |= value << SDHC_EISTER_CMDCRC_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_CMDEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_CMDEND) >> SDHC_EISTER_CMDEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_CMDEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_CMDEND;
+	tmp |= value << SDHC_EISTER_CMDEND_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_CMDIDX_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_CMDIDX) >> SDHC_EISTER_CMDIDX_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_CMDIDX_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_CMDIDX;
+	tmp |= value << SDHC_EISTER_CMDIDX_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_DATTEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_DATTEO) >> SDHC_EISTER_DATTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_DATTEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_DATTEO;
+	tmp |= value << SDHC_EISTER_DATTEO_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_DATCRC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_DATCRC) >> SDHC_EISTER_DATCRC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_DATCRC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_DATCRC;
+	tmp |= value << SDHC_EISTER_DATCRC_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_DATEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_DATEND) >> SDHC_EISTER_DATEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_DATEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_DATEND;
+	tmp |= value << SDHC_EISTER_DATEND_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_CURLIM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_CURLIM) >> SDHC_EISTER_CURLIM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_CURLIM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_CURLIM;
+	tmp |= value << SDHC_EISTER_CURLIM_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_ACMD_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_ACMD) >> SDHC_EISTER_ACMD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_ACMD_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_ACMD;
+	tmp |= value << SDHC_EISTER_ACMD_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_ADMA_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_ADMA) >> SDHC_EISTER_ADMA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_ADMA_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_ADMA;
+	tmp |= value << SDHC_EISTER_ADMA_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISTER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp = (tmp & SDHC_EISTER_EMMC_BOOTAE) >> SDHC_EISTER_EMMC_BOOTAE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_EMMC_BOOTAE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= ~SDHC_EISTER_EMMC_BOOTAE;
+	tmp |= value << SDHC_EISTER_EMMC_BOOTAE_Pos;
+	((Sdhc *)hw)->EISTER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_eister_reg_t hri_sdhc_get_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISTER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISTER.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_eister_reg_t hri_sdhc_read_EISTER_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->EISTER.reg;
+}
+
+static inline void hri_sdhc_set_NISIER_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_CMDC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_CMDC) >> SDHC_NISIER_CMDC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_CMDC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_CMDC;
+	tmp |= value << SDHC_NISIER_CMDC_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_CMDC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CMDC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_TRFC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_TRFC) >> SDHC_NISIER_TRFC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_TRFC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_TRFC;
+	tmp |= value << SDHC_NISIER_TRFC_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_TRFC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_TRFC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_BLKGE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_BLKGE) >> SDHC_NISIER_BLKGE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_BLKGE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_BLKGE;
+	tmp |= value << SDHC_NISIER_BLKGE_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_BLKGE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BLKGE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_DMAINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_DMAINT) >> SDHC_NISIER_DMAINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_DMAINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_DMAINT;
+	tmp |= value << SDHC_NISIER_DMAINT_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_DMAINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_DMAINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_BWRRDY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_BWRRDY) >> SDHC_NISIER_BWRRDY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_BWRRDY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_BWRRDY;
+	tmp |= value << SDHC_NISIER_BWRRDY_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_BWRRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BWRRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_BRDRDY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_BRDRDY) >> SDHC_NISIER_BRDRDY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_BRDRDY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_BRDRDY;
+	tmp |= value << SDHC_NISIER_BRDRDY_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_BRDRDY_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BRDRDY;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_CINS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_CINS) >> SDHC_NISIER_CINS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_CINS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_CINS;
+	tmp |= value << SDHC_NISIER_CINS_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_CINS_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINS;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_CREM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_CREM) >> SDHC_NISIER_CREM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_CREM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_CREM;
+	tmp |= value << SDHC_NISIER_CREM_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_CREM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CREM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_CINT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_CINT) >> SDHC_NISIER_CINT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_CINT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_CINT;
+	tmp |= value << SDHC_NISIER_CINT_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_CINT_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINT;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_NISIER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp = (tmp & SDHC_NISIER_EMMC_BOOTAR) >> SDHC_NISIER_EMMC_BOOTAR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_EMMC_BOOTAR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= ~SDHC_NISIER_EMMC_BOOTAR;
+	tmp |= value << SDHC_NISIER_EMMC_BOOTAR_Pos;
+	((Sdhc *)hw)->NISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_EMMC_BOOTAR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_BOOTAR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_nisier_reg_t hri_sdhc_get_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->NISIER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->NISIER.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_nisier_reg_t hri_sdhc_read_NISIER_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->NISIER.reg;
+}
+
+static inline void hri_sdhc_set_EISIER_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_CMDTEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_CMDTEO) >> SDHC_EISIER_CMDTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_CMDTEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_CMDTEO;
+	tmp |= value << SDHC_EISIER_CMDTEO_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_CMDTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_CMDCRC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_CMDCRC) >> SDHC_EISIER_CMDCRC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_CMDCRC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_CMDCRC;
+	tmp |= value << SDHC_EISIER_CMDCRC_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_CMDCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_CMDEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_CMDEND) >> SDHC_EISIER_CMDEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_CMDEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_CMDEND;
+	tmp |= value << SDHC_EISIER_CMDEND_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_CMDEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_CMDIDX_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_CMDIDX) >> SDHC_EISIER_CMDIDX_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_CMDIDX_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_CMDIDX;
+	tmp |= value << SDHC_EISIER_CMDIDX_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_CMDIDX_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDIDX;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_DATTEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_DATTEO) >> SDHC_EISIER_DATTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_DATTEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_DATTEO;
+	tmp |= value << SDHC_EISIER_DATTEO_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_DATTEO_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATTEO;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_DATCRC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_DATCRC) >> SDHC_EISIER_DATCRC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_DATCRC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_DATCRC;
+	tmp |= value << SDHC_EISIER_DATCRC_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_DATCRC_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATCRC;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_DATEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_DATEND) >> SDHC_EISIER_DATEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_DATEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_DATEND;
+	tmp |= value << SDHC_EISIER_DATEND_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_DATEND_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATEND;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_CURLIM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_CURLIM) >> SDHC_EISIER_CURLIM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_CURLIM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_CURLIM;
+	tmp |= value << SDHC_EISIER_CURLIM_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_CURLIM_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CURLIM;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_ACMD_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_ACMD) >> SDHC_EISIER_ACMD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_ACMD_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_ACMD;
+	tmp |= value << SDHC_EISIER_ACMD_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_ACMD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ACMD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_ADMA_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_ADMA) >> SDHC_EISIER_ADMA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_ADMA_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_ADMA;
+	tmp |= value << SDHC_EISIER_ADMA_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_ADMA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ADMA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_EISIER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp = (tmp & SDHC_EISIER_EMMC_BOOTAE) >> SDHC_EISIER_EMMC_BOOTAE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_EMMC_BOOTAE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= ~SDHC_EISIER_EMMC_BOOTAE;
+	tmp |= value << SDHC_EISIER_EMMC_BOOTAE_Pos;
+	((Sdhc *)hw)->EISIER.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_EMMC_BOOTAE_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_BOOTAE;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_eisier_reg_t hri_sdhc_get_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->EISIER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->EISIER.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_eisier_reg_t hri_sdhc_read_EISIER_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->EISIER.reg;
+}
+
+static inline void hri_sdhc_set_HC2R_VS18EN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_VS18EN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC2R_VS18EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_VS18EN) >> SDHC_HC2R_VS18EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_VS18EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_VS18EN;
+	tmp |= value << SDHC_HC2R_VS18EN_Pos;
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_VS18EN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_VS18EN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_VS18EN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_VS18EN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC2R_EXTUN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EXTUN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC2R_EXTUN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_EXTUN) >> SDHC_HC2R_EXTUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_EXTUN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_EXTUN;
+	tmp |= value << SDHC_HC2R_EXTUN_Pos;
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_EXTUN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EXTUN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_EXTUN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EXTUN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC2R_SLCKSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_SLCKSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC2R_SLCKSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_SLCKSEL) >> SDHC_HC2R_SLCKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_SLCKSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_SLCKSEL;
+	tmp |= value << SDHC_HC2R_SLCKSEL_Pos;
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_SLCKSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_SLCKSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_SLCKSEL_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_SLCKSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC2R_ASINTEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_ASINTEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC2R_ASINTEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_ASINTEN) >> SDHC_HC2R_ASINTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_ASINTEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_ASINTEN;
+	tmp |= value << SDHC_HC2R_ASINTEN_Pos;
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_ASINTEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_ASINTEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_ASINTEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_ASINTEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC2R_PVALEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_PVALEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_HC2R_PVALEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_PVALEN) >> SDHC_HC2R_PVALEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_PVALEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_PVALEN;
+	tmp |= value << SDHC_HC2R_PVALEN_Pos;
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_PVALEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_PVALEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_PVALEN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_PVALEN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_UHSMS(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_UHSMS(mask)) >> SDHC_HC2R_UHSMS_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_UHSMS_Msk;
+	tmp |= SDHC_HC2R_UHSMS(data);
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_UHSMS(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_UHSMS(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_UHSMS_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_UHSMS_Msk) >> SDHC_HC2R_UHSMS_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_HS200EN(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_EMMC_HS200EN(mask)) >> SDHC_HC2R_EMMC_HS200EN_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_EMMC_HS200EN_Msk;
+	tmp |= SDHC_HC2R_EMMC_HS200EN(data);
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_HS200EN(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_HS200EN(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_EMMC_HS200EN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_EMMC_HS200EN_Msk) >> SDHC_HC2R_EMMC_HS200EN_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_DRVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_DRVSEL(mask)) >> SDHC_HC2R_DRVSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= ~SDHC_HC2R_DRVSEL_Msk;
+	tmp |= SDHC_HC2R_DRVSEL(data);
+	((Sdhc *)hw)->HC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_DRVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_DRVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_DRVSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp = (tmp & SDHC_HC2R_DRVSEL_Msk) >> SDHC_HC2R_DRVSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->HC2R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->HC2R.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->HC2R.reg;
+}
+
+static inline void hri_sdhc_set_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg |= SDHC_ASAR_ADMASA(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_ADMASA_bf(const void *const hw, uint8_t index,
+                                                              hri_sdhc_asar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ASAR[index].reg;
+	tmp = (tmp & SDHC_ASAR_ADMASA(mask)) >> SDHC_ASAR_ADMASA_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->ASAR[index].reg;
+	tmp &= ~SDHC_ASAR_ADMASA_Msk;
+	tmp |= SDHC_ASAR_ADMASA(data);
+	((Sdhc *)hw)->ASAR[index].reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg &= ~SDHC_ASAR_ADMASA(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg ^= SDHC_ASAR_ADMASA(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_ADMASA_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ASAR[index].reg;
+	tmp = (tmp & SDHC_ASAR_ADMASA_Msk) >> SDHC_ASAR_ADMASA_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ASAR[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ASAR[index].reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_reg(const void *const hw, uint8_t index)
+{
+	return ((Sdhc *)hw)->ASAR[index].reg;
+}
+
+static inline void hri_sdhc_set_PVR_CLKGSEL_bit(const void *const hw, uint8_t index)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_CLKGSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_PVR_CLKGSEL_bit(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp = (tmp & SDHC_PVR_CLKGSEL) >> SDHC_PVR_CLKGSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_PVR_CLKGSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp &= ~SDHC_PVR_CLKGSEL;
+	tmp |= value << SDHC_PVR_CLKGSEL_Pos;
+	((Sdhc *)hw)->PVR[index].reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PVR_CLKGSEL_bit(const void *const hw, uint8_t index)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_CLKGSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PVR_CLKGSEL_bit(const void *const hw, uint8_t index)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_CLKGSEL;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_SDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index,
+                                                               hri_sdhc_pvr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp = (tmp & SDHC_PVR_SDCLKFSEL(mask)) >> SDHC_PVR_SDCLKFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp &= ~SDHC_PVR_SDCLKFSEL_Msk;
+	tmp |= SDHC_PVR_SDCLKFSEL(data);
+	((Sdhc *)hw)->PVR[index].reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_SDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_SDCLKFSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp = (tmp & SDHC_PVR_SDCLKFSEL_Msk) >> SDHC_PVR_SDCLKFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_DRVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_DRVSEL_bf(const void *const hw, uint8_t index,
+                                                            hri_sdhc_pvr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp = (tmp & SDHC_PVR_DRVSEL(mask)) >> SDHC_PVR_DRVSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data)
+{
+	uint16_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp &= ~SDHC_PVR_DRVSEL_Msk;
+	tmp |= SDHC_PVR_DRVSEL(data);
+	((Sdhc *)hw)->PVR[index].reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_DRVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_DRVSEL(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_DRVSEL_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp = (tmp & SDHC_PVR_DRVSEL_Msk) >> SDHC_PVR_DRVSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sdhc *)hw)->PVR[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->PVR[index].reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_reg(const void *const hw, uint8_t index)
+{
+	return ((Sdhc *)hw)->PVR[index].reg;
+}
+
+static inline void hri_sdhc_set_MC1R_DDR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_DDR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_MC1R_DDR_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_DDR) >> SDHC_MC1R_DDR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_DDR_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= ~SDHC_MC1R_DDR;
+	tmp |= value << SDHC_MC1R_DDR_Pos;
+	((Sdhc *)hw)->MC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_DDR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_DDR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_DDR_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_DDR;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_MC1R_OPD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_OPD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_MC1R_OPD_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_OPD) >> SDHC_MC1R_OPD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_OPD_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= ~SDHC_MC1R_OPD;
+	tmp |= value << SDHC_MC1R_OPD_Pos;
+	((Sdhc *)hw)->MC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_OPD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_OPD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_OPD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_OPD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_MC1R_BOOTA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_BOOTA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_MC1R_BOOTA_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_BOOTA) >> SDHC_MC1R_BOOTA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_BOOTA_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= ~SDHC_MC1R_BOOTA;
+	tmp |= value << SDHC_MC1R_BOOTA_Pos;
+	((Sdhc *)hw)->MC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_BOOTA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_BOOTA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_BOOTA_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_BOOTA;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_MC1R_RSTN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_RSTN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_MC1R_RSTN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_RSTN) >> SDHC_MC1R_RSTN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_RSTN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= ~SDHC_MC1R_RSTN;
+	tmp |= value << SDHC_MC1R_RSTN_Pos;
+	((Sdhc *)hw)->MC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_RSTN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_RSTN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_RSTN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_RSTN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_MC1R_FCD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_FCD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_MC1R_FCD_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_FCD) >> SDHC_MC1R_FCD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_FCD_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= ~SDHC_MC1R_FCD;
+	tmp |= value << SDHC_MC1R_FCD_Pos;
+	((Sdhc *)hw)->MC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_FCD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_FCD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_FCD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_FCD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_CMDTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_CMDTYP(mask)) >> SDHC_MC1R_CMDTYP_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t data)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= ~SDHC_MC1R_CMDTYP_Msk;
+	tmp |= SDHC_MC1R_CMDTYP(data);
+	((Sdhc *)hw)->MC1R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_CMDTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_CMDTYP(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_CMDTYP_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp = (tmp & SDHC_MC1R_CMDTYP_Msk) >> SDHC_MC1R_CMDTYP_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->MC1R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC1R.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->MC1R.reg;
+}
+
+static inline void hri_sdhc_set_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg |= SDHC_ACR_BMAX(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ACR.reg;
+	tmp = (tmp & SDHC_ACR_BMAX(mask)) >> SDHC_ACR_BMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->ACR.reg;
+	tmp &= ~SDHC_ACR_BMAX_Msk;
+	tmp |= SDHC_ACR_BMAX(data);
+	((Sdhc *)hw)->ACR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg &= ~SDHC_ACR_BMAX(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg ^= SDHC_ACR_BMAX(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_BMAX_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ACR.reg;
+	tmp = (tmp & SDHC_ACR_BMAX_Msk) >> SDHC_ACR_BMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->ACR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->ACR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->ACR.reg;
+}
+
+static inline void hri_sdhc_set_CC2R_FSDCLKD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg |= SDHC_CC2R_FSDCLKD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CC2R_FSDCLKD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CC2R.reg;
+	tmp = (tmp & SDHC_CC2R_FSDCLKD) >> SDHC_CC2R_FSDCLKD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CC2R_FSDCLKD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CC2R.reg;
+	tmp &= ~SDHC_CC2R_FSDCLKD;
+	tmp |= value << SDHC_CC2R_FSDCLKD_Pos;
+	((Sdhc *)hw)->CC2R.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CC2R_FSDCLKD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg &= ~SDHC_CC2R_FSDCLKD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CC2R_FSDCLKD_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg ^= SDHC_CC2R_FSDCLKD;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cc2r_reg_t hri_sdhc_get_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CC2R.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CC2R.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cc2r_reg_t hri_sdhc_read_CC2R_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->CC2R.reg;
+}
+
+static inline void hri_sdhc_set_CACR_CAPWREN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg |= SDHC_CACR_CAPWREN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_CACR_CAPWREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CACR.reg;
+	tmp = (tmp & SDHC_CACR_CAPWREN) >> SDHC_CACR_CAPWREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_CACR_CAPWREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CACR.reg;
+	tmp &= ~SDHC_CACR_CAPWREN;
+	tmp |= value << SDHC_CACR_CAPWREN_Pos;
+	((Sdhc *)hw)->CACR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CACR_CAPWREN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_CAPWREN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CACR_CAPWREN_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_CAPWREN;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg |= SDHC_CACR_KEY(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CACR.reg;
+	tmp = (tmp & SDHC_CACR_KEY(mask)) >> SDHC_CACR_KEY_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t data)
+{
+	uint32_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->CACR.reg;
+	tmp &= ~SDHC_CACR_KEY_Msk;
+	tmp |= SDHC_CACR_KEY(data);
+	((Sdhc *)hw)->CACR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_KEY(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_KEY(mask);
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_KEY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CACR.reg;
+	tmp = (tmp & SDHC_CACR_KEY_Msk) >> SDHC_CACR_KEY_Pos;
+	return tmp;
+}
+
+static inline void hri_sdhc_set_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sdhc *)hw)->CACR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->CACR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->CACR.reg;
+}
+
+static inline void hri_sdhc_set_DBGR_NIDBG_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg |= SDHC_DBGR_NIDBG;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sdhc_get_DBGR_NIDBG_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->DBGR.reg;
+	tmp = (tmp & SDHC_DBGR_NIDBG) >> SDHC_DBGR_NIDBG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sdhc_write_DBGR_NIDBG_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SDHC_CRITICAL_SECTION_ENTER();
+	tmp = ((Sdhc *)hw)->DBGR.reg;
+	tmp &= ~SDHC_DBGR_NIDBG;
+	tmp |= value << SDHC_DBGR_NIDBG_Pos;
+	((Sdhc *)hw)->DBGR.reg = tmp;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_DBGR_NIDBG_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg &= ~SDHC_DBGR_NIDBG;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_DBGR_NIDBG_bit(const void *const hw)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg ^= SDHC_DBGR_NIDBG;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_set_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg |= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_dbgr_reg_t hri_sdhc_get_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sdhc *)hw)->DBGR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sdhc_write_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_clear_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg &= ~mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_toggle_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->DBGR.reg ^= mask;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sdhc_dbgr_reg_t hri_sdhc_read_DBGR_reg(const void *const hw)
+{
+	return ((Sdhc *)hw)->DBGR.reg;
+}
+
+static inline void hri_sdhc_write_FERACES_reg(const void *const hw, hri_sdhc_feraces_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->FERACES.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_write_FEREIS_reg(const void *const hw, hri_sdhc_fereis_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->FEREIS.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sdhc_write_MC2R_reg(const void *const hw, hri_sdhc_mc2r_reg_t data)
+{
+	SDHC_CRITICAL_SECTION_ENTER();
+	((Sdhc *)hw)->MC2R.reg = data;
+	SDHC_CRITICAL_SECTION_LEAVE();
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_sdhc_set_SSAR_CMD23_reg(a, b) hri_sdhc_set_SSAR_reg(a, b)
+#define hri_sdhc_get_SSAR_CMD23_reg(a, b) hri_sdhc_get_SSAR_reg(a, b)
+#define hri_sdhc_write_SSAR_CMD23_reg(a, b) hri_sdhc_write_SSAR_reg(a, b)
+#define hri_sdhc_clear_SSAR_CMD23_reg(a, b) hri_sdhc_clear_SSAR_reg(a, b)
+#define hri_sdhc_toggle_SSAR_CMD23_reg(a, b) hri_sdhc_toggle_SSAR_reg(a, b)
+#define hri_sdhc_read_SSAR_CMD23_reg(a) hri_sdhc_read_SSAR_reg(a)
+#define hri_sdhc_set_HC1R_EMMC_DW_bit(a) hri_sdhc_set_HC1R_DW_bit(a)
+#define hri_sdhc_get_HC1R_EMMC_DW_bit(a) hri_sdhc_get_HC1R_DW_bit(a)
+#define hri_sdhc_write_HC1R_EMMC_DW_bit(a, b) hri_sdhc_write_HC1R_DW_bit(a, b)
+#define hri_sdhc_clear_HC1R_EMMC_DW_bit(a) hri_sdhc_clear_HC1R_DW_bit(a)
+#define hri_sdhc_toggle_HC1R_EMMC_DW_bit(a) hri_sdhc_toggle_HC1R_DW_bit(a)
+#define hri_sdhc_set_HC1R_EMMC_HSEN_bit(a) hri_sdhc_set_HC1R_HSEN_bit(a)
+#define hri_sdhc_get_HC1R_EMMC_HSEN_bit(a) hri_sdhc_get_HC1R_HSEN_bit(a)
+#define hri_sdhc_write_HC1R_EMMC_HSEN_bit(a, b) hri_sdhc_write_HC1R_HSEN_bit(a, b)
+#define hri_sdhc_clear_HC1R_EMMC_HSEN_bit(a) hri_sdhc_clear_HC1R_HSEN_bit(a)
+#define hri_sdhc_toggle_HC1R_EMMC_HSEN_bit(a) hri_sdhc_toggle_HC1R_HSEN_bit(a)
+#define hri_sdhc_set_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_set_HC1R_DMASEL_bf(a, b)
+#define hri_sdhc_get_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_get_HC1R_DMASEL_bf(a, b)
+#define hri_sdhc_write_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_write_HC1R_DMASEL_bf(a, b)
+#define hri_sdhc_clear_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_clear_HC1R_DMASEL_bf(a, b)
+#define hri_sdhc_toggle_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_toggle_HC1R_DMASEL_bf(a, b)
+#define hri_sdhc_read_HC1R_EMMC_DMASEL_bf(a) hri_sdhc_read_HC1R_DMASEL_bf(a)
+#define hri_sdhc_set_HC1R_EMMC_reg(a, b) hri_sdhc_set_HC1R_reg(a, b)
+#define hri_sdhc_get_HC1R_EMMC_reg(a, b) hri_sdhc_get_HC1R_reg(a, b)
+#define hri_sdhc_write_HC1R_EMMC_reg(a, b) hri_sdhc_write_HC1R_reg(a, b)
+#define hri_sdhc_clear_HC1R_EMMC_reg(a, b) hri_sdhc_clear_HC1R_reg(a, b)
+#define hri_sdhc_toggle_HC1R_EMMC_reg(a, b) hri_sdhc_toggle_HC1R_reg(a, b)
+#define hri_sdhc_read_HC1R_EMMC_reg(a) hri_sdhc_read_HC1R_reg(a)
+#define hri_sdhc_set_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_set_BGCR_STPBGR_bit(a)
+#define hri_sdhc_get_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_get_BGCR_STPBGR_bit(a)
+#define hri_sdhc_write_BGCR_EMMC_STPBGR_bit(a, b) hri_sdhc_write_BGCR_STPBGR_bit(a, b)
+#define hri_sdhc_clear_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_clear_BGCR_STPBGR_bit(a)
+#define hri_sdhc_toggle_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_toggle_BGCR_STPBGR_bit(a)
+#define hri_sdhc_set_BGCR_EMMC_CONTR_bit(a) hri_sdhc_set_BGCR_CONTR_bit(a)
+#define hri_sdhc_get_BGCR_EMMC_CONTR_bit(a) hri_sdhc_get_BGCR_CONTR_bit(a)
+#define hri_sdhc_write_BGCR_EMMC_CONTR_bit(a, b) hri_sdhc_write_BGCR_CONTR_bit(a, b)
+#define hri_sdhc_clear_BGCR_EMMC_CONTR_bit(a) hri_sdhc_clear_BGCR_CONTR_bit(a)
+#define hri_sdhc_toggle_BGCR_EMMC_CONTR_bit(a) hri_sdhc_toggle_BGCR_CONTR_bit(a)
+#define hri_sdhc_set_BGCR_EMMC_reg(a, b) hri_sdhc_set_BGCR_reg(a, b)
+#define hri_sdhc_get_BGCR_EMMC_reg(a, b) hri_sdhc_get_BGCR_reg(a, b)
+#define hri_sdhc_write_BGCR_EMMC_reg(a, b) hri_sdhc_write_BGCR_reg(a, b)
+#define hri_sdhc_clear_BGCR_EMMC_reg(a, b) hri_sdhc_clear_BGCR_reg(a, b)
+#define hri_sdhc_toggle_BGCR_EMMC_reg(a, b) hri_sdhc_toggle_BGCR_reg(a, b)
+#define hri_sdhc_read_BGCR_EMMC_reg(a) hri_sdhc_read_BGCR_reg(a)
+#define hri_sdhc_set_NISTR_EMMC_CMDC_bit(a) hri_sdhc_set_NISTR_CMDC_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_CMDC_bit(a) hri_sdhc_get_NISTR_CMDC_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTR_CMDC_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTR_CMDC_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTR_CMDC_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_TRFC_bit(a) hri_sdhc_set_NISTR_TRFC_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_TRFC_bit(a) hri_sdhc_get_NISTR_TRFC_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTR_TRFC_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTR_TRFC_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTR_TRFC_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTR_BLKGE_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTR_BLKGE_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTR_BLKGE_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTR_BLKGE_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTR_BLKGE_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTR_DMAINT_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTR_DMAINT_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTR_DMAINT_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTR_DMAINT_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTR_DMAINT_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTR_BWRRDY_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTR_BWRRDY_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTR_BWRRDY_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTR_BWRRDY_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTR_BWRRDY_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTR_BRDRDY_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTR_BRDRDY_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTR_BRDRDY_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTR_BRDRDY_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTR_BRDRDY_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_set_NISTR_ERRINT_bit(a)
+#define hri_sdhc_get_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_get_NISTR_ERRINT_bit(a)
+#define hri_sdhc_write_NISTR_EMMC_ERRINT_bit(a, b) hri_sdhc_write_NISTR_ERRINT_bit(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_clear_NISTR_ERRINT_bit(a)
+#define hri_sdhc_toggle_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_toggle_NISTR_ERRINT_bit(a)
+#define hri_sdhc_set_NISTR_EMMC_reg(a, b) hri_sdhc_set_NISTR_reg(a, b)
+#define hri_sdhc_get_NISTR_EMMC_reg(a, b) hri_sdhc_get_NISTR_reg(a, b)
+#define hri_sdhc_write_NISTR_EMMC_reg(a, b) hri_sdhc_write_NISTR_reg(a, b)
+#define hri_sdhc_clear_NISTR_EMMC_reg(a, b) hri_sdhc_clear_NISTR_reg(a, b)
+#define hri_sdhc_toggle_NISTR_EMMC_reg(a, b) hri_sdhc_toggle_NISTR_reg(a, b)
+#define hri_sdhc_read_NISTR_EMMC_reg(a) hri_sdhc_read_NISTR_reg(a)
+#define hri_sdhc_set_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTR_CMDTEO_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTR_CMDTEO_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTR_CMDTEO_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTR_CMDTEO_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTR_CMDTEO_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTR_CMDCRC_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTR_CMDCRC_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTR_CMDCRC_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTR_CMDCRC_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTR_CMDCRC_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTR_CMDEND_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTR_CMDEND_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTR_CMDEND_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTR_CMDEND_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTR_CMDEND_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTR_CMDIDX_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTR_CMDIDX_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTR_CMDIDX_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTR_CMDIDX_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTR_CMDIDX_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTR_DATTEO_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTR_DATTEO_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTR_DATTEO_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTR_DATTEO_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTR_DATTEO_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTR_DATCRC_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTR_DATCRC_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTR_DATCRC_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTR_DATCRC_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTR_DATCRC_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_DATEND_bit(a) hri_sdhc_set_EISTR_DATEND_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_DATEND_bit(a) hri_sdhc_get_EISTR_DATEND_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTR_DATEND_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTR_DATEND_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTR_DATEND_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTR_CURLIM_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTR_CURLIM_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTR_CURLIM_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTR_CURLIM_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTR_CURLIM_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_ACMD_bit(a) hri_sdhc_set_EISTR_ACMD_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_ACMD_bit(a) hri_sdhc_get_EISTR_ACMD_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTR_ACMD_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTR_ACMD_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTR_ACMD_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_ADMA_bit(a) hri_sdhc_set_EISTR_ADMA_bit(a)
+#define hri_sdhc_get_EISTR_EMMC_ADMA_bit(a) hri_sdhc_get_EISTR_ADMA_bit(a)
+#define hri_sdhc_write_EISTR_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTR_ADMA_bit(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTR_ADMA_bit(a)
+#define hri_sdhc_toggle_EISTR_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTR_ADMA_bit(a)
+#define hri_sdhc_set_EISTR_EMMC_reg(a, b) hri_sdhc_set_EISTR_reg(a, b)
+#define hri_sdhc_get_EISTR_EMMC_reg(a, b) hri_sdhc_get_EISTR_reg(a, b)
+#define hri_sdhc_write_EISTR_EMMC_reg(a, b) hri_sdhc_write_EISTR_reg(a, b)
+#define hri_sdhc_clear_EISTR_EMMC_reg(a, b) hri_sdhc_clear_EISTR_reg(a, b)
+#define hri_sdhc_toggle_EISTR_EMMC_reg(a, b) hri_sdhc_toggle_EISTR_reg(a, b)
+#define hri_sdhc_read_EISTR_EMMC_reg(a) hri_sdhc_read_EISTR_reg(a)
+#define hri_sdhc_set_NISTER_EMMC_CMDC_bit(a) hri_sdhc_set_NISTER_CMDC_bit(a)
+#define hri_sdhc_get_NISTER_EMMC_CMDC_bit(a) hri_sdhc_get_NISTER_CMDC_bit(a)
+#define hri_sdhc_write_NISTER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTER_CMDC_bit(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTER_CMDC_bit(a)
+#define hri_sdhc_toggle_NISTER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTER_CMDC_bit(a)
+#define hri_sdhc_set_NISTER_EMMC_TRFC_bit(a) hri_sdhc_set_NISTER_TRFC_bit(a)
+#define hri_sdhc_get_NISTER_EMMC_TRFC_bit(a) hri_sdhc_get_NISTER_TRFC_bit(a)
+#define hri_sdhc_write_NISTER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTER_TRFC_bit(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTER_TRFC_bit(a)
+#define hri_sdhc_toggle_NISTER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTER_TRFC_bit(a)
+#define hri_sdhc_set_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTER_BLKGE_bit(a)
+#define hri_sdhc_get_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTER_BLKGE_bit(a)
+#define hri_sdhc_write_NISTER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTER_BLKGE_bit(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTER_BLKGE_bit(a)
+#define hri_sdhc_toggle_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTER_BLKGE_bit(a)
+#define hri_sdhc_set_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTER_DMAINT_bit(a)
+#define hri_sdhc_get_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTER_DMAINT_bit(a)
+#define hri_sdhc_write_NISTER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTER_DMAINT_bit(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTER_DMAINT_bit(a)
+#define hri_sdhc_toggle_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTER_DMAINT_bit(a)
+#define hri_sdhc_set_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTER_BWRRDY_bit(a)
+#define hri_sdhc_get_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTER_BWRRDY_bit(a)
+#define hri_sdhc_write_NISTER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTER_BWRRDY_bit(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTER_BWRRDY_bit(a)
+#define hri_sdhc_toggle_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTER_BWRRDY_bit(a)
+#define hri_sdhc_set_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTER_BRDRDY_bit(a)
+#define hri_sdhc_get_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTER_BRDRDY_bit(a)
+#define hri_sdhc_write_NISTER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTER_BRDRDY_bit(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTER_BRDRDY_bit(a)
+#define hri_sdhc_toggle_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTER_BRDRDY_bit(a)
+#define hri_sdhc_set_NISTER_EMMC_reg(a, b) hri_sdhc_set_NISTER_reg(a, b)
+#define hri_sdhc_get_NISTER_EMMC_reg(a, b) hri_sdhc_get_NISTER_reg(a, b)
+#define hri_sdhc_write_NISTER_EMMC_reg(a, b) hri_sdhc_write_NISTER_reg(a, b)
+#define hri_sdhc_clear_NISTER_EMMC_reg(a, b) hri_sdhc_clear_NISTER_reg(a, b)
+#define hri_sdhc_toggle_NISTER_EMMC_reg(a, b) hri_sdhc_toggle_NISTER_reg(a, b)
+#define hri_sdhc_read_NISTER_EMMC_reg(a) hri_sdhc_read_NISTER_reg(a)
+#define hri_sdhc_set_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTER_CMDTEO_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTER_CMDTEO_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTER_CMDTEO_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTER_CMDTEO_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTER_CMDTEO_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTER_CMDCRC_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTER_CMDCRC_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTER_CMDCRC_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTER_CMDCRC_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTER_CMDCRC_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTER_CMDEND_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTER_CMDEND_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTER_CMDEND_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTER_CMDEND_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTER_CMDEND_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTER_CMDIDX_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTER_CMDIDX_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTER_CMDIDX_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTER_CMDIDX_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTER_CMDIDX_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTER_DATTEO_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTER_DATTEO_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTER_DATTEO_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTER_DATTEO_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTER_DATTEO_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTER_DATCRC_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTER_DATCRC_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTER_DATCRC_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTER_DATCRC_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTER_DATCRC_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_DATEND_bit(a) hri_sdhc_set_EISTER_DATEND_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_DATEND_bit(a) hri_sdhc_get_EISTER_DATEND_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTER_DATEND_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTER_DATEND_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTER_DATEND_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTER_CURLIM_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTER_CURLIM_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTER_CURLIM_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTER_CURLIM_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTER_CURLIM_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_ACMD_bit(a) hri_sdhc_set_EISTER_ACMD_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_ACMD_bit(a) hri_sdhc_get_EISTER_ACMD_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTER_ACMD_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTER_ACMD_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTER_ACMD_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_ADMA_bit(a) hri_sdhc_set_EISTER_ADMA_bit(a)
+#define hri_sdhc_get_EISTER_EMMC_ADMA_bit(a) hri_sdhc_get_EISTER_ADMA_bit(a)
+#define hri_sdhc_write_EISTER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTER_ADMA_bit(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTER_ADMA_bit(a)
+#define hri_sdhc_toggle_EISTER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTER_ADMA_bit(a)
+#define hri_sdhc_set_EISTER_EMMC_reg(a, b) hri_sdhc_set_EISTER_reg(a, b)
+#define hri_sdhc_get_EISTER_EMMC_reg(a, b) hri_sdhc_get_EISTER_reg(a, b)
+#define hri_sdhc_write_EISTER_EMMC_reg(a, b) hri_sdhc_write_EISTER_reg(a, b)
+#define hri_sdhc_clear_EISTER_EMMC_reg(a, b) hri_sdhc_clear_EISTER_reg(a, b)
+#define hri_sdhc_toggle_EISTER_EMMC_reg(a, b) hri_sdhc_toggle_EISTER_reg(a, b)
+#define hri_sdhc_read_EISTER_EMMC_reg(a) hri_sdhc_read_EISTER_reg(a)
+#define hri_sdhc_set_NISIER_EMMC_CMDC_bit(a) hri_sdhc_set_NISIER_CMDC_bit(a)
+#define hri_sdhc_get_NISIER_EMMC_CMDC_bit(a) hri_sdhc_get_NISIER_CMDC_bit(a)
+#define hri_sdhc_write_NISIER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISIER_CMDC_bit(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISIER_CMDC_bit(a)
+#define hri_sdhc_toggle_NISIER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISIER_CMDC_bit(a)
+#define hri_sdhc_set_NISIER_EMMC_TRFC_bit(a) hri_sdhc_set_NISIER_TRFC_bit(a)
+#define hri_sdhc_get_NISIER_EMMC_TRFC_bit(a) hri_sdhc_get_NISIER_TRFC_bit(a)
+#define hri_sdhc_write_NISIER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISIER_TRFC_bit(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISIER_TRFC_bit(a)
+#define hri_sdhc_toggle_NISIER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISIER_TRFC_bit(a)
+#define hri_sdhc_set_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISIER_BLKGE_bit(a)
+#define hri_sdhc_get_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISIER_BLKGE_bit(a)
+#define hri_sdhc_write_NISIER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISIER_BLKGE_bit(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISIER_BLKGE_bit(a)
+#define hri_sdhc_toggle_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISIER_BLKGE_bit(a)
+#define hri_sdhc_set_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISIER_DMAINT_bit(a)
+#define hri_sdhc_get_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISIER_DMAINT_bit(a)
+#define hri_sdhc_write_NISIER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISIER_DMAINT_bit(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISIER_DMAINT_bit(a)
+#define hri_sdhc_toggle_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISIER_DMAINT_bit(a)
+#define hri_sdhc_set_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISIER_BWRRDY_bit(a)
+#define hri_sdhc_get_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISIER_BWRRDY_bit(a)
+#define hri_sdhc_write_NISIER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISIER_BWRRDY_bit(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISIER_BWRRDY_bit(a)
+#define hri_sdhc_toggle_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISIER_BWRRDY_bit(a)
+#define hri_sdhc_set_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISIER_BRDRDY_bit(a)
+#define hri_sdhc_get_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISIER_BRDRDY_bit(a)
+#define hri_sdhc_write_NISIER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISIER_BRDRDY_bit(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISIER_BRDRDY_bit(a)
+#define hri_sdhc_toggle_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISIER_BRDRDY_bit(a)
+#define hri_sdhc_set_NISIER_EMMC_reg(a, b) hri_sdhc_set_NISIER_reg(a, b)
+#define hri_sdhc_get_NISIER_EMMC_reg(a, b) hri_sdhc_get_NISIER_reg(a, b)
+#define hri_sdhc_write_NISIER_EMMC_reg(a, b) hri_sdhc_write_NISIER_reg(a, b)
+#define hri_sdhc_clear_NISIER_EMMC_reg(a, b) hri_sdhc_clear_NISIER_reg(a, b)
+#define hri_sdhc_toggle_NISIER_EMMC_reg(a, b) hri_sdhc_toggle_NISIER_reg(a, b)
+#define hri_sdhc_read_NISIER_EMMC_reg(a) hri_sdhc_read_NISIER_reg(a)
+#define hri_sdhc_set_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISIER_CMDTEO_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISIER_CMDTEO_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISIER_CMDTEO_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISIER_CMDTEO_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISIER_CMDTEO_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISIER_CMDCRC_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISIER_CMDCRC_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISIER_CMDCRC_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISIER_CMDCRC_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISIER_CMDCRC_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISIER_CMDEND_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISIER_CMDEND_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISIER_CMDEND_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISIER_CMDEND_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISIER_CMDEND_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISIER_CMDIDX_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISIER_CMDIDX_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISIER_CMDIDX_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISIER_CMDIDX_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISIER_CMDIDX_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISIER_DATTEO_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISIER_DATTEO_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISIER_DATTEO_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISIER_DATTEO_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISIER_DATTEO_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISIER_DATCRC_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISIER_DATCRC_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISIER_DATCRC_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISIER_DATCRC_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISIER_DATCRC_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_DATEND_bit(a) hri_sdhc_set_EISIER_DATEND_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_DATEND_bit(a) hri_sdhc_get_EISIER_DATEND_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISIER_DATEND_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISIER_DATEND_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISIER_DATEND_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISIER_CURLIM_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISIER_CURLIM_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISIER_CURLIM_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISIER_CURLIM_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISIER_CURLIM_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_ACMD_bit(a) hri_sdhc_set_EISIER_ACMD_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_ACMD_bit(a) hri_sdhc_get_EISIER_ACMD_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISIER_ACMD_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISIER_ACMD_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISIER_ACMD_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_ADMA_bit(a) hri_sdhc_set_EISIER_ADMA_bit(a)
+#define hri_sdhc_get_EISIER_EMMC_ADMA_bit(a) hri_sdhc_get_EISIER_ADMA_bit(a)
+#define hri_sdhc_write_EISIER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISIER_ADMA_bit(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISIER_ADMA_bit(a)
+#define hri_sdhc_toggle_EISIER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISIER_ADMA_bit(a)
+#define hri_sdhc_set_EISIER_EMMC_reg(a, b) hri_sdhc_set_EISIER_reg(a, b)
+#define hri_sdhc_get_EISIER_EMMC_reg(a, b) hri_sdhc_get_EISIER_reg(a, b)
+#define hri_sdhc_write_EISIER_EMMC_reg(a, b) hri_sdhc_write_EISIER_reg(a, b)
+#define hri_sdhc_clear_EISIER_EMMC_reg(a, b) hri_sdhc_clear_EISIER_reg(a, b)
+#define hri_sdhc_toggle_EISIER_EMMC_reg(a, b) hri_sdhc_toggle_EISIER_reg(a, b)
+#define hri_sdhc_read_EISIER_EMMC_reg(a) hri_sdhc_read_EISIER_reg(a)
+#define hri_sdhc_set_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_set_HC2R_EXTUN_bit(a)
+#define hri_sdhc_get_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_get_HC2R_EXTUN_bit(a)
+#define hri_sdhc_write_HC2R_EMMC_EXTUN_bit(a, b) hri_sdhc_write_HC2R_EXTUN_bit(a, b)
+#define hri_sdhc_clear_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_clear_HC2R_EXTUN_bit(a)
+#define hri_sdhc_toggle_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_toggle_HC2R_EXTUN_bit(a)
+#define hri_sdhc_set_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_set_HC2R_SLCKSEL_bit(a)
+#define hri_sdhc_get_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_get_HC2R_SLCKSEL_bit(a)
+#define hri_sdhc_write_HC2R_EMMC_SLCKSEL_bit(a, b) hri_sdhc_write_HC2R_SLCKSEL_bit(a, b)
+#define hri_sdhc_clear_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_clear_HC2R_SLCKSEL_bit(a)
+#define hri_sdhc_toggle_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_toggle_HC2R_SLCKSEL_bit(a)
+#define hri_sdhc_set_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_set_HC2R_PVALEN_bit(a)
+#define hri_sdhc_get_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_get_HC2R_PVALEN_bit(a)
+#define hri_sdhc_write_HC2R_EMMC_PVALEN_bit(a, b) hri_sdhc_write_HC2R_PVALEN_bit(a, b)
+#define hri_sdhc_clear_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_clear_HC2R_PVALEN_bit(a)
+#define hri_sdhc_toggle_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_toggle_HC2R_PVALEN_bit(a)
+#define hri_sdhc_set_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_set_HC2R_DRVSEL_bf(a, b)
+#define hri_sdhc_get_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_get_HC2R_DRVSEL_bf(a, b)
+#define hri_sdhc_write_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_write_HC2R_DRVSEL_bf(a, b)
+#define hri_sdhc_clear_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_clear_HC2R_DRVSEL_bf(a, b)
+#define hri_sdhc_toggle_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_toggle_HC2R_DRVSEL_bf(a, b)
+#define hri_sdhc_read_HC2R_EMMC_DRVSEL_bf(a) hri_sdhc_read_HC2R_DRVSEL_bf(a)
+#define hri_sdhc_set_HC2R_EMMC_reg(a, b) hri_sdhc_set_HC2R_reg(a, b)
+#define hri_sdhc_get_HC2R_EMMC_reg(a, b) hri_sdhc_get_HC2R_reg(a, b)
+#define hri_sdhc_write_HC2R_EMMC_reg(a, b) hri_sdhc_write_HC2R_reg(a, b)
+#define hri_sdhc_clear_HC2R_EMMC_reg(a, b) hri_sdhc_clear_HC2R_reg(a, b)
+#define hri_sdhc_toggle_HC2R_EMMC_reg(a, b) hri_sdhc_toggle_HC2R_reg(a, b)
+#define hri_sdhc_read_HC2R_EMMC_reg(a) hri_sdhc_read_HC2R_reg(a)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SDHC_E54_H_INCLUDED */
+#endif /* _SAME54_SDHC_COMPONENT_ */
diff --git a/hri/hri_sercom_e54.h b/hri/hri_sercom_e54.h
new file mode 100644
index 0000000..f5a52b0
--- /dev/null
+++ b/hri/hri_sercom_e54.h
@@ -0,0 +1,8892 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_SERCOM_COMPONENT_
+#ifndef _HRI_SERCOM_E54_H_INCLUDED_
+#define _HRI_SERCOM_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS)
+#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SERCOM_CRITICAL_SECTION_ENTER()
+#define SERCOM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_sercomi2cm_status_reg_t;
+typedef uint16_t hri_sercomi2cs_length_reg_t;
+typedef uint16_t hri_sercomi2cs_status_reg_t;
+typedef uint16_t hri_sercomspi_length_reg_t;
+typedef uint16_t hri_sercomspi_status_reg_t;
+typedef uint16_t hri_sercomusart_baud_reg_t;
+typedef uint16_t hri_sercomusart_length_reg_t;
+typedef uint16_t hri_sercomusart_status_reg_t;
+typedef uint32_t hri_sercomi2cm_addr_reg_t;
+typedef uint32_t hri_sercomi2cm_baud_reg_t;
+typedef uint32_t hri_sercomi2cm_ctrla_reg_t;
+typedef uint32_t hri_sercomi2cm_ctrlb_reg_t;
+typedef uint32_t hri_sercomi2cm_ctrlc_reg_t;
+typedef uint32_t hri_sercomi2cm_data_reg_t;
+typedef uint32_t hri_sercomi2cm_syncbusy_reg_t;
+typedef uint32_t hri_sercomi2cs_addr_reg_t;
+typedef uint32_t hri_sercomi2cs_ctrla_reg_t;
+typedef uint32_t hri_sercomi2cs_ctrlb_reg_t;
+typedef uint32_t hri_sercomi2cs_ctrlc_reg_t;
+typedef uint32_t hri_sercomi2cs_data_reg_t;
+typedef uint32_t hri_sercomi2cs_syncbusy_reg_t;
+typedef uint32_t hri_sercomspi_addr_reg_t;
+typedef uint32_t hri_sercomspi_ctrla_reg_t;
+typedef uint32_t hri_sercomspi_ctrlb_reg_t;
+typedef uint32_t hri_sercomspi_ctrlc_reg_t;
+typedef uint32_t hri_sercomspi_data_reg_t;
+typedef uint32_t hri_sercomspi_syncbusy_reg_t;
+typedef uint32_t hri_sercomusart_ctrla_reg_t;
+typedef uint32_t hri_sercomusart_ctrlb_reg_t;
+typedef uint32_t hri_sercomusart_ctrlc_reg_t;
+typedef uint32_t hri_sercomusart_data_reg_t;
+typedef uint32_t hri_sercomusart_syncbusy_reg_t;
+typedef uint8_t  hri_sercomi2cm_dbgctrl_reg_t;
+typedef uint8_t  hri_sercomi2cm_intenset_reg_t;
+typedef uint8_t  hri_sercomi2cm_intflag_reg_t;
+typedef uint8_t  hri_sercomi2cs_intenset_reg_t;
+typedef uint8_t  hri_sercomi2cs_intflag_reg_t;
+typedef uint8_t  hri_sercomspi_baud_reg_t;
+typedef uint8_t  hri_sercomspi_dbgctrl_reg_t;
+typedef uint8_t  hri_sercomspi_intenset_reg_t;
+typedef uint8_t  hri_sercomspi_intflag_reg_t;
+typedef uint8_t  hri_sercomusart_dbgctrl_reg_t;
+typedef uint8_t  hri_sercomusart_intenset_reg_t;
+typedef uint8_t  hri_sercomusart_intflag_reg_t;
+typedef uint8_t  hri_sercomusart_rxerrcnt_reg_t;
+typedef uint8_t  hri_sercomusart_rxpl_reg_t;
+
+static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+}
+
+static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+}
+
+static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+}
+
+static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+}
+
+static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR;
+}
+
+static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const            hw,
+                                                                          hri_sercomi2cm_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.INTFLAG.reg;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = mask;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR;
+}
+
+static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const            hw,
+                                                                          hri_sercomi2cs_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.INTFLAG.reg;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = mask;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL;
+}
+
+static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR;
+}
+
+static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const           hw,
+                                                                        hri_sercomspi_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.INTFLAG.reg;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = mask;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+}
+
+static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+}
+
+static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+}
+
+static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
+}
+
+static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const             hw,
+                                                                            hri_sercomusart_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.INTFLAG.reg;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = mask;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB;
+}
+
+static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB;
+	} else {
+		((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB;
+	}
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB;
+}
+
+static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB;
+	} else {
+		((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB;
+	}
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = mask;
+}
+
+static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const             hw,
+                                                                         hri_sercomi2cm_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.INTENSET.reg;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = data;
+	((Sercom *)hw)->I2CM.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = mask;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = mask;
+}
+
+static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const             hw,
+                                                                         hri_sercomi2cs_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.INTENSET.reg;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = data;
+	((Sercom *)hw)->I2CS.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = mask;
+}
+
+static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE;
+}
+
+static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE;
+}
+
+static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC;
+}
+
+static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC;
+}
+
+static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC;
+}
+
+static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC;
+}
+
+static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL;
+}
+
+static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL;
+}
+
+static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR;
+}
+
+static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = mask;
+}
+
+static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const            hw,
+                                                                       hri_sercomspi_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.INTENSET.reg;
+}
+
+static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = data;
+	((Sercom *)hw)->SPI.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = mask;
+}
+
+static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE;
+}
+
+static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE;
+}
+
+static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
+}
+
+static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC;
+}
+
+static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC;
+}
+
+static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC;
+}
+
+static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS;
+}
+
+static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS;
+}
+
+static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC;
+}
+
+static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC;
+}
+
+static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK;
+}
+
+static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK;
+}
+
+static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR;
+}
+
+static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = mask;
+}
+
+static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const              hw,
+                                                                           hri_sercomusart_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.INTENSET.reg;
+}
+
+static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = data;
+	((Sercom *)hw)->USART.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = mask;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_LENGTH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_LENGTH) >> SERCOM_I2CM_SYNCBUSY_LENGTH_Pos;
+}
+
+static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const             hw,
+                                                                            hri_sercomi2cm_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.SYNCBUSY.reg;
+}
+
+static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomi2cs_get_SYNCBUSY_LENGTH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_LENGTH) >> SERCOM_I2CS_SYNCBUSY_LENGTH_Pos;
+}
+
+static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const             hw,
+                                                                            hri_sercomi2cs_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.SYNCBUSY.reg;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_LENGTH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_LENGTH) >> SERCOM_SPI_SYNCBUSY_LENGTH_Pos;
+}
+
+static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const            hw,
+                                                                          hri_sercomspi_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.SYNCBUSY.reg;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_RXERRCNT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_RXERRCNT) >> SERCOM_USART_SYNCBUSY_RXERRCNT_Pos;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_LENGTH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_LENGTH) >> SERCOM_USART_SYNCBUSY_LENGTH_Pos;
+}
+
+static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const              hw,
+                                                                              hri_sercomusart_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.SYNCBUSY.reg;
+}
+
+static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_get_RXERRCNT_reg(const void *const              hw,
+                                                                              hri_sercomusart_rxerrcnt_reg_t mask)
+{
+	uint8_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.RXERRCNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_read_RXERRCNT_reg(const void *const hw)
+{
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->USART.RXERRCNT.reg;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_ENABLE;
+	tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_PINOUT;
+	tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN;
+	tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN;
+	tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SCLSM;
+	tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const          hw,
+                                                                          hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_MODE(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const          hw,
+                                                                             hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const          hw,
+                                                                           hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_SPEED(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const          hw,
+                                                                              hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const          hw,
+                                                                      hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	return ((Sercom *)hw)->I2CM.CTRLA.reg;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_ENABLE;
+	tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_PINOUT;
+	tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN;
+	tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SCLSM;
+	tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const          hw,
+                                                                          hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk;
+	tmp |= SERCOM_I2CS_CTRLA_MODE(data);
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const          hw,
+                                                                             hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk;
+	tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data);
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const          hw,
+                                                                           hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk;
+	tmp |= SERCOM_I2CS_CTRLA_SPEED(data);
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const          hw,
+                                                                      hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg = data;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	return ((Sercom *)hw)->I2CS.CTRLA.reg;
+}
+
+static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_ENABLE;
+	tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_IBON;
+	tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_CPHA;
+	tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_CPOL;
+	tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_DORD;
+	tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk;
+	tmp |= SERCOM_SPI_CTRLA_MODE(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk;
+	tmp |= SERCOM_SPI_CTRLA_DOPO(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk;
+	tmp |= SERCOM_SPI_CTRLA_DIPO(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk;
+	tmp |= SERCOM_SPI_CTRLA_FORM(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const         hw,
+                                                                    hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg = data;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	return ((Sercom *)hw)->SPI.CTRLA.reg;
+}
+
+static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_ENABLE;
+	tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_IBON;
+	tmp |= value << SERCOM_USART_CTRLA_IBON_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_TXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_TXINV_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_TXINV) >> SERCOM_USART_CTRLA_TXINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_TXINV_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_TXINV;
+	tmp |= value << SERCOM_USART_CTRLA_TXINV_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_TXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_TXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_RXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_RXINV_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RXINV) >> SERCOM_USART_CTRLA_RXINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_RXINV_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_RXINV;
+	tmp |= value << SERCOM_USART_CTRLA_RXINV_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_RXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_RXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_CMODE;
+	tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_CPOL;
+	tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_DORD;
+	tmp |= value << SERCOM_USART_CTRLA_DORD_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_MODE_Msk;
+	tmp |= SERCOM_USART_CTRLA_MODE(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const           hw,
+                                                                             hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk;
+	tmp |= SERCOM_USART_CTRLA_SAMPR(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk;
+	tmp |= SERCOM_USART_CTRLA_TXPO(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk;
+	tmp |= SERCOM_USART_CTRLA_RXPO(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const           hw,
+                                                                             hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk;
+	tmp |= SERCOM_USART_CTRLA_SAMPA(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_FORM_Msk;
+	tmp |= SERCOM_USART_CTRLA_FORM(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const           hw,
+                                                                        hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg = data;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	return ((Sercom *)hw)->USART.CTRLA.reg;
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_SMEN;
+	tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_QCEN;
+	tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_ACKACT;
+	tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos;
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const          hw,
+                                                                         hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk;
+	tmp |= SERCOM_I2CM_CTRLB_CMD(data);
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const          hw,
+                                                                      hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->I2CM.CTRLB.reg;
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_SMEN;
+	tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_GCMD;
+	tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_AACKEN;
+	tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_ACKACT;
+	tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const          hw,
+                                                                           hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk;
+	tmp |= SERCOM_I2CS_CTRLB_AMODE(data);
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const          hw,
+                                                                         hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk;
+	tmp |= SERCOM_I2CS_CTRLB_CMD(data);
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const          hw,
+                                                                      hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.CTRLB.reg;
+}
+
+static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_PLOADEN;
+	tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_SSDE;
+	tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_MSSEN;
+	tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_RXEN;
+	tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const         hw,
+                                                                          hri_sercomspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk;
+	tmp |= SERCOM_SPI_CTRLB_CHSIZE(data);
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const         hw,
+                                                                         hri_sercomspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk;
+	tmp |= SERCOM_SPI_CTRLB_AMODE(data);
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const         hw,
+                                                                    hri_sercomspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg = data;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw)
+{
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->SPI.CTRLB.reg;
+}
+
+static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_SBMODE;
+	tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_COLDEN;
+	tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_SFDE;
+	tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_ENC;
+	tmp |= value << SERCOM_USART_CTRLB_ENC_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_PMODE;
+	tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_TXEN;
+	tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_RXEN;
+	tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const           hw,
+                                                                              hri_sercomusart_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk;
+	tmp |= SERCOM_USART_CTRLB_CHSIZE(data);
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_LINCMD(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_LINCMD_bf(const void *const           hw,
+                                                                              hri_sercomusart_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_LINCMD(mask)) >> SERCOM_USART_CTRLB_LINCMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_LINCMD_Msk;
+	tmp |= SERCOM_USART_CTRLB_LINCMD(data);
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_LINCMD(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_LINCMD(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_LINCMD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_LINCMD_Msk) >> SERCOM_USART_CTRLB_LINCMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const           hw,
+                                                                        hri_sercomusart_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg = data;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw)
+{
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->USART.CTRLB.reg;
+}
+
+static inline void hri_sercomi2cm_set_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg |= SERCOM_I2CM_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLC_DATA32B_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLC.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLC_DATA32B) >> SERCOM_I2CM_CTRLC_DATA32B_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLC_DATA32B_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLC.reg;
+	tmp &= ~SERCOM_I2CM_CTRLC_DATA32B;
+	tmp |= value << SERCOM_I2CM_CTRLC_DATA32B_Pos;
+	((Sercom *)hw)->I2CM.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg &= ~SERCOM_I2CM_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg ^= SERCOM_I2CM_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_get_CTRLC_reg(const void *const          hw,
+                                                                      hri_sercomi2cm_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLC.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_read_CTRLC_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.CTRLC.reg;
+}
+
+static inline void hri_sercomi2cs_set_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLC_DATA32B_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLC.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLC_DATA32B) >> SERCOM_I2CS_CTRLC_DATA32B_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLC_DATA32B_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLC.reg;
+	tmp &= ~SERCOM_I2CS_CTRLC_DATA32B;
+	tmp |= value << SERCOM_I2CS_CTRLC_DATA32B_Pos;
+	((Sercom *)hw)->I2CS.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_SDASETUP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_SDASETUP_bf(const void *const          hw,
+                                                                              hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLC.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP(mask)) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLC.reg;
+	tmp &= ~SERCOM_I2CS_CTRLC_SDASETUP_Msk;
+	tmp |= SERCOM_I2CS_CTRLC_SDASETUP(data);
+	((Sercom *)hw)->I2CS.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_SDASETUP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_SDASETUP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_SDASETUP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLC.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP_Msk) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_reg(const void *const          hw,
+                                                                      hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLC.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.CTRLC.reg;
+}
+
+static inline void hri_sercomspi_set_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLC_DATA32B_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLC.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLC_DATA32B) >> SERCOM_SPI_CTRLC_DATA32B_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLC_DATA32B_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLC.reg;
+	tmp &= ~SERCOM_SPI_CTRLC_DATA32B;
+	tmp |= value << SERCOM_SPI_CTRLC_DATA32B_Pos;
+	((Sercom *)hw)->SPI.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLC_DATA32B_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_DATA32B;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_ICSPACE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_ICSPACE_bf(const void *const         hw,
+                                                                           hri_sercomspi_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLC.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE(mask)) >> SERCOM_SPI_CTRLC_ICSPACE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLC.reg;
+	tmp &= ~SERCOM_SPI_CTRLC_ICSPACE_Msk;
+	tmp |= SERCOM_SPI_CTRLC_ICSPACE(data);
+	((Sercom *)hw)->SPI.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_ICSPACE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_ICSPACE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_ICSPACE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLC.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE_Msk) >> SERCOM_SPI_CTRLC_ICSPACE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_reg(const void *const         hw,
+                                                                    hri_sercomspi_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLC.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.CTRLC.reg;
+}
+
+static inline void hri_sercomusart_set_CTRLC_INACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_INACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLC_INACK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_INACK) >> SERCOM_USART_CTRLC_INACK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_INACK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_INACK;
+	tmp |= value << SERCOM_USART_CTRLC_INACK_Pos;
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_INACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_INACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_INACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_INACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLC_DSNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DSNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLC_DSNACK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_DSNACK) >> SERCOM_USART_CTRLC_DSNACK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_DSNACK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_DSNACK;
+	tmp |= value << SERCOM_USART_CTRLC_DSNACK_Pos;
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_DSNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DSNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_DSNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DSNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_GTIME_bf(const void *const           hw,
+                                                                             hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_GTIME(mask)) >> SERCOM_USART_CTRLC_GTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_GTIME_Msk;
+	tmp |= SERCOM_USART_CTRLC_GTIME(data);
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_GTIME(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_GTIME(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_GTIME_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_GTIME_Msk) >> SERCOM_USART_CTRLC_GTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_BRKLEN(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_BRKLEN_bf(const void *const           hw,
+                                                                              hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN(mask)) >> SERCOM_USART_CTRLC_BRKLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_BRKLEN_Msk;
+	tmp |= SERCOM_USART_CTRLC_BRKLEN(data);
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_BRKLEN(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_BRKLEN(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_BRKLEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN_Msk) >> SERCOM_USART_CTRLC_BRKLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_HDRDLY(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_HDRDLY_bf(const void *const           hw,
+                                                                              hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY(mask)) >> SERCOM_USART_CTRLC_HDRDLY_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_HDRDLY_Msk;
+	tmp |= SERCOM_USART_CTRLC_HDRDLY(data);
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_HDRDLY(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_HDRDLY(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_HDRDLY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY_Msk) >> SERCOM_USART_CTRLC_HDRDLY_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_MAXITER(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_MAXITER_bf(const void *const           hw,
+                                                                               hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_MAXITER(mask)) >> SERCOM_USART_CTRLC_MAXITER_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_MAXITER_Msk;
+	tmp |= SERCOM_USART_CTRLC_MAXITER(data);
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_MAXITER(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_MAXITER(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_MAXITER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_MAXITER_Msk) >> SERCOM_USART_CTRLC_MAXITER_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DATA32B(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_DATA32B_bf(const void *const           hw,
+                                                                               hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_DATA32B(mask)) >> SERCOM_USART_CTRLC_DATA32B_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_DATA32B_Msk;
+	tmp |= SERCOM_USART_CTRLC_DATA32B(data);
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DATA32B(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DATA32B(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_DATA32B_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_DATA32B_Msk) >> SERCOM_USART_CTRLC_DATA32B_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_reg(const void *const           hw,
+                                                                        hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.CTRLC.reg;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const         hw,
+                                                                        hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk;
+	tmp |= SERCOM_I2CM_BAUD_BAUD(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const         hw,
+                                                                           hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk;
+	tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const         hw,
+                                                                          hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk;
+	tmp |= SERCOM_I2CM_BAUD_HSBAUD(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const         hw,
+                                                                             hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk;
+	tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const         hw,
+                                                                    hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.BAUD.reg;
+}
+
+static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const        hw,
+                                                                      hri_sercomspi_baud_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk;
+	tmp |= SERCOM_SPI_BAUD_BAUD(data);
+	((Sercom *)hw)->SPI.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.BAUD.reg;
+}
+
+static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const          hw,
+                                                                               hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const          hw,
+                                                                                 hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const          hw,
+                                                                             hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const          hw,
+                                                                               hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk;
+	tmp |= SERCOM_USART_BAUD_FRAC_FP(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk;
+	tmp |= SERCOM_USART_BAUD_FRACFP_FP(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const          hw,
+                                                                          hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const          hw,
+                                                                                  hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const          hw,
+                                                                      hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.BAUD.reg;
+}
+
+static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const          hw,
+                                                                          hri_sercomusart_rxpl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp &= ~SERCOM_USART_RXPL_RXPL_Msk;
+	tmp |= SERCOM_USART_RXPL_RXPL(data);
+	((Sercom *)hw)->USART.RXPL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const          hw,
+                                                                      hri_sercomusart_rxpl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.RXPL.reg;
+}
+
+static inline void hri_sercomi2cs_set_LENGTH_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LENEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_LENGTH_LENEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.LENGTH.reg;
+	tmp = (tmp & SERCOM_I2CS_LENGTH_LENEN) >> SERCOM_I2CS_LENGTH_LENEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_LENGTH_LENEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.LENGTH.reg;
+	tmp &= ~SERCOM_I2CS_LENGTH_LENEN;
+	tmp |= value << SERCOM_I2CS_LENGTH_LENEN_Pos;
+	((Sercom *)hw)->I2CS.LENGTH.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_LENGTH_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LENEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_LENGTH_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LENEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LEN(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_LEN_bf(const void *const           hw,
+                                                                           hri_sercomi2cs_length_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.LENGTH.reg;
+	tmp = (tmp & SERCOM_I2CS_LENGTH_LEN(mask)) >> SERCOM_I2CS_LENGTH_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.LENGTH.reg;
+	tmp &= ~SERCOM_I2CS_LENGTH_LEN_Msk;
+	tmp |= SERCOM_I2CS_LENGTH_LEN(data);
+	((Sercom *)hw)->I2CS.LENGTH.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LEN(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LEN(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_LEN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.LENGTH.reg;
+	tmp = (tmp & SERCOM_I2CS_LENGTH_LEN_Msk) >> SERCOM_I2CS_LENGTH_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg |= mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_reg(const void *const           hw,
+                                                                        hri_sercomi2cs_length_reg_t mask)
+{
+	uint16_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CS.LENGTH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg = data;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg &= ~mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.LENGTH.reg ^= mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_reg(const void *const hw)
+{
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->I2CS.LENGTH.reg;
+}
+
+static inline void hri_sercomspi_set_LENGTH_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LENEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_LENGTH_LENEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->SPI.LENGTH.reg;
+	tmp = (tmp & SERCOM_SPI_LENGTH_LENEN) >> SERCOM_SPI_LENGTH_LENEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_LENGTH_LENEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.LENGTH.reg;
+	tmp &= ~SERCOM_SPI_LENGTH_LENEN;
+	tmp |= value << SERCOM_SPI_LENGTH_LENEN_Pos;
+	((Sercom *)hw)->SPI.LENGTH.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_LENGTH_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LENEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_LENGTH_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LENEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LEN(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_LEN_bf(const void *const          hw,
+                                                                         hri_sercomspi_length_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->SPI.LENGTH.reg;
+	tmp = (tmp & SERCOM_SPI_LENGTH_LEN(mask)) >> SERCOM_SPI_LENGTH_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.LENGTH.reg;
+	tmp &= ~SERCOM_SPI_LENGTH_LEN_Msk;
+	tmp |= SERCOM_SPI_LENGTH_LEN(data);
+	((Sercom *)hw)->SPI.LENGTH.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LEN(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LEN(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_LEN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->SPI.LENGTH.reg;
+	tmp = (tmp & SERCOM_SPI_LENGTH_LEN_Msk) >> SERCOM_SPI_LENGTH_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg |= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_reg(const void *const          hw,
+                                                                      hri_sercomspi_length_reg_t mask)
+{
+	uint16_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->SPI.LENGTH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg = data;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg &= ~mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.LENGTH.reg ^= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_reg(const void *const hw)
+{
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->SPI.LENGTH.reg;
+}
+
+static inline void hri_sercomusart_set_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LEN(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LEN_bf(const void *const            hw,
+                                                                             hri_sercomusart_length_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp = (tmp & SERCOM_USART_LENGTH_LEN(mask)) >> SERCOM_USART_LENGTH_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp &= ~SERCOM_USART_LENGTH_LEN_Msk;
+	tmp |= SERCOM_USART_LENGTH_LEN(data);
+	((Sercom *)hw)->USART.LENGTH.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LEN(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LEN(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LEN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp = (tmp & SERCOM_USART_LENGTH_LEN_Msk) >> SERCOM_USART_LENGTH_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LENEN(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LENEN_bf(const void *const            hw,
+                                                                               hri_sercomusart_length_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp = (tmp & SERCOM_USART_LENGTH_LENEN(mask)) >> SERCOM_USART_LENGTH_LENEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp &= ~SERCOM_USART_LENGTH_LENEN_Msk;
+	tmp |= SERCOM_USART_LENGTH_LENEN(data);
+	((Sercom *)hw)->USART.LENGTH.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LENEN(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LENEN(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LENEN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp = (tmp & SERCOM_USART_LENGTH_LENEN_Msk) >> SERCOM_USART_LENGTH_LENEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg |= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_reg(const void *const            hw,
+                                                                          hri_sercomusart_length_reg_t mask)
+{
+	uint16_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.LENGTH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg = data;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg &= ~mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.LENGTH.reg ^= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_reg(const void *const hw)
+{
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->USART.LENGTH.reg;
+}
+
+static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_LENEN;
+	tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos;
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_HS;
+	tmp |= value << SERCOM_I2CM_ADDR_HS_Pos;
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_TENBITEN;
+	tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos;
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const         hw,
+                                                                        hri_sercomi2cm_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk;
+	tmp |= SERCOM_I2CM_ADDR_ADDR(data);
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const         hw,
+                                                                       hri_sercomi2cm_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk;
+	tmp |= SERCOM_I2CM_ADDR_LEN(data);
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const         hw,
+                                                                    hri_sercomi2cm_addr_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.ADDR.reg;
+}
+
+static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_GENCEN;
+	tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos;
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_TENBITEN;
+	tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos;
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const         hw,
+                                                                        hri_sercomi2cs_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk;
+	tmp |= SERCOM_I2CS_ADDR_ADDR(data);
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const         hw,
+                                                                            hri_sercomi2cs_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk;
+	tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data);
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const         hw,
+                                                                    hri_sercomi2cs_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.ADDR.reg;
+}
+
+static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const        hw,
+                                                                      hri_sercomspi_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk;
+	tmp |= SERCOM_SPI_ADDR_ADDR(data);
+	((Sercom *)hw)->SPI.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const        hw,
+                                                                          hri_sercomspi_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk;
+	tmp |= SERCOM_SPI_ADDR_ADDRMASK(data);
+	((Sercom *)hw)->SPI.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.ADDR.reg;
+}
+
+static inline void hri_sercomi2cm_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg |= SERCOM_I2CM_DATA_DATA(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_DATA_bf(const void *const         hw,
+                                                                        hri_sercomi2cm_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp = (tmp & SERCOM_I2CM_DATA_DATA(mask)) >> SERCOM_I2CM_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp &= ~SERCOM_I2CM_DATA_DATA_Msk;
+	tmp |= SERCOM_I2CM_DATA_DATA(data);
+	((Sercom *)hw)->I2CM.DATA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg &= ~SERCOM_I2CM_DATA_DATA(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg ^= SERCOM_I2CM_DATA_DATA(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_reg(const void *const         hw,
+                                                                    hri_sercomi2cm_data_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.DATA.reg;
+}
+
+static inline void hri_sercomi2cs_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg |= SERCOM_I2CS_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_DATA_bf(const void *const         hw,
+                                                                        hri_sercomi2cs_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp = (tmp & SERCOM_I2CS_DATA_DATA(mask)) >> SERCOM_I2CS_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp &= ~SERCOM_I2CS_DATA_DATA_Msk;
+	tmp |= SERCOM_I2CS_DATA_DATA(data);
+	((Sercom *)hw)->I2CS.DATA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg &= ~SERCOM_I2CS_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg ^= SERCOM_I2CS_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_reg(const void *const         hw,
+                                                                    hri_sercomi2cs_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.DATA.reg;
+}
+
+static inline void hri_sercomspi_set_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg |= SERCOM_SPI_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_DATA_bf(const void *const        hw,
+                                                                      hri_sercomspi_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp = (tmp & SERCOM_SPI_DATA_DATA(mask)) >> SERCOM_SPI_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp &= ~SERCOM_SPI_DATA_DATA_Msk;
+	tmp |= SERCOM_SPI_DATA_DATA(data);
+	((Sercom *)hw)->SPI.DATA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg &= ~SERCOM_SPI_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg ^= SERCOM_SPI_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp = (tmp & SERCOM_SPI_DATA_DATA_Msk) >> SERCOM_SPI_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.DATA.reg;
+}
+
+static inline void hri_sercomusart_set_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg |= SERCOM_USART_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_DATA_bf(const void *const          hw,
+                                                                          hri_sercomusart_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp = (tmp & SERCOM_USART_DATA_DATA(mask)) >> SERCOM_USART_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp &= ~SERCOM_USART_DATA_DATA_Msk;
+	tmp |= SERCOM_USART_DATA_DATA(data);
+	((Sercom *)hw)->USART.DATA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg &= ~SERCOM_USART_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg ^= SERCOM_USART_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_reg(const void *const          hw,
+                                                                      hri_sercomusart_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.DATA.reg;
+}
+
+static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+	tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+	tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos;
+	((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const            hw,
+                                                                          hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+}
+
+static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
+	tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
+	tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP;
+	tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos;
+	((Sercom *)hw)->SPI.DBGCTRL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const           hw,
+                                                                        hri_sercomspi_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.DBGCTRL.reg;
+}
+
+static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
+	tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
+	tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP;
+	tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos;
+	((Sercom *)hw)->USART.DBGCTRL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const             hw,
+                                                                            hri_sercomusart_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.DBGCTRL.reg;
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_LENERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LENERR) >> SERCOM_I2CS_STATUS_LENERR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const           hw,
+                                                                        hri_sercomi2cs_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.STATUS.reg;
+}
+
+static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos;
+}
+
+static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_STATUS_LENERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_LENERR) >> SERCOM_SPI_STATUS_LENERR_Pos;
+}
+
+static inline void hri_sercomspi_clear_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const          hw,
+                                                                      hri_sercomspi_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->SPI.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.STATUS.reg = mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.STATUS.reg;
+}
+
+static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_TXE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_TXE) >> SERCOM_USART_STATUS_TXE_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_TXE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_TXE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_ITER_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ITER) >> SERCOM_USART_STATUS_ITER_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_ITER_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ITER;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const            hw,
+                                                                          hri_sercomusart_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.STATUS.reg;
+}
+
+static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_BUSERR;
+	tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_ARBLOST;
+	tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_RXNACK;
+	tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT;
+	tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD;
+	tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT;
+	tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT;
+	tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_LENERR;
+	tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const           hw,
+                                                                                hri_sercomi2cm_status_reg_t mask)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos;
+}
+
+static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk;
+	tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data);
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const           hw,
+                                                                        hri_sercomi2cm_status_reg_t mask)
+{
+	uint16_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.STATUS.reg |= mask;
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.STATUS.reg;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data)
+{
+	((Sercom *)hw)->I2CM.STATUS.reg = data;
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.STATUS.reg ^= mask;
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_sercomusart_set_BAUD_FRAC_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b)
+#define hri_sercomusart_get_BAUD_FRAC_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b)
+#define hri_sercomusart_write_BAUD_FRAC_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b)
+#define hri_sercomusart_clear_BAUD_FRAC_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b)
+#define hri_sercomusart_toggle_BAUD_FRAC_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b)
+#define hri_sercomusart_read_BAUD_FRAC_reg(a) hri_sercomusart_read_BAUD_reg(a)
+#define hri_sercomusart_set_BAUD_FRACFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b)
+#define hri_sercomusart_get_BAUD_FRACFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b)
+#define hri_sercomusart_write_BAUD_FRACFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b)
+#define hri_sercomusart_clear_BAUD_FRACFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b)
+#define hri_sercomusart_toggle_BAUD_FRACFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b)
+#define hri_sercomusart_read_BAUD_FRACFP_reg(a) hri_sercomusart_read_BAUD_reg(a)
+#define hri_sercomusart_set_BAUD_USARTFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b)
+#define hri_sercomusart_get_BAUD_USARTFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b)
+#define hri_sercomusart_write_BAUD_USARTFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b)
+#define hri_sercomusart_clear_BAUD_USARTFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b)
+#define hri_sercomusart_toggle_BAUD_USARTFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b)
+#define hri_sercomusart_read_BAUD_USARTFP_reg(a) hri_sercomusart_read_BAUD_reg(a)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SERCOM_E54_H_INCLUDED */
+#endif /* _SAME54_SERCOM_COMPONENT_ */
diff --git a/hri/hri_supc_e54.h b/hri/hri_supc_e54.h
new file mode 100644
index 0000000..3f38d15
--- /dev/null
+++ b/hri/hri_supc_e54.h
@@ -0,0 +1,2302 @@
+/**
+ * \file
+ *
+ * \brief SAM SUPC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_SUPC_COMPONENT_
+#ifndef _HRI_SUPC_E54_H_INCLUDED_
+#define _HRI_SUPC_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SUPC_CRITICAL_SECTIONS)
+#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SUPC_CRITICAL_SECTION_ENTER()
+#define SUPC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_supc_bbps_reg_t;
+typedef uint32_t hri_supc_bkin_reg_t;
+typedef uint32_t hri_supc_bkout_reg_t;
+typedef uint32_t hri_supc_bod12_reg_t;
+typedef uint32_t hri_supc_bod33_reg_t;
+typedef uint32_t hri_supc_intenset_reg_t;
+typedef uint32_t hri_supc_intflag_reg_t;
+typedef uint32_t hri_supc_status_reg_t;
+typedef uint32_t hri_supc_vref_reg_t;
+typedef uint32_t hri_supc_vreg_reg_t;
+
+static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET;
+}
+
+static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_BOD12RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_BOD12RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_BOD12DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_BOD12DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET;
+}
+
+static inline bool hri_supc_get_INTFLAG_B12SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_B12SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY;
+}
+
+static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY;
+}
+
+static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET;
+}
+
+static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY;
+}
+
+static inline bool hri_supc_get_interrupt_BOD12RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_BOD12RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY;
+}
+
+static inline bool hri_supc_get_interrupt_BOD12DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_BOD12DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET;
+}
+
+static inline bool hri_supc_get_interrupt_B12SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_B12SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY;
+}
+
+static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY;
+}
+
+static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY;
+}
+
+static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Supc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask)
+{
+	((Supc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY;
+}
+
+static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY;
+}
+
+static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET;
+}
+
+static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos;
+}
+
+static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET;
+}
+
+static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY;
+}
+
+static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY;
+}
+
+static inline void hri_supc_set_INTEN_BOD12RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY;
+}
+
+static inline bool hri_supc_get_INTEN_BOD12RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12RDY) >> SUPC_INTENSET_BOD12RDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_BOD12RDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_BOD12RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY;
+}
+
+static inline void hri_supc_set_INTEN_BOD12DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET;
+}
+
+static inline bool hri_supc_get_INTEN_BOD12DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12DET) >> SUPC_INTENSET_BOD12DET_Pos;
+}
+
+static inline void hri_supc_write_INTEN_BOD12DET_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_BOD12DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET;
+}
+
+static inline void hri_supc_set_INTEN_B12SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY;
+}
+
+static inline bool hri_supc_get_INTEN_B12SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B12SRDY) >> SUPC_INTENSET_B12SRDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_B12SRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_B12SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY;
+}
+
+static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY;
+}
+
+static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY;
+}
+
+static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY;
+}
+
+static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY;
+}
+
+static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask)
+{
+	((Supc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw)
+{
+	return ((Supc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data)
+{
+	((Supc *)hw)->INTENSET.reg = data;
+	((Supc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask)
+{
+	((Supc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_BOD12RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12RDY) >> SUPC_STATUS_BOD12RDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_BOD12DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12DET) >> SUPC_STATUS_BOD12DET_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_B12SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B12SRDY) >> SUPC_STATUS_B12SRDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos;
+}
+
+static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw)
+{
+	return ((Supc *)hw)->STATUS.reg;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask)
+{
+	return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw)
+{
+	return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKIN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BKIN.reg;
+}
+
+static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_ENABLE;
+	tmp |= value << SUPC_BOD33_ENABLE_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_STDBYCFG;
+	tmp |= value << SUPC_BOD33_STDBYCFG_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_RUNSTDBY;
+	tmp |= value << SUPC_BOD33_RUNSTDBY_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_RUNHIB_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNHIB;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_RUNHIB_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_RUNHIB) >> SUPC_BOD33_RUNHIB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_RUNHIB_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_RUNHIB;
+	tmp |= value << SUPC_BOD33_RUNHIB_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_RUNHIB_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNHIB;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_RUNHIB_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNHIB;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_RUNBKUP;
+	tmp |= value << SUPC_BOD33_RUNBKUP_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_ACTION_Msk;
+	tmp |= SUPC_BOD33_ACTION(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_HYST(mask)) >> SUPC_BOD33_HYST_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_HYST_Msk;
+	tmp |= SUPC_BOD33_HYST(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_HYST_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_HYST_Msk) >> SUPC_BOD33_HYST_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_PSEL_Msk;
+	tmp |= SUPC_BOD33_PSEL(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_LEVEL_Msk;
+	tmp |= SUPC_BOD33_LEVEL(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VBATLEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_VBATLEVEL(mask)) >> SUPC_BOD33_VBATLEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_VBATLEVEL_Msk;
+	tmp |= SUPC_BOD33_VBATLEVEL(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VBATLEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VBATLEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_VBATLEVEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_VBATLEVEL_Msk) >> SUPC_BOD33_VBATLEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BOD33.reg;
+}
+
+static inline void hri_supc_set_BOD12_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD12_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_ENABLE) >> SUPC_BOD12_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD12_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_ENABLE;
+	tmp |= value << SUPC_BOD12_ENABLE_Pos;
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD12_HYST_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_HYST;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD12_HYST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_HYST) >> SUPC_BOD12_HYST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD12_HYST_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_HYST;
+	tmp |= value << SUPC_BOD12_HYST_Pos;
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_HYST_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_HYST;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_HYST_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_HYST;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD12_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD12_STDBYCFG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_STDBYCFG) >> SUPC_BOD12_STDBYCFG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD12_STDBYCFG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_STDBYCFG;
+	tmp |= value << SUPC_BOD12_STDBYCFG_Pos;
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD12_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD12_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_RUNSTDBY) >> SUPC_BOD12_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD12_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_RUNSTDBY;
+	tmp |= value << SUPC_BOD12_RUNSTDBY_Pos;
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD12_ACTCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD12_ACTCFG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_ACTCFG) >> SUPC_BOD12_ACTCFG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD12_ACTCFG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_ACTCFG;
+	tmp |= value << SUPC_BOD12_ACTCFG_Pos;
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_ACTCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_ACTCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_ACTION(mask)) >> SUPC_BOD12_ACTION_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_ACTION_Msk;
+	tmp |= SUPC_BOD12_ACTION(data);
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_ACTION_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_ACTION_Msk) >> SUPC_BOD12_ACTION_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_PSEL(mask)) >> SUPC_BOD12_PSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_PSEL_Msk;
+	tmp |= SUPC_BOD12_PSEL(data);
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_PSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_PSEL_Msk) >> SUPC_BOD12_PSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_LEVEL(mask)) >> SUPC_BOD12_LEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_LEVEL_Msk;
+	tmp |= SUPC_BOD12_LEVEL(data);
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_LEVEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_LEVEL_Msk) >> SUPC_BOD12_LEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BOD12.reg;
+}
+
+static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_ENABLE;
+	tmp |= value << SUPC_VREG_ENABLE_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_SEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_SEL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_SEL) >> SUPC_VREG_SEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_SEL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_SEL;
+	tmp |= value << SUPC_VREG_SEL_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_SEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_SEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_RUNBKUP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_RUNBKUP) >> SUPC_VREG_RUNBKUP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_RUNBKUP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_RUNBKUP;
+	tmp |= value << SUPC_VREG_RUNBKUP_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_VSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_VSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_VSEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_VSEN) >> SUPC_VREG_VSEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_VSEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_VSEN;
+	tmp |= value << SUPC_VREG_VSEN_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_VSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_VSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_VSPER_Msk;
+	tmp |= SUPC_VREG_VSPER(data);
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw)
+{
+	return ((Supc *)hw)->VREG.reg;
+}
+
+static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_TSEN;
+	tmp |= value << SUPC_VREF_TSEN_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_VREFOE;
+	tmp |= value << SUPC_VREF_VREFOE_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_TSSEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_TSSEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_TSSEL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_TSSEL) >> SUPC_VREF_TSSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_TSSEL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_TSSEL;
+	tmp |= value << SUPC_VREF_TSSEL_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_TSSEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSSEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_TSSEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSSEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_RUNSTDBY;
+	tmp |= value << SUPC_VREF_RUNSTDBY_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_ONDEMAND;
+	tmp |= value << SUPC_VREF_ONDEMAND_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_SEL_Msk;
+	tmp |= SUPC_VREF_SEL(data);
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw)
+{
+	return ((Supc *)hw)->VREF.reg;
+}
+
+static inline void hri_supc_set_BBPS_CONF_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BBPS_CONF_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp = (tmp & SUPC_BBPS_CONF) >> SUPC_BBPS_CONF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BBPS_CONF_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp &= ~SUPC_BBPS_CONF;
+	tmp |= value << SUPC_BBPS_CONF_Pos;
+	((Supc *)hw)->BBPS.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BBPS_CONF_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BBPS_CONF_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp &= ~SUPC_BBPS_WAKEEN;
+	tmp |= value << SUPC_BBPS_WAKEEN_Pos;
+	((Supc *)hw)->BBPS.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BBPS.reg;
+}
+
+static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_EN_Msk;
+	tmp |= SUPC_BKOUT_EN(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_CLR_Msk;
+	tmp |= SUPC_BKOUT_CLR(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_SET_Msk;
+	tmp |= SUPC_BKOUT_SET(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_RTCTGL_Msk;
+	tmp |= SUPC_BKOUT_RTCTGL(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BKOUT.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SUPC_E54_H_INCLUDED */
+#endif /* _SAME54_SUPC_COMPONENT_ */
diff --git a/hri/hri_systemcontrol_e54.h b/hri/hri_systemcontrol_e54.h
new file mode 100644
index 0000000..000ef90
--- /dev/null
+++ b/hri/hri_systemcontrol_e54.h
@@ -0,0 +1,992 @@
+/**
+ * \file
+ *
+ * \brief SAM SystemControl
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_SystemControl_COMPONENT_
+#ifndef _HRI_SystemControl_E54_H_INCLUDED_
+#define _HRI_SystemControl_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SystemControl_CRITICAL_SECTIONS)
+#define SystemControl_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SystemControl_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SystemControl_CRITICAL_SECTION_ENTER()
+#define SystemControl_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_systemcontrol_actlr_reg_t;
+typedef uint32_t hri_systemcontrol_adr_reg_t;
+typedef uint32_t hri_systemcontrol_afsr_reg_t;
+typedef uint32_t hri_systemcontrol_aircr_reg_t;
+typedef uint32_t hri_systemcontrol_bfar_reg_t;
+typedef uint32_t hri_systemcontrol_ccr_reg_t;
+typedef uint32_t hri_systemcontrol_cfsr_reg_t;
+typedef uint32_t hri_systemcontrol_cpacr_reg_t;
+typedef uint32_t hri_systemcontrol_cpuid_reg_t;
+typedef uint32_t hri_systemcontrol_dfr_reg_t;
+typedef uint32_t hri_systemcontrol_dfsr_reg_t;
+typedef uint32_t hri_systemcontrol_hfsr_reg_t;
+typedef uint32_t hri_systemcontrol_icsr_reg_t;
+typedef uint32_t hri_systemcontrol_ictr_reg_t;
+typedef uint32_t hri_systemcontrol_isar_reg_t;
+typedef uint32_t hri_systemcontrol_mmfar_reg_t;
+typedef uint32_t hri_systemcontrol_mmfr_reg_t;
+typedef uint32_t hri_systemcontrol_pfr_reg_t;
+typedef uint32_t hri_systemcontrol_scr_reg_t;
+typedef uint32_t hri_systemcontrol_shcsr_reg_t;
+typedef uint32_t hri_systemcontrol_shpr1_reg_t;
+typedef uint32_t hri_systemcontrol_shpr2_reg_t;
+typedef uint32_t hri_systemcontrol_shpr3_reg_t;
+typedef uint32_t hri_systemcontrol_vtor_reg_t;
+
+static inline hri_systemcontrol_ictr_reg_t hri_systemcontrol_get_ICTR_INTLINESNUM_bf(const void *const            hw,
+                                                                                     hri_systemcontrol_ictr_reg_t mask)
+{
+	return (((Systemcontrol *)hw)->ICTR.reg & SystemControl_ICTR_INTLINESNUM(mask)) >> 0;
+}
+
+static inline hri_systemcontrol_ictr_reg_t hri_systemcontrol_read_ICTR_INTLINESNUM_bf(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->ICTR.reg & SystemControl_ICTR_INTLINESNUM_Msk) >> 0;
+}
+
+static inline hri_systemcontrol_ictr_reg_t hri_systemcontrol_get_ICTR_reg(const void *const            hw,
+                                                                          hri_systemcontrol_ictr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->ICTR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_systemcontrol_ictr_reg_t hri_systemcontrol_read_ICTR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->ICTR.reg;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_REVISION_bf(const void *const             hw,
+                                                                                    hri_systemcontrol_cpuid_reg_t mask)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION(mask)) >> 0;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_REVISION_bf(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION_Msk) >> 0;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_PARTNO_bf(const void *const             hw,
+                                                                                  hri_systemcontrol_cpuid_reg_t mask)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO(mask)) >> 4;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_PARTNO_bf(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO_Msk) >> 4;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_CONSTANT_bf(const void *const             hw,
+                                                                                    hri_systemcontrol_cpuid_reg_t mask)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_CONSTANT(mask)) >> 16;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_CONSTANT_bf(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_CONSTANT_Msk) >> 16;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_VARIANT_bf(const void *const             hw,
+                                                                                   hri_systemcontrol_cpuid_reg_t mask)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT(mask)) >> 20;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_VARIANT_bf(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT_Msk) >> 20;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t
+hri_systemcontrol_get_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER(mask)) >> 24;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_IMPLEMENTER_bf(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER_Msk) >> 24;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_reg(const void *const             hw,
+                                                                            hri_systemcontrol_cpuid_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CPUID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->CPUID.reg;
+}
+
+static inline hri_systemcontrol_dfr_reg_t hri_systemcontrol_get_DFR_reg(const void *const           hw,
+                                                                        hri_systemcontrol_dfr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->DFR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_systemcontrol_dfr_reg_t hri_systemcontrol_read_DFR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->DFR.reg;
+}
+
+static inline hri_systemcontrol_adr_reg_t hri_systemcontrol_get_ADR_reg(const void *const           hw,
+                                                                        hri_systemcontrol_adr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->ADR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_systemcontrol_adr_reg_t hri_systemcontrol_read_ADR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->ADR.reg;
+}
+
+static inline hri_systemcontrol_mmfr_reg_t hri_systemcontrol_get_MMFR_reg(const void *const hw, uint8_t index,
+                                                                          hri_systemcontrol_mmfr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->MMFR[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_systemcontrol_mmfr_reg_t hri_systemcontrol_read_MMFR_reg(const void *const hw, uint8_t index)
+{
+	return ((Systemcontrol *)hw)->MMFR[index].reg;
+}
+
+static inline hri_systemcontrol_isar_reg_t hri_systemcontrol_get_ISAR_reg(const void *const hw, uint8_t index,
+                                                                          hri_systemcontrol_isar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->ISAR[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_systemcontrol_isar_reg_t hri_systemcontrol_read_ISAR_reg(const void *const hw, uint8_t index)
+{
+	return ((Systemcontrol *)hw)->ISAR[index].reg;
+}
+
+static inline void hri_systemcontrol_set_ACTLR_reg(const void *const hw, hri_systemcontrol_actlr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ACTLR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_actlr_reg_t hri_systemcontrol_get_ACTLR_reg(const void *const             hw,
+                                                                            hri_systemcontrol_actlr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->ACTLR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_ACTLR_reg(const void *const hw, hri_systemcontrol_actlr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ACTLR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_ACTLR_reg(const void *const hw, hri_systemcontrol_actlr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ACTLR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_ACTLR_reg(const void *const hw, hri_systemcontrol_actlr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ACTLR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_actlr_reg_t hri_systemcontrol_read_ACTLR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->ACTLR.reg;
+}
+
+static inline void hri_systemcontrol_set_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_reg(const void *const            hw,
+                                                                          hri_systemcontrol_icsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->ICSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->ICSR.reg;
+}
+
+static inline void hri_systemcontrol_set_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->VTOR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_reg(const void *const            hw,
+                                                                          hri_systemcontrol_vtor_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->VTOR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->VTOR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->VTOR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->VTOR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->VTOR.reg;
+}
+
+static inline void hri_systemcontrol_set_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_reg(const void *const             hw,
+                                                                            hri_systemcontrol_aircr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->AIRCR.reg;
+}
+
+static inline void hri_systemcontrol_set_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_get_SCR_reg(const void *const           hw,
+                                                                        hri_systemcontrol_scr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_read_SCR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->SCR.reg;
+}
+
+static inline void hri_systemcontrol_set_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CCR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_get_CCR_reg(const void *const           hw,
+                                                                        hri_systemcontrol_ccr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CCR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CCR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CCR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_read_CCR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->CCR.reg;
+}
+
+static inline void hri_systemcontrol_set_SHPR1_reg(const void *const hw, hri_systemcontrol_shpr1_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR1.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr1_reg_t hri_systemcontrol_get_SHPR1_reg(const void *const             hw,
+                                                                            hri_systemcontrol_shpr1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SHPR1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_SHPR1_reg(const void *const hw, hri_systemcontrol_shpr1_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR1.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SHPR1_reg(const void *const hw, hri_systemcontrol_shpr1_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR1.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SHPR1_reg(const void *const hw, hri_systemcontrol_shpr1_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR1.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr1_reg_t hri_systemcontrol_read_SHPR1_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->SHPR1.reg;
+}
+
+static inline void hri_systemcontrol_set_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR2.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_reg(const void *const             hw,
+                                                                            hri_systemcontrol_shpr2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SHPR2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR2.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR2.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR2.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->SHPR2.reg;
+}
+
+static inline void hri_systemcontrol_set_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_reg(const void *const             hw,
+                                                                            hri_systemcontrol_shpr3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SHPR3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->SHPR3.reg;
+}
+
+static inline void hri_systemcontrol_set_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHCSR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_get_SHCSR_reg(const void *const             hw,
+                                                                            hri_systemcontrol_shcsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SHCSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHCSR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHCSR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHCSR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_read_SHCSR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->SHCSR.reg;
+}
+
+static inline void hri_systemcontrol_set_CFSR_reg(const void *const hw, hri_systemcontrol_cfsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CFSR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_cfsr_reg_t hri_systemcontrol_get_CFSR_reg(const void *const            hw,
+                                                                          hri_systemcontrol_cfsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CFSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_CFSR_reg(const void *const hw, hri_systemcontrol_cfsr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CFSR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_CFSR_reg(const void *const hw, hri_systemcontrol_cfsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CFSR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_CFSR_reg(const void *const hw, hri_systemcontrol_cfsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CFSR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_cfsr_reg_t hri_systemcontrol_read_CFSR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->CFSR.reg;
+}
+
+static inline void hri_systemcontrol_set_HFSR_reg(const void *const hw, hri_systemcontrol_hfsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->HFSR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_hfsr_reg_t hri_systemcontrol_get_HFSR_reg(const void *const            hw,
+                                                                          hri_systemcontrol_hfsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->HFSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_HFSR_reg(const void *const hw, hri_systemcontrol_hfsr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->HFSR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_HFSR_reg(const void *const hw, hri_systemcontrol_hfsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->HFSR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_HFSR_reg(const void *const hw, hri_systemcontrol_hfsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->HFSR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_hfsr_reg_t hri_systemcontrol_read_HFSR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->HFSR.reg;
+}
+
+static inline void hri_systemcontrol_set_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->DFSR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_get_DFSR_reg(const void *const            hw,
+                                                                          hri_systemcontrol_dfsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->DFSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->DFSR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->DFSR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->DFSR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_read_DFSR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->DFSR.reg;
+}
+
+static inline void hri_systemcontrol_set_MMFAR_reg(const void *const hw, hri_systemcontrol_mmfar_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->MMFAR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_mmfar_reg_t hri_systemcontrol_get_MMFAR_reg(const void *const             hw,
+                                                                            hri_systemcontrol_mmfar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->MMFAR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_MMFAR_reg(const void *const hw, hri_systemcontrol_mmfar_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->MMFAR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_MMFAR_reg(const void *const hw, hri_systemcontrol_mmfar_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->MMFAR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_MMFAR_reg(const void *const hw, hri_systemcontrol_mmfar_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->MMFAR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_mmfar_reg_t hri_systemcontrol_read_MMFAR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->MMFAR.reg;
+}
+
+static inline void hri_systemcontrol_set_BFAR_reg(const void *const hw, hri_systemcontrol_bfar_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->BFAR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_bfar_reg_t hri_systemcontrol_get_BFAR_reg(const void *const            hw,
+                                                                          hri_systemcontrol_bfar_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->BFAR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_BFAR_reg(const void *const hw, hri_systemcontrol_bfar_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->BFAR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_BFAR_reg(const void *const hw, hri_systemcontrol_bfar_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->BFAR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_BFAR_reg(const void *const hw, hri_systemcontrol_bfar_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->BFAR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_bfar_reg_t hri_systemcontrol_read_BFAR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->BFAR.reg;
+}
+
+static inline void hri_systemcontrol_set_AFSR_reg(const void *const hw, hri_systemcontrol_afsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AFSR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_afsr_reg_t hri_systemcontrol_get_AFSR_reg(const void *const            hw,
+                                                                          hri_systemcontrol_afsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->AFSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_AFSR_reg(const void *const hw, hri_systemcontrol_afsr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AFSR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_AFSR_reg(const void *const hw, hri_systemcontrol_afsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AFSR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_AFSR_reg(const void *const hw, hri_systemcontrol_afsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AFSR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_afsr_reg_t hri_systemcontrol_read_AFSR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->AFSR.reg;
+}
+
+static inline void hri_systemcontrol_set_PFR_reg(const void *const hw, uint8_t index, hri_systemcontrol_pfr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->PFR[index].reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_pfr_reg_t hri_systemcontrol_get_PFR_reg(const void *const hw, uint8_t index,
+                                                                        hri_systemcontrol_pfr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->PFR[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_PFR_reg(const void *const hw, uint8_t index,
+                                                   hri_systemcontrol_pfr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->PFR[index].reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_PFR_reg(const void *const hw, uint8_t index,
+                                                   hri_systemcontrol_pfr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->PFR[index].reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_PFR_reg(const void *const hw, uint8_t index,
+                                                    hri_systemcontrol_pfr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->PFR[index].reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_pfr_reg_t hri_systemcontrol_read_PFR_reg(const void *const hw, uint8_t index)
+{
+	return ((Systemcontrol *)hw)->PFR[index].reg;
+}
+
+static inline void hri_systemcontrol_set_CPACR_reg(const void *const hw, hri_systemcontrol_cpacr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPACR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_cpacr_reg_t hri_systemcontrol_get_CPACR_reg(const void *const             hw,
+                                                                            hri_systemcontrol_cpacr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CPACR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_CPACR_reg(const void *const hw, hri_systemcontrol_cpacr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPACR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_CPACR_reg(const void *const hw, hri_systemcontrol_cpacr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPACR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_CPACR_reg(const void *const hw, hri_systemcontrol_cpacr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->CPACR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_cpacr_reg_t hri_systemcontrol_read_CPACR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->CPACR.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SystemControl_E54_H_INCLUDED */
+#endif /* _SAME54_SystemControl_COMPONENT_ */
diff --git a/hri/hri_systick_e54.h b/hri/hri_systick_e54.h
new file mode 100644
index 0000000..11a9224
--- /dev/null
+++ b/hri/hri_systick_e54.h
@@ -0,0 +1,219 @@
+/**
+ * \file
+ *
+ * \brief SAM SysTick
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_SysTick_COMPONENT_
+#ifndef _HRI_SysTick_E54_H_INCLUDED_
+#define _HRI_SysTick_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SysTick_CRITICAL_SECTIONS)
+#define SysTick_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SysTick_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SysTick_CRITICAL_SECTION_ENTER()
+#define SysTick_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_systick_calib_reg_t;
+typedef uint32_t hri_systick_csr_reg_t;
+typedef uint32_t hri_systick_cvr_reg_t;
+typedef uint32_t hri_systick_rvr_reg_t;
+
+static inline bool hri_systick_get_CALIB_SKEW_bit(const void *const hw)
+{
+	return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_SKEW) >> 30;
+}
+
+static inline bool hri_systick_get_CALIB_NOREF_bit(const void *const hw)
+{
+	return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_NOREF) >> 31;
+}
+
+static inline hri_systick_calib_reg_t hri_systick_get_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask)
+{
+	return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS(mask)) >> 0;
+}
+
+static inline hri_systick_calib_reg_t hri_systick_read_CALIB_TENMS_bf(const void *const hw)
+{
+	return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS_Msk) >> 0;
+}
+
+static inline hri_systick_calib_reg_t hri_systick_get_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CALIB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_systick_calib_reg_t hri_systick_read_CALIB_reg(const void *const hw)
+{
+	return ((Systick *)hw)->CALIB.reg;
+}
+
+static inline void hri_systick_set_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg |= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_csr_reg_t hri_systick_get_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systick_write_CSR_reg(const void *const hw, hri_systick_csr_reg_t data)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg = data;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg &= ~mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg ^= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_csr_reg_t hri_systick_read_CSR_reg(const void *const hw)
+{
+	return ((Systick *)hw)->CSR.reg;
+}
+
+static inline void hri_systick_set_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->RVR.reg |= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_rvr_reg_t hri_systick_get_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->RVR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systick_write_RVR_reg(const void *const hw, hri_systick_rvr_reg_t data)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->RVR.reg = data;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->RVR.reg &= ~mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->RVR.reg ^= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_rvr_reg_t hri_systick_read_RVR_reg(const void *const hw)
+{
+	return ((Systick *)hw)->RVR.reg;
+}
+
+static inline void hri_systick_set_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CVR.reg |= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_cvr_reg_t hri_systick_get_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CVR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systick_write_CVR_reg(const void *const hw, hri_systick_cvr_reg_t data)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CVR.reg = data;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CVR.reg &= ~mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CVR.reg ^= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_cvr_reg_t hri_systick_read_CVR_reg(const void *const hw)
+{
+	return ((Systick *)hw)->CVR.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SysTick_E54_H_INCLUDED */
+#endif /* _SAME54_SysTick_COMPONENT_ */
diff --git a/hri/hri_tc_e54.h b/hri/hri_tc_e54.h
new file mode 100644
index 0000000..a31cb2c
--- /dev/null
+++ b/hri/hri_tc_e54.h
@@ -0,0 +1,3003 @@
+/**
+ * \file
+ *
+ * \brief SAM TC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_TC_COMPONENT_
+#ifndef _HRI_TC_E54_H_INCLUDED_
+#define _HRI_TC_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_TC_CRITICAL_SECTIONS)
+#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define TC_CRITICAL_SECTION_ENTER()
+#define TC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_tc_evctrl_reg_t;
+typedef uint16_t hri_tccount16_cc_reg_t;
+typedef uint16_t hri_tccount16_ccbuf_reg_t;
+typedef uint16_t hri_tccount16_count_reg_t;
+typedef uint32_t hri_tc_ctrla_reg_t;
+typedef uint32_t hri_tc_syncbusy_reg_t;
+typedef uint32_t hri_tccount32_cc_reg_t;
+typedef uint32_t hri_tccount32_ccbuf_reg_t;
+typedef uint32_t hri_tccount32_count_reg_t;
+typedef uint8_t  hri_tc_ctrlbset_reg_t;
+typedef uint8_t  hri_tc_dbgctrl_reg_t;
+typedef uint8_t  hri_tc_drvctrl_reg_t;
+typedef uint8_t  hri_tc_intenset_reg_t;
+typedef uint8_t  hri_tc_intflag_reg_t;
+typedef uint8_t  hri_tc_status_reg_t;
+typedef uint8_t  hri_tc_wave_reg_t;
+typedef uint8_t  hri_tccount8_cc_reg_t;
+typedef uint8_t  hri_tccount8_ccbuf_reg_t;
+typedef uint8_t  hri_tccount8_count_reg_t;
+typedef uint8_t  hri_tccount8_per_reg_t;
+typedef uint8_t  hri_tccount8_perbuf_reg_t;
+
+static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg)
+{
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg)
+{
+	return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF;
+}
+
+static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR;
+}
+
+static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0;
+}
+
+static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1;
+}
+
+static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF;
+}
+
+static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR;
+}
+
+static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0;
+}
+
+static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1;
+}
+
+static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.INTFLAG.reg;
+}
+
+static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = mask;
+}
+
+static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR;
+}
+
+static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos;
+}
+
+static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR;
+	} else {
+		((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR;
+	}
+}
+
+static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR;
+}
+
+static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD;
+}
+
+static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos;
+}
+
+static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD;
+	} else {
+		((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD;
+	}
+}
+
+static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD;
+}
+
+static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT;
+}
+
+static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos;
+}
+
+static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT;
+	} else {
+		((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT;
+	}
+}
+
+static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT;
+}
+
+static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(mask);
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+	tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+	tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(data);
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data);
+}
+
+static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask);
+}
+
+static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = mask;
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+}
+
+static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = data;
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data;
+}
+
+static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = mask;
+}
+
+static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF;
+}
+
+static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos;
+}
+
+static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF;
+}
+
+static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR;
+}
+
+static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR;
+}
+
+static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0;
+}
+
+static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos;
+}
+
+static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0;
+}
+
+static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1;
+}
+
+static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos;
+}
+
+static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1;
+}
+
+static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = mask;
+}
+
+static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.INTENSET.reg;
+}
+
+static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = data;
+	((Tc *)hw)->COUNT16.INTENCLR.reg = ~data;
+}
+
+static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = mask;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos;
+}
+
+static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.SYNCBUSY.reg;
+}
+
+static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST);
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_ENABLE;
+	tmp |= value << TC_CTRLA_ENABLE_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_RUNSTDBY;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_RUNSTDBY;
+	tmp |= value << TC_CTRLA_RUNSTDBY_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_RUNSTDBY;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ONDEMAND;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_ONDEMAND;
+	tmp |= value << TC_CTRLA_ONDEMAND_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ONDEMAND;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ONDEMAND;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ALOCK;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_ALOCK;
+	tmp |= value << TC_CTRLA_ALOCK_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ALOCK;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ALOCK;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_CAPTEN0;
+	tmp |= value << TC_CTRLA_CAPTEN0_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_CAPTEN1;
+	tmp |= value << TC_CTRLA_CAPTEN1_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_COPEN0;
+	tmp |= value << TC_CTRLA_COPEN0_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_COPEN1;
+	tmp |= value << TC_CTRLA_COPEN1_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_MODE(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_MODE_Msk;
+	tmp |= TC_CTRLA_MODE(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_MODE(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_MODE(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_PRESCSYNC_Msk;
+	tmp |= TC_CTRLA_PRESCSYNC(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_PRESCALER_Msk;
+	tmp |= TC_CTRLA_PRESCALER(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE0(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTMODE0(mask)) >> TC_CTRLA_CAPTMODE0_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_CAPTMODE0_Msk;
+	tmp |= TC_CTRLA_CAPTMODE0(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE0(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE0(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTMODE0_Msk) >> TC_CTRLA_CAPTMODE0_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE1(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTMODE1(mask)) >> TC_CTRLA_CAPTMODE1_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_CAPTMODE1_Msk;
+	tmp |= TC_CTRLA_CAPTMODE1(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE1(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE1(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTMODE1_Msk) >> TC_CTRLA_CAPTMODE1_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	return ((Tc *)hw)->COUNT16.CTRLA.reg;
+}
+
+static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCINV;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_TCINV;
+	tmp |= value << TC_EVCTRL_TCINV_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCINV;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCINV;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCEI;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_TCEI;
+	tmp |= value << TC_EVCTRL_TCEI_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCEI;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCEI;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_OVFEO;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_OVFEO;
+	tmp |= value << TC_EVCTRL_OVFEO_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_OVFEO;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_OVFEO;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_MCEO0;
+	tmp |= value << TC_EVCTRL_MCEO0_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_MCEO1;
+	tmp |= value << TC_EVCTRL_MCEO1_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_EVACT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_EVACT_Msk;
+	tmp |= TC_EVCTRL_EVACT(data);
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.EVCTRL.reg;
+}
+
+static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg |= TC_WAVE_WAVEGEN(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp &= ~TC_WAVE_WAVEGEN_Msk;
+	tmp |= TC_WAVE_WAVEGEN(data);
+	((Tc *)hw)->COUNT16.WAVE.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg ^= TC_WAVE_WAVEGEN(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.WAVE.reg;
+}
+
+static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp &= ~TC_DRVCTRL_INVEN0;
+	tmp |= value << TC_DRVCTRL_INVEN0_Pos;
+	((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp &= ~TC_DRVCTRL_INVEN1;
+	tmp |= value << TC_DRVCTRL_INVEN1_Pos;
+	((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+}
+
+static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+	tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+	tmp &= ~TC_DBGCTRL_DBGRUN;
+	tmp |= value << TC_DBGCTRL_DBGRUN_Pos;
+	((Tc *)hw)->COUNT16.DBGCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+}
+
+static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const        hw,
+                                                                       hri_tccount8_count_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp &= ~TC_COUNT8_COUNT_COUNT_Msk;
+	tmp |= TC_COUNT8_COUNT_COUNT(data);
+	((Tc *)hw)->COUNT8.COUNT.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	return ((Tc *)hw)->COUNT8.COUNT.reg;
+}
+
+static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const         hw,
+                                                                         hri_tccount16_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp &= ~TC_COUNT16_COUNT_COUNT_Msk;
+	tmp |= TC_COUNT16_COUNT_COUNT(data);
+	((Tc *)hw)->COUNT16.COUNT.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_reg(const void *const         hw,
+                                                                    hri_tccount16_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	return ((Tc *)hw)->COUNT16.COUNT.reg;
+}
+
+static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const         hw,
+                                                                         hri_tccount32_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp &= ~TC_COUNT32_COUNT_COUNT_Msk;
+	tmp |= TC_COUNT32_COUNT_COUNT(data);
+	((Tc *)hw)->COUNT32.COUNT.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_reg(const void *const         hw,
+                                                                    hri_tccount32_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	return ((Tc *)hw)->COUNT32.COUNT.reg;
+}
+
+static inline void hri_tccount8_set_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp &= ~TC_COUNT8_PER_PER_Msk;
+	tmp |= TC_COUNT8_PER_PER(data);
+	((Tc *)hw)->COUNT8.PER.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_PER_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PER_reg(const void *const hw, hri_tccount8_per_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	return ((Tc *)hw)->COUNT8.PER.reg;
+}
+
+static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index,
+                                                              hri_tccount8_cc_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp &= ~TC_COUNT8_CC_CC_Msk;
+	tmp |= TC_COUNT8_CC_CC(data);
+	((Tc *)hw)->COUNT8.CC[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index,
+                                                            hri_tccount8_cc_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	return ((Tc *)hw)->COUNT8.CC[index].reg;
+}
+
+static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index,
+                                                                hri_tccount16_cc_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp &= ~TC_COUNT16_CC_CC_Msk;
+	tmp |= TC_COUNT16_CC_CC(data);
+	((Tc *)hw)->COUNT16.CC[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index,
+                                                              hri_tccount16_cc_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	return ((Tc *)hw)->COUNT16.CC[index].reg;
+}
+
+static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index,
+                                                                hri_tccount32_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp &= ~TC_COUNT32_CC_CC_Msk;
+	tmp |= TC_COUNT32_CC_CC(data);
+	((Tc *)hw)->COUNT32.CC[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index,
+                                                              hri_tccount32_cc_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	return ((Tc *)hw)->COUNT32.CC[index].reg;
+}
+
+static inline void hri_tccount8_set_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_PERBUF_bf(const void *const         hw,
+                                                                          hri_tccount8_perbuf_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk;
+	tmp |= TC_COUNT8_PERBUF_PERBUF(data);
+	((Tc *)hw)->COUNT8.PERBUF.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_PERBUF_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_reg(const void *const         hw,
+                                                                    hri_tccount8_perbuf_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT8.PERBUF.reg;
+}
+
+static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tccount8_ccbuf_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk;
+	tmp |= TC_COUNT8_CCBUF_CCBUF(data);
+	((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index,
+                                                                  hri_tccount8_ccbuf_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+}
+
+static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                         hri_tccount16_ccbuf_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount16_ccbuf_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk;
+	tmp |= TC_COUNT16_CCBUF_CCBUF(data);
+	((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                       hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index,
+                                                                    hri_tccount16_ccbuf_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+}
+
+static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                         hri_tccount32_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount32_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk;
+	tmp |= TC_COUNT32_CCBUF_CCBUF(data);
+	((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                       hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index,
+                                                                    hri_tccount32_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+}
+
+static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_STOP;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_SLAVE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_PERBUFV;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT16.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT16.STATUS.reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_tc_set_PER_PER_bf(a, b) hri_tccount8_set_PER_PER_bf(a, b)
+#define hri_tc_get_PER_PER_bf(a, b) hri_tccount8_get_PER_PER_bf(a, b)
+#define hri_tc_write_PER_PER_bf(a, b) hri_tccount8_write_PER_PER_bf(a, b)
+#define hri_tc_clear_PER_PER_bf(a, b) hri_tccount8_clear_PER_PER_bf(a, b)
+#define hri_tc_toggle_PER_PER_bf(a, b) hri_tccount8_toggle_PER_PER_bf(a, b)
+#define hri_tc_read_PER_PER_bf(a) hri_tccount8_read_PER_PER_bf(a)
+#define hri_tc_set_PER_reg(a, b) hri_tccount8_set_PER_reg(a, b)
+#define hri_tc_get_PER_reg(a, b) hri_tccount8_get_PER_reg(a, b)
+#define hri_tc_write_PER_reg(a, b) hri_tccount8_write_PER_reg(a, b)
+#define hri_tc_clear_PER_reg(a, b) hri_tccount8_clear_PER_reg(a, b)
+#define hri_tc_toggle_PER_reg(a, b) hri_tccount8_toggle_PER_reg(a, b)
+#define hri_tc_read_PER_reg(a) hri_tccount8_read_PER_reg(a)
+#define hri_tc_set_PERBUF_PERBUF_bf(a, b) hri_tccount8_set_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_get_PERBUF_PERBUF_bf(a, b) hri_tccount8_get_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_write_PERBUF_PERBUF_bf(a, b) hri_tccount8_write_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_clear_PERBUF_PERBUF_bf(a, b) hri_tccount8_clear_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_toggle_PERBUF_PERBUF_bf(a, b) hri_tccount8_toggle_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_read_PERBUF_PERBUF_bf(a) hri_tccount8_read_PERBUF_PERBUF_bf(a)
+#define hri_tc_set_PERBUF_reg(a, b) hri_tccount8_set_PERBUF_reg(a, b)
+#define hri_tc_get_PERBUF_reg(a, b) hri_tccount8_get_PERBUF_reg(a, b)
+#define hri_tc_write_PERBUF_reg(a, b) hri_tccount8_write_PERBUF_reg(a, b)
+#define hri_tc_clear_PERBUF_reg(a, b) hri_tccount8_clear_PERBUF_reg(a, b)
+#define hri_tc_toggle_PERBUF_reg(a, b) hri_tccount8_toggle_PERBUF_reg(a, b)
+#define hri_tc_read_PERBUF_reg(a) hri_tccount8_read_PERBUF_reg(a)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_TC_E54_H_INCLUDED */
+#endif /* _SAME54_TC_COMPONENT_ */
diff --git a/hri/hri_tcc_e54.h b/hri/hri_tcc_e54.h
new file mode 100644
index 0000000..55f46bd
--- /dev/null
+++ b/hri/hri_tcc_e54.h
@@ -0,0 +1,9992 @@
+/**
+ * \file
+ *
+ * \brief SAM TCC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_TCC_COMPONENT_
+#ifndef _HRI_TCC_E54_H_INCLUDED_
+#define _HRI_TCC_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_TCC_CRITICAL_SECTIONS)
+#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define TCC_CRITICAL_SECTION_ENTER()
+#define TCC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_tcc_patt_reg_t;
+typedef uint16_t hri_tcc_pattbuf_reg_t;
+typedef uint32_t hri_tcc_cc_reg_t;
+typedef uint32_t hri_tcc_ccbuf_reg_t;
+typedef uint32_t hri_tcc_count_reg_t;
+typedef uint32_t hri_tcc_ctrla_reg_t;
+typedef uint32_t hri_tcc_drvctrl_reg_t;
+typedef uint32_t hri_tcc_evctrl_reg_t;
+typedef uint32_t hri_tcc_fctrla_reg_t;
+typedef uint32_t hri_tcc_fctrlb_reg_t;
+typedef uint32_t hri_tcc_intenset_reg_t;
+typedef uint32_t hri_tcc_intflag_reg_t;
+typedef uint32_t hri_tcc_per_reg_t;
+typedef uint32_t hri_tcc_perbuf_reg_t;
+typedef uint32_t hri_tcc_status_reg_t;
+typedef uint32_t hri_tcc_syncbusy_reg_t;
+typedef uint32_t hri_tcc_wave_reg_t;
+typedef uint32_t hri_tcc_wexctrl_reg_t;
+typedef uint8_t  hri_tcc_ctrlbset_reg_t;
+typedef uint8_t  hri_tcc_dbgctrl_reg_t;
+
+static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg)
+{
+	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg)
+{
+	return ((Tcc *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF;
+}
+
+static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG;
+}
+
+static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT;
+}
+
+static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR;
+}
+
+static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS;
+}
+
+static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC4_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC4_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC5_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC5_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5;
+}
+
+static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF;
+}
+
+static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG;
+}
+
+static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT;
+}
+
+static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR;
+}
+
+static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS;
+}
+
+static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1;
+}
+
+static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0;
+}
+
+static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1;
+}
+
+static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2;
+}
+
+static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3;
+}
+
+static inline bool hri_tcc_get_interrupt_MC4_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC4_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4;
+}
+
+static inline bool hri_tcc_get_interrupt_MC5_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC5_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5;
+}
+
+static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask)
+{
+	((Tcc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR;
+}
+
+static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos;
+}
+
+static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR;
+	} else {
+		((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR;
+	}
+}
+
+static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR;
+}
+
+static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD;
+}
+
+static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos;
+}
+
+static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD;
+	} else {
+		((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD;
+	}
+}
+
+static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD;
+}
+
+static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT;
+}
+
+static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos;
+}
+
+static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT;
+	} else {
+		((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT;
+	}
+}
+
+static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT;
+}
+
+static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask);
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos;
+	return tmp;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data);
+	((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data);
+}
+
+static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask);
+}
+
+static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask);
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data);
+	((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data);
+}
+
+static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask);
+}
+
+static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBSET.reg = mask;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->CTRLBSET.reg;
+}
+
+static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data)
+{
+	((Tcc *)hw)->CTRLBSET.reg = data;
+	((Tcc *)hw)->CTRLBCLR.reg = ~data;
+}
+
+static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = mask;
+}
+
+static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF;
+}
+
+static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF;
+}
+
+static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG;
+}
+
+static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG;
+}
+
+static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT;
+}
+
+static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT;
+}
+
+static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR;
+}
+
+static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR;
+}
+
+static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS;
+}
+
+static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS;
+}
+
+static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS;
+}
+
+static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS;
+}
+
+static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA;
+}
+
+static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB;
+}
+
+static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0;
+}
+
+static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1;
+}
+
+static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0;
+}
+
+static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0;
+}
+
+static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1;
+}
+
+static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1;
+}
+
+static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2;
+}
+
+static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2;
+}
+
+static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3;
+}
+
+static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3;
+}
+
+static inline void hri_tcc_set_INTEN_MC4_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4;
+}
+
+static inline bool hri_tcc_get_INTEN_MC4_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC4) >> TCC_INTENSET_MC4_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC4_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4;
+}
+
+static inline void hri_tcc_set_INTEN_MC5_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5;
+}
+
+static inline bool hri_tcc_get_INTEN_MC5_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC5) >> TCC_INTENSET_MC5_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC5_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5;
+}
+
+static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
+{
+	((Tcc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data)
+{
+	((Tcc *)hw)->INTENSET.reg = data;
+	((Tcc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
+{
+	((Tcc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC4_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC4) >> TCC_SYNCBUSY_CC4_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC5_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC5) >> TCC_SYNCBUSY_CC5_Pos;
+}
+
+static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_ENABLE;
+	tmp |= value << TCC_CTRLA_ENABLE_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_RUNSTDBY;
+	tmp |= value << TCC_CTRLA_RUNSTDBY_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_ALOCK;
+	tmp |= value << TCC_CTRLA_ALOCK_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_MSYNC;
+	tmp |= value << TCC_CTRLA_MSYNC_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_DMAOS;
+	tmp |= value << TCC_CTRLA_DMAOS_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN0;
+	tmp |= value << TCC_CTRLA_CPTEN0_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN1;
+	tmp |= value << TCC_CTRLA_CPTEN1_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN2;
+	tmp |= value << TCC_CTRLA_CPTEN2_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN3;
+	tmp |= value << TCC_CTRLA_CPTEN3_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN4) >> TCC_CTRLA_CPTEN4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN4;
+	tmp |= value << TCC_CTRLA_CPTEN4_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN5) >> TCC_CTRLA_CPTEN5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN5;
+	tmp |= value << TCC_CTRLA_CPTEN5_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_RESOLUTION_Msk;
+	tmp |= TCC_CTRLA_RESOLUTION(data);
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_PRESCALER_Msk;
+	tmp |= TCC_CTRLA_PRESCALER(data);
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_PRESCSYNC_Msk;
+	tmp |= TCC_CTRLA_PRESCSYNC(data);
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	return ((Tcc *)hw)->CTRLA.reg;
+}
+
+static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_KEEP;
+	tmp |= value << TCC_FCTRLA_KEEP_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_QUAL;
+	tmp |= value << TCC_FCTRLA_QUAL_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_RESTART;
+	tmp |= value << TCC_FCTRLA_RESTART_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_BLANKPRESC;
+	tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_SRC_Msk;
+	tmp |= TCC_FCTRLA_SRC(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_BLANK_Msk;
+	tmp |= TCC_FCTRLA_BLANK(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_HALT_Msk;
+	tmp |= TCC_FCTRLA_HALT(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_CHSEL_Msk;
+	tmp |= TCC_FCTRLA_CHSEL(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_CAPTURE_Msk;
+	tmp |= TCC_FCTRLA_CAPTURE(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_BLANKVAL_Msk;
+	tmp |= TCC_FCTRLA_BLANKVAL(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_FILTERVAL_Msk;
+	tmp |= TCC_FCTRLA_FILTERVAL(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->FCTRLA.reg;
+}
+
+static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_KEEP;
+	tmp |= value << TCC_FCTRLB_KEEP_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_QUAL;
+	tmp |= value << TCC_FCTRLB_QUAL_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_RESTART;
+	tmp |= value << TCC_FCTRLB_RESTART_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_BLANKPRESC;
+	tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_SRC_Msk;
+	tmp |= TCC_FCTRLB_SRC(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_BLANK_Msk;
+	tmp |= TCC_FCTRLB_BLANK(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_HALT_Msk;
+	tmp |= TCC_FCTRLB_HALT(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_CHSEL_Msk;
+	tmp |= TCC_FCTRLB_CHSEL(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_CAPTURE_Msk;
+	tmp |= TCC_FCTRLB_CAPTURE(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_BLANKVAL_Msk;
+	tmp |= TCC_FCTRLB_BLANKVAL(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_FILTERVAL_Msk;
+	tmp |= TCC_FCTRLB_FILTERVAL(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->FCTRLB.reg;
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN0;
+	tmp |= value << TCC_WEXCTRL_DTIEN0_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN1;
+	tmp |= value << TCC_WEXCTRL_DTIEN1_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN2;
+	tmp |= value << TCC_WEXCTRL_DTIEN2_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN3;
+	tmp |= value << TCC_WEXCTRL_DTIEN3_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_OTMX_Msk;
+	tmp |= TCC_WEXCTRL_OTMX(data);
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTLS_Msk;
+	tmp |= TCC_WEXCTRL_DTLS(data);
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTHS_Msk;
+	tmp |= TCC_WEXCTRL_DTHS(data);
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->WEXCTRL.reg;
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE0;
+	tmp |= value << TCC_DRVCTRL_NRE0_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE1;
+	tmp |= value << TCC_DRVCTRL_NRE1_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE2;
+	tmp |= value << TCC_DRVCTRL_NRE2_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE3;
+	tmp |= value << TCC_DRVCTRL_NRE3_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE4;
+	tmp |= value << TCC_DRVCTRL_NRE4_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE5;
+	tmp |= value << TCC_DRVCTRL_NRE5_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE6;
+	tmp |= value << TCC_DRVCTRL_NRE6_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE7;
+	tmp |= value << TCC_DRVCTRL_NRE7_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV0;
+	tmp |= value << TCC_DRVCTRL_NRV0_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV1;
+	tmp |= value << TCC_DRVCTRL_NRV1_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV2;
+	tmp |= value << TCC_DRVCTRL_NRV2_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV3;
+	tmp |= value << TCC_DRVCTRL_NRV3_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV4;
+	tmp |= value << TCC_DRVCTRL_NRV4_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV5;
+	tmp |= value << TCC_DRVCTRL_NRV5_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV6;
+	tmp |= value << TCC_DRVCTRL_NRV6_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV7;
+	tmp |= value << TCC_DRVCTRL_NRV7_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN0;
+	tmp |= value << TCC_DRVCTRL_INVEN0_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN1;
+	tmp |= value << TCC_DRVCTRL_INVEN1_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN2;
+	tmp |= value << TCC_DRVCTRL_INVEN2_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN3;
+	tmp |= value << TCC_DRVCTRL_INVEN3_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN4;
+	tmp |= value << TCC_DRVCTRL_INVEN4_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN5;
+	tmp |= value << TCC_DRVCTRL_INVEN5_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN6;
+	tmp |= value << TCC_DRVCTRL_INVEN6_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN7;
+	tmp |= value << TCC_DRVCTRL_INVEN7_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk;
+	tmp |= TCC_DRVCTRL_FILTERVAL0(data);
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk;
+	tmp |= TCC_DRVCTRL_FILTERVAL1(data);
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->DRVCTRL.reg;
+}
+
+static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp &= ~TCC_DBGCTRL_DBGRUN;
+	tmp |= value << TCC_DBGCTRL_DBGRUN_Pos;
+	((Tcc *)hw)->DBGCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp &= ~TCC_DBGCTRL_FDDBD;
+	tmp |= value << TCC_DBGCTRL_FDDBD_Pos;
+	((Tcc *)hw)->DBGCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_OVFEO;
+	tmp |= value << TCC_EVCTRL_OVFEO_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TRGEO;
+	tmp |= value << TCC_EVCTRL_TRGEO_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_CNTEO;
+	tmp |= value << TCC_EVCTRL_CNTEO_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCINV0;
+	tmp |= value << TCC_EVCTRL_TCINV0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCINV1;
+	tmp |= value << TCC_EVCTRL_TCINV1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCEI0;
+	tmp |= value << TCC_EVCTRL_TCEI0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCEI1;
+	tmp |= value << TCC_EVCTRL_TCEI1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI0;
+	tmp |= value << TCC_EVCTRL_MCEI0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI1;
+	tmp |= value << TCC_EVCTRL_MCEI1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI2;
+	tmp |= value << TCC_EVCTRL_MCEI2_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI3;
+	tmp |= value << TCC_EVCTRL_MCEI3_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI4) >> TCC_EVCTRL_MCEI4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI4;
+	tmp |= value << TCC_EVCTRL_MCEI4_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI5) >> TCC_EVCTRL_MCEI5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI5;
+	tmp |= value << TCC_EVCTRL_MCEI5_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO0;
+	tmp |= value << TCC_EVCTRL_MCEO0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO1;
+	tmp |= value << TCC_EVCTRL_MCEO1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO2;
+	tmp |= value << TCC_EVCTRL_MCEO2_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO3;
+	tmp |= value << TCC_EVCTRL_MCEO3_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO4) >> TCC_EVCTRL_MCEO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO4;
+	tmp |= value << TCC_EVCTRL_MCEO4_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO5) >> TCC_EVCTRL_MCEO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO5;
+	tmp |= value << TCC_EVCTRL_MCEO5_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_EVACT0_Msk;
+	tmp |= TCC_EVCTRL_EVACT0(data);
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_EVACT1_Msk;
+	tmp |= TCC_EVCTRL_EVACT1(data);
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_CNTSEL_Msk;
+	tmp |= TCC_EVCTRL_CNTSEL(data);
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	return ((Tcc *)hw)->COUNT.reg;
+}
+
+static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE0;
+	tmp |= value << TCC_PATT_PGE0_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE1;
+	tmp |= value << TCC_PATT_PGE1_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE2;
+	tmp |= value << TCC_PATT_PGE2_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE3;
+	tmp |= value << TCC_PATT_PGE3_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE4;
+	tmp |= value << TCC_PATT_PGE4_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE5;
+	tmp |= value << TCC_PATT_PGE5_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE6;
+	tmp |= value << TCC_PATT_PGE6_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE7;
+	tmp |= value << TCC_PATT_PGE7_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV0;
+	tmp |= value << TCC_PATT_PGV0_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV1;
+	tmp |= value << TCC_PATT_PGV1_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV2;
+	tmp |= value << TCC_PATT_PGV2_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV3;
+	tmp |= value << TCC_PATT_PGV3_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV4;
+	tmp |= value << TCC_PATT_PGV4_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV5;
+	tmp |= value << TCC_PATT_PGV5_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV6;
+	tmp |= value << TCC_PATT_PGV6_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV7;
+	tmp |= value << TCC_PATT_PGV7_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	return ((Tcc *)hw)->PATT.reg;
+}
+
+static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CIPEREN;
+	tmp |= value << TCC_WAVE_CIPEREN_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN0;
+	tmp |= value << TCC_WAVE_CICCEN0_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN1;
+	tmp |= value << TCC_WAVE_CICCEN1_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN2;
+	tmp |= value << TCC_WAVE_CICCEN2_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN3;
+	tmp |= value << TCC_WAVE_CICCEN3_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL0;
+	tmp |= value << TCC_WAVE_POL0_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL1;
+	tmp |= value << TCC_WAVE_POL1_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL2;
+	tmp |= value << TCC_WAVE_POL2_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL3;
+	tmp |= value << TCC_WAVE_POL3_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL4) >> TCC_WAVE_POL4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL4;
+	tmp |= value << TCC_WAVE_POL4_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL5) >> TCC_WAVE_POL5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL5;
+	tmp |= value << TCC_WAVE_POL5_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP0;
+	tmp |= value << TCC_WAVE_SWAP0_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP1;
+	tmp |= value << TCC_WAVE_SWAP1_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP2;
+	tmp |= value << TCC_WAVE_SWAP2_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP3;
+	tmp |= value << TCC_WAVE_SWAP3_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_WAVEGEN_Msk;
+	tmp |= TCC_WAVE_WAVEGEN(data);
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_RAMP_Msk;
+	tmp |= TCC_WAVE_RAMP(data);
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	return ((Tcc *)hw)->WAVE.reg;
+}
+
+static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH4_DITHER_Msk;
+	tmp |= TCC_PER_DITH4_DITHER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH5_DITHER_Msk;
+	tmp |= TCC_PER_DITH5_DITHER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH6_DITHER_Msk;
+	tmp |= TCC_PER_DITH6_DITHER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	return ((Tcc *)hw)->PER.reg;
+}
+
+static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index,
+                                                              hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH4_DITHER_Msk;
+	tmp |= TCC_CC_DITH4_DITHER(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index,
+                                                              hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH5_DITHER_Msk;
+	tmp |= TCC_CC_DITH5_DITHER(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index,
+                                                              hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH6_DITHER_Msk;
+	tmp |= TCC_CC_DITH6_DITHER(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= mask;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg = data;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~mask;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= mask;
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tcc_wait_for_sync(hw,
+	                      TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4
+	                          | TCC_SYNCBUSY_CC5);
+	return ((Tcc *)hw)->CC[index].reg;
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB0;
+	tmp |= value << TCC_PATTBUF_PGEB0_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB1;
+	tmp |= value << TCC_PATTBUF_PGEB1_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB2;
+	tmp |= value << TCC_PATTBUF_PGEB2_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB3;
+	tmp |= value << TCC_PATTBUF_PGEB3_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB4;
+	tmp |= value << TCC_PATTBUF_PGEB4_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB5;
+	tmp |= value << TCC_PATTBUF_PGEB5_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB6;
+	tmp |= value << TCC_PATTBUF_PGEB6_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB7;
+	tmp |= value << TCC_PATTBUF_PGEB7_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB0;
+	tmp |= value << TCC_PATTBUF_PGVB0_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB1;
+	tmp |= value << TCC_PATTBUF_PGVB1_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB2;
+	tmp |= value << TCC_PATTBUF_PGVB2_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB3;
+	tmp |= value << TCC_PATTBUF_PGVB3_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB4;
+	tmp |= value << TCC_PATTBUF_PGVB4_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB5;
+	tmp |= value << TCC_PATTBUF_PGVB5_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB6;
+	tmp |= value << TCC_PATTBUF_PGVB6_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB7;
+	tmp |= value << TCC_PATTBUF_PGVB7_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PATTBUF.reg;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const    hw,
+                                                                         hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk;
+	tmp |= TCC_PERBUF_DITH4_DITHERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const    hw,
+                                                                         hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk;
+	tmp |= TCC_PERBUF_DITH5_DITHERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const    hw,
+                                                                         hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk;
+	tmp |= TCC_PERBUF_DITH6_DITHERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PERBUF.reg;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                   hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk;
+	tmp |= TCC_CCBUF_DITH5_DITHERBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                           hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk;
+	tmp |= TCC_CCBUF_DITH6_DITHERBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                           hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                   hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                   hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk;
+	tmp |= TCC_CCBUF_DITH4_DITHERBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                           hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                             hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	return ((Tcc *)hw)->CCBUF[index].reg;
+}
+
+static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV4_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV4) >> TCC_STATUS_CCBUFV4_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV5_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV5) >> TCC_STATUS_CCBUFV5_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP4_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP4) >> TCC_STATUS_CMP4_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP5_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP5) >> TCC_STATUS_CMP5_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	return ((Tcc *)hw)->STATUS.reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_tcc_set_COUNT_DITH4_reg(a, b) hri_tcc_set_COUNT_reg(a, b)
+#define hri_tcc_get_COUNT_DITH4_reg(a, b) hri_tcc_get_COUNT_reg(a, b)
+#define hri_tcc_write_COUNT_DITH4_reg(a, b) hri_tcc_write_COUNT_reg(a, b)
+#define hri_tcc_clear_COUNT_DITH4_reg(a, b) hri_tcc_clear_COUNT_reg(a, b)
+#define hri_tcc_toggle_COUNT_DITH4_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b)
+#define hri_tcc_read_COUNT_DITH4_reg(a) hri_tcc_read_COUNT_reg(a)
+#define hri_tcc_set_COUNT_DITH5_reg(a, b) hri_tcc_set_COUNT_reg(a, b)
+#define hri_tcc_get_COUNT_DITH5_reg(a, b) hri_tcc_get_COUNT_reg(a, b)
+#define hri_tcc_write_COUNT_DITH5_reg(a, b) hri_tcc_write_COUNT_reg(a, b)
+#define hri_tcc_clear_COUNT_DITH5_reg(a, b) hri_tcc_clear_COUNT_reg(a, b)
+#define hri_tcc_toggle_COUNT_DITH5_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b)
+#define hri_tcc_read_COUNT_DITH5_reg(a) hri_tcc_read_COUNT_reg(a)
+#define hri_tcc_set_COUNT_DITH6_reg(a, b) hri_tcc_set_COUNT_reg(a, b)
+#define hri_tcc_get_COUNT_DITH6_reg(a, b) hri_tcc_get_COUNT_reg(a, b)
+#define hri_tcc_write_COUNT_DITH6_reg(a, b) hri_tcc_write_COUNT_reg(a, b)
+#define hri_tcc_clear_COUNT_DITH6_reg(a, b) hri_tcc_clear_COUNT_reg(a, b)
+#define hri_tcc_toggle_COUNT_DITH6_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b)
+#define hri_tcc_read_COUNT_DITH6_reg(a) hri_tcc_read_COUNT_reg(a)
+#define hri_tcc_set_PER_DITH4_reg(a, b) hri_tcc_set_PER_reg(a, b)
+#define hri_tcc_get_PER_DITH4_reg(a, b) hri_tcc_get_PER_reg(a, b)
+#define hri_tcc_write_PER_DITH4_reg(a, b) hri_tcc_write_PER_reg(a, b)
+#define hri_tcc_clear_PER_DITH4_reg(a, b) hri_tcc_clear_PER_reg(a, b)
+#define hri_tcc_toggle_PER_DITH4_reg(a, b) hri_tcc_toggle_PER_reg(a, b)
+#define hri_tcc_read_PER_DITH4_reg(a) hri_tcc_read_PER_reg(a)
+#define hri_tcc_set_PER_DITH5_reg(a, b) hri_tcc_set_PER_reg(a, b)
+#define hri_tcc_get_PER_DITH5_reg(a, b) hri_tcc_get_PER_reg(a, b)
+#define hri_tcc_write_PER_DITH5_reg(a, b) hri_tcc_write_PER_reg(a, b)
+#define hri_tcc_clear_PER_DITH5_reg(a, b) hri_tcc_clear_PER_reg(a, b)
+#define hri_tcc_toggle_PER_DITH5_reg(a, b) hri_tcc_toggle_PER_reg(a, b)
+#define hri_tcc_read_PER_DITH5_reg(a) hri_tcc_read_PER_reg(a)
+#define hri_tcc_set_PER_DITH6_reg(a, b) hri_tcc_set_PER_reg(a, b)
+#define hri_tcc_get_PER_DITH6_reg(a, b) hri_tcc_get_PER_reg(a, b)
+#define hri_tcc_write_PER_DITH6_reg(a, b) hri_tcc_write_PER_reg(a, b)
+#define hri_tcc_clear_PER_DITH6_reg(a, b) hri_tcc_clear_PER_reg(a, b)
+#define hri_tcc_toggle_PER_DITH6_reg(a, b) hri_tcc_toggle_PER_reg(a, b)
+#define hri_tcc_read_PER_DITH6_reg(a) hri_tcc_read_PER_reg(a)
+#define hri_tcc_set_CC_DITH4_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c)
+#define hri_tcc_get_CC_DITH4_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c)
+#define hri_tcc_write_CC_DITH4_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c)
+#define hri_tcc_clear_CC_DITH4_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c)
+#define hri_tcc_toggle_CC_DITH4_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c)
+#define hri_tcc_read_CC_DITH4_reg(a, b) hri_tcc_read_CC_reg(a, b)
+#define hri_tcc_set_CC_DITH5_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c)
+#define hri_tcc_get_CC_DITH5_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c)
+#define hri_tcc_write_CC_DITH5_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c)
+#define hri_tcc_clear_CC_DITH5_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c)
+#define hri_tcc_toggle_CC_DITH5_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c)
+#define hri_tcc_read_CC_DITH5_reg(a, b) hri_tcc_read_CC_reg(a, b)
+#define hri_tcc_set_CC_DITH6_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c)
+#define hri_tcc_get_CC_DITH6_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c)
+#define hri_tcc_write_CC_DITH6_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c)
+#define hri_tcc_clear_CC_DITH6_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c)
+#define hri_tcc_toggle_CC_DITH6_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c)
+#define hri_tcc_read_CC_DITH6_reg(a, b) hri_tcc_read_CC_reg(a, b)
+#define hri_tcc_set_PERBUF_DITH4_reg(a, b) hri_tcc_set_PERBUF_reg(a, b)
+#define hri_tcc_get_PERBUF_DITH4_reg(a, b) hri_tcc_get_PERBUF_reg(a, b)
+#define hri_tcc_write_PERBUF_DITH4_reg(a, b) hri_tcc_write_PERBUF_reg(a, b)
+#define hri_tcc_clear_PERBUF_DITH4_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b)
+#define hri_tcc_toggle_PERBUF_DITH4_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b)
+#define hri_tcc_read_PERBUF_DITH4_reg(a) hri_tcc_read_PERBUF_reg(a)
+#define hri_tcc_set_PERBUF_DITH5_reg(a, b) hri_tcc_set_PERBUF_reg(a, b)
+#define hri_tcc_get_PERBUF_DITH5_reg(a, b) hri_tcc_get_PERBUF_reg(a, b)
+#define hri_tcc_write_PERBUF_DITH5_reg(a, b) hri_tcc_write_PERBUF_reg(a, b)
+#define hri_tcc_clear_PERBUF_DITH5_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b)
+#define hri_tcc_toggle_PERBUF_DITH5_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b)
+#define hri_tcc_read_PERBUF_DITH5_reg(a) hri_tcc_read_PERBUF_reg(a)
+#define hri_tcc_set_PERBUF_DITH6_reg(a, b) hri_tcc_set_PERBUF_reg(a, b)
+#define hri_tcc_get_PERBUF_DITH6_reg(a, b) hri_tcc_get_PERBUF_reg(a, b)
+#define hri_tcc_write_PERBUF_DITH6_reg(a, b) hri_tcc_write_PERBUF_reg(a, b)
+#define hri_tcc_clear_PERBUF_DITH6_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b)
+#define hri_tcc_toggle_PERBUF_DITH6_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b)
+#define hri_tcc_read_PERBUF_DITH6_reg(a) hri_tcc_read_PERBUF_reg(a)
+#define hri_tcc_set_CCBUF_DITH4_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c)
+#define hri_tcc_get_CCBUF_DITH4_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c)
+#define hri_tcc_write_CCBUF_DITH4_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c)
+#define hri_tcc_clear_CCBUF_DITH4_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c)
+#define hri_tcc_toggle_CCBUF_DITH4_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c)
+#define hri_tcc_read_CCBUF_DITH4_reg(a, b) hri_tcc_read_CCBUF_reg(a, b)
+#define hri_tcc_set_CCBUF_DITH5_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c)
+#define hri_tcc_get_CCBUF_DITH5_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c)
+#define hri_tcc_write_CCBUF_DITH5_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c)
+#define hri_tcc_clear_CCBUF_DITH5_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c)
+#define hri_tcc_toggle_CCBUF_DITH5_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c)
+#define hri_tcc_read_CCBUF_DITH5_reg(a, b) hri_tcc_read_CCBUF_reg(a, b)
+#define hri_tcc_set_CCBUF_DITH6_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c)
+#define hri_tcc_get_CCBUF_DITH6_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c)
+#define hri_tcc_write_CCBUF_DITH6_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c)
+#define hri_tcc_clear_CCBUF_DITH6_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c)
+#define hri_tcc_toggle_CCBUF_DITH6_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c)
+#define hri_tcc_read_CCBUF_DITH6_reg(a, b) hri_tcc_read_CCBUF_reg(a, b)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_TCC_E54_H_INCLUDED */
+#endif /* _SAME54_TCC_COMPONENT_ */
diff --git a/hri/hri_trng_e54.h b/hri/hri_trng_e54.h
new file mode 100644
index 0000000..e42caab
--- /dev/null
+++ b/hri/hri_trng_e54.h
@@ -0,0 +1,380 @@
+/**
+ * \file
+ *
+ * \brief SAM TRNG
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_TRNG_COMPONENT_
+#ifndef _HRI_TRNG_E54_H_INCLUDED_
+#define _HRI_TRNG_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_TRNG_CRITICAL_SECTIONS)
+#define TRNG_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define TRNG_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define TRNG_CRITICAL_SECTION_ENTER()
+#define TRNG_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_trng_data_reg_t;
+typedef uint8_t  hri_trng_ctrla_reg_t;
+typedef uint8_t  hri_trng_evctrl_reg_t;
+typedef uint8_t  hri_trng_intenset_reg_t;
+typedef uint8_t  hri_trng_intflag_reg_t;
+
+static inline bool hri_trng_get_INTFLAG_DATARDY_bit(const void *const hw)
+{
+	return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos;
+}
+
+static inline void hri_trng_clear_INTFLAG_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY;
+}
+
+static inline bool hri_trng_get_interrupt_DATARDY_bit(const void *const hw)
+{
+	return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos;
+}
+
+static inline void hri_trng_clear_interrupt_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY;
+}
+
+static inline hri_trng_intflag_reg_t hri_trng_get_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_trng_intflag_reg_t hri_trng_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Trng *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_trng_clear_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask)
+{
+	((Trng *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_trng_set_INTEN_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY;
+}
+
+static inline bool hri_trng_get_INTEN_DATARDY_bit(const void *const hw)
+{
+	return (((Trng *)hw)->INTENSET.reg & TRNG_INTENSET_DATARDY) >> TRNG_INTENSET_DATARDY_Pos;
+}
+
+static inline void hri_trng_write_INTEN_DATARDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY;
+	} else {
+		((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY;
+	}
+}
+
+static inline void hri_trng_clear_INTEN_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY;
+}
+
+static inline void hri_trng_set_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask)
+{
+	((Trng *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_trng_intenset_reg_t hri_trng_get_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_trng_intenset_reg_t hri_trng_read_INTEN_reg(const void *const hw)
+{
+	return ((Trng *)hw)->INTENSET.reg;
+}
+
+static inline void hri_trng_write_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t data)
+{
+	((Trng *)hw)->INTENSET.reg = data;
+	((Trng *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_trng_clear_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask)
+{
+	((Trng *)hw)->INTENCLR.reg = mask;
+}
+
+static inline hri_trng_data_reg_t hri_trng_get_DATA_DATA_bf(const void *const hw, hri_trng_data_reg_t mask)
+{
+	return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA(mask)) >> TRNG_DATA_DATA_Pos;
+}
+
+static inline hri_trng_data_reg_t hri_trng_read_DATA_DATA_bf(const void *const hw)
+{
+	return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA_Msk) >> TRNG_DATA_DATA_Pos;
+}
+
+static inline hri_trng_data_reg_t hri_trng_get_DATA_reg(const void *const hw, hri_trng_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Trng *)hw)->DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_trng_data_reg_t hri_trng_read_DATA_reg(const void *const hw)
+{
+	return ((Trng *)hw)->DATA.reg;
+}
+
+static inline void hri_trng_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_ENABLE;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_trng_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp = (tmp & TRNG_CTRLA_ENABLE) >> TRNG_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_trng_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TRNG_CRITICAL_SECTION_ENTER();
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp &= ~TRNG_CTRLA_ENABLE;
+	tmp |= value << TRNG_CTRLA_ENABLE_Pos;
+	((Trng *)hw)->CTRLA.reg = tmp;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_ENABLE;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_ENABLE;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_RUNSTDBY;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_trng_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp = (tmp & TRNG_CTRLA_RUNSTDBY) >> TRNG_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_trng_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TRNG_CRITICAL_SECTION_ENTER();
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp &= ~TRNG_CTRLA_RUNSTDBY;
+	tmp |= value << TRNG_CTRLA_RUNSTDBY_Pos;
+	((Trng *)hw)->CTRLA.reg = tmp;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_RUNSTDBY;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_RUNSTDBY;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_set_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg |= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_ctrla_reg_t hri_trng_get_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_trng_write_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t data)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg = data;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg &= ~mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg ^= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_ctrla_reg_t hri_trng_read_CTRLA_reg(const void *const hw)
+{
+	return ((Trng *)hw)->CTRLA.reg;
+}
+
+static inline void hri_trng_set_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_trng_get_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->EVCTRL.reg;
+	tmp = (tmp & TRNG_EVCTRL_DATARDYEO) >> TRNG_EVCTRL_DATARDYEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_trng_write_EVCTRL_DATARDYEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TRNG_CRITICAL_SECTION_ENTER();
+	tmp = ((Trng *)hw)->EVCTRL.reg;
+	tmp &= ~TRNG_EVCTRL_DATARDYEO;
+	tmp |= value << TRNG_EVCTRL_DATARDYEO_Pos;
+	((Trng *)hw)->EVCTRL.reg = tmp;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg ^= TRNG_EVCTRL_DATARDYEO;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_set_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg |= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_evctrl_reg_t hri_trng_get_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_trng_write_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t data)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg = data;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg &= ~mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg ^= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_evctrl_reg_t hri_trng_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Trng *)hw)->EVCTRL.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_TRNG_E54_H_INCLUDED */
+#endif /* _SAME54_TRNG_COMPONENT_ */
diff --git a/hri/hri_usb_e54.h b/hri/hri_usb_e54.h
new file mode 100644
index 0000000..34b5e02
--- /dev/null
+++ b/hri/hri_usb_e54.h
@@ -0,0 +1,9335 @@
+/**
+ * \file
+ *
+ * \brief SAM USB
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_USB_COMPONENT_
+#ifndef _HRI_USB_E54_H_INCLUDED_
+#define _HRI_USB_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_USB_CRITICAL_SECTIONS)
+#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define USB_CRITICAL_SECTION_ENTER()
+#define USB_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_usb_padcal_reg_t;
+typedef uint16_t hri_usbdesc_bank_ctrl_pipe_reg_t;
+typedef uint16_t hri_usbdesc_bank_extreg_reg_t;
+typedef uint16_t hri_usbdesc_bank_status_pipe_reg_t;
+typedef uint16_t hri_usbdescriptordevice_extreg_reg_t;
+typedef uint16_t hri_usbdescriptorhost_ctrl_pipe_reg_t;
+typedef uint16_t hri_usbdescriptorhost_extreg_reg_t;
+typedef uint16_t hri_usbdescriptorhost_status_pipe_reg_t;
+typedef uint16_t hri_usbdevice_ctrlb_reg_t;
+typedef uint16_t hri_usbdevice_epintsmry_reg_t;
+typedef uint16_t hri_usbdevice_fnum_reg_t;
+typedef uint16_t hri_usbdevice_intenset_reg_t;
+typedef uint16_t hri_usbdevice_intflag_reg_t;
+typedef uint16_t hri_usbhost_ctrlb_reg_t;
+typedef uint16_t hri_usbhost_fnum_reg_t;
+typedef uint16_t hri_usbhost_intenset_reg_t;
+typedef uint16_t hri_usbhost_intflag_reg_t;
+typedef uint16_t hri_usbhost_pintsmry_reg_t;
+typedef uint32_t hri_usb_descadd_reg_t;
+typedef uint32_t hri_usbdesc_bank_addr_reg_t;
+typedef uint32_t hri_usbdesc_bank_pcksize_reg_t;
+typedef uint32_t hri_usbdescriptordevice_addr_reg_t;
+typedef uint32_t hri_usbdescriptordevice_pcksize_reg_t;
+typedef uint32_t hri_usbdescriptorhost_addr_reg_t;
+typedef uint32_t hri_usbdescriptorhost_pcksize_reg_t;
+typedef uint8_t  hri_usb_ctrla_reg_t;
+typedef uint8_t  hri_usb_fsmstatus_reg_t;
+typedef uint8_t  hri_usb_qosctrl_reg_t;
+typedef uint8_t  hri_usb_syncbusy_reg_t;
+typedef uint8_t  hri_usbdesc_bank_status_bk_reg_t;
+typedef uint8_t  hri_usbdescriptordevice_status_bk_reg_t;
+typedef uint8_t  hri_usbdescriptorhost_status_bk_reg_t;
+typedef uint8_t  hri_usbdevice_dadd_reg_t;
+typedef uint8_t  hri_usbdevice_epcfg_reg_t;
+typedef uint8_t  hri_usbdevice_epintenset_reg_t;
+typedef uint8_t  hri_usbdevice_epintflag_reg_t;
+typedef uint8_t  hri_usbdevice_epstatus_reg_t;
+typedef uint8_t  hri_usbdevice_status_reg_t;
+typedef uint8_t  hri_usbendpoint_epcfg_reg_t;
+typedef uint8_t  hri_usbendpoint_epintenset_reg_t;
+typedef uint8_t  hri_usbendpoint_epintflag_reg_t;
+typedef uint8_t  hri_usbendpoint_epstatus_reg_t;
+typedef uint8_t  hri_usbhost_binterval_reg_t;
+typedef uint8_t  hri_usbhost_flenhigh_reg_t;
+typedef uint8_t  hri_usbhost_hsofc_reg_t;
+typedef uint8_t  hri_usbhost_pcfg_reg_t;
+typedef uint8_t  hri_usbhost_pintenset_reg_t;
+typedef uint8_t  hri_usbhost_pintflag_reg_t;
+typedef uint8_t  hri_usbhost_pstatus_reg_t;
+typedef uint8_t  hri_usbhost_status_reg_t;
+typedef uint8_t  hri_usbpipe_binterval_reg_t;
+typedef uint8_t  hri_usbpipe_pcfg_reg_t;
+typedef uint8_t  hri_usbpipe_pintenset_reg_t;
+typedef uint8_t  hri_usbpipe_pintflag_reg_t;
+typedef uint8_t  hri_usbpipe_pstatus_reg_t;
+
+static inline void hri_usb_wait_for_sync(const void *const hw, hri_usb_syncbusy_reg_t reg)
+{
+	while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_usb_is_syncing(const void *const hw, hri_usb_syncbusy_reg_t reg)
+{
+	return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0)
+	       >> USB_HOST_PINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1)
+	       >> USB_HOST_PINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL)
+	       >> USB_HOST_PINTFLAG_TRFAIL_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR)
+	       >> USB_HOST_PINTFLAG_PERR_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP)
+	       >> USB_HOST_PINTFLAG_TXSTP_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP;
+}
+
+static inline bool hri_usbpipe_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL)
+	       >> USB_HOST_PINTFLAG_STALL_Pos;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL;
+}
+
+static inline bool hri_usbpipe_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0)
+	       >> USB_HOST_PINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbpipe_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1)
+	       >> USB_HOST_PINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbpipe_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL)
+	       >> USB_HOST_PINTFLAG_TRFAIL_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL;
+}
+
+static inline bool hri_usbpipe_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR)
+	       >> USB_HOST_PINTFLAG_PERR_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR;
+}
+
+static inline bool hri_usbpipe_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP)
+	       >> USB_HOST_PINTFLAG_TXSTP_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP;
+}
+
+static inline bool hri_usbpipe_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL)
+	       >> USB_HOST_PINTFLAG_STALL_Pos;
+}
+
+static inline void hri_usbpipe_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL;
+}
+
+static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                                      hri_usbpipe_pintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg;
+}
+
+static inline void hri_usbpipe_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbpipe_pintflag_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = mask;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL)
+	       >> USB_HOST_PSTATUS_DTGL_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK)
+	       >> USB_HOST_PSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE)
+	       >> USB_HOST_PSTATUS_PFREEZE_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY)
+	       >> USB_HOST_PSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbpipe_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY)
+	       >> USB_HOST_PSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY;
+}
+
+static inline void hri_usbpipe_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbpipe_pstatus_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = mask;
+}
+
+static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbpipe_pstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg;
+}
+
+static inline void hri_usbpipe_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbpipe_pstatus_reg_t data)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = data;
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbpipe_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbpipe_pstatus_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbpipe_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0)
+	       >> USB_HOST_PINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0;
+}
+
+static inline void hri_usbpipe_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1)
+	       >> USB_HOST_PINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1;
+}
+
+static inline void hri_usbpipe_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL)
+	       >> USB_HOST_PINTENSET_TRFAIL_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL;
+}
+
+static inline void hri_usbpipe_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR)
+	       >> USB_HOST_PINTENSET_PERR_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR;
+}
+
+static inline void hri_usbpipe_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP)
+	       >> USB_HOST_PINTENSET_TXSTP_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP;
+}
+
+static inline void hri_usbpipe_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+}
+
+static inline bool hri_usbpipe_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL)
+	       >> USB_HOST_PINTENSET_STALL_Pos;
+}
+
+static inline void hri_usbpipe_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL;
+	} else {
+		((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+	}
+}
+
+static inline void hri_usbpipe_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL;
+}
+
+static inline void hri_usbpipe_set_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbpipe_pintenset_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = mask;
+}
+
+static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_get_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbpipe_pintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_read_PINTEN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg;
+}
+
+static inline void hri_usbpipe_write_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_usbpipe_pintenset_reg_t data)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = data;
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbpipe_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_usbpipe_pintenset_reg_t mask)
+{
+	((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = mask;
+}
+
+static inline void hri_usbpipe_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbpipe_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbpipe_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_BK;
+	tmp |= value << USB_HOST_PCFG_BK_Pos;
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbpipe_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbpipe_pcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_PTOKEN_Msk;
+	tmp |= USB_HOST_PCFG_PTOKEN(data);
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbpipe_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbpipe_pcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_PTYPE_Msk;
+	tmp |= USB_HOST_PCFG_PTYPE(data);
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbpipe_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbpipe_pcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbpipe_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg;
+}
+
+static inline void hri_usbpipe_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_BITINTERVAL_bf(const void *const hw,
+                                                                                   uint8_t           submodule_index,
+                                                                                   hri_usbpipe_binterval_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+	tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbpipe_binterval_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+	tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk;
+	tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data);
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_BITINTERVAL_bf(const void *const hw,
+                                                                                    uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+	tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_usbpipe_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbpipe_binterval_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbpipe_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbpipe_binterval_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbpipe_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbpipe_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0)
+	       >> USB_HOST_PINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1)
+	       >> USB_HOST_PINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL)
+	       >> USB_HOST_PINTFLAG_TRFAIL_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR)
+	       >> USB_HOST_PINTFLAG_PERR_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP)
+	       >> USB_HOST_PINTFLAG_TXSTP_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP;
+}
+
+static inline bool hri_usbhost_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL)
+	       >> USB_HOST_PINTFLAG_STALL_Pos;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL;
+}
+
+static inline bool hri_usbhost_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0)
+	       >> USB_HOST_PINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbhost_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1)
+	       >> USB_HOST_PINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbhost_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL)
+	       >> USB_HOST_PINTFLAG_TRFAIL_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL;
+}
+
+static inline bool hri_usbhost_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR)
+	       >> USB_HOST_PINTFLAG_PERR_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR;
+}
+
+static inline bool hri_usbhost_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP)
+	       >> USB_HOST_PINTFLAG_TXSTP_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP;
+}
+
+static inline bool hri_usbhost_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL)
+	       >> USB_HOST_PINTFLAG_STALL_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL;
+}
+
+static inline hri_usbhost_pintflag_reg_t hri_usbhost_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                                      hri_usbhost_pintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_pintflag_reg_t hri_usbhost_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg;
+}
+
+static inline void hri_usbhost_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbhost_pintflag_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = mask;
+}
+
+static inline void hri_usbhost_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL)
+	       >> USB_HOST_PSTATUS_DTGL_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL;
+}
+
+static inline void hri_usbhost_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK)
+	       >> USB_HOST_PSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK;
+}
+
+static inline void hri_usbhost_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE)
+	       >> USB_HOST_PSTATUS_PFREEZE_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE;
+}
+
+static inline void hri_usbhost_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY)
+	       >> USB_HOST_PSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY;
+}
+
+static inline void hri_usbhost_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbhost_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY)
+	       >> USB_HOST_PSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbhost_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbhost_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY;
+}
+
+static inline void hri_usbhost_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbhost_pstatus_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = mask;
+}
+
+static inline hri_usbhost_pstatus_reg_t hri_usbhost_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbhost_pstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_pstatus_reg_t hri_usbhost_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg;
+}
+
+static inline void hri_usbhost_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbhost_pstatus_reg_t data)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = data;
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbhost_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbhost_pstatus_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbhost_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbhost_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0)
+	       >> USB_HOST_PINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0;
+}
+
+static inline void hri_usbhost_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbhost_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1)
+	       >> USB_HOST_PINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1;
+}
+
+static inline void hri_usbhost_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL;
+}
+
+static inline bool hri_usbhost_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL)
+	       >> USB_HOST_PINTENSET_TRFAIL_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL;
+}
+
+static inline void hri_usbhost_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR;
+}
+
+static inline bool hri_usbhost_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR)
+	       >> USB_HOST_PINTENSET_PERR_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR;
+}
+
+static inline void hri_usbhost_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+}
+
+static inline bool hri_usbhost_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP)
+	       >> USB_HOST_PINTENSET_TXSTP_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP;
+}
+
+static inline void hri_usbhost_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+}
+
+static inline bool hri_usbhost_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL)
+	       >> USB_HOST_PINTENSET_STALL_Pos;
+}
+
+static inline void hri_usbhost_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL;
+	} else {
+		((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+	}
+}
+
+static inline void hri_usbhost_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL;
+}
+
+static inline void hri_usbhost_set_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbhost_pintenset_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = mask;
+}
+
+static inline hri_usbhost_pintenset_reg_t hri_usbhost_get_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbhost_pintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_pintenset_reg_t hri_usbhost_read_PINTEN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg;
+}
+
+static inline void hri_usbhost_write_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_usbhost_pintenset_reg_t data)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = data;
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbhost_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_usbhost_pintenset_reg_t mask)
+{
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = mask;
+}
+
+static inline void hri_usbhost_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_BK;
+	tmp |= value << USB_HOST_PCFG_BK_Pos;
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbhost_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbhost_pcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_PTOKEN_Msk;
+	tmp |= USB_HOST_PCFG_PTOKEN(data);
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbhost_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbhost_pcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp &= ~USB_HOST_PCFG_PTYPE_Msk;
+	tmp |= USB_HOST_PCFG_PTYPE(data);
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbhost_pcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbhost_pcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbhost_pcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg;
+}
+
+static inline void hri_usbhost_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_BITINTERVAL_bf(const void *const hw,
+                                                                                   uint8_t           submodule_index,
+                                                                                   hri_usbhost_binterval_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+	tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbhost_binterval_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+	tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk;
+	tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data);
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_BITINTERVAL_bf(const void *const hw,
+                                                                                    uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+	tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbhost_binterval_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbhost_binterval_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbhost_binterval_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg;
+}
+
+static inline void hri_usbhostdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg |= USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_ADDR_bf(const void *const           hw,
+                                                                               hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->ADDR.reg;
+	tmp &= ~USB_HOST_ADDR_ADDR_Msk;
+	tmp |= USB_HOST_ADDR_ADDR(data);
+	((UsbHostDescBank *)hw)->ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg ^= USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_reg(const void *const           hw,
+                                                                           hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->ADDR.reg;
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                 hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbhostdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                   hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data);
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                   hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                    hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                        hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbhostdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                          hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                          hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                           hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbhostdescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk;
+	tmp |= USB_HOST_PCKSIZE_SIZE(data);
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_get_PCKSIZE_reg(const void *const              hw,
+                                                                                 hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->PCKSIZE.reg;
+}
+
+static inline void hri_usbhostdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_SUBPID_bf(const void *const             hw,
+                                                                                     hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_HOST_EXTREG_SUBPID_Msk;
+	tmp |= USB_HOST_EXTREG_SUBPID(data);
+	((UsbHostDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_SUBPID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t
+hri_usbhostdescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk;
+	tmp |= USB_HOST_EXTREG_VARIABLE(data);
+	((UsbHostDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                 hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_VARIABLE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_reg(const void *const             hw,
+                                                                               hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->EXTREG.reg;
+}
+
+static inline void hri_usbhostdescbank_set_CTRL_PIPE_PDADDR_bf(const void *const                hw,
+                                                               hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t
+hri_usbhostdescbank_get_CTRL_PIPE_PDADDR_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_CTRL_PIPE_PDADDR_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PDADDR(data);
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PDADDR_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PDADDR_bf(const void *const                hw,
+                                                                  hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PDADDR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_CTRL_PIPE_PEPNUM_bf(const void *const                hw,
+                                                               hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t
+hri_usbhostdescbank_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_CTRL_PIPE_PEPNUM_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data);
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PEPNUM_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PEPNUM_bf(const void *const                hw,
+                                                                  hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PEPNUM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_CTRL_PIPE_PERMAX_bf(const void *const                hw,
+                                                               hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t
+hri_usbhostdescbank_get_CTRL_PIPE_PERMAX_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_CTRL_PIPE_PERMAX_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PERMAX(data);
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PERMAX_bf(const void *const                hw,
+                                                                 hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PERMAX_bf(const void *const                hw,
+                                                                  hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PERMAX_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_set_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t
+hri_usbhostdescbank_get_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_write_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_clear_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->CTRL_PIPE.reg;
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) >> USB_HOST_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) >> USB_HOST_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t
+hri_usbhostdescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t hri_usbhostdescbank_read_STATUS_BK_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->STATUS_BK.reg;
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DTGLER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) >> USB_HOST_STATUS_PIPE_DTGLER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DTGLER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DAPIDER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER)
+	       >> USB_HOST_STATUS_PIPE_DAPIDER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_PIDER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) >> USB_HOST_STATUS_PIPE_PIDER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_PIDER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_TOUTER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) >> USB_HOST_STATUS_PIPE_TOUTER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_TOUTER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescbank_get_STATUS_PIPE_CRC16ER_bit(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER)
+	       >> USB_HOST_STATUS_PIPE_CRC16ER_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_pipe_reg_t
+hri_usbhostdescbank_get_STATUS_PIPE_ERCNT_bf(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask))
+	       >> USB_HOST_STATUS_PIPE_ERCNT_Pos;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_ERCNT_bf(const void *const                  hw,
+                                                                  hri_usbdesc_bank_status_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_ERCNT_bf(const void *const hw)
+{
+	return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk)
+	       >> USB_HOST_STATUS_PIPE_ERCNT_Pos;
+}
+
+static inline hri_usbdesc_bank_status_pipe_reg_t
+hri_usbhostdescbank_get_STATUS_PIPE_reg(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescBank *)hw)->STATUS_PIPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescbank_clear_STATUS_PIPE_reg(const void *const                  hw,
+                                                             hri_usbdesc_bank_status_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescBank *)hw)->STATUS_PIPE.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_reg(const void *const hw)
+{
+	return ((UsbHostDescBank *)hw)->STATUS_PIPE.reg;
+}
+
+static inline void hri_usbhostdescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptorhost_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_addr_reg_t
+hri_usbhostdescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                       hri_usbdescriptorhost_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptorhost_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+	tmp &= ~USB_HOST_ADDR_ADDR_Msk;
+	tmp |= USB_HOST_ADDR_ADDR(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptorhost_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptorhost_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= USB_HOST_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_ADDR_bf(const void *const hw,
+                                                                                       uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbdescriptorhost_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_addr_reg_t
+hri_usbhostdescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, hri_usbdescriptorhost_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdescriptorhost_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdescriptorhost_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdescriptorhost_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_reg(const void *const hw,
+                                                                                   uint8_t           submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg;
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index,
+                                                                    bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t
+hri_usbhostdescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbdescriptorhost_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t
+hri_usbhostdescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                          hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t
+hri_usbhostdescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw,
+                                                                            uint8_t           submodule_index,
+                                                                            hri_usbdescriptorhost_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw,
+                                                                            uint8_t           submodule_index,
+                                                                            hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw,
+                                                                             uint8_t           submodule_index,
+                                                                             hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t
+hri_usbhostdescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t
+hri_usbhostdescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                          hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptorhost_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk;
+	tmp |= USB_HOST_PCKSIZE_SIZE(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_SIZE_bf(const void *const hw,
+                                                                                             uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t
+hri_usbhostdescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                      hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptorhost_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptorhost_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_reg(const void *const hw,
+                                                                                         uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg;
+}
+
+static inline void hri_usbhostdescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_extreg_reg_t
+hri_usbhostdescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                           hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbdescriptorhost_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_HOST_EXTREG_SUBPID_Msk;
+	tmp |= USB_HOST_EXTREG_SUBPID(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_SUBPID_bf(const void *const hw,
+                                                                                             uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_extreg_reg_t
+hri_usbhostdescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                             hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptorhost_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk;
+	tmp |= USB_HOST_EXTREG_VARIABLE(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_VARIABLE_bf(const void *const hw,
+                                                                                               uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_extreg_reg_t
+hri_usbhostdescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                     hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptorhost_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptorhost_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_reg(const void *const hw,
+                                                                                       uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg;
+}
+
+static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_get_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                              hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PDADDR(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_read_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                              hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_read_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_get_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                              hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_ctrl_pipe_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk;
+	tmp |= USB_HOST_CTRL_PIPE_PERMAX(data);
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_read_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_set_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t
+hri_usbhostdescriptor_get_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                        hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_write_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptorhost_ctrl_pipe_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptorhost_ctrl_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_ctrl_pipe_reg_t hri_usbhostdescriptor_read_CTRL_PIPE_reg(const void *const hw,
+                                                                                             uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg;
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR)
+	       >> USB_HOST_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW)
+	       >> USB_HOST_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_status_bk_reg_t
+hri_usbhostdescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                        hri_usbdescriptorhost_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptorhost_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_status_bk_reg_t hri_usbhostdescriptor_read_STATUS_BK_reg(const void *const hw,
+                                                                                             uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg;
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER)
+	       >> USB_HOST_STATUS_PIPE_DTGLER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER)
+	       >> USB_HOST_STATUS_PIPE_DAPIDER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER)
+	       >> USB_HOST_STATUS_PIPE_PIDER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER)
+	       >> USB_HOST_STATUS_PIPE_TOUTER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER)
+	       >> USB_HOST_STATUS_PIPE_CRC16ER_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_status_pipe_reg_t
+hri_usbhostdescriptor_get_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_usbdescriptorhost_status_pipe_reg_t mask)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask))
+	       >> USB_HOST_STATUS_PIPE_ERCNT_Pos;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptorhost_status_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_status_pipe_reg_t
+hri_usbhostdescriptor_read_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk)
+	       >> USB_HOST_STATUS_PIPE_ERCNT_Pos;
+}
+
+static inline hri_usbdescriptorhost_status_pipe_reg_t
+hri_usbhostdescriptor_get_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                          hri_usbdescriptorhost_status_pipe_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptorhost_status_pipe_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptorhost_status_pipe_reg_t
+hri_usbhostdescriptor_read_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline hri_usbendpoint_epintflag_reg_t
+hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw,
+                                                                                 uint8_t           submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                       hri_usbendpoint_epintflag_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT)
+	       >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN)
+	       >> USB_DEVICE_EPSTATUS_DTGLIN_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK)
+	       >> USB_DEVICE_EPSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index,
+                                                               bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index,
+                                                               bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY)
+	       >> USB_DEVICE_EPSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY)
+	       >> USB_DEVICE_EPSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbendpoint_epstatus_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask;
+}
+
+static inline hri_usbendpoint_epstatus_reg_t
+hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw,
+                                                                               uint8_t           submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbendpoint_epstatus_reg_t data)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data;
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbendpoint_epstatus_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0)
+	       >> USB_DEVICE_EPINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1)
+	       >> USB_DEVICE_EPINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP)
+	       >> USB_DEVICE_EPINTENSET_RXSTP_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0)
+	       >> USB_DEVICE_EPINTENSET_STALL0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1)
+	       >> USB_DEVICE_EPINTENSET_STALL1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbendpoint_epintenset_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask;
+}
+
+static inline hri_usbendpoint_epintenset_reg_t
+hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbendpoint_epintenset_reg_t data)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data;
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbendpoint_epintenset_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask;
+}
+
+static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_NYETDIS;
+	tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos;
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t
+hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE0(data);
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t
+hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE1(data);
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbendpoint_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbendpoint_epcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline hri_usbdevice_epintflag_reg_t
+hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw,
+                                                                             uint8_t           submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbdevice_epintflag_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT)
+	       >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN)
+	       >> USB_DEVICE_EPSTATUS_DTGLIN_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK)
+	       >> USB_DEVICE_EPSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY)
+	       >> USB_DEVICE_EPSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY)
+	       >> USB_DEVICE_EPSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbdevice_epstatus_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask;
+}
+
+static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                          hri_usbdevice_epstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw,
+                                                                           uint8_t           submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbdevice_epstatus_reg_t data)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data;
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbdevice_epstatus_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0)
+	       >> USB_DEVICE_EPINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1)
+	       >> USB_DEVICE_EPINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP)
+	       >> USB_DEVICE_EPINTENSET_RXSTP_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0)
+	       >> USB_DEVICE_EPINTENSET_STALL0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1)
+	       >> USB_DEVICE_EPINTENSET_STALL1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbdevice_epintenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask;
+}
+
+static inline hri_usbdevice_epintenset_reg_t
+hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbdevice_epintenset_reg_t data)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data;
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbdevice_epintenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask;
+}
+
+static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_NYETDIS;
+	tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos;
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t
+hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE0(data);
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t
+hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE1(data);
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdevice_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbdevice_epcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP;
+}
+
+static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND;
+}
+
+static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF;
+}
+
+static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF;
+}
+
+static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST;
+}
+
+static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM;
+}
+
+static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET;
+}
+
+static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP;
+}
+
+static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const           hw,
+                                                                        hri_usbdevice_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.INTFLAG.reg;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = mask;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_HSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_HSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_RST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_RST_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_DNRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_DNRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_DCONN_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_DCONN_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN;
+}
+
+static inline bool hri_usbhost_get_INTFLAG_DDISC_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_DDISC_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC;
+}
+
+static inline bool hri_usbhost_get_interrupt_HSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_HSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF;
+}
+
+static inline bool hri_usbhost_get_interrupt_RST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_RST_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST;
+}
+
+static inline bool hri_usbhost_get_interrupt_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbhost_get_interrupt_DNRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_DNRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM;
+}
+
+static inline bool hri_usbhost_get_interrupt_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbhost_get_interrupt_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbhost_get_interrupt_DCONN_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_DCONN_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN;
+}
+
+static inline bool hri_usbhost_get_interrupt_DDISC_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos;
+}
+
+static inline void hri_usbhost_clear_interrupt_DDISC_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC;
+}
+
+static inline hri_usbhost_intflag_reg_t hri_usbhost_get_INTFLAG_reg(const void *const         hw,
+                                                                    hri_usbhost_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_intflag_reg_t hri_usbhost_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.INTFLAG.reg;
+}
+
+static inline void hri_usbhost_clear_INTFLAG_reg(const void *const hw, hri_usbhost_intflag_reg_t mask)
+{
+	((Usb *)hw)->HOST.INTFLAG.reg = mask;
+}
+
+static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND;
+}
+
+static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND;
+}
+
+static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF;
+}
+
+static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF;
+}
+
+static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF;
+}
+
+static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF;
+}
+
+static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST;
+}
+
+static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST;
+}
+
+static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP;
+}
+
+static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP;
+}
+
+static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM;
+}
+
+static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM;
+}
+
+static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM;
+}
+
+static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM;
+}
+
+static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER;
+}
+
+static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER;
+}
+
+static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET;
+}
+
+static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET;
+}
+
+static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP;
+}
+
+static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP;
+}
+
+static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = mask;
+}
+
+static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const            hw,
+                                                                       hri_usbdevice_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.INTENSET.reg;
+}
+
+static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = data;
+	((Usb *)hw)->DEVICE.INTENCLR.reg = ~data;
+}
+
+static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = mask;
+}
+
+static inline void hri_usbhost_set_INTEN_HSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF;
+}
+
+static inline bool hri_usbhost_get_INTEN_HSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_HSOF) >> USB_HOST_INTENSET_HSOF_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_HSOF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_HSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF;
+}
+
+static inline void hri_usbhost_set_INTEN_RST_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST;
+}
+
+static inline bool hri_usbhost_get_INTEN_RST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RST) >> USB_HOST_INTENSET_RST_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_RST_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_RST_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST;
+}
+
+static inline void hri_usbhost_set_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP;
+}
+
+static inline bool hri_usbhost_get_INTEN_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_WAKEUP) >> USB_HOST_INTENSET_WAKEUP_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_WAKEUP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP;
+}
+
+static inline void hri_usbhost_set_INTEN_DNRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM;
+}
+
+static inline bool hri_usbhost_get_INTEN_DNRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DNRSM) >> USB_HOST_INTENSET_DNRSM_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_DNRSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_DNRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM;
+}
+
+static inline void hri_usbhost_set_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM;
+}
+
+static inline bool hri_usbhost_get_INTEN_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_UPRSM) >> USB_HOST_INTENSET_UPRSM_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_UPRSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM;
+}
+
+static inline void hri_usbhost_set_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER;
+}
+
+static inline bool hri_usbhost_get_INTEN_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RAMACER) >> USB_HOST_INTENSET_RAMACER_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_RAMACER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER;
+}
+
+static inline void hri_usbhost_set_INTEN_DCONN_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN;
+}
+
+static inline bool hri_usbhost_get_INTEN_DCONN_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DCONN) >> USB_HOST_INTENSET_DCONN_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_DCONN_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_DCONN_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN;
+}
+
+static inline void hri_usbhost_set_INTEN_DDISC_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC;
+}
+
+static inline bool hri_usbhost_get_INTEN_DDISC_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DDISC) >> USB_HOST_INTENSET_DDISC_Pos;
+}
+
+static inline void hri_usbhost_write_INTEN_DDISC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC;
+	} else {
+		((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC;
+	}
+}
+
+static inline void hri_usbhost_clear_INTEN_DDISC_bit(const void *const hw)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC;
+}
+
+static inline void hri_usbhost_set_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = mask;
+}
+
+static inline hri_usbhost_intenset_reg_t hri_usbhost_get_INTEN_reg(const void *const          hw,
+                                                                   hri_usbhost_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_intenset_reg_t hri_usbhost_read_INTEN_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.INTENSET.reg;
+}
+
+static inline void hri_usbhost_write_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t data)
+{
+	((Usb *)hw)->HOST.INTENSET.reg = data;
+	((Usb *)hw)->HOST.INTENCLR.reg = ~data;
+}
+
+static inline void hri_usbhost_clear_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask)
+{
+	((Usb *)hw)->HOST.INTENCLR.reg = mask;
+}
+
+static inline bool hri_usb_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_usb_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_usb_syncbusy_reg_t hri_usb_get_SYNCBUSY_reg(const void *const hw, hri_usb_syncbusy_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usb_syncbusy_reg_t hri_usb_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.SYNCBUSY.reg;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const          hw,
+                                                                           hri_usbdevice_status_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const          hw,
+                                                                               hri_usbdevice_status_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const          hw,
+                                                                      hri_usbdevice_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.STATUS.reg;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_FSMSTATE_bf(const void *const       hw,
+                                                                        hri_usb_fsmstatus_reg_t mask)
+{
+	return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_FSMSTATE_bf(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_reg(const void *const hw, hri_usb_fsmstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.FSMSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.FSMSTATUS.reg;
+}
+
+static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const        hw,
+                                                                       hri_usbdevice_fnum_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const        hw,
+                                                                      hri_usbdevice_fnum_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.FNUM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.FNUM.reg;
+}
+
+static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_FLENHIGH_bf(const void *const          hw,
+                                                                              hri_usbhost_flenhigh_reg_t mask)
+{
+	return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH(mask)) >> USB_HOST_FLENHIGH_FLENHIGH_Pos;
+}
+
+static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_FLENHIGH_bf(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH_Msk) >> USB_HOST_FLENHIGH_FLENHIGH_Pos;
+}
+
+static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_reg(const void *const          hw,
+                                                                      hri_usbhost_flenhigh_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.FLENHIGH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.FLENHIGH.reg;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos;
+}
+
+static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const             hw,
+                                                                            hri_usbdevice_epintsmry_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.EPINTSMRY.reg;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT0_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT0) >> USB_HOST_PINTSMRY_EPINT0_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT1_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT1) >> USB_HOST_PINTSMRY_EPINT1_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT2_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT2) >> USB_HOST_PINTSMRY_EPINT2_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT3_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT3) >> USB_HOST_PINTSMRY_EPINT3_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT4_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT4) >> USB_HOST_PINTSMRY_EPINT4_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT5_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT5) >> USB_HOST_PINTSMRY_EPINT5_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT6_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT6) >> USB_HOST_PINTSMRY_EPINT6_Pos;
+}
+
+static inline bool hri_usbhost_get_PINTSMRY_EPINT7_bit(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT7) >> USB_HOST_PINTSMRY_EPINT7_Pos;
+}
+
+static inline hri_usbhost_pintsmry_reg_t hri_usbhost_get_PINTSMRY_reg(const void *const          hw,
+                                                                      hri_usbhost_pintsmry_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PINTSMRY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbhost_pintsmry_reg_t hri_usbhost_read_PINTSMRY_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.PINTSMRY.reg;
+}
+
+static inline void hri_usb_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_SWRST;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST);
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_ENABLE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp &= ~USB_CTRLA_ENABLE;
+	tmp |= value << USB_CTRLA_ENABLE_Pos;
+	((Usb *)hw)->HOST.CTRLA.reg = tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_ENABLE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_ENABLE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_RUNSTDBY;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp &= ~USB_CTRLA_RUNSTDBY;
+	tmp |= value << USB_CTRLA_RUNSTDBY_Pos;
+	((Usb *)hw)->HOST.CTRLA.reg = tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_RUNSTDBY;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_set_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_MODE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_MODE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_write_CTRLA_MODE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp &= ~USB_CTRLA_MODE;
+	tmp |= value << USB_CTRLA_MODE_Pos;
+	((Usb *)hw)->HOST.CTRLA.reg = tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_MODE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_MODE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_set_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg |= mask;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_ctrla_reg_t hri_usb_get_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	tmp = ((Usb *)hw)->HOST.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg = data;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg &= ~mask;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLA.reg ^= mask;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_ctrla_reg_t hri_usb_read_CTRLA_reg(const void *const hw)
+{
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	return ((Usb *)hw)->HOST.CTRLA.reg;
+}
+
+static inline void hri_usb_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp &= ~USB_QOSCTRL_CQOS_Msk;
+	tmp |= USB_QOSCTRL_CQOS(data);
+	((Usb *)hw)->HOST.QOSCTRL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_CQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp &= ~USB_QOSCTRL_DQOS_Msk;
+	tmp |= USB_QOSCTRL_DQOS(data);
+	((Usb *)hw)->HOST.QOSCTRL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_DQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.QOSCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.QOSCTRL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.QOSCTRL.reg;
+}
+
+static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_DETACH;
+	tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_UPRSM;
+	tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_NREPLY;
+	tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_TSTJ;
+	tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_TSTK;
+	tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_TSTPCKT;
+	tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_OPMODE2;
+	tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_GNAK;
+	tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const         hw,
+                                                                           hri_usbdevice_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk;
+	tmp |= USB_DEVICE_CTRLB_SPDCONF(data);
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const         hw,
+                                                                           hri_usbdevice_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk;
+	tmp |= USB_DEVICE_CTRLB_LPMHDSK(data);
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const         hw,
+                                                                    hri_usbdevice_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.CTRLB.reg;
+}
+
+static inline void hri_usbhost_set_CTRLB_RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_RESUME_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_RESUME) >> USB_HOST_CTRLB_RESUME_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_RESUME_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_RESUME;
+	tmp |= value << USB_HOST_CTRLB_RESUME_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_AUTORESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_AUTORESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_AUTORESUME_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_AUTORESUME) >> USB_HOST_CTRLB_AUTORESUME_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_AUTORESUME_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_AUTORESUME;
+	tmp |= value << USB_HOST_CTRLB_AUTORESUME_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_AUTORESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_AUTORESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_AUTORESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_AUTORESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_TSTJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_TSTJ) >> USB_HOST_CTRLB_TSTJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_TSTJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_TSTJ;
+	tmp |= value << USB_HOST_CTRLB_TSTJ_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_TSTK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_TSTK) >> USB_HOST_CTRLB_TSTK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_TSTK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_TSTK;
+	tmp |= value << USB_HOST_CTRLB_TSTK_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_SOFE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SOFE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_SOFE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_SOFE) >> USB_HOST_CTRLB_SOFE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_SOFE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_SOFE;
+	tmp |= value << USB_HOST_CTRLB_SOFE_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_SOFE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SOFE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_SOFE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SOFE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_BUSRESET_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_BUSRESET;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_BUSRESET_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_BUSRESET) >> USB_HOST_CTRLB_BUSRESET_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_BUSRESET_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_BUSRESET;
+	tmp |= value << USB_HOST_CTRLB_BUSRESET_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_BUSRESET_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_BUSRESET;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_BUSRESET_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_BUSRESET;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_VBUSOK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_VBUSOK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_VBUSOK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_VBUSOK) >> USB_HOST_CTRLB_VBUSOK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_VBUSOK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_VBUSOK;
+	tmp |= value << USB_HOST_CTRLB_VBUSOK_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_VBUSOK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_VBUSOK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_VBUSOK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_VBUSOK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_L1RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_L1RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_CTRLB_L1RESUME_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_L1RESUME) >> USB_HOST_CTRLB_L1RESUME_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_L1RESUME_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_L1RESUME;
+	tmp |= value << USB_HOST_CTRLB_L1RESUME_Pos;
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_L1RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_L1RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_L1RESUME_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_L1RESUME;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_SPDCONF_bf(const void *const       hw,
+                                                                       hri_usbhost_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_SPDCONF(mask)) >> USB_HOST_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= ~USB_HOST_CTRLB_SPDCONF_Msk;
+	tmp |= USB_HOST_CTRLB_SPDCONF(data);
+	((Usb *)hw)->HOST.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_SPDCONF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp = (tmp & USB_HOST_CTRLB_SPDCONF_Msk) >> USB_HOST_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.CTRLB.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.CTRLB.reg;
+}
+
+static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp &= ~USB_DEVICE_DADD_ADDEN;
+	tmp |= value << USB_DEVICE_DADD_ADDEN_Pos;
+	((Usb *)hw)->DEVICE.DADD.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const        hw,
+                                                                      hri_usbdevice_dadd_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp &= ~USB_DEVICE_DADD_DADD_Msk;
+	tmp |= USB_DEVICE_DADD_DADD(data);
+	((Usb *)hw)->DEVICE.DADD.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.DADD.reg;
+}
+
+static inline void hri_usbhost_set_HSOFC_FLENCE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENCE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbhost_get_HSOFC_FLENCE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp = (tmp & USB_HOST_HSOFC_FLENCE) >> USB_HOST_HSOFC_FLENCE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbhost_write_HSOFC_FLENCE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp &= ~USB_HOST_HSOFC_FLENCE;
+	tmp |= value << USB_HOST_HSOFC_FLENCE_Pos;
+	((Usb *)hw)->HOST.HSOFC.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_HSOFC_FLENCE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENCE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_HSOFC_FLENCE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENCE;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_set_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENC(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp = (tmp & USB_HOST_HSOFC_FLENC(mask)) >> USB_HOST_HSOFC_FLENC_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp &= ~USB_HOST_HSOFC_FLENC_Msk;
+	tmp |= USB_HOST_HSOFC_FLENC(data);
+	((Usb *)hw)->HOST.HSOFC.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENC(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENC(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_FLENC_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp = (tmp & USB_HOST_HSOFC_FLENC_Msk) >> USB_HOST_HSOFC_FLENC_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.HSOFC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.HSOFC.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.HSOFC.reg;
+}
+
+static inline void hri_usbhost_set_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_MFNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp = (tmp & USB_HOST_FNUM_MFNUM(mask)) >> USB_HOST_FNUM_MFNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp &= ~USB_HOST_FNUM_MFNUM_Msk;
+	tmp |= USB_HOST_FNUM_MFNUM(data);
+	((Usb *)hw)->HOST.FNUM.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_MFNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_MFNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_MFNUM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp = (tmp & USB_HOST_FNUM_MFNUM_Msk) >> USB_HOST_FNUM_MFNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_FNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp = (tmp & USB_HOST_FNUM_FNUM(mask)) >> USB_HOST_FNUM_FNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp &= ~USB_HOST_FNUM_FNUM_Msk;
+	tmp |= USB_HOST_FNUM_FNUM(data);
+	((Usb *)hw)->HOST.FNUM.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_FNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_FNUM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_FNUM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp = (tmp & USB_HOST_FNUM_FNUM_Msk) >> USB_HOST_FNUM_FNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_usbhost_set_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.FNUM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_write_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_clear_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbhost_toggle_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.FNUM.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.FNUM.reg;
+}
+
+static inline void hri_usb_set_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg |= USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->HOST.DESCADD.reg;
+	tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.DESCADD.reg;
+	tmp &= ~USB_DESCADD_DESCADD_Msk;
+	tmp |= USB_DESCADD_DESCADD(data);
+	((Usb *)hw)->HOST.DESCADD.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg ^= USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_DESCADD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->HOST.DESCADD.reg;
+	tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->HOST.DESCADD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.DESCADD.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.DESCADD.reg;
+}
+
+static inline void hri_usb_set_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRANSP_Msk;
+	tmp |= USB_PADCAL_TRANSP(data);
+	((Usb *)hw)->HOST.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRANSN_Msk;
+	tmp |= USB_PADCAL_TRANSN(data);
+	((Usb *)hw)->HOST.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRIM_Msk;
+	tmp |= USB_PADCAL_TRIM(data);
+	((Usb *)hw)->HOST.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRIM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->HOST.PADCAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.PADCAL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.PADCAL.reg;
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_SPEED_bf(const void *const        hw,
+                                                                       hri_usbhost_status_reg_t mask)
+{
+	return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED(mask)) >> USB_HOST_STATUS_SPEED_Pos;
+}
+
+static inline void hri_usbhost_clear_STATUS_SPEED_bf(const void *const hw, hri_usbhost_status_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_SPEED(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_SPEED_bf(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED_Msk) >> USB_HOST_STATUS_SPEED_Pos;
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_LINESTATE_bf(const void *const        hw,
+                                                                           hri_usbhost_status_reg_t mask)
+{
+	return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE(mask)) >> USB_HOST_STATUS_LINESTATE_Pos;
+}
+
+static inline void hri_usbhost_clear_STATUS_LINESTATE_bf(const void *const hw, hri_usbhost_status_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_LINESTATE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_LINESTATE_bf(const void *const hw)
+{
+	return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE_Msk) >> USB_HOST_STATUS_LINESTATE_Pos;
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->HOST.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbhost_clear_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->HOST.STATUS.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_reg(const void *const hw)
+{
+	return ((Usb *)hw)->HOST.STATUS.reg;
+}
+
+static inline void hri_usbdevicedescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_ADDR_bf(const void *const           hw,
+                                                                                 hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp &= ~USB_DEVICE_ADDR_ADDR_Msk;
+	tmp |= USB_DEVICE_ADDR_ADDR(data);
+	((UsbDeviceDescBank *)hw)->ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_reg(const void *const           hw,
+                                                                             hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->ADDR.reg;
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                   hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdevicedescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                     hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data);
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                     hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                      hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                          hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdevicedescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                            hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                            hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                             hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdevicedescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdevicedescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_SIZE_bf(const void *const              hw,
+                                                               hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_SIZE(data);
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_SIZE_bf(const void *const              hw,
+                                                               hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_SIZE_bf(const void *const              hw,
+                                                                hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_get_PCKSIZE_reg(const void *const              hw,
+                                                                                   hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+}
+
+static inline void hri_usbdevicedescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t
+hri_usbdevicedescbank_get_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_EXTREG_SUBPID_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk;
+	tmp |= USB_DEVICE_EXTREG_SUBPID(data);
+	((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_EXTREG_SUBPID_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_EXTREG_SUBPID_bf(const void *const             hw,
+                                                                 hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_SUBPID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t
+hri_usbdevicedescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                  hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk;
+	tmp |= USB_DEVICE_EXTREG_VARIABLE(data);
+	((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                  hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                   hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_VARIABLE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_get_EXTREG_reg(const void *const             hw,
+                                                                                 hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+}
+
+static inline bool hri_usbdevicedescbank_get_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbdevicedescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW)
+	       >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbdevicedescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t
+hri_usbdevicedescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescbank_clear_STATUS_BK_reg(const void *const                hw,
+                                                             hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdevicedescbank_read_STATUS_BK_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg;
+}
+
+static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t
+hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                         hri_usbdescriptordevice_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptordevice_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp &= ~USB_DEVICE_ADDR_ADDR_Msk;
+	tmp |= USB_DEVICE_ADDR_ADDR(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw,
+                                                                                           uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t
+hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                     hri_usbdescriptordevice_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptordevice_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw,
+                                                                                       uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index,
+                                                                      bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw,
+                                                                            uint8_t           submodule_index,
+                                                                            hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg
+	    |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void
+hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void
+hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg
+	    &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void
+hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg
+	    ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                            hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_SIZE(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                        hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw,
+                                                                                             uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+}
+
+static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                             hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk;
+	tmp |= USB_DEVICE_EXTREG_SUBPID(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptordevice_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk;
+	tmp |= USB_DEVICE_EXTREG_VARIABLE(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                       hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw,
+                                                                                           uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+}
+
+static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR)
+	       >> USB_DEVICE_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW)
+	       >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_status_bk_reg_t
+hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                          hri_usbdescriptordevice_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptordevice_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_status_bk_reg_t
+hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_usbdevice_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b)
+#define hri_usbdevice_is_syncing(a, b) hri_usb_is_syncing(a, b)
+#define hri_usbhost_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b)
+#define hri_usbhost_is_syncing(a, b) hri_usb_is_syncing(a, b)
+#define hri_usbhost_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a)
+#define hri_usbhost_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a)
+#define hri_usbhost_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a)
+#define hri_usbhost_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a)
+#define hri_usbhost_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b)
+#define hri_usbhost_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a)
+#define hri_usbhost_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a)
+#define hri_usbhost_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbhost_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbhost_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b)
+#define hri_usbhost_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbhost_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbhost_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a)
+#define hri_usbhost_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a)
+#define hri_usbhost_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b)
+#define hri_usbhost_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a)
+#define hri_usbhost_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a)
+#define hri_usbhost_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b)
+#define hri_usbhost_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b)
+#define hri_usbhost_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b)
+#define hri_usbhost_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b)
+#define hri_usbhost_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b)
+#define hri_usbhost_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a)
+#define hri_usbhost_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbhost_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbhost_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbhost_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbhost_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbhost_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a)
+#define hri_usbhost_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbhost_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbhost_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbhost_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbhost_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbhost_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a)
+#define hri_usbhost_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b)
+#define hri_usbhost_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b)
+#define hri_usbhost_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b)
+#define hri_usbhost_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b)
+#define hri_usbhost_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b)
+#define hri_usbhost_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a)
+#define hri_usbhost_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b)
+#define hri_usbhost_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b)
+#define hri_usbhost_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b)
+#define hri_usbhost_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b)
+#define hri_usbhost_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b)
+#define hri_usbhost_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a)
+#define hri_usbhost_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b)
+#define hri_usbhost_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b)
+#define hri_usbhost_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b)
+#define hri_usbhost_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b)
+#define hri_usbhost_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b)
+#define hri_usbhost_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a)
+#define hri_usbhost_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b)
+#define hri_usbhost_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b)
+#define hri_usbhost_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b)
+#define hri_usbhost_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b)
+#define hri_usbhost_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b)
+#define hri_usbhost_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a)
+#define hri_usbhost_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b)
+#define hri_usbhost_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b)
+#define hri_usbhost_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b)
+#define hri_usbhost_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b)
+#define hri_usbhost_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b)
+#define hri_usbhost_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a)
+#define hri_usbhost_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b)
+#define hri_usbhost_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b)
+#define hri_usbhost_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b)
+#define hri_usbhost_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b)
+#define hri_usbhost_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b)
+#define hri_usbhost_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a)
+#define hri_usbhost_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b)
+#define hri_usbhost_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b)
+#define hri_usbhost_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b)
+#define hri_usbhost_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b)
+#define hri_usbhost_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b)
+#define hri_usbhost_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a)
+#define hri_usbhost_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a)
+#define hri_usbhost_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a)
+#define hri_usbhost_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b)
+#define hri_usbhost_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a)
+#define hri_usbhost_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b)
+#define hri_usbhost_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a)
+#define hri_usbhost_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b)
+#define hri_usbhost_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a)
+#define hri_usbdevice_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a)
+#define hri_usbdevice_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a)
+#define hri_usbdevice_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b)
+#define hri_usbdevice_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b)
+#define hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a)
+#define hri_usbdevice_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a)
+#define hri_usbdevice_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b)
+#define hri_usbdevice_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a)
+#define hri_usbdevice_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a)
+#define hri_usbdevice_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b)
+#define hri_usbdevice_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b)
+#define hri_usbdevice_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b)
+#define hri_usbdevice_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b)
+#define hri_usbdevice_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b)
+#define hri_usbdevice_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a)
+#define hri_usbdevice_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a)
+#define hri_usbdevice_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a)
+#define hri_usbdevice_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b)
+#define hri_usbdevice_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b)
+#define hri_usbdevice_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b)
+#define hri_usbdevice_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b)
+#define hri_usbdevice_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b)
+#define hri_usbdevice_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a)
+#define hri_usbdevice_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a)
+#define hri_usbdevice_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b)
+#define hri_usbdevice_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b)
+#define hri_usbdevice_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b)
+#define hri_usbdevice_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b)
+#define hri_usbdevice_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b)
+#define hri_usbdevice_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a)
+#define hri_usbdevice_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a)
+#define hri_usbdevice_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a)
+#define hri_usbdevice_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a)
+#define hri_usbdevice_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b)
+#define hri_usbdevice_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b)
+#define hri_usbdevice_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b)
+#define hri_usbdevice_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b)
+#define hri_usbdevice_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b)
+#define hri_usbdevice_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a)
+#define hri_usbdevice_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a)
+#define hri_usbdevice_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a)
+#define hri_usbdevice_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b)
+#define hri_usbdevice_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a)
+#define hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b)
+#define hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a)
+#define hri_usbdevice_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b)
+#define hri_usbdevice_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_USB_E54_H_INCLUDED */
+#endif /* _SAME54_USB_COMPONENT_ */
diff --git a/hri/hri_wdt_e54.h b/hri/hri_wdt_e54.h
new file mode 100644
index 0000000..3549e2f
--- /dev/null
+++ b/hri/hri_wdt_e54.h
@@ -0,0 +1,617 @@
+/**
+ * \file
+ *
+ * \brief SAM WDT
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAME54_WDT_COMPONENT_
+#ifndef _HRI_WDT_E54_H_INCLUDED_
+#define _HRI_WDT_E54_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_WDT_CRITICAL_SECTIONS)
+#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define WDT_CRITICAL_SECTION_ENTER()
+#define WDT_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_wdt_syncbusy_reg_t;
+typedef uint8_t  hri_wdt_clear_reg_t;
+typedef uint8_t  hri_wdt_config_reg_t;
+typedef uint8_t  hri_wdt_ctrla_reg_t;
+typedef uint8_t  hri_wdt_ewctrl_reg_t;
+typedef uint8_t  hri_wdt_intenset_reg_t;
+typedef uint8_t  hri_wdt_intflag_reg_t;
+
+static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg)
+{
+	while (((Wdt *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg)
+{
+	return ((Wdt *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos;
+}
+
+static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW;
+}
+
+static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos;
+}
+
+static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW;
+}
+
+static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask)
+{
+	((Wdt *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW;
+}
+
+static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos;
+}
+
+static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW;
+	} else {
+		((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW;
+	}
+}
+
+static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW;
+}
+
+static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
+{
+	((Wdt *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->INTENSET.reg;
+}
+
+static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data)
+{
+	((Wdt *)hw)->INTENSET.reg = data;
+	((Wdt *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
+{
+	((Wdt *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos;
+}
+
+static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Wdt *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= ~WDT_CTRLA_ENABLE;
+	tmp |= value << WDT_CTRLA_ENABLE_Pos;
+	((Wdt *)hw)->CTRLA.reg = tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= ~WDT_CTRLA_WEN;
+	tmp |= value << WDT_CTRLA_WEN_Pos;
+	((Wdt *)hw)->CTRLA.reg = tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= ~WDT_CTRLA_ALWAYSON;
+	tmp |= value << WDT_CTRLA_ALWAYSON_Pos;
+	((Wdt *)hw)->CTRLA.reg = tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= mask;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg = data;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~mask;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= mask;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw)
+{
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	return ((Wdt *)hw)->CTRLA.reg;
+}
+
+static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp &= ~WDT_CONFIG_PER_Msk;
+	tmp |= WDT_CONFIG_PER(data);
+	((Wdt *)hw)->CONFIG.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp &= ~WDT_CONFIG_WINDOW_Msk;
+	tmp |= WDT_CONFIG_WINDOW(data);
+	((Wdt *)hw)->CONFIG.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg |= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg = data;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg &= ~mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg ^= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->CONFIG.reg;
+}
+
+static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp &= ~WDT_EWCTRL_EWOFFSET_Msk;
+	tmp |= WDT_EWCTRL_EWOFFSET(data);
+	((Wdt *)hw)->EWCTRL.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg |= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg = data;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg &= ~mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg ^= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->EWCTRL.reg;
+}
+
+static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CLEAR.reg = data;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_CLEAR);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_WDT_E54_H_INCLUDED */
+#endif /* _SAME54_WDT_COMPONENT_ */