diff options
| author | Pau Espin Pedrol <pespin@sysmocom.de> | 2017-11-23 19:06:09 +0100 |
|---|---|---|
| committer | Pau Espin Pedrol <pespin@sysmocom.de> | 2017-11-27 12:33:19 +0100 |
| commit | 5d69fa52cf1e679e391519dd841da1579d640087 (patch) | |
| tree | 20aa11ff19f5aa0a1a991eaad0af1d4183fe97b6 /openbsc/src/libbsc/system_information.c | |
| parent | 75042ff46a7e89ffb9a8897214c63e0bda378147 (diff) | |
vty: Add cmd to configure 3g Early Classmark Sending
In state prior to this patch, "3G Early Classmark Sending Restriction"
bit in SI3 rest octets was always set to H, which is a sane default as
the policy to send the information is then controlled by "Early
Classmark Sending Control" bit in the same octet.
However, it seems Quortus SoftCore can have some issues decoding the
option, so let's add a vty cmd to be able to disable it for those
having any issues.
Related: SYS#4021
Change-Id: Ic1afe071038a3bb5871d7ff40f665c8644f801ec
Diffstat (limited to 'openbsc/src/libbsc/system_information.c')
| -rw-r--r-- | openbsc/src/libbsc/system_information.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/openbsc/src/libbsc/system_information.c b/openbsc/src/libbsc/system_information.c index b27465e77..a878b52ef 100644 --- a/openbsc/src/libbsc/system_information.c +++ b/openbsc/src/libbsc/system_information.c @@ -812,6 +812,7 @@ static struct gsm48_si_ro_info si_info = { .ra_colour = 0, .present = 1, }, + .early_cm_restrict_3g = false, .si2quater_indicator = false, .lsa_params = { .present = 0, @@ -858,6 +859,7 @@ static int generate_si3(enum osmo_sysinfo_type t, struct gsm_bts *bts) si_info.si2quater_indicator = false; } si_info.early_cm_ctrl = bts->early_classmark_allowed; + si_info.early_cm_restrict_3g = !bts->early_classmark_allowed_3g; /* SI3 Rest Octets (10.5.2.34), containing CBQ, CELL_RESELECT_OFFSET, TEMPORARY_OFFSET, PENALTY_TIME |