diff options
author | patacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679> | 2010-08-24 02:03:45 +0000 |
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committer | patacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679> | 2010-08-24 02:03:45 +0000 |
commit | e39ba378a23242aab6795cdfd4d119680dd39e9b (patch) | |
tree | ae2f9cadbd8836df12b15f10422df02b8124233b /nuttx | |
parent | c0c8ae298dda62718c35617ad30a14f9752e5c3b (diff) |
Fix heap/page table overlap; Switch to 1Kb pages
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@2881 7fd9a85b-ad96-42d3-883c-3090e2eb8679
Diffstat (limited to 'nuttx')
-rw-r--r-- | nuttx/arch/arm/src/arm/pg_macros.h | 26 | ||||
-rw-r--r-- | nuttx/arch/arm/src/dm320/dm320_boot.c | 10 | ||||
-rw-r--r-- | nuttx/arch/arm/src/dm320/dm320_memorymap.h | 20 | ||||
-rwxr-xr-x | nuttx/arch/arm/src/lpc313x/lpc313x_allocateheap.c | 21 | ||||
-rwxr-xr-x | nuttx/arch/arm/src/lpc313x/lpc313x_boot.c | 4 | ||||
-rwxr-xr-x | nuttx/arch/arm/src/lpc313x/lpc313x_memorymap.h | 37 | ||||
-rwxr-xr-x | nuttx/configs/ea3131/pgnsh/defconfig | 10 | ||||
-rwxr-xr-x | nuttx/include/nuttx/page.h | 8 |
8 files changed, 73 insertions, 63 deletions
diff --git a/nuttx/arch/arm/src/arm/pg_macros.h b/nuttx/arch/arm/src/arm/pg_macros.h index 305ae4304d..d8f295e1d0 100644 --- a/nuttx/arch/arm/src/arm/pg_macros.h +++ b/nuttx/arch/arm/src/arm/pg_macros.h @@ -77,11 +77,6 @@ # define PG_L1_PADDRMASK PMD_FINE_TEX_MASK - /* L2 Page table address */ - -# define PG_L2_BASE_PADDR PGTABLE_FINE_BASE_PADDR -# define PG_L2_BASE_VADDR PGTABLE_FINE_BASE_VADDR - /* MMU Flags for each memory region */ # define MMU_L1_TEXTFLAGS (PMD_TYPE_FINE|PMD_BIT4) @@ -104,11 +99,6 @@ # define PG_L1_PADDRMASK PMD_COARSE_TEX_MASK - /* L2 Page table address */ - -# define PG_L2_BASE_PADDR PGTABLE_COARSE_BASE_PADDR -# define PG_L2_BASE_VADDR PGTABLE_COARSE_BASE_VADDR - /* MMU Flags for each memory region. */ # define MMU_L1_TEXTFLAGS (PMD_TYPE_COARSE|PMD_BIT4) @@ -133,8 +123,8 @@ #define PG_L1_LOCKED_PADDR (PGTABLE_BASE_PADDR + ((PG_LOCKED_VBASE >> 20) << 2)) #define PG_L1_LOCKED_VADDR (PGTABLE_BASE_VADDR + ((PG_LOCKED_VBASE >> 20) << 2)) -#define PG_L2_LOCKED_PADDR PG_L2_BASE_PADDR -#define PG_L2_LOCKED_VADDR PG_L2_BASE_VADDR +#define PG_L2_LOCKED_PADDR PGTABLE_L2_BASE_PADDR +#define PG_L2_LOCKED_VADDR PGTABLE_L2_BASE_VADDR #define PG_L2_LOCKED_SIZE (4*CONFIG_PAGING_NLOCKED) /* We position the paged region PTEs immediately after the locked @@ -145,9 +135,9 @@ #define PG_L1_PAGED_PADDR (PGTABLE_BASE_PADDR + ((PG_PAGED_VBASE >> 20) << 2)) #define PG_L1_PAGED_VADDR (PGTABLE_BASE_VADDR + ((PG_PAGED_VBASE >> 20) << 2)) -#define PG_L2_PAGED_PADDR (PG_L2_BASE_PADDR + PG_L2_LOCKED_SIZE) -#define PG_L2_PAGED_VADDR (PG_L2_BASE_VADDR + PG_L2_LOCKED_SIZE) -#define PG_L2_PAGED_SIZE (4*CONFIG_PAGING_NVPAGED) +#define PG_L2_PAGED_PADDR (PGTABLE_L2_BASE_PADDR + PG_L2_LOCKED_SIZE) +#define PG_L2_PAGED_VADDR (PGTABLE_L2_BASE_VADDR + PG_L2_LOCKED_SIZE) +#define PG_L2_PAGED_SIZE (4*CONFIG_PAGING_NVPAGED) /* This describes the overall text region */ @@ -161,8 +151,8 @@ #define PG_L1_DATA_PADDR (PGTABLE_BASE_PADDR + ((PG_DATA_VBASE >> 20) << 2)) #define PG_L1_DATA_VADDR (PGTABLE_BASE_VADDR + ((PG_DATA_VBASE >> 20) << 2)) -#define PG_L2_DATA_PADDR (PG_L2_BASE_PADDR + PG_L2_TEXT_SIZE) -#define PG_L2_DATA_VADDR (PG_L2_BASE_VADDR + PG_L2_TEXT_SIZE) +#define PG_L2_DATA_PADDR (PGTABLE_L2_BASE_PADDR + PG_L2_TEXT_SIZE) +#define PG_L2_DATA_VADDR (PGTABLE_L2_BASE_VADDR + PG_L2_TEXT_SIZE) #define PG_L2_DATA_SIZE (4*PG_DATA_NPAGES) /* Page Table Info: The number of pages in the in the page table @@ -311,7 +301,7 @@ * written. This macro is used when CONFIG_PAGING is enable. This case, * it is used asfollows: * - * ldr r0, =PG_L2_BASE_PADDR <-- Address in L2 table + * ldr r0, =PGTABLE_L2_BASE_PADDR <-- Address in L2 table * ldr r1, =PG_LOCKED_PBASE <-- Physical page memory address * ldr r2, =CONFIG_PAGING_NLOCKED <-- number of pages * ldr r3, =MMUFLAGS <-- L2 MMU flags diff --git a/nuttx/arch/arm/src/dm320/dm320_boot.c b/nuttx/arch/arm/src/dm320/dm320_boot.c index be541d1c65..7757ddab15 100644 --- a/nuttx/arch/arm/src/dm320/dm320_boot.c +++ b/nuttx/arch/arm/src/dm320/dm320_boot.c @@ -173,19 +173,15 @@ static void up_vectormapping(void) while (vector_paddr < end_paddr) { - up_setlevel2coarseentry(PGTABLE_COARSE_BASE_VADDR, - vector_paddr, - vector_vaddr, - MMU_L2_VECTORFLAGS); + up_setlevel2coarseentry(PGTABLE_L2_BASE_VADDR, vector_paddr, vector_vaddr, + MMU_L2_VECTORFLAGS); vector_paddr += 4096; vector_vaddr += 4096; } /* Now set the level 1 descriptor to refer to the level 2 coarse page table. */ - up_setlevel1entry(PGTABLE_COARSE_BASE_PADDR, - DM320_VECTOR_VCOARSE, - MMU_L1_VECTORFLAGS); + up_setlevel1entry(PGTABLE_L2_BASE_PADDR, DM320_VECTOR_VCOARSE, MMU_L1_VECTORFLAGS); } /************************************************************************************ diff --git a/nuttx/arch/arm/src/dm320/dm320_memorymap.h b/nuttx/arch/arm/src/dm320/dm320_memorymap.h index 1f1e49d437..e673bc1b62 100644 --- a/nuttx/arch/arm/src/dm320/dm320_memorymap.h +++ b/nuttx/arch/arm/src/dm320/dm320_memorymap.h @@ -42,6 +42,8 @@ #include <nuttx/config.h> +#include "arm.h" + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ @@ -168,23 +170,25 @@ * page table for the virtual mappings. A portion of this table is * not accessible in the virtual address space (for normal operation). * We will reuse this memory for coarse page tables as follows: + * FIXME! Where does that 0x00000800 come from. I can't remember + * and it does not feel right! */ #define PGTABLE_BASE_PADDR DM320_SDRAM_PADDR #define PGTABLE_SDRAM_PADDR PGTABLE_BASE_PADDR -#define PGTABLE_COARSE_BASE_PADDR (PGTABLE_BASE_PADDR+0x00000800) -#define PGTABLE_COARSE_END_PADDR (PGTABLE_BASE_PADDR+0x00004000) -#define PGTABLE_END_PADDR (PGTABLE_BASE_PADDR+0x00004000) +#define PGTABLE_L2_BASE_PADDR (PGTABLE_BASE_PADDR+0x00000800) +#define PGTABLE_L2_END_PADDR (PGTABLE_BASE_PADDR+PGTABLE_SIZE) #define PGTABLE_BASE_VADDR DM320_SDRAM_VADDR #define PGTABLE_SDRAM_VADDR PGTABLE_BASE_VADDR -#define PGTABLE_COARSE_BASE_VADDR (PGTABLE_BASE_VADDR+0x00000800) -#define PGTABLE_COARSE_END_VADDR (PGTABLE_BASE_VADDR+0x00004000) -#define PGTABLE_END_VADDR (PGTABLE_BASE_VADDR+0x00004000) +#define PGTABLE_L2_BASE_VADDR (PGTABLE_BASE_VADDR+0x00000800) +#define PGTABLE_L2_END_VADDR (PGTABLE_BASE_VADDR+PGTABLE_SIZE) +#define PGTABLE_L2_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_BASE_VADDR) #define PGTABLE_COARSE_TABLE_SIZE (4*256) -#define PGTABLE_COARSE_ALLOC (PGTABLE_COARSE_END_VADDR-PGTABLE_COARSE_BASE_VADDR) -#define PGTABLE_NCOARSE_TABLES (PGTABLE_COARSE_SIZE / PGTBALE_COARSE_TABLE_ALLOC) +#define PGTABLE_NCOARSE_TABLES (PGTABLE_L2_ALLOC / PGTABLE_COARSE_TABLE_SIZE) +#define PGTABLE_FINE_TABLE_SIZE (4*1024) +#define PGTABLE_NFINE_TABLES (PGTABLE_L2_ALLOC / PGTABLE_FINE_TABLE_SIZE) /* This is the base address of the interrupt vectors on the ARM926 */ diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_allocateheap.c b/nuttx/arch/arm/src/lpc313x/lpc313x_allocateheap.c index f87d67ab6e..e6b587fd36 100755 --- a/nuttx/arch/arm/src/lpc313x/lpc313x_allocateheap.c +++ b/nuttx/arch/arm/src/lpc313x/lpc313x_allocateheap.c @@ -1,7 +1,7 @@ /************************************************************************ * arch/arm/src/lpc313x/lpc313x_allocateheap.c * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <spudmonkey@racsa.co.cr> * * Redistribution and use in source and binary forms, with or without @@ -45,6 +45,7 @@ #include <nuttx/arch.h> #include <arch/board/board.h> +#include "arm.h" #include "chip.h" #include "up_arch.h" #include "up_internal.h" @@ -110,6 +111,22 @@ # endif #endif +/* The following determines the end+1 address the heap (in SRAM0 or SRAM1) + * and that, in turn, determines the size of the heap. Specifically, this + * logic it checks if a page table has been allocated at the end of SRAM + * and, if so, subtracts that the size of the page table from the end+1 + * address of heap. + * + * If the page table was not allocated at the end of SRAM, then this logic + * will let the heap run all the way to the end of SRAM. + */ + +#ifdef PGTABLE_IN_HIGHSRAM +# define LPC313X_HEAP_VEND (LPC313X_INTSRAM_VSECTION + LPC313X_ISRAM_SIZE - PGTABLE_SIZE) +#else +# define LPC313X_HEAP_VEND (LPC313X_INTSRAM_VSECTION + LPC313X_ISRAM_SIZE) +#endif + /************************************************************************ * Private Data ************************************************************************/ @@ -146,7 +163,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { up_ledon(LED_HEAPALLOCATE); *heap_start = (FAR void*)g_heapbase; - *heap_size = (LPC313X_INTSRAM_VSECTION + LPC313X_ISRAM_SIZE) - g_heapbase; + *heap_size = LPC313X_HEAP_VEND - g_heapbase; } /************************************************************************ diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_boot.c b/nuttx/arch/arm/src/lpc313x/lpc313x_boot.c index 09176cedd2..81f5e5c440 100755 --- a/nuttx/arch/arm/src/lpc313x/lpc313x_boot.c +++ b/nuttx/arch/arm/src/lpc313x/lpc313x_boot.c @@ -275,7 +275,7 @@ static void up_vectormapping(void) while (vector_paddr < end_paddr) { - up_setlevel2coarseentry(PGTABLE_COARSE_BASE_VADDR, vector_paddr, + up_setlevel2coarseentry(PGTABLE_L2_BASE_VADDR, vector_paddr, vector_vaddr, MMU_L2_VECTORFLAGS); vector_paddr += 4096; vector_vaddr += 4096; @@ -283,7 +283,7 @@ static void up_vectormapping(void) /* Now set the level 1 descriptor to refer to the level 2 coarse page table. */ - up_setlevel1entry(PGTABLE_COARSE_BASE_PADDR, LPC313X_VECTOR_VCOARSE, + up_setlevel1entry(PGTABLE_L2_BASE_PADDR, LPC313X_VECTOR_VCOARSE, MMU_L1_VECTORFLAGS); } #endif diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_memorymap.h b/nuttx/arch/arm/src/lpc313x/lpc313x_memorymap.h index 0ecb3bb980..57d1404a71 100755 --- a/nuttx/arch/arm/src/lpc313x/lpc313x_memorymap.h +++ b/nuttx/arch/arm/src/lpc313x/lpc313x_memorymap.h @@ -263,12 +263,15 @@ * CONFIG_PGTABLE_VADDR and CONFIG_PGTABLE_PADDR in the configuration or board.h file. */ +#undef PGTABLE_IN_HIGHSRAM +#undef PGTABLE_IN_LOWSRAM + #if !defined(PGTABLE_BASE_PADDR) || !defined(PGTABLE_BASE_VADDR) /* Sanity check.. if one is undefined, both should be undefined */ # if defined(PGTABLE_BASE_PADDR) || defined(PGTABLE_BASE_VADDR) -# error "One of PGTABLE_BASE_PADDR or PGTABLE_BASE_VADDR is defined" +# error "Only one of PGTABLE_BASE_PADDR or PGTABLE_BASE_VADDR is defined" # endif /* A sanity check, if the configuration says that the page table is read-only @@ -290,15 +293,14 @@ * table must lie at the top 16Kb of ISRAM1 (or ISRAM0 if this is a LPC3130) */ -# ifndef PGTABLE_BASE_VADDR -# if CONFIG_ARCH_CHIP_LPC3131 +# if CONFIG_ARCH_CHIP_LPC3131 # define PGTABLE_BASE_PADDR (LPC313X_INTSRAM1_PADDR+LPC313X_INTSRAM1_SIZE-PGTABLE_SIZE) # define PGTABLE_BASE_VADDR (LPC313X_INTSRAM1_VADDR+LPC313X_INTSRAM1_SIZE-PGTABLE_SIZE) -# else +# else # define PGTABLE_BASE_PADDR (LPC313X_INTSRAM0_PADDR+LPC313X_INTSRAM0_SIZE-PGTABLE_SIZE) # define PGTABLE_BASE_VADDR (LPC313X_INTSRAM0_VADDR+LPC313X_INTSRAM0_SIZE-PGTABLE_SIZE) -# endif # endif +# define PGTABLE_IN_HIGHSRAM 1 # else /* Otherwise, ISRAM1 (or ISRAM0 for the LPC3130) will be mapped so that @@ -307,8 +309,9 @@ * the shadow memory region. */ -# define PGTABLE_BASE_PADDR LPC313X_SHADOWSPACE_PSECTION -# define PGTABLE_BASE_VADDR LPC313X_SHADOWSPACE_VSECTION +# define PGTABLE_BASE_PADDR LPC313X_SHADOWSPACE_PSECTION +# define PGTABLE_BASE_VADDR LPC313X_SHADOWSPACE_VSECTION +# define PGTABLE_IN_LOWSRAM 1 # endif # endif #endif @@ -318,19 +321,17 @@ * normal operation). We will reuse this memory for coarse page tables as follows: */ -#define PGTABLE_COARSE_POFFSET ((LPC313X_LAST_PSECTION >> 20) << 2) -#define PGTABLE_COARSE_BASE_PADDR (PGTABLE_BASE_PADDR+PGTABLE_COARSE_POFFSET) -#define PGTABLE_COARSE_END_PADDR (PGTABLE_BASE_PADDR+0x00004000) -#define PGTABLE_END_PADDR (PGTABLE_BASE_PADDR+0x00004000) - -#define PGTABLE_COARSE_VOFFSET ((LPC313X_LAST_VSECTION >>20) << 2) -#define PGTABLE_COARSE_BASE_VADDR (PGTABLE_BASE_VADDR+PGTABLE_COARSE_VOFFSET) -#define PGTABLE_COARSE_END_VADDR (PGTABLE_BASE_VADDR+0x00004000) -#define PGTABLE_END_VADDR (PGTABLE_BASE_VADDR+0x00004000) +#define PGTABLE_L2_OFFSET ((LPC313X_LAST_PSECTION >> 20) << 2) +#define PGTABLE_L2_BASE_PADDR (PGTABLE_BASE_PADDR+PGTABLE_L2_OFFSET) +#define PGTABLE_L2_END_PADDR (PGTABLE_BASE_PADDR+PGTABLE_SIZE) +#define PGTABLE_L2_BASE_VADDR (PGTABLE_BASE_VADDR+PGTABLE_L2_OFFSET) +#define PGTABLE_L2_END_VADDR (PGTABLE_BASE_VADDR+PGTABLE_SIZE) +#define PGTABLE_L2_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_BASE_VADDR) #define PGTABLE_COARSE_TABLE_SIZE (4*256) -#define PGTABLE_COARSE_ALLOC (PGTABLE_COARSE_END_VADDR-PGTABLE_COARSE_BASE_VADDR) -#define PGTABLE_NCOARSE_TABLES (PGTABLE_COARSE_SIZE / PGTBALE_COARSE_TABLE_ALLOC) +#define PGTABLE_NCOARSE_TABLES (PGTABLE_L2_ALLOC / PGTABLE_COARSE_TABLE_SIZE) +#define PGTABLE_FINE_TABLE_SIZE (4*1024) +#define PGTABLE_NFINE_TABLES (PGTABLE_L2_ALLOC / PGTABLE_FINE_TABLE_SIZE) /* Determine the base address of the vector table: * diff --git a/nuttx/configs/ea3131/pgnsh/defconfig b/nuttx/configs/ea3131/pgnsh/defconfig index 3dcd7f667a..696b5f310a 100755 --- a/nuttx/configs/ea3131/pgnsh/defconfig +++ b/nuttx/configs/ea3131/pgnsh/defconfig @@ -399,13 +399,13 @@ CONFIG_SIG_SIGWORK=4 # page table entry to use for the vector mapping. # CONFIG_PAGING=y -CONFIG_PAGING_PAGESIZE=4096 -CONFIG_PAGING_NLOCKED=8 +CONFIG_PAGING_PAGESIZE=1024 +CONFIG_PAGING_NLOCKED=36 #CONFIG_PAGING_LOCKED_PBASE #CONFIG_PAGING_LOCKED_VBASE -CONFIG_PAGING_NPPAGED=24 -CONFIG_PAGING_NVPAGED=96 -CONFIG_PAGING_NDATA=12 +CONFIG_PAGING_NPPAGED=96 +CONFIG_PAGING_NVPAGED=384 +CONFIG_PAGING_NDATA=44 #CONFIG_PAGING_DEFPRIO CONFIG_PAGING_STACKSIZE=2048 CONFIG_PAGING_BLOCKINGFILL=y diff --git a/nuttx/include/nuttx/page.h b/nuttx/include/nuttx/page.h index 15b8bbcd92..9ca88a0506 100755 --- a/nuttx/include/nuttx/page.h +++ b/nuttx/include/nuttx/page.h @@ -94,9 +94,11 @@ * * NOTE: In some architectures, it may be necessary to take some memory * from the beginning of this region for vectors or for a page table. - * In such cases, CONFIG_PAGING_LOCKED_P/VBASE should take that into - * consideration to prevent overlapping the locked memory region and the - * system data at the beginning of SRAM. + * In such cases, either (1) CONFIG_PAGING_LOCKED_P/VBASE might take that + * into consideration to prevent overlapping the locked memory region + * and the system data at the beginning of SRAM, (2) you extend CONFIG_PAGING_NLOCKED + * include these pages at the beginning of memory and map let them be + * mapped read-only. */ #if defined(CONFIG_PAGING_LOCKED_PBASE) && defined(CONFIG_PAGING_LOCKED_VBASE) |