Corrections for LP17xx UARTs and Nucleus 2G

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4331 7fd9a85b-ad96-42d3-883c-3090e2eb8679

3 files changed, 61 insertions, 0 deletions

diff --git a/nuttx/configs/nucleus2g/tools/olimex-tiny.cfg b/nuttx/configs/nucleus2g/tools/olimex-tiny.cfg
new file mode 100644
index 0000000000..03d3ac6bc0
--- /dev/null
+++ b/nuttx/configs/nucleus2g/tools/olimex-tiny.cfg
@@ -0,0 +1,61 @@
+#daemon configuration
+telnet_port 4444
+gdb_port 3333
+
+#interface
+interface ft2232
+ft2232_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
+ft2232_layout "olimex-jtag"
+ft2232_vid_pid 0x15ba 0x002a
+
+# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, clocked with 4MHz internal RC oscillator
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME lpc1768
+}
+
+if { [info exists ENDIAN] } {
+	set  _ENDIAN $ENDIAN
+} else {
+	set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x4ba00477
+}
+
+#delays on reset lines
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+# LPC2000 & LPC1700 -> SRST causes TRST
+reset_config trst_and_srst srst_pulls_trst
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0
+
+# REVISIT is there any good reason to have this reset-init event handler??
+# Normally they should set up (board-specific) clocking then probe the flash...
+$_TARGETNAME configure -event reset-init {
+	# Force NVIC.VTOR to point to flash at 0 ...
+	# WHY?  This is it's reset value; we run right after reset!!
+	mwb 0xE000ED08 0x00
+}
+
+# LPC1768 has 512kB of user-available FLASH (bootloader is located in separate dedicated region).
+# flash bank lpc1700 <base> <size> 0 0 <target#> <variant> <cclk> [calc_checksum]
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 80000 calc_checksum
+
+# 4MHz / 6 = 666kHz, so use 500
+jtag_khz 500
diff --git a/nuttx/configs/nucleus2g/tools/olimex.cfg b/nuttx/configs/nucleus2g/tools/olimex.cfg
index 8183ffd922..8183ffd922 100755..100644
--- a/nuttx/configs/nucleus2g/tools/olimex.cfg
+++ b/nuttx/configs/nucleus2g/tools/olimex.cfg
diff --git a/nuttx/configs/nucleus2g/tools/scarab.cfg b/nuttx/configs/nucleus2g/tools/scarab.cfg
index a94c6071a2..a94c6071a2 100755..100644
--- a/nuttx/configs/nucleus2g/tools/scarab.cfg
+++ b/nuttx/configs/nucleus2g/tools/scarab.cfg