Add clock initialization logic for the Nucleus2g boad

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@2741 7fd9a85b-ad96-42d3-883c-3090e2eb8679

1 files changed, 69 insertions, 0 deletions

diff --git a/nuttx/configs/nucleus2g/include/board.h b/nuttx/configs/nucleus2g/include/board.h
index b10b7c4bd0..edbc1bacc1 100755
--- a/nuttx/configs/nucleus2g/include/board.h
+++ b/nuttx/configs/nucleus2g/include/board.h
@@ -48,9 +48,78 @@
  ************************************************************************************/
 
 /* Clocking *************************************************************************/
+/* NOTE:  The following definitions require lpc17_syscon.h.  It is not included here
+ * because the including C file may not have that file in its include path.
+ */
+
+#define BOARD_XTAL_FREQUENCY        (12000000)            /* XTAL oscillator frequency */
+#define BOARD_OSCCLK_FREQUENCY      BOARD_XTAL_FREQUENCY  /* Main oscillator frequency */
+#define BOARD_RTCCLK_FREQUENCY      (32000)               /* RTC oscillator frequency */
+#define BOARD_INTRCOSC_FREQUENCY    (4000000)             /* Internal RC oscillator frequency */
+
+/* This is the clock setup we configure for:
+ *
+ *   SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz  -> Select Main oscillator for source
+ *   PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multipler=20, pre-divider=1
+ *   CCLCK = 480MHz / 6 = 80MHz               -> CCLK divider = 6
+ */
 
 #define LPC17_CCLK                 80000000 /* 80Mhz*/
 
+/* Select the main oscillator as the frequency source.  SYSCLK is then the frequency
+ * of the main osciallator.
+ */
+
+#undef CONFIG_LPC17_MAINOSC
+#define CONFIG_LPC17_MAINOSC 1
+#define BOARD_SCS_VALUE            SYSCON_SCS_OSCEN
+
+/* Select the main oscillator and CCLK divider. The output of the divider is CCLK.
+ * The input to the divider (PLLCLK) will be determined by the PLL output.
+ */
+
+#define BOARD_CCLKCFG_DIVIDER      6
+#define BOARD_CCLKCFG_VALUE        ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_SHIFT)
+
+/* PLL0.  PLL0 is used to generate the CPU clock divider input (PLLCLK).
+ *
+ *  Source clock:               Main oscillator
+ *  PLL0 Multiplier value (M):  20 
+ *  PLL0 Pre-divider value (N): 1
+ */
+
+#undef CONFIG_LPC17_PLL0
+#define CONFIG_LPC17_PLL0 1
+#define BOARD_CLKSRCSEL_VALUE      SYSCON_CLKSRCSEL_MAIN
+
+#define BOARD_PLL0CFG_MSEL         20
+#define BOARD_PLL0CFG_NSEL         1
+#define BOARD_PLL0CFG_VALUE \
+  (((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLL0CFG_MSEL_SHIFT) | \
+   ((BOARD_PLL0CFG_NSEL-1) << SYSCON_PLL0CFG_NSEL_SHIFT))
+
+/* PLL1 -- Not used. */
+
+#undef CONFIG_LPC17_PLL0
+#define BOARD_PLL1CFG_MSEL         36
+#define BOARD_PLL1CFG_NSEL         1
+#define BOARD_PLL1CFG_VALUE \
+  (((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLL1CFG_MSEL_SHIFT) | \
+   ((BOARD_PLL1CFG_NSEL-1) << SYSCON_PLL1CFG_NSEL_SHIFT))
+
+/* USB divider.  This divder is used when PLL1 is not enabled to get the USB clock
+ * from PLL0:
+ *
+ *  USBCLK = PLL0CLK / 10 = 48MHz
+ */
+
+#define BOARD_USBCLKCFG_VALUE      SYSCON_USBCLKCFG_DIV10
+
+/* FLASH Configuration */
+
+#undef  CONFIG_LP17_FLASH
+#define CONFIG_LP17_FLASH          1
+#define BOARD_FLASHCFG_VALUE       0x0000303a
 
 /* LED definitions ******************************************************************/