More PIC32 header files

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@3611 7fd9a85b-ad96-42d3-883c-3090e2eb8679

5 files changed, 459 insertions, 84 deletions

diff --git a/nuttx/arch/mips/arch.h b/nuttx/arch/mips/arch.h
deleted file mode 100644
index 389e5689a8..0000000000
--- a/nuttx/arch/mips/arch.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/****************************************************************************
- * arch/avr/include/arch.h
- *
- *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* This file should never be included directed but, rather,
- * only indirectly through nuttx/arch.h
- */
-
-#ifndef __ARCH_AVR_INCLUDE_ARCH_H
-#define __ARCH_AVR_INCLUDE_ARCH_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-/****************************************************************************
- * Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Public Variables
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ARCH_AVR_INCLUDE_ARCH_H */
-
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-i2c.h b/nuttx/arch/mips/src/pic32mx/pic32mx-i2c.h
new file mode 100755
index 0000000000..ad20c2bf03
--- /dev/null
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-i2c.h
@@ -0,0 +1,216 @@
+/************************************************************************************

+ * arch/mips/src/pic32mx/pic32mx-i2c.h

+ *

+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.

+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>

+ *

+ * Redistribution and use in source and binary forms, with or without

+ * modification, are permitted provided that the following conditions

+ * are met:

+ *

+ * 1. Redistributions of source code must retain the above copyright

+ *    notice, this list of conditions and the following disclaimer.

+ * 2. Redistributions in binary form must reproduce the above copyright

+ *    notice, this list of conditions and the following disclaimer in

+ *    the documentation and/or other materials provided with the

+ *    distribution.

+ * 3. Neither the name NuttX nor the names of its contributors may be

+ *    used to endorse or promote products derived from this software

+ *    without specific prior written permission.

+ *

+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,

+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,

+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS

+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED

+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN

+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+ * POSSIBILITY OF SUCH DAMAGE.

+ *

+ ************************************************************************************/

+

+#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_I2C_H

+#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_I2C_H

+

+/************************************************************************************

+ * Included Files

+ ************************************************************************************/

+

+#include <nuttx/config.h>

+

+#include "pic32mx-memorymap.h"

+

+/************************************************************************************

+ * Pre-Processor Definitions

+ ************************************************************************************/

+/* Register Offsets *****************************************************************/

+

+#define PIC32MX_I2C_CON_OFFSET     0x0000 /* I2C control register */

+#define PIC32MX_I2C_CONCLR_OFFSET  0x0004 /* I2C control clear register */

+#define PIC32MX_I2C_CONSET_OFFSET  0x0008 /* I2C control set register */

+#define PIC32MX_I2C_CONINV_OFFSET  0x000c /* I2C control invert register */

+#define PIC32MX_I2C_STAT_OFFSET    0x0010 /* I2C status register */

+#define PIC32MX_I2C_STATCLR_OFFSET 0x0014 /* I2C status clear register */

+#define PIC32MX_I2C_STATSET_OFFSET 0x0018 /* I2C status set register */

+#define PIC32MX_I2C_STATINV_OFFSET 0x001c /* I2C status invert register */

+#define PIC32MX_I2C_ADD_OFFSET     0x0020 /* I2C address register */

+#define PIC32MX_I2C_ADDCLR_OFFSET  0x0024 /* I2C address clear register */

+#define PIC32MX_I2C_ADDSET_OFFSET  0x0028 /* I2C address set register */

+#define PIC32MX_I2C_ADDINV_OFFSET  0x002c /* I2C address invert register */

+#define PIC32MX_I2C_MSK_OFFSET     0x0030 /* I2C address mask register */

+#define PIC32MX_I2C_MSKCLR_OFFSET  0x0034 /* I2C address mask clear register */

+#define PIC32MX_I2C_MSKSET_OFFSET  0x0038 /* I2C address mask set register */

+#define PIC32MX_I2C_MSKINV_OFFSET  0x003c /* I2C address mask invert register */

+#define PIC32MX_I2C_BRG_OFFSET     0x0040 /* Baud rate generator reload register */

+#define PIC32MX_I2C_BRGSET_OFFSET  0x0044 /* Baud rate generator reload clear register */

+#define PIC32MX_I2C_BRGCLR_OFFSET  0x0048 /* Baud rate generator reload set register */

+#define PIC32MX_I2C_BRGINV_OFFSET  0x004c /* Baud rate generator reload invert register */

+#define PIC32MX_I2C_TRN_OFFSET     0x0050 /* I2C transmit register */

+#define PIC32MX_I2C_TRNCLR_OFFSET  0x0054 /* I2C transmit clear register */

+#define PIC32MX_I2C_TRNSET_OFFSET  0x0058 /* I2C transmit set register */

+#define PIC32MX_I2C_TRNINV_OFFSET  0x005c /* I2C transmit invert register */

+#define PIC32MX_I2C_RCV_OFFSET     0x0060 /* I2C receive buffer register */

+

+/* Register Addresses ***************************************************************/

+

+#define PIC32MX_I2C1_CON           (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CON_OFFSET)

+#define PIC32MX_I2C1_CONCLR        (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CONCLR_OFFSET)

+#define PIC32MX_I2C1_CONSET        (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CONSET_OFFSET)

+#define PIC32MX_I2C1_CONINV        (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CONINV_OFFSET)

+#define PIC32MX_I2C1_STAT          (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STAT_OFFSET)

+#define PIC32MX_I2C1_STATCLR       (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STATCLR_OFFSET)

+#define PIC32MX_I2C1_STATSET       (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STATSET_OFFSET)

+#define PIC32MX_I2C1_STATINV       (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STATINV_OFFSET)

+#define PIC32MX_I2C1_ADD           (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADD_OFFSET)

+#define PIC32MX_I2C1_ADDCLR        (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET)

+#define PIC32MX_I2C1_ADDSET        (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADDSET_OFFSET)

+#define PIC32MX_I2C1_ADDINV        (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADDINV_OFFSET)

+#define PIC32MX_I2C1_MSK           (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSK_OFFSET)

+#define PIC32MX_I2C1_MSKCLR        (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET)

+#define PIC32MX_I2C1_MSKSET        (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSKSET_OFFSET)

+#define PIC32MX_I2C1_MSKINV        (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSKINV_OFFSET)

+#define PIC32MX_I2C1_BRG           (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRG_OFFSET)

+#define PIC32MX_I2C1_BRGSET        (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRGSET_OFFSET)

+#define PIC32MX_I2C1_BRGCLR        (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET)

+#define PIC32MX_I2C1_BRGINV        (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRGINV_OFFSET)

+#define PIC32MX_I2C1_TRN           (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRN_OFFSET)

+#define PIC32MX_I2C1_TRNCLR        (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET)

+#define PIC32MX_I2C1_TRNSET        (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRNSET_OFFSET)

+#define PIC32MX_I2C1_TRNINV        (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRNINV_OFFSET)

+#define PIC32MX_I2C1_RCV           (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_RCV_OFFSET)

+

+#define PIC32MX_I2C2_CON           (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CON_OFFSET)

+#define PIC32MX_I2C2_CONCLR        (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CONCLR_OFFSET)

+#define PIC32MX_I2C2_CONSET        (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CONSET_OFFSET)

+#define PIC32MX_I2C2_CONINV        (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CONINV_OFFSET)

+#define PIC32MX_I2C2_STAT          (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STAT_OFFSET)

+#define PIC32MX_I2C2_STATCLR       (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STATCLR_OFFSET)

+#define PIC32MX_I2C2_STATSET       (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STATSET_OFFSET)

+#define PIC32MX_I2C2_STATINV       (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STATINV_OFFSET)

+#define PIC32MX_I2C2_ADD           (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADD_OFFSET)

+#define PIC32MX_I2C2_ADDCLR        (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET)

+#define PIC32MX_I2C2_ADDSET        (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADDSET_OFFSET)

+#define PIC32MX_I2C2_ADDINV        (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADDINV_OFFSET)

+#define PIC32MX_I2C2_MSK           (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSK_OFFSET)

+#define PIC32MX_I2C2_MSKCLR        (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET)

+#define PIC32MX_I2C2_MSKSET        (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSKSET_OFFSET)

+#define PIC32MX_I2C2_MSKINV        (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSKINV_OFFSET)

+#define PIC32MX_I2C2_BRG           (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRG_OFFSET)

+#define PIC32MX_I2C2_BRGSET        (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRGSET_OFFSET)

+#define PIC32MX_I2C2_BRGCLR        (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET)

+#define PIC32MX_I2C2_BRGINV        (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRGINV_OFFSET)

+#define PIC32MX_I2C2_TRN           (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRN_OFFSET)

+#define PIC32MX_I2C2_TRNCLR        (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET)

+#define PIC32MX_I2C2_TRNSET        (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRNSET_OFFSET)

+#define PIC32MX_I2C2_TRNINV        (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRNINV_OFFSET)

+#define PIC32MX_I2C2_RCV           (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_RCV_OFFSET)

+

+/* Register Bit-Field Definitions ***************************************************/

+

+/* I2C control register */

+

+#define I2C_CON_SEN                (1 << 0)  /* Bit 0:   Start condition enable */

+#define I2C_CON_RSEN               (1 << 1)  /* Bit 1:   Restart condition enable */

+#define I2C_CON_PEN                (1 << 2)  /* Bit 2:   Stop condition enable */

+#define I2C_CON_RCEN               (1 << 3)  /* Bit 3:   Receive enable */

+#define I2C_CON_ACKEN              (1 << 4)  /* Bit 4:   Acknowledge sequence enable */

+#define I2C_CON_ACKDT              (1 << 5)  /* Bit 5:   Acknowledge data */

+#define I2C_CON_STREN              (1 << 6)  /* Bit 6:   SCL clock stretch enable */

+#define I2C_CON_GCEN               (1 << 7)  /* Bit 7:   General call enable */

+#define I2C_CON_SMEN               (1 << 8)  /* Bit 8:   SMBus input levels disable */

+#define I2C_CON_DISSLW             (1 << 9)  /* Bit 9:   Slew rate control disable */

+#define I2C_CON_A10M               (1 << 10) /* Bit 10:  10-bit slave addrewss flag */

+#define I2C_CON_STRICT             (1 << 11) /* Bit 11:  Strict I2C reserved address rules enable */

+#define I2C_CON_SCLREL             (1 << 12) /* Bit 12:  SCL release control */

+#define I2C_CON_SIDL               (1 << 13) /* Bit 13:  Stop in idle mode */

+#define I2C_CON_FRZ                (1 << 14) /* Bit 14:  Freeze in debug mode control */

+#define I2C_CON_ON                 (1 << 15) /* Bit 15:  I2C enable */

+

+/* I2C status register */

+

+#define I2C_STAT_TBF               (1 << 0)  /* Bit 0:  Transmit buffer full */

+#define I2C_STAT_RBF               (1 << 1)  /* Bit 1:  Receive buffer full */

+#define I2C_STAT_RW                (1 << 2)  /* Bit 2:  Read/write information */

+#define I2C_STAT_S                 (1 << 3)  /* Bit 3:  Start */

+#define I2C_STAT_P                 (1 << 4)  /* Bit 4:  Stop */

+#define I2C_STAT_DA                (1 << 5)  /* Bit 5:  Data/address */

+#define I2C_STAT_I2COV             (1 << 6)  /* Bit 6:  I2C overflow status */

+#define I2C_STAT_IWCOL             (1 << 7)  /* Bit 7:  Write collision detect */

+#define I2C_STAT_ADD10             (1 << 8)  /* Bit 8:  10-bit address status */

+#define I2C_STAT_GCSTAT            (1 << 9)  /* Bit 9:  General call status */

+#define I2C_STAT_BCL               (1 << 10) /* Bit 10: Master bus collision detect */

+#define I2C_STAT_TRSTAT            (1 << 14) /* Bit 14: Transmit status */

+#define I2C_STAT_ACKSTAT           (1 << 15) /* Bit 15: Acknowledge status */

+

+/* I2C address register */

+

+#define I2C_ADD_MASK               0x3ff     /* 10-bit I2C address */

+

+/* I2C address mask register */

+

+#define I2C_MSK_MASK               0x3ff     /* 10-bit I2C address mask */

+

+/* Baud rate generator reload register */

+

+#define I2C_BRG_MASK               0xfff     /* 12-bit I2C BRG value */

+

+/* I2C transmit register */

+

+#define I2C_TRN_MASK               0xff      /* 8-bit transmit data */

+

+/* I2C receive buffer register */

+

+#define I2C_RCV_MASK               0xff      /* 8-bit receive data */

+

+/************************************************************************************

+ * Public Types

+ ************************************************************************************/

+

+#ifndef __ASSEMBLY__

+

+/************************************************************************************

+ * Inline Functions

+ ************************************************************************************/

+

+/************************************************************************************

+ * Public Function Prototypes

+ ************************************************************************************/

+

+#ifdef __cplusplus

+#define EXTERN extern "C"

+extern "C" {

+#else

+#define EXTERN extern

+#endif

+

+#undef EXTERN

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __ASSEMBLY__ */

+#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_I2C_H */

diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-memorymap.h b/nuttx/arch/mips/src/pic32mx/pic32mx-memorymap.h
index 2251bc1aac..ed981be002 100755
--- a/nuttx/arch/mips/src/pic32mx/pic32mx-memorymap.h
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-memorymap.h
@@ -123,7 +123,7 @@
 

 /* Parallel Master Register Base Address */

 

-#  define PCI32MX_PMSTR_K1BASE      (PIC32MX_SFR_K1BASE + 0x00007000)

+#  define PCI32MX_PMP_K1BASE        (PIC32MX_SFR_K1BASE + 0x00007000)

 

 /* ADC Register Base Addresses */

 

diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-pmp.h b/nuttx/arch/mips/src/pic32mx/pic32mx-pmp.h
new file mode 100755
index 0000000000..a68176bded
--- /dev/null
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-pmp.h
@@ -0,0 +1,241 @@
+/************************************************************************************

+ * arch/mips/src/pic32mx/pic32mx-pmp.h

+ *

+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.

+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>

+ *

+ * Redistribution and use in source and binary forms, with or without

+ * modification, are permitted provided that the following conditions

+ * are met:

+ *

+ * 1. Redistributions of source code must retain the above copyright

+ *    notice, this list of conditions and the following disclaimer.

+ * 2. Redistributions in binary form must reproduce the above copyright

+ *    notice, this list of conditions and the following disclaimer in

+ *    the documentation and/or other materials provided with the

+ *    distribution.

+ * 3. Neither the name NuttX nor the names of its contributors may be

+ *    used to endorse or promote products derived from this software

+ *    without specific prior written permission.

+ *

+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,

+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,

+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS

+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED

+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN

+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+ * POSSIBILITY OF SUCH DAMAGE.

+ *

+ ************************************************************************************/

+

+#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PMP_H

+#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PMP_H

+

+/************************************************************************************

+ * Included Files

+ ************************************************************************************/

+

+#include <nuttx/config.h>

+

+#include "pic32mx-memorymap.h"

+

+/************************************************************************************

+ * Pre-Processor Definitions

+ ************************************************************************************/

+/* Register Offsets *****************************************************************/

+

+#define PIC32MX_PMP_CON_OFFSET     0x0000 /* Parallel Port Control Register */

+#define PIC32MX_PMP_CONCLR_OFFSET  0x0000 /* Parallel Port Control Clear Register */

+#define PIC32MX_PMP_CONSET_OFFSET  0x0000 /* Parallel Port Control Set Register */

+#define PIC32MX_PMP_CONINV_OFFSET  0x0000 /* Parallel Port Control Invert Register */

+#define PIC32MX_PMP_MODE_OFFSET    0x0000 /* Parallel Port Mode Register */

+#define PIC32MX_PMP_MODECLR_OFFSET 0x0000 /* Parallel Port Mode Clear Register */

+#define PIC32MX_PMP_MODESET_OFFSET 0x0000 /* Parallel Port Mode Set Register */

+#define PIC32MX_PMP_MODEINV_OFFSET 0x0000 /* Parallel Port Mode Invert Register */

+#define PIC32MX_PMP_ADDR_OFFSET    0x0000 /* Parallel Port Address Register */

+#define PIC32MX_PMP_ADDRCLR_OFFSET 0x0000 /* Parallel Port Address Clear Register */

+#define PIC32MX_PMP_ADDRSET_OFFSET 0x0000 /* Parallel Port Address Set Register */

+#define PIC32MX_PMP_ADDRINV_OFFSET 0x0000 /* Parallel Port Address Invert Register */

+#define PIC32MX_PMP_DOUT_OFFSET    0x0000 /* Parallel Port Data Output Register */

+#define PIC32MX_PMP_DOUTCLR_OFFSET 0x0000 /* Parallel Port Data Output Clear Register */

+#define PIC32MX_PMP_DOUTSET_OFFSET 0x0000 /* Parallel Port Data Output Set Register */

+#define PIC32MX_PMP_DOUTINV_OFFSET 0x0000 /* Parallel Port Data Output Invert Register */

+#define PIC32MX_PMP_DIN_OFFSET     0x0000 /* Parallel Port Data Input Register */

+#define PIC32MX_PMP_DINCLR_OFFSET  0x0000 /* Parallel Port Data Input Clear Register */

+#define PIC32MX_PMP_DINSET_OFFSET  0x0000 /* Parallel Port Data Input Set Register */

+#define PIC32MX_PMP_DININV_OFFSET  0x0000 /* Parallel Port Data Input Invert Register */

+#define PIC32MX_PMP_AEN_OFFSET     0x0000 /* Parallel Port Pin Enable Register */

+#define PIC32MX_PMP_AENCLR_OFFSET  0x0000 /* Parallel Port Pin Enable Clear Register */

+#define PIC32MX_PMP_AENSET_OFFSET  0x0000 /* Parallel Port Pin Enable Set Register */

+#define PIC32MX_PMP_AENINV_OFFSET  0x0000 /* Parallel Port Pin Enable Invert Register */

+#define PIC32MX_PMP_STAT_OFFSET    0x0000 /* Parallel Port Status Register */

+#define PIC32MX_PMP_STATCLR_OFFSET 0x0000 /* Parallel Port Status Clear Register */

+#define PIC32MX_PMP_STATSET_OFFSET 0x0000 /* Parallel Port Status Set Register */

+#define PIC32MX_PMP_STATINV_OFFSET 0x0000 /* Parallel Port Status Invert Register */

+

+/* Register Addresses ***************************************************************/

+

+#define PIC32MX_PMP_CON            (PCI32MX_PMP_K1BASE+PIC32MX_PMP_CON_OFFSET)

+#define PIC32MX_PMP_CONCLR         (PCI32MX_PMP_K1BASE+PIC32MX_PMP_CONCLR_OFFSET)

+#define PIC32MX_PMP_CONSET         (PCI32MX_PMP_K1BASE+PIC32MX_PMP_CONSET_OFFSET)

+#define PIC32MX_PMP_CONINV         (PCI32MX_PMP_K1BASE+PIC32MX_PMP_CONINV_OFFSET)

+#define PIC32MX_PMP_MODE           (PCI32MX_PMP_K1BASE+PIC32MX_PMP_MODE_OFFSET)

+#define PIC32MX_PMP_MODECLR        (PCI32MX_PMP_K1BASE+PIC32MX_PMP_MODECLR_OFFSET)

+#define PIC32MX_PMP_MODESET        (PCI32MX_PMP_K1BASE+PIC32MX_PMP_MODESET_OFFSET)

+#define PIC32MX_PMP_MODEINV        (PCI32MX_PMP_K1BASE+PIC32MX_PMP_MODEINV_OFFSET)

+#define PIC32MX_PMP_ADDR           (PCI32MX_PMP_K1BASE+PIC32MX_PMP_ADDR_OFFSET)

+#define PIC32MX_PMP_ADDRCLR        (PCI32MX_PMP_K1BASE+PIC32MX_PMP_ADDRCLR_OFFSET)

+#define PIC32MX_PMP_ADDRSET        (PCI32MX_PMP_K1BASE+PIC32MX_PMP_ADDRSET_OFFSET)

+#define PIC32MX_PMP_ADDRINV        (PCI32MX_PMP_K1BASE+PIC32MX_PMP_ADDRINV_OFFSET)

+#define PIC32MX_PMP_DOUT           (PCI32MX_PMP_K1BASE+PIC32MX_PMP_DOUT_OFFSET)

+#define PIC32MX_PMP_DOUTCLR        (PCI32MX_PMP_K1BASE+PIC32MX_PMP_DOUTCLR_OFFSET)

+#define PIC32MX_PMP_DOUTSET        (PCI32MX_PMP_K1BASE+PIC32MX_PMP_DOUTSET_OFFSET)

+#define PIC32MX_PMP_DOUTINV        (PCI32MX_PMP_K1BASE+PIC32MX_PMP_DOUTINV_OFFSET)

+#define PIC32MX_PMP_DIN            (PCI32MX_PMP_K1BASE+PIC32MX_PMP_DIN_OFFSET)

+#define PIC32MX_PMP_DINCLR         (PCI32MX_PMP_K1BASE+PIC32MX_PMP_DINCLR_OFFSET)

+#define PIC32MX_PMP_DINSET         (PCI32MX_PMP_K1BASE+PIC32MX_PMP_DINSET_OFFSET)

+#define PIC32MX_PMP_DININV         (PCI32MX_PMP_K1BASE+PIC32MX_PMP_DININV_OFFSET)

+#define PIC32MX_PMP_AEN            (PCI32MX_PMP_K1BASE+PIC32MX_PMP_AEN_OFFSET)

+#define PIC32MX_PMP_AENCLR         (PCI32MX_PMP_K1BASE+PIC32MX_PMP_AENCLR_OFFSET)

+#define PIC32MX_PMP_AENSET         (PCI32MX_PMP_K1BASE+PIC32MX_PMP_AENSET_OFFSET)

+#define PIC32MX_PMP_AENINV         (PCI32MX_PMP_K1BASE+PIC32MX_PMP_AENINV_OFFSET)

+#define PIC32MX_PMP_STAT           (PCI32MX_PMP_K1BASE+PIC32MX_PMP_STAT_OFFSET)

+#define PIC32MX_PMP_STATCLR        (PCI32MX_PMP_K1BASE+PIC32MX_PMP_STATCLR_OFFSET)

+#define PIC32MX_PMP_STATSET        (PCI32MX_PMP_K1BASE+PIC32MX_PMP_STATSET_OFFSET)

+#define PIC32MX_PMP_STATINV        (PCI32MX_PMP_K1BASE+PIC32MX_PMP_STATINV_OFFSET)

+

+/* Register Bit-Field Definitions ***************************************************/

+

+/* Parallel Port Control Register */

+

+#define PMP_CON_RDSP               (1 << 0)  /* Bit 0:  Read strobe polarity */

+#define PMP_CON_WRSP               (1 << 1)  /* Bit 1:  Write strobe polarity */

+#define PMP_CON_CS1P               (1 << 3)  /* Bit 3:  Chip select 0 polarity */

+#define PMP_CON_CS2P               (1 << 4)  /* Bit 4:  Chip select 1 polarity */

+#define PMP_CON_ALP                (1 << 5)  /* Bit 5:  Address latch polarity */

+#define PMP_CON_CSF_SHIFT          (6)       /* Bits 6-7: Chip select function */

+#define PMP_CON_CSF_MASK           (3 << PMP_CON_CSF_SHIFT)

+#define PMP_CON_CSF_ADDR1415       (0 << PMP_CON_CSF_SHIFT) /* PMCS2/PMCS1 = address bits 15 and 14 */

+#define PMP_CON_CSF_CS2ADDR14      (1 << PMP_CON_CSF_SHIFT) /* PMCS2 = Chip Select, PMCS1 = address bit 14 */

+#define PMP_CON_CSF_CS12           (2 << PMP_CON_CSF_SHIFT) /* PMCS2/PMCS1 = Chip Select */

+#define PMP_CON_PTRDEN             (1 << 8)  /* Bit 8:  Read/write strobe port enable */

+#define PMP_CON_PTWREN             (1 << 9)  /* Bit 9:  Write enable strobe port enable */

+#define PMP_CON_PMPTTL             (1 << 10) /* Bit 10: PMP module TTL input buffer select */

+#define PMP_CON_ADRMUX_SHIFT       (11)      /* Bits 11-12: Address/data multiplexing selection */

+#define PMP_CON_ADRMUX_MASK        (3 << PMP_CON_ADRMUX_SHIFT)

+#  define PMP_CON_ADRMUX_NONE      (0 << PMP_CON_ADRMUX_SHIFT) /* Address and data appear separate */

+#  define PMP_CON_ADRMUX_BYTE      (1 << PMP_CON_ADRMUX_SHIFT) /* LS address are mux'ed on PMD 7:0 MS on PMA 15:8 */

+#  define PMP_CON_ADRMUX_MUX8      (2 << PMP_CON_ADRMUX_SHIFT) /* Address mux'ed on PMD 7:0 */

+#  define PMP_CON_ADRMUX_MUX16     (3 << PMP_CON_ADRMUX_SHIFT) /* Address mux'ed on PMD 15:0 */

+#define PMP_CON_SIDL               (1 << 13) /* Bit 13: Stop in idle mode */

+#define PMP_CON_FRZ                (1 << 14) /* Bit 14: Freeze in debug exception mode */

+#define PMP_CON_ON                 (1 << 15) /* Bit 15: Parallel master port enable */

+

+/* Parallel Port Mode Register */

+

+#define PMP_MODE_WAITE_SHIFT       (0)       /* Bits 0-1: Data hold after R/W strobe wait states */ 

+#define PMP_MODE_WAITE_MASK        (3 << PMP_MODE_WAITE_SHIFT)

+#  define PMP_MODE_WAITE_WR(n)     ((n-1) << PMP_MODE_WAITE_SHIFT) /* Wait of n TPB n=1..4 */

+#  define PMP_MODE_WAITE_RD(n)     ((n) << PMP_MODE_WAITE_SHIFT)   /* Wait of n TPB n=0..3 */

+#define PMP_MODE_WAITM_SHIFT       (2)       /* Bits 2-5: Data R/W strobe wait states */ 

+#define PMP_MODE_WAITM_MASK        (15 << PMP_MODE_WAITM_SHIFT)

+#  define PMP_MODE_WAITM(n)        ((n-1) << PMP_MODE_WAITM_SHIFT) /* Wait of n TPB n=1..16 */

+#define PMP_MODE_WAITB_SHIFT       (6)       /* Bits 6-7: Data setup to R/W strobe wait states */  

+#define PMP_MODE_WAITB_MASK        (3 << PMP_MODE_WAITB_SHIFT)

+#  define PMP_MODE_WAITB_1TPB      (0 << PMP_MODE_WAITB_SHIFT) /* Data wait of 1 TPB */

+#  define PMP_MODE_WAITB_2TPB      (1 << PMP_MODE_WAITB_SHIFT) /* Data wait of 2 TPB */

+#  define PMP_MODE_WAITB_3TPB      (2 << PMP_MODE_WAITB_SHIFT) /* Data wait of 3 TPB */

+#  define PMP_MODE_WAITB_4TPB      (3 << PMP_MODE_WAITB_SHIFT) /* Data wait of 4 TPB */

+#define PMP_MODE_MODE_SHIFT        (8)       /* Bits 8-9: Parallel port mode select */  

+#define PMP_MODE_MODE_MASK         (3 << PMP_MODE_MODE_SHIFT)

+#  define PMP_MODE_MODE_LEGACY     (0 << PMP_MODE_MODE_SHIFT) /* Legacy parallel slave port */

+#  define PMP_MODE_MODE_SLAVE      (1 << PMP_MODE_MODE_SHIFT) /* Enhanced slave mode */

+#  define PMP_MODE_MODE_MODE2      (2 << PMP_MODE_MODE_SHIFT) /* Master mode 2 */

+#  define PMP_MODE_MODE_MODE1      (3 << PMP_MODE_MODE_SHIFT) /* Master mode 1 */

+#define PMP_MODE_MODE16            (1 << 10) /* Bit 10: 8/16-bit mode */

+#define PMP_MODE_INCM_SHIFT        (11)      /* Bits 11-12: Increment Mode */ 

+#define PMP_MODE_INCM_MASK         (3 << PMP_MODE_INCM_MASK)

+#  define PMP_MODE_INCM_NONE       (0 << PMP_MODE_INCM_MASK) /* No incr or decr of addr */

+#  define PMP_MODE_INCM_INCR       (1 << PMP_MODE_INCM_MASK) /* Incr addr on R/W cycle */

+#  define PMP_MODE_INCM_DECR       (2 << PMP_MODE_INCM_MASK) /* Decr addr on R/Wcycle */

+#  define PMP_MODE_INCM_SLAVE      (3 << PMP_MODE_INCM_MASK) /* Slave mode auto-increment */

+#define PMP_MODE_IRQM_SHIFT        (13)      /* Bits 13-14: Interrupt request mode */ 

+#define PMP_MODE_IRQM_MASK         (3 << PMP_MODE_IRQM_SHIFT)

+#  define PMP_MODE_IRQM_NONE       (0 << PMP_MODE_IRQM_SHIFT) /* No Interrupt generated */

+#  define PMP_MODE_IRQM_RW         (1 << PMP_MODE_IRQM_SHIFT) /* Interrupt at end of R/W cycle */

+#  define PMP_MODE_IRQM_BUFFER     (2 << PMP_MODE_IRQM_SHIFT) /* R/W buffer 3 or write PMA=11 */

+#define PMP_MODE_BUSY              (1 << 15) /* Bit 15: Busy (master mode only) */

+

+/* Parallel Port Address Register */

+

+#define PMP_ADDR_ADDR_SHIFT        (0)       /* Bits 0-13: Destination address */ 

+#define PMP_ADDR_ADDR_MASK         (0x3fff << PMP_ADDR_ADDR_SHIFT)

+#define PMP_ADDR_CS1EN             (1 << 14) /* Bit 14: Chip select 1 */

+#define PMP_ADDR_CS2EN             (1 << 15) /* Bit 15: Chip select 2 */

+

+/* Parallel Port Data Output Register -- 32-bit data register */

+

+/* Parallel Port Data Input Register -- 32-bit data register */

+

+/* Parallel Port Pin Enable Register */

+

+#define PMP_AEN_PTEN_SHIFT         (0)       /* Bits 0-15: xx */

+#define PMP_AEN_PTEN_MASK          (0xffff << PMP_AEN_PTEN_SHIFT)

+

+#define PMP_AEN_PMCSEN_SHIFT       (14)      /* PTEN 14-15: PMCSx Strobe enable */

+#define PMP_AEN_PMCSEN_MASK        (3 << PMP_AEN_STROBEN_SHIFT)

+#define PMP_AEN_ADDR_SHIFT         (2)       /* PTEN 2-13: PMP address port enable */

+#define PMP_AEN_ADDR_MASK          (0xfff << PMP_AEN_STROBEN_SHIFT)

+#define PMP_AEN_PMALEN_SHIFT       (0)       /* PTEN 0-1: PMALH/PMALL strobe enable */

+#define PMP_AEN_PMALEN_MASK        (3 << PMP_AEN_STROBEN_SHIFT)

+

+/* Parallel Port Status Register */

+

+#define PMP_STAT_OBE(n)            (1 << (n))

+#define PMP_STAT_OB0E              (1 << 0)  /* Bit 0:  Output buffer 0 status empty bits */

+#define PMP_STAT_OB1E              (1 << 1)  /* Bit 1:  Output buffer 1 status empty bits */

+#define PMP_STAT_OB2E              (1 << 2)  /* Bit 2:  Output buffer 2 status empty bits */

+#define PMP_STAT_OB3E              (1 << 3)  /* Bit 3:  Output buffer 3 status empty bits */

+#define PMP_STAT_OBUF              (1 << 6)  /* Bit 6:  Output buffer underflow status */

+#define PMP_STAT_OBE               (1 << 7)  /* Bit 7:  Output buffer empty status */

+#define PMP_STAT_IBF(n)            (1 << (n+8))

+#define PMP_STAT_IB0F              (1 << 8)  /* Bit 8:  Input buffer 0 status full */

+#define PMP_STAT_IB1F              (1 << 9)  /* Bit 9:  Input buffer 1 status full */

+#define PMP_STAT_IB2F              (1 << 10) /* Bit 10: Input buffer 2 status full */

+#define PMP_STAT_IB3F              (1 << 11) /* Bit 11: Input buffer 3 status full */

+#define PMP_STAT_IBOV              (1 << 14) /* Bit 14: Input buffer overflow status */

+#define PMP_STAT_IBF               (1 << 15) /* Bit 15: Input buffer full status */

+

+/************************************************************************************

+ * Public Types

+ ************************************************************************************/

+

+#ifndef __ASSEMBLY__

+

+/************************************************************************************

+ * Inline Functions

+ ************************************************************************************/

+

+/************************************************************************************

+ * Public Function Prototypes

+ ************************************************************************************/

+

+#ifdef __cplusplus

+#define EXTERN extern "C"

+extern "C" {

+#else

+#define EXTERN extern

+#endif

+

+#undef EXTERN

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __ASSEMBLY__ */

+#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PMP_H */

diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-reset.h b/nuttx/arch/mips/src/pic32mx/pic32mx-reset.h
index cb8b1bf2f6..1ba54be68e 100755
--- a/nuttx/arch/mips/src/pic32mx/pic32mx-reset.h
+++ b/nuttx/arch/mips/src/pic32mx/pic32mx-reset.h
@@ -56,7 +56,7 @@
 #define PIC32MX_RESET_RSWRST_OFFSET    0x0010 /* Software reset register */

 #define PIC32MX_RESET_RSWRSTCLR_OFFSET 0x0014 /* RSWRST clear register */

 #define PIC32MX_RESET_RSWRSTSET_OFFSET 0x0018 /* RSWRST set register */

-#define PIC32MX_RESET_RSWRSTINV_OFFSET 0x001c /* RSWRST nvert register */

+#define PIC32MX_RESET_RSWRSTINV_OFFSET 0x001c /* RSWRST invert register */

 

 /* Register Addresses *******************************************************/