Misc GPIO-related changes

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@2132 7fd9a85b-ad96-42d3-883c-3090e2eb8679

5 files changed, 38 insertions, 31 deletions

diff --git a/nuttx/arch/arm/src/lm3s/lm3s_start.c b/nuttx/arch/arm/src/lm3s/lm3s_start.c
index 8fc05bdefe..272cb8210e 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_start.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_start.c
@@ -136,9 +136,7 @@ void __start(void)
 
   /* Initialize onboard resources */
 
-#ifdef CONFIG_ARCH_LEDS
   lm3s_boardinitialize();
-#endif
   showprogress('E');
 
   /* Then start NuttX */
diff --git a/nuttx/arch/arm/src/stm32/stm32_gpio.c b/nuttx/arch/arm/src/stm32/stm32_gpio.c
index 280760aca7..454e833518 100755
--- a/nuttx/arch/arm/src/stm32/stm32_gpio.c
+++ b/nuttx/arch/arm/src/stm32/stm32_gpio.c
@@ -59,27 +59,27 @@
  * Private Data
  ****************************************************************************/
 
-static const uint32 g_gpiobase[STM32_NGPIO] =
+static const uint32 g_gpiobase[STM32_NGPIO_PORTS] =
 {
-#if STM32_NGPIO > 0
+#if STM32_NGPIO_PORTS > 0
 	STM32_GPIOA_BASE,
 #endif
-#if STM32_NGPIO > 1
+#if STM32_NGPIO_PORTS > 1
 	STM32_GPIOB_BASE,
 #endif
-#if STM32_NGPIO > 2
+#if STM32_NGPIO_PORTS > 2
 	STM32_GPIOC_BASE,
 #endif
-#if STM32_NGPIO > 3
+#if STM32_NGPIO_PORTS > 3
 	STM32_GPIOD_BASE,
 #endif
-#if STM32_NGPIO > 4
+#if STM32_NGPIO_PORTS > 4
 	STM32_GPIOE_BASE,
 #endif
-#if STM32_NGPIO > 5
+#if STM32_NGPIO_PORTS > 5
 	STM32_GPIOF_BASE,
 #endif
-#if STM32_NGPIO > 6
+#if STM32_NGPIO_PORTS > 6
 	STM32_GPIOG_BASE,
 #endif
 };
@@ -119,7 +119,7 @@ int stm32_configgpio(uint32 cfgset)
   /* Verify that this hardware supports the select GPIO port */
 
   port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
-  if (port < STM32_NGPIO)
+  if (port < STM32_NGPIO_PORTS)
     {
       /* Get the port base address */
 
@@ -252,7 +252,7 @@ void stm32_gpiowrite(uint32 pinset, boolean value)
   unsigned int pin;
 
   port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
-  if (port < STM32_NGPIO)
+  if (port < STM32_NGPIO_PORTS)
     {
       /* Get the port base address */
 
@@ -291,7 +291,7 @@ boolean stm32_gpioread(uint32 pinset)
   unsigned int pin;
 
   port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
-  if (port < STM32_NGPIO)
+  if (port < STM32_NGPIO_PORTS)
     {
       /* Get the port base address */
 
@@ -329,17 +329,25 @@ int stm32_dumpgpio(uint32 pinset, const char *msg)
 
   /* The following requires exclusive access to the GPIO registers */
 
-  flags   = irqsave();
+  flags = irqsave();
   lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
         g_portchar[port], pinset, base, msg);
-  lldbg("  CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n",
-        getreg32(base + STM32_GPIO_CRH_OFFSET), getreg32(base + STM32_GPIO_CRL_OFFSET),
-        getreg32(base + STM32_GPIO_IDR_OFFSET), getreg32(base + STM32_GPIO_ODR_OFFSET),
-        getreg32(base + STM32_GPIO_LCKR_OFFSET));
-  lldbg("  EVCR: %02x MAPR: %08x CR: %04x %04x %04x %04x\n",
-        getreg32(STM32_AFIO_EVCR), getreg32(STM32_AFIO_MAPR),
-        getreg32(STM32_AFIO_EXTICR1), getreg32(STM32_AFIO_EXTICR2),
-        getreg32(STM32_AFIO_EXTICR3), getreg32(STM32_AFIO_EXTICR4));
+  if ((getreg32(STM32_RCC_APB2ENR) & RCC_APB2ENR_IOPEN(port)) != 0)
+    {
+      lldbg("  CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n",
+            getreg32(base + STM32_GPIO_CRH_OFFSET), getreg32(base + STM32_GPIO_CRL_OFFSET),
+            getreg32(base + STM32_GPIO_IDR_OFFSET), getreg32(base + STM32_GPIO_ODR_OFFSET),
+            getreg32(base + STM32_GPIO_LCKR_OFFSET));
+      lldbg("  EVCR: %02x MAPR: %08x CR: %04x %04x %04x %04x\n",
+            getreg32(STM32_AFIO_EVCR), getreg32(STM32_AFIO_MAPR),
+            getreg32(STM32_AFIO_EXTICR1), getreg32(STM32_AFIO_EXTICR2),
+            getreg32(STM32_AFIO_EXTICR3), getreg32(STM32_AFIO_EXTICR4));
+    }
+  else
+    {
+      lldbg("  GPIO%c not enabled: APB2ENR: %08x\n",
+            g_portchar[port], getreg32(STM32_RCC_APB2ENR));
+    }
   irqrestore(flags);
   return OK;
 }
diff --git a/nuttx/arch/arm/src/stm32/stm32_gpio.h b/nuttx/arch/arm/src/stm32/stm32_gpio.h
index 863f66f69e..8875d261e0 100644
--- a/nuttx/arch/arm/src/stm32/stm32_gpio.h
+++ b/nuttx/arch/arm/src/stm32/stm32_gpio.h
@@ -48,6 +48,8 @@
  * Definitions
  ************************************************************************************/
 
+#define STM32_NGPIO_PORTS            ((STM32_NGPIO + 15) >> 4)
+
 /* Register Offsets *****************************************************************/
 
 #define STM32_GPIO_CRL_OFFSET        0x0000  /* Port configuration register low */
@@ -67,7 +69,7 @@
 
 /* Register Addresses ***************************************************************/
 
-#if STM32_NGPIO > 0
+#if STM32_NGPIO_PORTS > 0
 #  define STM32_GPIOA_CRL            (STM32_GPIOA_BASE+STM32_GPIO_CRL_OFFSET)
 #  define STM32_GPIOA_CRH            (STM32_GPIOA_BASE+STM32_GPIO_CRH_OFFSET)
 #  define STM32_GPIOA_IDR            (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET)
@@ -77,7 +79,7 @@
 #  define STM32_GPIOA_LCKR           (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET)
 #endif
 
-#if STM32_NGPIO > 1
+#if STM32_NGPIO_PORTS > 1
 #  define STM32_GPIOB_CRL            (STM32_GPIOB_BASE+STM32_GPIO_CRL_OFFSET)
 #  define STM32_GPIOB_CRH            (STM32_GPIOB_BASE+STM32_GPIO_CRH_OFFSET)
 #  define STM32_GPIOB_IDR            (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET)
@@ -87,7 +89,7 @@
 #  define STM32_GPIOB_LCKR           (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET)
 #endif
 
-#if STM32_NGPIO > 2
+#if STM32_NGPIO_PORTS > 2
 #  define STM32_GPIOC_CRL            (STM32_GPIOC_BASE+STM32_GPIO_CRL_OFFSET)
 #  define STM32_GPIOC_CRH            (STM32_GPIOC_BASE+STM32_GPIO_CRH_OFFSET)
 #  define STM32_GPIOC_IDR            (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET)
@@ -97,7 +99,7 @@
 #  define STM32_GPIOC_LCKR           (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET)
 #endif
 
-#if STM32_NGPIO > 3
+#if STM32_NGPIO_PORTS > 3
 #  define STM32_GPIOD_CRL            (STM32_GPIOD_BASE+STM32_GPIO_CRL_OFFSET)
 #  define STM32_GPIOD_CRH            (STM32_GPIOD_BASE+STM32_GPIO_CRH_OFFSET)
 #  define STM32_GPIOD_IDR            (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET)
@@ -107,7 +109,7 @@
 #  define STM32_GPIOD_LCKR           (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET)
 #endif
 
-#if STM32_NGPIO > 4
+#if STM32_NGPIO_PORTS > 4
 #  define STM32_GPIOE_CRL            (STM32_GPIOE_BASE+STM32_GPIO_CRL_OFFSET)
 #  define STM32_GPIOE_CRH            (STM32_GPIOE_BASE+STM32_GPIO_CRH_OFFSET)
 #  define STM32_GPIOE_IDR            (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET)
@@ -117,7 +119,7 @@
 #  define STM32_GPIOE_LCKR           (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET)
 #endif
 
-#if STM32_NGPIO > 5
+#if STM32_NGPIO_PORTS > 5
 #  define STM32_GPIOF_CRL            (STM32_GPIOF_BASE+STM32_GPIO_CRL_OFFSET)
 #  define STM32_GPIOF_CRH            (STM32_GPIOF_BASE+STM32_GPIO_CRH_OFFSET)
 #  define STM32_GPIOF_IDR            (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET)
@@ -127,7 +129,7 @@
 #  define STM32_GPIOF_LCKR           (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET)
 #endif
 
-#if STM32_NGPIO > 6
+#if STM32_NGPIO_PORTS > 6
 #  define STM32_GPIOG_CRL            (STM32_GPIOG_BASE+STM32_GPIO_CRL_OFFSET)
 #  define STM32_GPIOG_CRH            (STM32_GPIOG_BASE+STM32_GPIO_CRH_OFFSET)
 #  define STM32_GPIOG_IDR            (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET)
diff --git a/nuttx/arch/arm/src/stm32/stm32_rcc.h b/nuttx/arch/arm/src/stm32/stm32_rcc.h
index a7227cd79c..1cc601e71d 100755
--- a/nuttx/arch/arm/src/stm32/stm32_rcc.h
+++ b/nuttx/arch/arm/src/stm32/stm32_rcc.h
@@ -236,6 +236,7 @@
 /* APB2 Peripheral Clock enable register */
 
 #define RCC_APB2ENR_AFIOEN          (1 << 0)  /* Bit 0: Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPEN(n)        (1 << ((n)+2))
 #define RCC_APB2ENR_IOPAEN          (1 << 2)  /* Bit 2: I/O port A clock enable */
 #define RCC_APB2ENR_IOPBEN          (1 << 3)  /* Bit 3: I/O port B clock enable */
 #define RCC_APB2ENR_IOPCEN          (1 << 4)  /* Bit 4: I/O port C clock enable */
diff --git a/nuttx/arch/arm/src/stm32/stm32_start.c b/nuttx/arch/arm/src/stm32/stm32_start.c
index 85164af841..6b9ed14951 100644
--- a/nuttx/arch/arm/src/stm32/stm32_start.c
+++ b/nuttx/arch/arm/src/stm32/stm32_start.c
@@ -134,9 +134,7 @@ void __start(void)
 
   /* Initialize onboard resources */
 
-#ifdef CONFIG_ARCH_LEDS
   stm32_boardinitialize();
-#endif
   showprogress('E');
 
   /* Then start NuttX */