diff options
| author | patacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679> | 2012-07-01 14:51:06 +0000 |
|---|---|---|
| committer | patacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679> | 2012-07-01 14:51:06 +0000 |
| commit | 7ae7fd606c00958cfe448a7ccc3fd9189a594865 (patch) | |
| tree | 0bf4630c142d9eb16cffc51f7c1e692d39a2e843 /nuttx/arch/arm/src/lpc17xx | |
| parent | cf4cad5f9ec3a295eec07ac7ed2684f4dd6041cd (diff) | |
Add LPC43 UART, USART, SSP, and SPI header files
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4893 7fd9a85b-ad96-42d3-883c-3090e2eb8679
Diffstat (limited to 'nuttx/arch/arm/src/lpc17xx')
| -rw-r--r-- | nuttx/arch/arm/src/lpc17xx/lpc17_ssp.h | 8 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc17xx/lpc17_uart.h | 12 |
2 files changed, 10 insertions, 10 deletions
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.h b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.h index 32142a0ee8..52b88da68d 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.h @@ -1,8 +1,8 @@ /************************************************************************************
* arch/arm/src/lpc17xx/lpc17_ssp.h
*
- * Copyright (C) 2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ * Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -95,8 +95,8 @@ #define SSP_CR0_DSS_SHIFT (0) /* Bits 0-3: DSS Data Size Select */
#define SSP_CR0_DSS_MASK (15 << SSP_CR0_DSS_SHIFT)
# define SSP_CR0_DSS_4BIT (3 << SSP_CR0_DSS_SHIFT)
-# define SSP_CR0_DSS_5BIT (5 << SSP_CR0_DSS_SHIFT)
-# define SSP_CR0_DSS_6BIT (4 << SSP_CR0_DSS_SHIFT)
+# define SSP_CR0_DSS_5BIT (4 << SSP_CR0_DSS_SHIFT)
+# define SSP_CR0_DSS_6BIT (5 << SSP_CR0_DSS_SHIFT)
# define SSP_CR0_DSS_7BIT (6 << SSP_CR0_DSS_SHIFT)
# define SSP_CR0_DSS_8BIT (7 << SSP_CR0_DSS_SHIFT)
# define SSP_CR0_DSS_9BIT (8 << SSP_CR0_DSS_SHIFT)
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_uart.h b/nuttx/arch/arm/src/lpc17xx/lpc17_uart.h index 830c3244d5..3664a0cb8c 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_uart.h +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_uart.h @@ -1,8 +1,8 @@ /************************************************************************************
* arch/arm/src/lpc17xx/lpc17_uart.h
*
- * Copyright (C) 2010 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ * Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -202,7 +202,7 @@ /* Bits 4-5: Reserved */
#define UART_FCR_RXTRIGGER_SHIFT (6) /* Bits 6-7: RX Trigger Level */
#define UART_FCR_RXTRIGGER_MASK (3 << UART_FCR_RXTRIGGER_SHIFT)
-# define UART_FCR_RXTRIGGER_0 (0 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 0 (1 character) */
+# define UART_FCR_RXTRIGGER_0 (0 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 0 (1 character) */
# define UART_FCR_RXTRIGGER_4 (1 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 1 (4 characters) */
# define UART_FCR_RXTRIGGER_8 (2 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 2 (8 characters) */
# define UART_FCR_RXTRIGGER_14 (3 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 3 (14 characters) */
@@ -232,7 +232,7 @@ #define UART_MCR_RTS (1 << 1) /* Bit 1: Control Source for RTS output */
/* Bits 2-3: Reserved */
#define UART_MCR_LPBK (1 << 4) /* Bit 4: Loopback Mode Select */
- /* Bit 5: Reserved */
+ /* Bit 5: Reserved */
#define UART_MCR_RTSEN (1 << 6) /* Bit 6: Enable auto-rts flow control */
#define UART_MCR_CTSEN (1 << 7) /* Bit 7: Enable auto-cts flow control */
/* Bits 8-31: Reserved */
@@ -275,7 +275,7 @@ #define UART_ICR_IRDAEN (1 << 0) /* Bit 0: Enable IrDA mode */
#define UART_ICR_IRDAINV (1 << 1) /* Bit 1: Invert serial input */
-#define UART_ICR_FIXPULSEEN (1 << 2) /* Bit 2: Enable IrDA fixed pulse width mode */
+#define UART_ICR_FIXPULSEEN (1 << 2) /* Bit 2: Enable IrDA fixed pulse width mode */
#define UART_ICR_PULSEDIV_SHIFT (3) /* Bits 3-5: Configures the pulse when FixPulseEn = 1 */
#define UART_ICR_PULSEDIV_MASK (7 << UART_ICR_PULSEDIV_SHIFT)
# define UART_ICR_PULSEDIV_2TPCLK (0 << UART_ICR_PULSEDIV_SHIFT) /* 2 x TPCLK */
@@ -313,7 +313,7 @@ /* Bits 8-31: Reserved */
/* RS-485/EIA-485 direction control delay (UART1 only) */
-#define UART_RS485DLY_MASK (0xff) /* Bits 0-7: Firection control (RTS/DTR) delay */
+#define UART_RS485DLY_MASK (0xff) /* Bits 0-7: Direction control (RTS/DTR) delay */
/* Bits 8-31: Reserved */
/* FIFOLVL FIFO Level register (all) */
|