diff options
| author | patacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679> | 2011-04-06 01:51:07 +0000 |
|---|---|---|
| committer | patacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679> | 2011-04-06 01:51:07 +0000 |
| commit | 55540073dc3d5842e1f1e30d880682f0bb5ec11b (patch) | |
| tree | 174d0d75436a2dbf8b0e2381a7173c7bad7f9336 /nuttx/arch/arm/include | |
| parent | 89316d0ee9b59ebf92a6e72d18aaf0d3cda310f5 (diff) | |
Attach mem mgmt fault handle if MPU is enabled
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@3471 7fd9a85b-ad96-42d3-883c-3090e2eb8679
Diffstat (limited to 'nuttx/arch/arm/include')
| -rw-r--r-- | nuttx/arch/arm/include/lm3s/irq.h | 4 | ||||
| -rwxr-xr-x | nuttx/arch/arm/include/lpc17xx/irq.h | 2 | ||||
| -rwxr-xr-x | nuttx/arch/arm/include/sam3u/irq.h | 4 | ||||
| -rw-r--r-- | nuttx/arch/arm/include/stm32/irq.h | 2 |
4 files changed, 6 insertions, 6 deletions
diff --git a/nuttx/arch/arm/include/lm3s/irq.h b/nuttx/arch/arm/include/lm3s/irq.h index e65540e976..761bf81da5 100644 --- a/nuttx/arch/arm/include/lm3s/irq.h +++ b/nuttx/arch/arm/include/lm3s/irq.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/include/lm3s/irq.h * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <spudmonkey@racsa.co.cr> * * Redistribution and use in source and binary forms, with or without @@ -63,7 +63,7 @@ /* Vector 1: Reset (not handler as an IRQ) */ #define LM3S_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ #define LM3S_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define LM3S_IRQ_MPU (4) /* Vector 4: Memory management (MPU) */ +#define LM3S_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ #define LM3S_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ #define LM3S_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ #define LM3S_IRQ_SVCALL (11) /* Vector 11: SVC call */ diff --git a/nuttx/arch/arm/include/lpc17xx/irq.h b/nuttx/arch/arm/include/lpc17xx/irq.h index 8c9777d908..7807e0260e 100755 --- a/nuttx/arch/arm/include/lpc17xx/irq.h +++ b/nuttx/arch/arm/include/lpc17xx/irq.h @@ -64,7 +64,7 @@ /* Vector 1: Reset (not handler as an IRQ) */ #define LPC17_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ #define LPC17_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define LPC17_IRQ_MPU (4) /* Vector 4: Memory management (MPU) */ +#define LPC17_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ #define LPC17_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ #define LPC17_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ #define LPC17_IRQ_SVCALL (11) /* Vector 11: SVC call */ diff --git a/nuttx/arch/arm/include/sam3u/irq.h b/nuttx/arch/arm/include/sam3u/irq.h index a79c15b5ea..2c6940b68f 100755 --- a/nuttx/arch/arm/include/sam3u/irq.h +++ b/nuttx/arch/arm/include/sam3u/irq.h @@ -1,7 +1,7 @@ /**************************************************************************************** * arch/arm/include/sam3u/irq.h * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <spudmonkey@racsa.co.cr> * * Redistribution and use in source and binary forms, with or without @@ -94,7 +94,7 @@ /* Vector 1: Reset (not handler as an IRQ) */ #define SAM3U_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ #define SAM3U_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define SAM3U_IRQ_MPU (4) /* Vector 4: Memory management (MPU) */ +#define SAM3U_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ #define SAM3U_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ #define SAM3U_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ #define SAM3U_IRQ_SVCALL (11) /* Vector 11: SVC call */ diff --git a/nuttx/arch/arm/include/stm32/irq.h b/nuttx/arch/arm/include/stm32/irq.h index 108dfd10b9..f80e91d706 100644 --- a/nuttx/arch/arm/include/stm32/irq.h +++ b/nuttx/arch/arm/include/stm32/irq.h @@ -63,7 +63,7 @@ /* Vector 1: Reset (not handler as an IRQ) */ #define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ #define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define STM32_IRQ_MPU (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ #define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ #define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ #define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ |