Finish port of GPIO driver for STM3240

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4122 7fd9a85b-ad96-42d3-883c-3090e2eb8679

4 files changed, 397 insertions, 210 deletions

diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_syscfg.h b/nuttx/arch/arm/src/stm32/chip/stm32_syscfg.h
index 792a719db1..f1788beeb8 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32_syscfg.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32_syscfg.h
@@ -51,91 +51,101 @@
 
 /* Register Offsets *********************************************************************************/
 
-#define STM32_SYSCFG_MEMRMP_OFFSET  0x0000 /* SYSCFG memory remap register */
-#define STM32_SYSCFG_PMC_OFFSET     0x0004 /* SYSCFG peripheral mode configuration register */
-#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
-#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
-#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
-#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
-#define STM32_SYSCFG_CMPCR_OFFSET   0x0020 /* Compensation cell control register */
+#define STM32_SYSCFG_MEMRMP_OFFSET    0x0000 /* SYSCFG memory remap register */
+#define STM32_SYSCFG_PMC_OFFSET       0x0004 /* SYSCFG peripheral mode configuration register */
+
+#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
+#define STM32_SYSCFG_EXTICR1_OFFSET   0x0008 /* SYSCFG external interrupt configuration register 1 */
+#define STM32_SYSCFG_EXTICR2_OFFSET   0x000c /* SYSCFG external interrupt configuration register 2 */
+#define STM32_SYSCFG_EXTICR3_OFFSET   0x0010 /* SYSCFG external interrupt configuration register 3 */
+#define STM32_SYSCFG_EXTICR4_OFFSET   0x0014 /* SYSCFG external interrupt configuration register 4 */
+
+#define STM32_SYSCFG_CMPCR_OFFSET     0x0020 /* Compensation cell control register */
 
 /* Register Addresses *******************************************************************************/
 
-#define STM32_SYSCFG_MEMRMP         (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
-#define STM32_SYSCFG_PMC            (STM32_SYSCFG_BASE+STM32_SYSCFG_PMC_OFFSET)
-#define STM32_SYSCFG_EXTICR1        (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
-#define STM32_SYSCFG_EXTICR2        (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
-#define STM32_SYSCFG_EXTICR3        (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
-#define STM32_SYSCFG_EXTICR4        (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
-#define STM32_SYSCFG_CMPCR          (STM32_SYSCFG_BASE+STM32_SYSCFG_CMPCR_OFFSET)
+#define STM32_SYSCFG_MEMRMP           (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
+#define STM32_SYSCFG_PMC              (STM32_SYSCFG_BASE+STM32_SYSCFG_PMC_OFFSET)
+
+#define STM32_SYSCFG_EXTICR(p)        (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
+#define STM32_SYSCFG_EXTICR1          (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
+#define STM32_SYSCFG_EXTICR2          (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
+#define STM32_SYSCFG_EXTICR3          (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
+#define STM32_SYSCFG_EXTICR4          (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
+
+#define STM32_SYSCFG_CMPCR            (STM32_SYSCFG_BASE+STM32_SYSCFG_CMPCR_OFFSET)
 
 /* Register Bitfield Definitions ********************************************************************/
 
 /* SYSCFG memory remap register */
 
-#define SYSCFG_MEMRMP_SHIFT         (0)       /* Bits 1:0 MEM_MODE: Memory mapping selection */
-#define SYSCFG_MEMRMP_MASK          (3 << SYSCFG_MEMRMP_SHIFT)
-#  define SYSCFG_MEMRMP _MASK       (0 << SYSCFG_MEMRMP_SHIFT) /* 00: Main Flash memory mapped at 0x0000 0000 */
-#  define SYSCFG_MEMRMP _MASK       (1 << SYSCFG_MEMRMP_SHIFT) /* 01: System Flash memory mapped at 0x0000 0000 */
-#  define SYSCFG_MEMRMP _MASK       (2 << SYSCFG_MEMRMP_SHIFT) /* 10: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000 */
-#  define SYSCFG_MEMRMP _MASK       (3 << SYSCFG_MEMRMP_SHIFT) /* 11: Embedded SRAM (112kB) mapped at 0x0000 0000 */
+#define SYSCFG_MEMRMP_SHIFT           (0)       /* Bits 1:0 MEM_MODE: Memory mapping selection */
+#define SYSCFG_MEMRMP_MASK            (3 << SYSCFG_MEMRMP_SHIFT)
+#  define SYSCFG_MEMRMP_FLASH         (0 << SYSCFG_MEMRMP_SHIFT) /* 00: Main Flash memory mapped at 0x0000 0000 */
+#  define SYSCFG_MEMRMP_SYSTEM        (1 << SYSCFG_MEMRMP_SHIFT) /* 01: System Flash memory mapped at 0x0000 0000 */
+#  define SYSCFG_MEMRMP_FSMC          (2 << SYSCFG_MEMRMP_SHIFT) /* 10: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000 */
+#  define SYSCFG_MEMRMP_SRAM          (3 << SYSCFG_MEMRMP_SHIFT) /* 11: Embedded SRAM (112kB) mapped at 0x0000 0000 */
 
 /* SYSCFG peripheral mode configuration register */
 
-#define SYSCFG_PMC_MII_RMII_SEL     (1 << 23) /* Bit 23: Ethernet PHY interface selection */
+#define SYSCFG_PMC_MII_RMII_SEL       (1 << 23) /* Bit 23: Ethernet PHY interface selection */
 
 /* SYSCFG external interrupt configuration register 1-4 */
 
-#define SYSCFG_EXTICR_PORTA         (0)       /* 0000: PA[x] pin */
-#define SYSCFG_EXTICR_PORTB         (1)       /* 0001: PB[x] pin */
-#define SYSCFG_EXTICR_PORTC         (2)       /* 0010: PC[x] pin */
-#define SYSCFG_EXTICR_PORTD         (3)       /* 0011: PD[x] pin */
-#define SYSCFG_EXTICR_PORTE         (4)       /* 0100: PE[x] pin */
-#define SYSCFG_EXTICR_PORTF         (5)       /* 0101: PF[C] pin */
-#define SYSCFG_EXTICR_PORTG         (6)       /* 0110: PG[x] pin */
-#define SYSCFG_EXTICR_PORTH         (7)       /* 0111: PH[x] pin */
-#define SYSCFG_EXTICR_PORTI         (8)       /* 1000: PI[x] pin */
-
-#define SYSCFG_EXTICR1_EXTI0_SHIFT  (0)       /* Bits 0-3: EXIT 0 coinfiguration */
-#define SYSCFG_EXTICR1_EXTI0_MASK   (15 << SYSCFG_EXTICR1_EXTI0_SHIFT)
-#define SYSCFG_EXTICR1_EXTI1_SHIFT  (0)       /* Bits 4-7: EXIT 1 coinfiguration */
-#define SYSCFG_EXTICR1_EXTI1_MASK   (15 << SYSCFG_EXTICR1_EXTI1_SHIFT)
-#define SYSCFG_EXTICR1_EXTI2_SHIFT  (0)       /* Bits 8-11: EXIT 2 coinfiguration */
-#define SYSCFG_EXTICR1_EXTI2_MASK   (15 << SYSCFG_EXTICR1_EXTI2_SHIFT)
-#define SYSCFG_EXTICR1_EXTI3_SHIFT  (0)       /* Bits 12-15: EXIT 3 coinfiguration */
-#define SYSCFG_EXTICR1_EXTI3_MASK   (15 << SYSCFG_EXTICR1_EXTI3_SHIFT)
-
-#define SYSCFG_EXTICR2_EXTI4_SHIFT  (0)       /* Bits 0-3: EXIT 4 coinfiguration */
-#define SYSCFG_EXTICR2_EXTI4_MASK   (15 << SYSCFG_EXTICR2_EXTI4_SHIFT)
-#define SYSCFG_EXTICR2_EXTI5_SHIFT  (0)       /* Bits 4-7: EXIT 5 coinfiguration */
-#define SYSCFG_EXTICR2_EXTI5_MASK   (15 << SYSCFG_EXTICR2_EXTI5_SHIFT)
-#define SYSCFG_EXTICR2_EXTI6_SHIFT  (0)       /* Bits 8-11: EXIT 6 coinfiguration */
-#define SYSCFG_EXTICR2_EXTI6_MASK   (15 << SYSCFG_EXTICR2_EXTI6_SHIFT)
-#define SYSCFG_EXTICR2_EXTI7_SHIFT  (0)       /* Bits 12-15: EXIT 7 coinfiguration */
-#define SYSCFG_EXTICR2_EXTI7_MASK   (15 << SYSCFG_EXTICR2_EXTI7_SHIFT)
-
-#define SYSCFG_EXTICR3_EXTI8_SHIFT  (0)       /* Bits 0-3: EXIT 8 coinfiguration */
-#define SYSCFG_EXTICR3_EXTI8_MASK   (15 << SYSCFG_EXTICR3_EXTI8_SHIFT)
-#define SYSCFG_EXTICR3_EXTI9_SHIFT  (0)       /* Bits 4-7: EXIT 9 coinfiguration */
-#define SYSCFG_EXTICR3_EXTI9_MASK   (15 << SYSCFG_EXTICR3_EXTI9_SHIFT)
-#define SYSCFG_EXTICR3_EXTI10_SHIFT (0)       /* Bits 8-11: EXIT 10 coinfiguration */
-#define SYSCFG_EXTICR3_EXTI10_MASK  (15 << SYSCFG_EXTICR3_EXTI10_SHIFT)
-#define SYSCFG_EXTICR3_EXTI11_SHIFT (0)       /* Bits 12-15: EXIT 11 coinfiguration */
-#define SYSCFG_EXTICR3_EXTI11_MASK  (15 << SYSCFG_EXTICR3_EXTI11_SHIFT)
-
-#define SYSCFG_EXTICR4_EXTI12_SHIFT (0)       /* Bits 0-3: EXIT 12 coinfiguration */
-#define SYSCFG_EXTICR4_EXTI12_MASK  (15 << SYSCFG_EXTICR4_EXTI12_SHIFT)
-#define SYSCFG_EXTICR4_EXTI13_SHIFT (0)       /* Bits 4-7: EXIT 13 coinfiguration */
-#define SYSCFG_EXTICR4_EXTI13_MASK  (15 << SYSCFG_EXTICR4_EXTI13_SHIFT)
-#define SYSCFG_EXTICR4_EXTI14_SHIFT (0)       /* Bits 8-11: EXIT 14 coinfiguration */
-#define SYSCFG_EXTICR4_EXTI14_MASK  (15 << SYSCFG_EXTICR4_EXTI14_SHIFT)
-#define SYSCFG_EXTICR4_EXTI15_SHIFT (0)       /* Bits 12-15: EXIT 15 coinfiguration */
-#define SYSCFG_EXTICR4_EXTI15_MASK  (15 << SYSCFG_EXTICR4_EXTI15_SHIFT)
+#define SYSCFG_EXTICR_PORTA           (0)       /* 0000: PA[x] pin */
+#define SYSCFG_EXTICR_PORTB           (1)       /* 0001: PB[x] pin */
+#define SYSCFG_EXTICR_PORTC           (2)       /* 0010: PC[x] pin */
+#define SYSCFG_EXTICR_PORTD           (3)       /* 0011: PD[x] pin */
+#define SYSCFG_EXTICR_PORTE           (4)       /* 0100: PE[x] pin */
+#define SYSCFG_EXTICR_PORTF           (5)       /* 0101: PF[C] pin */
+#define SYSCFG_EXTICR_PORTG           (6)       /* 0110: PG[x] pin */
+#define SYSCFG_EXTICR_PORTH           (7)       /* 0111: PH[x] pin */
+#define SYSCFG_EXTICR_PORTI           (8)       /* 1000: PI[x] pin */
+
+#define SYSCFG_EXTICR_PORT_MASK       (15)
+#define SYSCFG_EXTICR_EXTI_SHIFT(g)   (((g) & 3) << 2)
+#define SYSCFG_EXTICR_EXTI_MASK(g)    (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
+
+#define SYSCFG_EXTICR1_EXTI0_SHIFT    (0)       /* Bits 0-3: EXTI 0 coinfiguration */
+#define SYSCFG_EXTICR1_EXTI0_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
+#define SYSCFG_EXTICR1_EXTI1_SHIFT    (4)       /* Bits 4-7: EXTI 1 coinfiguration */
+#define SYSCFG_EXTICR1_EXTI1_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
+#define SYSCFG_EXTICR1_EXTI2_SHIFT    (8)       /* Bits 8-11: EXTI 2 coinfiguration */
+#define SYSCFG_EXTICR1_EXTI2_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
+#define SYSCFG_EXTICR1_EXTI3_SHIFT    (12)      /* Bits 12-15: EXTI 3 coinfiguration */
+#define SYSCFG_EXTICR1_EXTI3_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
+
+#define SYSCFG_EXTICR2_EXTI4_SHIFT    (0)       /* Bits 0-3: EXTI 4 coinfiguration */
+#define SYSCFG_EXTICR2_EXTI4_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
+#define SYSCFG_EXTICR2_EXTI5_SHIFT    (4)       /* Bits 4-7: EXTI 5 coinfiguration */
+#define SYSCFG_EXTICR2_EXTI5_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
+#define SYSCFG_EXTICR2_EXTI6_SHIFT    (8)       /* Bits 8-11: EXTI 6 coinfiguration */
+#define SYSCFG_EXTICR2_EXTI6_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
+#define SYSCFG_EXTICR2_EXTI7_SHIFT    (12)      /* Bits 12-15: EXTI 7 coinfiguration */
+#define SYSCFG_EXTICR2_EXTI7_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
+
+#define SYSCFG_EXTICR3_EXTI8_SHIFT    (0)       /* Bits 0-3: EXTI 8 coinfiguration */
+#define SYSCFG_EXTICR3_EXTI8_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
+#define SYSCFG_EXTICR3_EXTI9_SHIFT    (4)       /* Bits 4-7: EXTI 9 coinfiguration */
+#define SYSCFG_EXTICR3_EXTI9_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
+#define SYSCFG_EXTICR3_EXTI10_SHIFT   (8)       /* Bits 8-11: EXTI 10 coinfiguration */
+#define SYSCFG_EXTICR3_EXTI10_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
+#define SYSCFG_EXTICR3_EXTI11_SHIFT   (12)      /* Bits 12-15: EXTI 11 coinfiguration */
+#define SYSCFG_EXTICR3_EXTI11_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
+
+#define SYSCFG_EXTICR4_EXTI12_SHIFT   (0)       /* Bits 0-3: EXTI 12 coinfiguration */
+#define SYSCFG_EXTICR4_EXTI12_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
+#define SYSCFG_EXTICR4_EXTI13_SHIFT   (4)       /* Bits 4-7: EXTI 13 coinfiguration */
+#define SYSCFG_EXTICR4_EXTI13_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
+#define SYSCFG_EXTICR4_EXTI14_SHIFT   (8)       /* Bits 8-11: EXTI 14 coinfiguration */
+#define SYSCFG_EXTICR4_EXTI14_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
+#define SYSCFG_EXTICR4_EXTI15_SHIFT   (12)      /* Bits 12-15: EXTI 15 coinfiguration */
+#define SYSCFG_EXTICR4_EXTI15_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
 
 /* Compensation cell control register */
 
-#define SYSCFG_CMPCR_CMPPD          (1 << 0)  /* Bit 0: Compensation cell power-down */
-#define SYSCFG_CMPCR_READY          (1 << 8)  /* Bit 8: Compensation cell ready flag */
+#define SYSCFG_CMPCR_CMPPD            (1 << 0)  /* Bit 0: Compensation cell power-down */
+#define SYSCFG_CMPCR_READY            (1 << 8)  /* Bit 8: Compensation cell ready flag */
 
 #endif /* CONFIG_STM32_STM32F40XX */
 #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_SYSCFG_H */
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h
index 4a171af21c..effe8a8b54 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h
@@ -54,7 +54,7 @@
 
 #define STM32_AFIO_EVCR_OFFSET       0x0000  /* Event control register */
 #define STM32_AFIO_MAPR_OFFSET       0x0004  /* AF remap and debug I/O configuration register */
-#define STM32_AFIO_EXTICR_OFFSET(p)  (0x0008 + ((p) & 0xC)) /* Registers are displaced by 4! */
+#define STM32_AFIO_EXTICR_OFFSET(p)  (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
 #define STM32_AFIO_EXTICR1_OFFSET    0x0008  /* External interrupt configuration register 1 */
 #define STM32_AFIO_EXTICR2_OFFSET    0x000c  /* External interrupt configuration register 2 */
 #define STM32_AFIO_EXTICR3_OFFSET    0x0010  /* External interrupt configuration register 3 */
diff --git a/nuttx/arch/arm/src/stm32/stm32_gpio.c b/nuttx/arch/arm/src/stm32/stm32_gpio.c
index 75a893beec..7c59f4a094 100644
--- a/nuttx/arch/arm/src/stm32/stm32_gpio.c
+++ b/nuttx/arch/arm/src/stm32/stm32_gpio.c
@@ -52,6 +52,14 @@
 #include "chip.h"
 #include "stm32_gpio.h"
 
+#if defined(CONFIG_STM32_STM32F40XX)
+#  include "chip/stm32_syscfg.h"
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -97,11 +105,136 @@ const uint32_t g_gpiobase[STM32_NGPIO_PORTS] =
  ****************************************************************************/
 
 /****************************************************************************
- * Name: stm32_gpio_configlock (for the STM32F10xxx family
+ * Function:  stm32_gpioremap
+ *
+ * Description:
+ *
+ *   Based on configuration within the .config file, this function will
+ *   remaps positions of alternative functions. 
+ * 
  ****************************************************************************/
 
+static inline void stm32_gpioremap(void)
+{
 #if defined(CONFIG_STM32_STM32F10XX)
-static int stm32_gpio_configlock(uint32_t cfgset, bool altlock)
+
+  /* Remap according to the configuration within .config file */
+
+  uint32_t val = 0;
+
+#ifdef CONFIG_STM32_JTAG_FULL_ENABLE
+  /* The reset default */
+#elif CONFIG_STM32_JTAG_NOJNTRST_ENABLE
+  val |= AFIO_MAPR_SWJ;    /* enabled but without JNTRST */
+#elif CONFIG_STM32_JTAG_SW_ENABLE
+  val |= AFIO_MAPR_SWDP;      /* set JTAG-DP disabled and SW-DP enabled */
+#else
+  val |= AFIO_MAPR_DISAB;     /* set JTAG-DP and SW-DP Disabled */
+#endif
+
+#ifdef CONFIG_STM32_TIM1_FULL_REMAP
+  val |= AFIO_MAPR_TIM1_FULLREMAP;
+#endif
+#ifdef CONFIG_STM32_TIM1_PARTIAL_REMAP
+  val |= AFIO_MAPR_TIM1_PARTREMAP;
+#endif
+#ifdef CONFIG_STM32_TIM2_FULL_REMAP
+  val |= AFIO_MAPR_TIM2_FULLREMAP;
+#endif
+#ifdef CONFIG_STM32_TIM2_PARTIAL_REMAP_1
+  val |= AFIO_MAPR_TIM2_PARTREMAP1;
+#endif
+#ifdef CONFIG_STM32_TIM2_PARTIAL_REMAP_2
+  val |= AFIO_MAPR_TIM2_PARTREMAP2;
+#endif
+#ifdef CONFIG_STM32_TIM3_FULL_REMAP
+  val |= AFIO_MAPR_TIM3_FULLREMAP;
+#endif
+#ifdef CONFIG_STM32_TIM3_PARTIAL_REMAP
+  val |= AFIO_MAPR_TIM3_PARTREMAP;
+#endif
+#ifdef CONFIG_STM32_TIM4_REMAP
+  val |= AFIO_MAPR_TIM4_REMAP;
+#endif
+
+#ifdef CONFIG_STM32_USART1_REMAP
+  val |= AFIO_MAPR_USART1_REMAP;
+#endif
+#ifdef CONFIG_STM32_USART2_REMAP
+  val |= AFIO_MAPR_USART2_REMAP;
+#endif
+#ifdef CONFIG_STM32_USART3_FULL_REMAP
+  val |= AFIO_MAPR_USART3_FULLREMAP;
+#endif
+#ifdef CONFIG_STM32_USART3_PARTIAL_REMAP
+  val |= AFIO_MAPR_USART3_PARTREMAP;
+#endif
+
+#ifdef CONFIG_STM32_SPI1_REMAP
+  val |= AFIO_MAPR_SPI1_REMAP;
+#endif
+#ifdef CONFIG_STM32_SPI3_REMAP
+#endif
+
+#ifdef CONFIG_STM32_I2C1_REMAP
+  val |= AFIO_MAPR_I2C1_REMAP;
+#endif
+
+#ifdef CONFIG_STM32_CAN1_REMAP1
+  val |= AFIO_MAPR_PB89;
+#endif
+#ifdef CONFIG_STM32_CAN1_REMAP2
+  val |= AFIO_MAPR_PD01;
+#endif
+
+  putreg32(val, STM32_AFIO_MAPR);  
+#endif
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function:  stm32_gpioinit
+ *
+ * Description:
+ *   Based on configuration within the .config file, it does:
+ *    - Remaps positions of alternative functions. 
+ * 
+ * Typically called from stm32_start().
+ ****************************************************************************/
+
+void stm32_gpioinit(void)
+{
+  /* Remap according to the configuration within .config file */
+
+  stm32_gpioremap();
+}
+
+/****************************************************************************
+ * Name: stm32_configgpio
+ *
+ * Description:
+ *   Configure a GPIO pin based on bit-encoded description of the pin.
+ *   Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) 
+ *   function, it must be unconfigured with stm32_unconfiggpio() with 
+ *   the same cfgset first before it can be set to non-alternative function.
+ * 
+ * Returns:
+ *   OK on success
+ *   A negated errono valu on invalid port, or when pin is locked as ALT
+ *   function.
+ * 
+ * To-Do: Auto Power Enable
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_configgpio (for the STM32F10xxx family)
+ ****************************************************************************/
+
+#if defined(CONFIG_STM32_STM32F10XX)
+int stm32_configgpio(uint32_t cfgset)
 {
   uint32_t base;
   uint32_t cr;
@@ -149,25 +282,6 @@ static int stm32_gpio_configlock(uint32_t cfgset, bool altlock)
   
   regval  = getreg32(cr);
   
-  /* Is present (old) config already in GPIO_ALT? and we got request to
-   * lock the alternative configuration. If so we allow the following
-   * changes only:
-   *  - to HiZ (unlocking the configuration)
-   *  - AFPP
-   *  - AFOD
-   */
-
-  uint32_t oldmode = (regval >> GPIO_CR_MODECNF_SHIFT(pos));
-
-  if (altlock && 
-        (oldmode & (GPIO_MODE_MASK >> GPIO_MODE_SHIFT)) &&                  /* previous state was output? */
-        ((oldmode>>2) & GPIO_CR_CNF_ALTOD) > GPIO_CR_CNF_OUTOD &&           /* previous state is ALT? */
-      ( ((cfgset & GPIO_CNF_MASK) >> GPIO_CNF_SHIFT) < GPIO_CR_CNF_ALTPP || /* new state is not output ALT? */
-        input ) )                                                           /* or it is input */
-    {
-      return -EINVAL;
-    }
-      
   if (input)
     {
       /* Input.. force mode = INPUT */
@@ -258,146 +372,209 @@ static int stm32_gpio_configlock(uint32_t cfgset, bool altlock)
 #endif
 
 /****************************************************************************
- * Name: stm32_gpio_configlock (for the STM32F40xxx family
+ * Name: stm32_configgpio (for the STM32F40xxx family)
  ****************************************************************************/
 
 #if defined(CONFIG_STM32_STM32F40XX)
-static int stm32_gpio_configlock(uint32_t cfgset, bool altlock)
+int stm32_configgpio(uint32_t cfgset)
 {
-# warning "Missing logic"
-  return -ENOSYS;
-}
-#endif
+  uintptr_t base;
+  uint32_t regval;
+  uint32_t setting;
+  unsigned int regoffset;
+  unsigned int port;
+  unsigned int pin;
+  unsigned int pos;
+  unsigned int pinmode;
+ 
+  /* Verify that this hardware supports the select GPIO port */
 
-/****************************************************************************
- * Function:  stm32_gpioremap
- *
- * Description:
- *
- *   Based on configuration within the .config file, this function will
- *   remaps positions of alternative functions. 
- * 
- ****************************************************************************/
+  port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+  if (port >= STM32_NGPIO_PORTS)
+    {
+      return -EINVAL;
+    }
+    
+  /* Get the port base address */
 
-static inline void stm32_gpioremap(void)
-{
-#if defined(CONFIG_STM32_STM32F10XX)
+  base = g_gpiobase[port];
 
-  /* Remap according to the configuration within .config file */
+  /* Get the pin number and select the port configuration register for that
+   * pin
+   */
 
-  uint32_t val = 0;
+  pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
 
-#ifdef CONFIG_STM32_JTAG_FULL_ENABLE
-  /* The reset default */
-#elif CONFIG_STM32_JTAG_NOJNTRST_ENABLE
-  val |= AFIO_MAPR_SWJ;    /* enabled but without JNTRST */
-#elif CONFIG_STM32_JTAG_SW_ENABLE
-  val |= AFIO_MAPR_SWDP;      /* set JTAG-DP disabled and SW-DP enabled */
-#else
-  val |= AFIO_MAPR_DISAB;     /* set JTAG-DP and SW-DP Disabled */
-#endif
+  /* Set up the mode register (and remember whether the pin mode) */
 
-#ifdef CONFIG_STM32_TIM1_FULL_REMAP
-  val |= AFIO_MAPR_TIM1_FULLREMAP;
-#endif
-#ifdef CONFIG_STM32_TIM1_PARTIAL_REMAP
-  val |= AFIO_MAPR_TIM1_PARTREMAP;
-#endif
-#ifdef CONFIG_STM32_TIM2_FULL_REMAP
-  val |= AFIO_MAPR_TIM2_FULLREMAP;
-#endif
-#ifdef CONFIG_STM32_TIM2_PARTIAL_REMAP_1
-  val |= AFIO_MAPR_TIM2_PARTREMAP1;
-#endif
-#ifdef CONFIG_STM32_TIM2_PARTIAL_REMAP_2
-  val |= AFIO_MAPR_TIM2_PARTREMAP2;
-#endif
-#ifdef CONFIG_STM32_TIM3_FULL_REMAP
-  val |= AFIO_MAPR_TIM3_FULLREMAP;
-#endif
-#ifdef CONFIG_STM32_TIM3_PARTIAL_REMAP
-  val |= AFIO_MAPR_TIM3_PARTREMAP;
-#endif
-#ifdef CONFIG_STM32_TIM4_REMAP
-  val |= AFIO_MAPR_TIM4_REMAP;
-#endif
+  switch (cfgset & GPIO_MODE_MASK)
+    {
+      default:
+      case GPIO_INPUT:      /* Input mode */
+        pinmode = GPIO_MODER_INPUT;
+        break;
+
+      case GPIO_OUTPUT:     /* General purpose output mode */
+        pinmode = GPIO_MODER_OUTPUT;
+        break;
+
+      case GPIO_ALT:        /* Alternate function mode */
+        pinmode = GPIO_MODER_ALT;
+        break;
+
+      case GPIO_ANALOG:     /* Analog mode */
+        pinmode = GPIO_MODER_ANALOG;
+        break;
+    }
 
-#ifdef CONFIG_STM32_USART1_REMAP
-  val |= AFIO_MAPR_USART1_REMAP;
-#endif
-#ifdef CONFIG_STM32_USART2_REMAP
-  val |= AFIO_MAPR_USART2_REMAP;
-#endif
-#ifdef CONFIG_STM32_USART3_FULL_REMAP
-  val |= AFIO_MAPR_USART3_FULLREMAP;
-#endif
-#ifdef CONFIG_STM32_USART3_PARTIAL_REMAP
-  val |= AFIO_MAPR_USART3_PARTREMAP;
-#endif
+  regval  = getreg32(base + STM32_GPIO_MODER_OFFSET);
+  regval &= ~GPIO_MODER_MASK(pin);
+  regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin));
+  putreg32(regval, base + STM32_GPIO_MODER_OFFSET);
 
-#ifdef CONFIG_STM32_SPI1_REMAP
-  val |= AFIO_MAPR_SPI1_REMAP;
-#endif
-#ifdef CONFIG_STM32_SPI3_REMAP
-#endif
+  /* Set up the pull-up/pull-down configuration (all but analog pins) */
 
-#ifdef CONFIG_STM32_I2C1_REMAP
-  val |= AFIO_MAPR_I2C1_REMAP;
-#endif
+  setting = GPIO_PUPDR_NONE;
+  if (pinmode != GPIO_MODER_ANALOG)
+    {
+      switch (cfgset & GPIO_PUPD_MASK)
+        {
+          default:
+          case GPIO_FLOAT:      /* No pull-up, pull-down */
+            break;
 
-#ifdef CONFIG_STM32_CAN1_REMAP1
-  val |= AFIO_MAPR_PB89;
-#endif
-#ifdef CONFIG_STM32_CAN1_REMAP2
-  val |= AFIO_MAPR_PD01;
-#endif
+          case GPIO_PULLUP:     /* Pull-up */
+            setting = GPIO_PUPDR_PULLUP;
+            break;
 
-  putreg32(val, STM32_AFIO_MAPR);  
-#endif
-}
+          case GPIO_PULLDOWN:   /* Pull-down */
+            setting = GPIO_PUPDR_PULLDOWN;
+            break;
+        }
+    }
 
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
+  regval  = getreg32(base + STM32_GPIO_PUPDR_OFFSET);
+  regval &= ~GPIO_PUPDR_MASK(pin);
+  regval |= (setting << GPIO_PUPDR_SHIFT(pin));
+  putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET);
 
-/****************************************************************************
- * Function:  stm32_gpioinit
- *
- * Description:
- *   Based on configuration within the .config file, it does:
- *    - Remaps positions of alternative functions. 
- * 
- * Typically called from stm32_start().
- ****************************************************************************/
+  /* Set the alternate function (Only alternate function pins) */
 
-void stm32_gpioinit(void)
-{
-  /* Remap according to the configuration within .config file */
+  if (pinmode == GPIO_MODER_ALT)
+    {
+      setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT;
+    }
+  else
+    {
+      setting = 0;
+    }
 
-  stm32_gpioremap();
-}
+  if (pin < 8)
+    {
+      regoffset = STM32_GPIO_AFRL_OFFSET;
+      pos       = pin;
+    }
+  else
+    {
+      regoffset = STM32_GPIO_ARFH_OFFSET;
+      pos       = pin - 8;
+    }
 
-/****************************************************************************
- * Name: stm32_configgpio
- *
- * Description:
- *   Configure a GPIO pin based on bit-encoded description of the pin.
- *   Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) 
- *   function, it must be unconfigured with stm32_unconfiggpio() with 
- *   the same cfgset first before it can be set to non-alternative function.
- * 
- * Returns:
- *   OK on success
- *   A negated errono valu on invalid port, or when pin is locked as ALT
- *   function.
- * 
- * To-Do: Auto Power Enable
- ****************************************************************************/
+  regval  = getreg32(base + regoffset);
+  regval &= ~GPIO_AFR_MASK(pos);
+  regval |= (setting << GPIO_AFR_SHIFT(pos));
+  putreg32(regval, base + regoffset);
 
-int stm32_configgpio(uint32_t cfgset)
-{
-  return stm32_gpio_configlock(cfgset, true);
+  /* Set speed (Only outputs and alternate function pins) */
+
+  if (pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT)
+    {
+      switch (cfgset & GPIO_SPEED_MASK)
+        {
+          default:
+          case GPIO_SPEED_2MHz:    /* 2 MHz Low speed output */
+            setting = GPIO_OSPEED_2MHz;
+            break;
+
+          case GPIO_SPEED_25MHz:   /* 25 MHz Medium speed output */
+            setting = GPIO_OSPEED_25MHz;
+            break;
+
+          case GPIO_SPEED_20MHz:   /* 50 MHz Fast speed output  */
+            setting = GPIO_OSPEED_50MHz;
+            break;
+
+          case GPIO_SPEED_100MHz:   /* 100 MHz High speed output */
+            setting = GPIO_OSPEED_100MHz;
+            break;
+        }
+    }
+  else
+    {
+      setting = 0;
+    }
+
+  regval  = getreg32(base + STM32_GPIO_OSPEED_OFFSET);
+  regval &= ~GPIO_OSPEED_MASK(pos);
+  regval |= (setting << GPIO_OSPEED_SHIFT(pos));
+  putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET);
+
+  /* Set push-pull/open-drain (Only outputs and alternate function pins) */
+
+  regval  = getreg32(base + STM32_GPIO_OTYPER_OFFSET);
+  setting = GPIO_OTYPER_OD(pin);
+
+  if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) &&
+      (cfgset & GPIO_OPENDRAIN) != 0)
+    {
+      regval |= setting;
+    }
+  else
+    {
+      regval &= ~setting;
+    }
+
+  putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET);
+
+  /* If it is an input pin, hould it configured as an EXTI interrupt? */
+
+  if ((cfgset & GPIO_EXTI) != 0)
+    {
+      /* "In STM32 F1 the selection of the EXTI line source is performed through
+       *  the EXTIx bits in the AFIO_EXTICRx registers, while in F2 series this
+       *  selection is done through the EXTIx bits in the SYSCFG_EXTICRx registers.
+       *
+       * "Only the mapping of the EXTICRx registers has been changed, without any
+       *  changes to the meaning of the EXTIx bits. However, the range of EXTI
+       *  bits values has been extended to 0b1000 to support the two ports added
+       *  in F2, port H and I (in F1 series the maximum value is 0b0110)."
+       */
+
+      uint32_t regaddr;
+      int shift;
+
+      /* Set the bits in the SYSCFG EXTICR register */
+
+      regaddr = STM32_SYSCFG_EXTICR(pin);
+      regval  = getreg32(regaddr);
+      shift   = SYSCFG_EXTICR_EXTI_SHIFT(pin);
+      regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift);
+      regval |= (((uint32_t)port) << shift);
+          
+      putreg32(regval, regaddr);
+    }
+   
+  /* If it is an output... set the pin to the correct initial state. */
+
+  else if (pinmode == GPIO_MODER_OUTPUT)
+    {
+      bool value = ((cfgset & GPIO_OUTPUT_SET) != 0);
+      stm32_gpiowrite(cfgset, value);
+    }
+
+  return OK;
 }
+#endif
 
 /****************************************************************************
  * Name: stm32_unconfiggpio
@@ -434,7 +611,7 @@ int stm32_unconfiggpio(uint32_t cfgset)
     
   /* To-Do: Mark its unuse for automatic power saving options */
 
-  return stm32_gpio_configlock(cfgset, false);
+  return stm32_configgpio(cfgset);
 }
 
 /****************************************************************************
diff --git a/nuttx/arch/arm/src/stm32/stm32_gpio.h b/nuttx/arch/arm/src/stm32/stm32_gpio.h
index 19e0adbe0d..ecd96863b1 100644
--- a/nuttx/arch/arm/src/stm32/stm32_gpio.h
+++ b/nuttx/arch/arm/src/stm32/stm32_gpio.h
@@ -307,7 +307,7 @@ extern "C" {
  * .... .... ..O. .... ....
  */
 
-#define GPIO_OPENDRAM                 (1 << 9)                   /* Bit9: 1=Open-drain output */
+#define GPIO_OPENDRAIN                (1 << 9)                   /* Bit9: 1=Open-drain output */
 #define GPIO_PUSHPULL                 (0)                        /* Bit9: 0=Push-pull output */
 
 /* If the pin is a GPIO digital output, then this identifies the initial output value.